AD53513 [ADI]
Quad Ultrahigh-Speed Pin Driver with High-Z and VTERM Modes; 四核超高速引脚驱动高-Z和VTERM模式
| 型号： | AD53513 |
| 厂家： | 
ADI |
| 描述： | Quad Ultrahigh-Speed Pin Driver with High-Z and VTERM Modes |
| 文件： | 总4页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Ultrahigh-Speed Pin Driver
with High-Z and VTERM Modes
a
AD53513
FUNCTIONAL BLOCK DIAGRAM
FEATURES
500 MHz Driver Operation (1 Gb/s)
Driver Inhibit Function
VCC
VEE
100 ps Edge Matching
Guaranteed Industry Specifications
20 ⍀ Output Impedance
RLD1
5 V/ns Slew Rate
VBB
39nF
VH1
DATA1
DATAB1
INH1
INHB1
VL1
VHDCPL1
Variable Output Voltages for ECL, TTL, and CMOS
High-Speed Differential Inputs for Maximum Flexibility
Ultrasmall 100-Lead LQFP Package with Built-In
Heat Sink
20⍀
50⍀
50⍀
30⍀
ROUT
VOUT1
DRIVER 1
DRIVER 2
39nF
VLDCPL1
VT1
APPLICATIONS
39nF
VHDCPL2
VH2
DATA2
DATAB2
INH2
INHB2
VL2
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
20⍀
ROUT
30⍀
VOUT2
39nF
VLDCPL2
Instrumentation and Characterization Equipment
VT2
VBB
RLD2
RLD3
VBB
AD53513
PRODUCT DESCRIPTION
39nF
The AD53513 is a quad high-speed pin driver designed for use
in digital or mixed-signal test systems. Combining a high-speed
monolithic process with a convenient surface-mount package,
this product attains superb electrical performance while preserving
optimum packaging densities and long-term reliability in a
100-lead, LQFP package with built-in heat sink.
VH3
VHDCPL3
DATA3
DATAB3
INH3
INHB3
VL3
20⍀
50⍀
30⍀
ROUT
VOUT3
DRIVER 3
39nF
VLDCPL3
VT3
39nF
VHDCPL4
VH4
DATA4
DATAB4
INH4
INHB4
VL4
VT4
VBB
RLD4
Featuring unity gain programmable output levels of –2.5 V to
+5.5 V, with output swing capability of less than 200 mV to
8 V, the AD53513 is designed to stimulate ECL, TTL, and
CMOS logic families, as well as high-speed memory. The
1.0 Gb/s data rate capacity and matched output impedance
allow for real-time stimulation of these digital logic families.
To test I/O devices, the pin driver can be switched into a high
impedance state (Inhibit Mode), electrically removing the driver
from the path. The pin driver leakage current in inhibit is typically
100 nA and output charge transfer entering inhibit is typically less
than 20 pC.
20⍀
ROUT
50⍀
30⍀
VOUT4
DRIVER 4
39nF
VLDCPL4
TVCC
THERM
GND
GND GND GND
GND
1.0A/K
The AD53513 transition from HI/LO or to inhibit is controlled
through the data and inhibit inputs. The input circuitry uses
high-speed differential inputs with a common-mode range of
2 V. This allows for direct interface to precision differential
ECL timing. The analog logic HI/LO inputs are equally easy
to interface. Typically requiring 10 µA of bias current, the
AD53513 can be directly coupled to the output of a digital-
to-analog converter.
the VBB input which is common to all four channels. The RLD
Mode Select controls whether inhibit puts the driver in High-Z
or VTERM mode. (Refer to Table I.) All of the digital logic inputs
(DATA, DATAB, INH, INHB, RLD, VBB), must share a
common set of logic levels. The VBB threshold should be set to
the midrange of the logic levels. For example, if ECL levels of
–0.8 V to –1.8 V are used, VBB should be set to –1.3 V.
The AD53513 is available in a 100-lead, LQFP package with a
built-in heat sink and is specified to operate over the ambient
commercial temperature range of –25°C to +85°C.
Each channel of the AD53513 has a Mode Select Pin RLD,
which is a single-sided logic input. The logic threshold is set by
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
AD53513–SPECIFICATIONS
(All specifications are at TJ = 85؇C ؎ 5؇C, +VS = +9 V ؎ 3%, –VS = –6 V ؎ 3% unless otherwise noted. All temperature coefficients are measured
at TJ = 75؇C–95؇C). (A 39 nF capacitor must be connected between VCC and VHDCPL and between VEE and VLDCPL.)
Parameter
Min Typ*
Max
Unit
Test Conditions
DIFFERENTIAL INPUT CHARACTERISTICS
(Data to DATA, INH to INH), RLD, VBB
Input Voltage
VBB = –1.3 V
–2
0
Volts
Differential Input Range
Bias Current
ECL
–1
+1
mA
V
VIN = –2 V, 0.0 V
Set to Midrange of Logic Levels
VBB Threshold Input
Midrange
REFERENCE INPUTS (VL, VH, VT)
Bias Currents
–50
+50
µA
VL, VH = 2 V
OUTPUT CHARACTERISTICS
Logic High Range
Logic Low Range
Amplitude (VH–VL)
Absolute Accuracy
VH Offset
–2.3
–2.5
0.2
+5.5
+5.3
8.0
Volts
Volts
Volts
DATA = H
DATA = L
–100
–100
–100
+100 mV
DATA = H, VH = 0 V, VL = –2 V, VT = +3 V
V
H Gain and Linearity Error
0.3
0.3
5
5
5
% of VH + mV DATA = H, VH = –2 V to +5 V, VL = –2.5 V,
VT = +3 V
V
L Offset
+100 mV
DATA = L, VL = 0 V, VH = +5 V, VT = +4.5 V
VL Gain and Linearity Error
VT Offset
% of VL + mV DATA = L, VL = –2 V to +5 V, VH = +5.5 V,
V
T = +4.5 V
+100 mV
Term Mode, VT = 0 V, VL = –1 V, VH = +3 V
V
T Gain and Linearity Error
0.3
0.5
% of VT + mV Term Mode, VT = –2.0 V to +5.0 V, VL = 0,
VH = +3 V
mV/°C
Ω
µA
Offset TC, VH, or VL, or VTERM
Output Resistance
Output Leakage
VL, VH = 0 V
DATA = H, VH = 3 V, VL = 0 V, IOUT = 45 mA
VOUT = –2 V to +5 V
20
–1.0
+1.0
Dynamic Current Limit
Static Current Limit
130
85
mA
mA
CBYP = 39 nF, VH = +5 V, VL = –2 V
Output to –2.5 V, VH = +5.5 V, VL = –2.5 V,
VT = 0; DATA = H and Output to 5.5 V,
VH = +5.5 V, VL = –2.5 V, VT = 0
VL = –3 V, DATA = L
VS = VS 3%
PSRR, Drive Mode
35
dB
DYNAMIC PERFORMANCE, DRIVE
(VH and VL)
Propagation Delay Time
0.3
1.1
ns
Measured at 50%, VH = 800 mV, 50 Ω Load,
VL = –800 mV
Propagation Delay TC
0.5
ps/°C
ps
Measured at 50%, VH = 800 mV, 50 Ω Load,
VL = –800 mV
Measured at 50%, VH = 800 mV, 50 Ω Load,
VL = –800 mV
Delay Matching, Edge to Edge
100
Rise and Fall Time
1 V Swing
2 V Swing
300
450
650
ps
ps
ps
Measured 20%–80%, VL = 0 V, VH = 1 V, VT = –2 V
Measured 10%–90%, VL = 0 V, VH = 2 V, VT = –2 V
Measured 10%–90%, VL = 0 V, VH = 3 V, VT = –2 V
3 V Swing
Rise and Fall Time TC
1 V Swing
2 V Swing
3 V Swing
Overshoot, Undershoot, and Preshoot
1
1
1
ps/°C
ps/°C
ps/°C
Measured 20%–80%, VL = 0 V, VH = 1 V, VT = –2 V
Measured 10%–90%, VL = 0 V, VH = 2 V, VT = –2 V
Measured 10%–90%, VL = 0 V, VH = 3 V, VT = –2 V
(6% +50 mV)
% of Step + mV a. VL, VH = 0 V, +1 V, VT = –2 V, 50 Ω
b. VL, VH = 0 V, +3 V, VT = –2 V, 50 Ω
c. VL, VH = 0 V, +5 V, VT = –2 V, 50 Ω
Settling Time
to 15 mV
to 4 mV
Delay Change vs. Pulsewidth
50
10
10
ns
µs
ps
VL = 0 V, VH = +0.5 V, VT = –2 V
VL = 0 V, VH = +0.5 V, VT = –2 V
VL = 0 V, VH = +2 V, VT = –2 V,
Pulsewidth/Period = 1.0 ns/4.0 ns, 30 ns/120 ns
Minimum Pulsewidth
2 V Swing
700
3.2
ps
700 ps Input, 10%/90% Output, VT = –2 V,
VL = 0 V, VH = +2 V, 50 Ω Terminated
VL = –1.8 V, VH = –0.8 V, VT = –2 V,
Toggle Rate
GHz
VOUT > 300 mV p-p at 50 Ω Terminated
REV. 0
–2–
AD53513
Parameter
Min Typ*
Max
Unit
Test Conditions
DYNAMIC PERFORMANCE, INHIBIT
Delay Time, Active to Inhibit
Delay Time, Inhibit to Active
I/O Spike
1.5
0.7
<200
6
2.5
1.7
ns
ns
mV p-p
pF
Measured at 50%, VH = +2 V, VL = –2 V, VT = –2 V
Measured at 50%, VH = +2 V, VL = –2 V, VT = –2 V
VH = 0 V, VL = 0 V, VT = –2 V
Output Capacitance
Driver Inhibited
DYNAMIC PERFORMANCE, VTERM
Delay Time, Active to VTERM
Delay Time, VTERM to Active
Overshoot, Undershoot, and Preshoot
VTERM to VL or VH
0.50
0.45
1.30
1.25
ns
ns
Measured at 50%, VH = +0.8 V, VL = –0.8 V, VT = 0 V
50 Ω Terminated
VL = –2 V, VH = +2 V, VT = 0 V
VL = –0.8 V, VH = +0.8 V, VT = 0 V
Output Terminated 50 Ω
6%/ 75
mV
POWER SUPPLIES
Total Supply Range
Positive Supply
15
9
V
V
Negative Supply
–6
V
Positive Supply Current
Negative Supply Current
Total Power Dissipation
Temperature Sensor Gain Factor
570
570
8.6
mA
mA
W
1.0
µA/K
RLOAD = 4.2 kΩ, VSOURCE = 9 V
NOTES
Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device.
*Typical parameters are not production tested but guaranteed through characterization.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
Power Supply Voltage
Environmental
Operating Temperature (Junction) . . . . . . . . . . . . . . . 175°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec)3 . . . . . . . . . . . 260°C
+VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 V
–VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
+VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Inputs
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
DATA, DATA, INH, INH, RLD, VBB . . . . . . . +5 V, –3 V
DATA to DATA, INH to INH, RLD, VBB . . . . . . . . . 3 V
VH, VL, VT to GND . . . . . . . . . . . . . . . . . . . . . . +7 V, –2 V
VH to VL (VH – VT) and (VT – VL) . . . . . . . . . . . . . . . . 9 V
Outputs
2Output short circuit protection is guaranteed as long as proper heat sinking is
employed to ensure compliance with the operating temperature limits.
3To ensure lead coplanarity ( 0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in environments at 24°C
5°C (75°F 10°F) with relative humidity not to exceed 65%.
V
OUT Short Circuit Duration . . . . . . . . . . . . . . . Indefinite2
VOUT Range in Inhibit Mode
VHDCPL . . . . . Do Not Connect Except for Capacitor to VCC
VLDCPL . . . . . Do Not Connect Except for Capacitor to VEE
THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 V, 0 V
ORDERING GUIDE
Shipment Method,
Quantity Per
Shipping Container
Package
Description
Package
Option
Model
AD53513JSQ
100-Lead LQFP-CDQUAD Tray, 90 Pieces
SQ-100
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53513 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD53513
PIN CONFIGURATION
s
75
74
73
72
71
70
69
68
67
66
65
1
2
HQGND1
HQGND1
OUT1
HQGND1
VLDCPL1
PWRGND
VHDCPL2
HQGND2
OUT2
HQGND2
HQGND2
VLDCPL2
PWRGND
VLDCPL3
HQGND3
HQGND3
OUT3
HQGND3
VHDCPL3
PWRGND
VLDCPL4
GND
PIN 1
IDENTIFIER
DATA1
DATAB1
INH1
3
4
5
INB1
HEAT SLUG
6
PWRGND
INHB2
INH2
VEE
VEE
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
DATAB2
64 DATA2
63 PWRGND
62 DATA3
61 DATAB3
60 VEE
AD53513
TOP VIEW
(Not to Scale)
59 VEE
58 INH3
57 INHB3
PWRGND
INHB4
INH4
DATAB4
DATA4
GND
56
55
54
53
52
51
HQGND4 22
OUT4 23
HQGND4 24
HQGND4 25
NC = NO CONNECT
NOTE THAT THE DIE IS MOUNTED TO THE BACK OF THE HEAT SLUG.
THE PACKAGE IS MOUNTED TO THE BOARD HEAT SLUG UP.
Table I. Driver Truth Table
Output
State
DATA
DATA
INH INH
RLD
VBB
0
1
X
X
1
0
X
X
0
0
1
1
1
1
0
0
X
X
0
VBB
VBB
VBB
VBB
VL
VH
INH
VTERM
1
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
100-Lead LQFP_ED Package
(SQ-100)
0.630 (16.00) BSC
0.063 (1.60)
MAX
0.551 (14.00) BSC
0.472 (12.00) BSC
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
100
1
76
75
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
SEATING
PLANE
0.008 (0.20)
0.004 (0.09)
0.551
(14.00)
BSC
7؇
3.5؇
0؇
0.472
(12.00)
BSC
0.006 (0.15)
0.002 (0.05)
TOP VIEW
(PINS DOWN)
0.003 (0.08)
MAX
0.630
(16.00)
BSC
VIEW A
ROTATED 90؇ CCW
VIEW A
50
25
26
49
0.020 (0.50) BSC
LEAD PITCH
0.011 (0.27)
0.009 (0.22)
0.007 (0.17)
–4–
REV. 0
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