AD5392BSTZ-5_技术文档

40-Channel, 3 V/5 V, Single-Supply,

12-Bit, denseDAC^®

Data Sheet

AD5381

FEATURES

Guaranteed monotonic

INTEGRATED FUNCTIONS

Channel monitor

Simultaneous output update via

LDAC

INL error: 1 LSB max

On-chip 1.25 V/2.5 V, 10 ppm/°C reference

Temperature range: –40°C to +85°C

Rail-to-rail output amplifier

Power-down

Clear function to user-programmable code

Amplifier boost mode to optimize slew rate

User-programmable offset and gain adjust

Toggle mode enables square wave generation

Thermal monitors

Package type: 100-lead LQFP (14 mm × 14 mm)

User interfaces:

APPLICATIONS

Variable optical attenuators (VOAs)

Parallel

Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,

featuring data readback)

I²C®-compatible

Level setting (ATE)

Optical micro-electro-mechanical systems (MEMs)

Control systems

Robust 6.5 kV HBM and 2 kV FICDM ESD rating

Instrumentation

FUNCTIONAL BLOCK DIAGRAM

DVDD (×3)

DGND (×3)

AVDD (×5)

AGND (×5)

DAC_GND (×5)

REFGND

REFOUT/REFIN SIGNAL_GND (×5)

PD

SER/PAR

AD5381

1.25V/2.5V

REFERENCE

FIFO EN

CS/(SYNC/AD0)

WR/(DCEN/AD1)

SDO

12

INPUT

REG0

DAC

REG0

DAC 0

VOUT0

DB11/(DIN/SDA)

12

m REG0

c REG0

DB10/(SCLK/SCL)

FIFO

+

STATE

MACHINE

+

2

DB9/(SPI/I C)

R

DB8

INTERFACE

CONTROL

LOGIC

12

INPUT

REG1

DAC

REG1

DAC 1

DB0

CONTROL

LOGIC

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

12

A5

A0

m REG1

c REG1

REG0

REG1

RESET

BUSY

CLR

12

INPUT

REG6

DAC

REG6

DAC 6

POWER-ON

RESET

12

m REG6

c REG6

12

INPUT

REG7

DAC

REG7

VOUT0………VOUT38

DAC 7

VOUT7

VOUT8

12

m REG7

c REG7

39-TO-1

MUX

VOUT38

×5

VOUT39/MON_OUT

LDAC

Figure 1.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD5381

Data Sheet

TABLE OF CONTENTS

General Description......................................................................... 3

Asynchronous Clear Function.................................................. 25

Specifications..................................................................................... 4

AD5381-5 Specifications............................................................. 4

AD5381-3 Specifications............................................................. 6

AC Characteristics........................................................................ 7

Timing Characteristics..................................................................... 8

Serial Interface Timing ................................................................ 8

I²C Serial Interface Timing........................................................ 10

Parallel Interface Timing........................................................... 11

Absolute Maximum Ratings.......................................................... 13

ESD Caution................................................................................ 13

Pin Configuration and Function Descriptions........................... 14

Terminology .................................................................................... 17

Typical Performance Characteristics ........................................... 18

Functional Description.................................................................. 21

DAC Architecture—General..................................................... 21

Data Decoding............................................................................ 21

On-Chip Special Function Registers (SFR) ............................ 22

SFR Commands.......................................................................... 22

Hardware Functions....................................................................... 25

Reset Function ............................................................................ 25

and

Functions...................................................... 25

LDAC

BUSY

FIFO Operation in Parallel Mode............................................ 25

Power-On Reset.......................................................................... 25

Power-Down ............................................................................... 25

Interfaces.......................................................................................... 26

DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces ..... 26

I²C Serial Interface ..................................................................... 28

Parallel Interface......................................................................... 30

Microprocessor Interfacing....................................................... 31

Application Information................................................................ 33

Power Supply Decoupling ......................................................... 33

Typical Configuration Circuit .................................................. 33

Monitor Function....................................................................... 34

Toggle Mode Function............................................................... 34

Thermal Monitor Function....................................................... 34

Optical Attenuators.................................................................... 35

Utilizing FIFO............................................................................. 35

Outline Dimensions....................................................................... 37

Ordering Guide .......................................................................... 37

REVISION HISTORY

9/12—Rev. C to Rev. D

8/05—Rev. A to Rev. B

Changes to Product Title..................................................................1

Changes to General Description Section and Table 1 ..................3

Deleted Table 2; Renumbered Sequentially ...................................3

Changes to Table 2.............................................................................3

Changes to Specifications Section...................................................4

Changes to Absolute Maximum Ratings Section....................... 13

Changes to Figure 43...................................................................... 35

Changes to Ordering Guide.......................................................... 37

5/12—Rev. B to Rev. C

Changes to Features.......................................................................... 1

Changes to Table 3............................................................................ 4

Changes to Table 4............................................................................ 6

Changes to Output Voltage Settling Time and Slew Rate

Parameters, Table 5........................................................................... 7

Changes to t₁₄, t₁₇, and t₁₉Parameters, Table 6 .............................. 8

Changes to Table 9.......................................................................... 13

Changes to Figure 10, Figure 11, and Figure 14 ......................... 18

Changes to Figure 16 to Figure 18 and Figure 20....................... 19

Updated Outline Dimensions and Changes to Ordering Guide....37

6/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Ordering Guide...........................................................36

5/04—Revision 0: Initial Version

Rev. D | Page 2 of 40

Data Sheet

AD5381

GENERALDESCRIPTION

The AD5381 is a complete, single-supply, 40-channel, 12-bit

denseDAC® availablein a 100-lead LQFP package. All 40 channels

have an on-chip outputamplifier with rail-to-rail operation.

The AD5381 includes a programmableinternal 1.25 V/2.5 V,

10 ppm/°C reference, an on-chip channel monitorfunction that

multiplexes the analog outputs to a common MON_OUT pin

for external monitoring, and an output amplifier boost mode,

which allowsoptimization of the amplifierslew rate. The AD5381

An input register followed bya DACregister providesdouble

buffering, allowing the DACoutputsto be updated independ-

ently or simultaneously using the

input.

LDAC

Each channelhas a programmablegain and offset adjust

register that allows the userto fully calibrate any DACchan-

nel. Power consumption is typically 0.25mA/channel with

boost mode disabled.

contains a double-buffered parallelinterface featuring 20 ns

WR

pulse width, an SPI-/QSPI-/MICROWIRE-/DSP-compatible serial

interface with interface speeds in excess of 30MHz, and an I²C-

compatible interface that supports a 400kHzdata transfer rate.

Table 1. Other Low Voltage Single-Supply DACs inProduct Family

Linearity Error Package

Model

Resolution AVDD Range

Output Channels

(LSB)

Description

Package Option

ST-100

ST-52

CP-64

ST-52

CP-64

ST-52

AD5380BSTZ-5

AD5380BSTZ-3

AD5382BSTZ-5

AD5382BSTZ-3

AD5383BSTZ-5

AD5383BSTZ-3

AD5390BSTZ-5

AD5390BCPZ-5

AD5390BSTZ-3

AD5390BCPZ-3

AD5391BSTZ-5

AD5391BCPZ-5

AD5391BSTZ-3

AD5391BCPZ-3

AD5392BSTZ-5

AD5392BCPZ-5

AD5392BSTZ-3

AD5392BCPZ-3

14 Bits

12 Bits

14 Bits

12 Bits

14 Bits

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

40

32

16

8

4

100-Lead LQFP

52-Lead LQFP

64-Lead LFCSP

52-Lead LQFP

64-Lead LFCSP

52-Lead LQFP

64-Lead LFCSP

52-Lead LQFP

64-Lead LFCSP

52-Lead LQFP

64-Lead LFCSP

52-Lead LQFP

64-Lead LFCSP

4

1

3

4

1

3

CP-64

ST-52

CP-64

ST-52

8

3

4

CP-64

ST-52

CP-64

Rev. D | Page 3 of 40

AD5381

Data Sheet

SPECIFICATIONS

AD5381-5 SPECIFICATIONS

AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications T_MINto T_MAX

unless otherwise noted.

,

Table 2.

Parameter

AD5381-5¹

Unit

Test Conditions/Comments

ACCURACY

Output unloaded

Resolution

12

1

Bits

Relative Accuracy ²(INL)

Differential Nonlinearity (DNL)

Zero-Scale Error

Offset Error

LSB max

mV max

Guaranteed monotonic over temperature

Measured at Code 8 in the linear region

4

mV max

Offset Error TC

Gain Error

5

µV/°C typ

% FSR max

ppm FSR/°C typ

LSB max

0.05

0.06

2

At 25°C

T_MINto T_MAX

Gain Temperature Coefficient³

DC Crosstalk³

1

REFERENCE INPUT/OUTPUT

Reference Input³

1% for specified performance, AVDD = 2 × REFIN + 50

mV

Reference Input Voltage

2.5

V

DC Input Impedance

Input Current

1

MΩ min

µA max

Typically 100 MΩ

Typically 30 nA

10

Reference Range

Reference Output⁴

1 to AVDD/2 V min/max

Enabled via CR8 in the AD5381 control register,

CR10 selects the reference voltage

Output Voltage

Reference TC

2.495/2.505

1.22/1.28

10

15

800

V min/max

ppm/°C max

Ω typ

At ambient, optimized for 2.5 V operation. CR10 = 1

CR10 = 0

Temperature Range: +25°C to +85°C

Temperature Range: −40°C to +85°C

Output Impedance

OUTPUT CHARACTERISTICS³

Output Voltage Range²

Short-Circuit Current

Load Current

0/AVDD

V min/max

mA max

40

1

Capacitive Load Stability

R_L= ∞

200

1000

0.6

pF max

Ω max

R_L= 5 kΩ

DC Output Impedance

MONITOR PIN

Output Impedance

Three-State Leakage Current

LOGIC INPUTS (EXCEPT SDA/SCL)³

V_IH, Input High Voltage

V_IL, Input Low Voltage

DVDD > 3.6 V

1

100

kΩ typ

nA typ

DVDD = 2.7 V to 5.5 V

2

V min

0.8

0.6

10

V max

µA max

pF max

DVDD ≤ 3.6 V

Input Current

Total for all pins;T_A= T_MINto T_MAX

Pin Capacitance

Rev. D | Page 4 of 40

Data Sheet

AD5381

Parameter

AD5381-5¹

Unit

Test Conditions/Comments

LOGIC INPUTS (SDA, SCL ONLY)³

V_IH, Input High Voltage

V_IL, Input Low Voltage

I_IN, Input Leakage Current

V_HYST, Input Hysteresis

C_IN, Input Capacitance

Glitch Rejection

0.7 × DVDD

0.3 × DVDD

1

0.05 × DVDD V min

8

V min

SMBus compatible at DVDD < 3.6 V

V max

µA max

pF typ

ns max

50

Input filtering suppresses noise spikes of less than50 ns

LOGIC OUTPUTS (

BUSY

, SDO)³

V_OL, Output Low Voltage

V_OH, Output High Voltage

V_OL, Output Low Voltage

0.4

DVDD – 1

0.4

V max

V min

V max

V min

µA max

pF typ

DVDD = 5 V 10%, sinking 200 µA

DVDD = 5 V 10%, sourcing 200 µA

DVDD = 2.7 V to 3.6 V, sinking 200 µA

DVDD = 2.7 V to 3.6 V, sourcing 200 µA

SDO only

V_OH, Output High Voltage

High Impedance Leakage Current

High Impedance Output Capacitance

LOGIC OUTPUT (SDA)³

DVDD – 0.5

1

5

SDO only

V_OL, Output Low Voltage

0.4

0.6

1

V max

µA max

pF typ

I_SINK= 3 mA

I_SINK= 6 mA

Three-State Leakage Current

Three-State Output Capacitance

POWER REQUIREMENTS

AVDD

8

4.5/5.5

2.7/5.5

V min/max

DVDD

Power Supply Sensitivity³

∆Midscale/∆ΑV_DD

AI_DD

–85

0.375

0.475

1

dB typ

mA/channel max

mA max

Outputs unloaded, boost off; 0.25 mA/channel typ

Outputs unloaded, boost on.; 0.325 mA /channel typ

V_IH= DVDD, V_IL= DGND

DI_DD

AI_DD(Power-Down)

DI_DD(Power-Down)

Power Dissipation

20

80

µA max

mW max

Typically 100 nA

Typically 1 µA

Outputs unloaded, boost off, AVDD = DVDD = 5 V

¹AD5381-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C.

²Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV.

³Guaranteed by characterization, not production tested.

⁴Default on the AD5381-5 is 2.5 V. Programmable to 1.25 V via CR10 in the AD5381 control register; operating the AD5381-5 with a 1.25 V reference will lead to

degraded accuracy specifications.

Rev. D | Page 5 of 40

AD5381

Data Sheet

AD5381-3 SPECIFICATIONS

AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V;

all specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter

AD5381-3¹

Unit

Test Conditions/Comments

ACCURACY

Output unloaded

Resolution

12

1

Bits

LSB max

Relative Accuracy²(INL)

Differential Nonlinearity (DNL)

Zero-Scale Error

Offset Error

1

LSB max

mV max

Guaranteed monotonic over temperature

Measured at Code 16 in the linear region

4

mV max

Offset Error TC

Gain Error

5

µV/°C typ

% FSR max

ppm FSR/°C typ

LSB max

0.05

0.1

2

At 25 °C

T_MINto T_MAX

Gain Temperature Coefficient³

DC Crosstalk³

1

REFERENCE INPUT/OUTPUT

Reference Input³

Reference Input Voltage

DC Input Impedance

Input Current

1.25

V

1% for specified performance

Typically 100 MΩ

Typically 30 nA

1

MΩ min

µA max

V min/max

10

Reference Range

Reference Output ⁴

1 to AVDD/2

Enabled via CR8 in the AD5381 control register

CR10 selects the reference voltage.

Output Voltage

Reference TC

1.245/1.255

2.47/2.53

10

V min/max

ppm/°C max

Ω typ

At ambient; optimized for 1.25 V operation; CR10 = 0

CR10 = 1

Temperature Range: +25°C to +85°C

Temperature Range: –40°C to +85°C

15

800

Output Impedance

OUTPUT CHARACTERISTICS³

Output Voltage Range²

Short-Circuit Current

Load Current

0/AVDD

V min/max

mA max

40

1

Capacitive Load Stability

R_L= ∞

R_L= 5 kΩ

200

1000

0.6

pF max

Ω max

DC Output Impedance

MONITOR PIN

Output Impedance

Three-State Leakage Current

LOGIC INPUTS (EXCEPT SDA/SCL)³

V_IH, Input High Voltage

V_IL,Input Low Voltage

DVDD > 3.6

1

100

kΩ typ

nA typ

DVDD = 2.7 V to 3.6 V

2

V min

0.8

0.6

1

V max

DVDD ≤ 3.6

Input Current

Pin Capacitance

µA max

pF max

Total for all pins; T_A= T_MINto T_MAX

10

LOGIC INPUTS (SDA, SCL ONLY)³

V_IH, Input High Voltage

V_IL, Input Low Voltage

I_IN, Input Leakage Current

V_HYST, Input Hysteresis

C_IN, Input Capacitance

Glitch Rejection

0.7 × DVDD

0.3 × DVDD

V min

V max

µA max

V min

pF typ

ns max

SMBus compatible at DVDD < 3.6 V

1

0.05 × DVDD

8

50

Input filtering suppresses noise spikes of less than 50 ns

Rev. D | Page 6 of 40

Data Sheet

AD5381

Parameter

AD5381-3¹

Unit

Test Conditions/Comments

LOGIC OUTPUTS (

, SDO)³

BUSY

V_OL, Output Low Voltage

V_OH, Output High Voltage

High Impedance Leakage Current

High Impedance Output Capacitance

LOGIC OUTPUT (SDA)³

0.4

V max

V min

µA max

pF typ

Sinking 200 µA

Sourcing 200 µA

SDO only

DVDD – 0.5

1

5

SDO only

V_OL, Output Low Voltage

0.4

0.6

1

V max

µA max

pF typ

I_SINK= 3 mA

I_SINK= 6 mA

Three-State Leakage Current

Three-State Output Capacitance

POWER REQUIREMENTS

AVDD

8

2.7/3.6

2.7/5.5

V min/max

DVDD

Power Supply Sensitivity³

∆Midscale/∆ΑV_DD

AI_DD

–85

0.375

0.475

1

dB typ

mA/channel max

mA max

Outputs unloaded, boost off; 0.25 mA/channel typ

Outputs unloaded, boost on; 0.325 mA/channel typ

V_IH= DVDD, V_IL= DGND

DI_DD

AI_DD(Power-Down)

DI_DD(Power-Down)

Power Dissipation

20

µA max

Typically 100 nA

Typically 1 µA

48

mW max

Outputs unloaded, boost off, AVDD = DVDD = 3 V

¹AD5381-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C.

²Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV.

³Guaranteed by characterization, not production tested.

⁴Default on the AD5381-3 is 1.25 V. Programmable to 2.5 V via CR10 in the AD5381 control register; operating the AD5381-3 with a 2.5 V reference will lead to degraded

accuracy specifications and limited input code range.

AC CHARACTERISTICS¹

AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; DVDD = 2.7V to 5.5V; AGND = DGND = 0V.

Table 4.

Parameter

All

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

1/4 scale to 3/4 scale change settling to 1 LSB

3

µs typ

8

µs max

V/µs typ

nV-s typ

mV typ

Slew Rate ²

1.5

2.5

12

15

Boost mode off, CR9 = 0

Boost mode on, CR9 = 1

Digital-to-Analog Glitch Energy

Glitch Impulse Peak Amplitude

DAC-to-DAC Crosstalk

Digital Crosstalk

1

nV-s typ

See Terminology section

0.8

0.1

15

40

Digital Feedthrough

Output Noise 0.1 Hz to 10 Hz

nV-s typ

µV p-p typ

Effect of input bus activity on DAC output under test

External reference, midscale loaded to DAC

Internal reference, midscale loaded to DAC

Output Noise Spectral Density

@ 1 kHz

@ 10 kHz

150

100

nV/√Hz typ

¹Guaranteed by design and characterization, not production tested.

²Slew rate can be programmed via the current boost control bit in the AD5381 control register.

Rev. D | Page 7 of 40

AD5381

Data Sheet

TIMING CHARACTERISTICS

SERIAL INTERFACE TIMING

DVDD = 2.7 V to 5.5 V; AVDD= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V;

all specifications T_MINto T_MAX, unless otherwise noted.

Table 5.

Parameter ^{1, 2, 3}

Limit at T_MIN, T_MAX

Unit

Description

t₁

t₂

t₃

t₄

33

13

ns min

SCLK cycle time

SCLK high time

SCLK low time

falling edge to SCLK falling edge setup time

24^thSCLK falling edge to

SYNC

4

falling edge

t₅

13

33

10

50

ns min

SYNC

low time

4

Minimum

t₆

SYNC

high time

high time in Readback mode

t₇

t_7A

t₈

t₉

t₁₀

5

4.5

30

ns min

ns max

Data setup time

Data hold time

24^thSCLK falling edge to

falling edge

4

BUSY

pulse width low (single channel update)

t₁₁

670

20

2

ns max

ns min

µs max

ns min

µs typ

BUSY

24th SCLK falling edge to

4

falling edge

t₁₂

LDAC

pulse width low

t₁₃

t₁₄

t₁₅

t₁₆

t₁₇

t₁₈

t₁₉

LDAC

BUSY

LDAC

rising edge to DAC output response time

rising edge to falling edge

0

LDAC

falling edge to DAC output response time

100

3

DAC output settling time

pulse width low

CLR

pulse activation time

CLR

20

40

ns min

µs max

5

t₂₀

t₂₁

20

5

ns max

ns min

SCLK rising edge to SDO valid

5

SCLK falling edge to

rising edge

SYNC

rising edge to SCLK rising edge

5

t₂₂

8

SYNC

rising edge to

falling edge

t₂₃

20

ns min

LDAC

¹Guaranteed by design and characterization, not production tested.

²All input signals are specified with t_r= t_f= 5 ns (10% to 90% of V_CC) and are timed from a voltage level of 1.2 V.

³See Figure 2, Figure 3, Figure 4, and Figure 5.

⁴Standalone mode only.

⁵Daisy-chain mode only.

200µA

I

OL

V

(MIN) OR

(MAX)

OH

OL

TO OUTPUT PIN

C

L

50pF

I

200µA

OH

Figure 2. Load Circuit for Digital Output Timing

Rev. D | Page 8 of 40

Data Sheet

AD5381

t₁

24

SCLK

t₃

t₆

t₂

t₅

t₄

SYNC

DIN

t₇

t₈t₉

DB0

DB23

t₁₀

t₁₁

t₁₃

BUSY

t₁₂

t₁₇

1

LDAC

t₁₄

VOUT1

t₁₅

t₁₃

t₁₇

2

LDAC

t₁₆

VOUT2

t₁₈

CLR

t₁₉

VOUT

1

2

LDAC ACTIVE DURING BUSY.

LDAC ACTIVE AFTER BUSY.

Figure 3. Serial Interface Timing Diagram (Standalone Mode)

SCLK

24

48

t_7A

SYNC

DIN

DB23

DB0

DB23

DB0

INPUT WORD SPECIFIES

REGISTER TO BE READ

NOP CONDITION

DB0

SDO

UNDEFINED

SELECTED REGISTER

DATA CLOCKED OUT

Figure 4. Serial Interface Timing Diagram (Data Readback Mode)

t₁

SCLK

24

48

t₃

t₂

t₂₁

t₇

t₂₂

t₄

SYNC

DIN

t₈t₉

DB23

DB0 DB23

DB0

INPUT WORD FOR DAC N

INPUT WORD FOR DAC N + 1

t₂₀

DB23

DB0

SDO

UNDEFINED

INPUT WORD FOR DAC N

t₁₃

t₂₃

LDAC

Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)

Rev. D | Page 9 of 40

AD5381

Data Sheet

I²C SERIAL INTERFACE TIMING

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T_MINto T_MAX

unless otherwise noted.

,

Table 6.

Parameter ^{1, 2}

Limit at T_MIN, T_MAX

Unit

Description

F_SCL

t₁

400

2.5

0.6

1.3

0.6

100

0.9

0

0.6

1.3

300

0

kHz max

µs min

ns min

µs max

µs min

ns max

ns min

ns max

ns min

ns max

ns min

pF max

SCL clock frequency

SCL cycle time

t₂

t₃

t₄

t_HIGH, SCL high time

t_LOW, SCL low time

t_HD,STA, start/repeated start condition hold time

t_{SU ,DAT}, data setup time

t_HD,DAT, data hold time

t₅

t₆

3

t_HD,DAT, data hold time

t₇

t₈

t₉

t_{SU ,STA}, setup time for repeated start

t_{SU ,STO}, stop condition setup time

t_BUF, bus free time between a STOP and a START condition

t_R, rise time of SCL and SDA when receiving

t_R, rise time of SCL and SDA when receiving (CMOS compatible)

t_F, fall time of SDA when transmitting

t_F, fall time of SDA when receiving (CMOS compatible)

t_F, fall time of SCL and SDA when receiving

t_F, fall time of SCL and SDA when transmitting

Capacitive load for each bus line

t₁₀

t₁₁

300

0

300

20 + 0.1 C_b

400

4

C_b

¹Guaranteed by design and characterization, not production tested.

²See Figure 6.

³A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) in order to bridge the undefined region of

SCL’s falling edge.

⁴C_bis the total capacitance, in pF, of one bus line. t_Rand t_Fare measured between 0.3 DVDD and 0.7 DVDD.

SDA

t₉

t₃

t₁₀

t₁₁

t₄

SCL

t₄

t₆

t₂

t₁

t₈

t₅

t₇

START

CONDITION

REPEATED

START

STOP

CONDITION

Figure 6. I²C-Compatible Serial Interface Timing Diagram

Rev. D | Page 10 of 40

Data Sheet

AD5381

PARALLEL INTERFACE TIMING

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T_MINto T_MAX

unless otherwise noted.

,

Table 7.

Parameter ^{1, 2, 3}

Limit at T_MIN, T_MAX

Unit

Description

REG0, REG1, address to

rising edge setup time

rising edge hold time

t₀

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

4.5

20

0

ns min

ns max

ns min

ns max

ns min

µs typ

ns min

µsmax

WR

REG0, REG1, address to

pulse width low

CS

pulse width low

WR

to

falling edge setup time

rising edge hold time

rising edge setup time

rising edge hold time

CS WR

to

0

WR CS

Data to

4.5

20

700

30

670

30

20

100

20

0

WR

Data to

WR

pulse width high

WR

Minimum

4

cycle time (single-channel write)

t₉

WR

rising edge to

4

falling edge

t₁₀

WR

BUSY

pulse width low (single-channelupdate)

4, 5

t₁₁

BUSY

rising edge to

falling edge

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

t₁₇

t₁₈

t₁₉

t₂₀

WR

LDAC

pulse width low

LDAC

BUSY

LDAC

BUSY

LDAC

rising edge to DAC output response time

rising edge to

rising edge

falling edge

WR

LDAC

falling edge to DAC output response time

100

8

DAC output settling time, boost mode off

pulse width low

CLR

pulse activation time

CLR

20

12

¹Guaranteed by design and characterization, not production tested.

²All input signals are specified with t_R= t_R= 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.

³See Figure 7.

⁴See Figure 29.

⁵Measured with the load circuit of Figure 2.

Rev. D | Page 11 of 40

AD5381

Data Sheet

t₀

t₁

REG0, REG1, A5...A0

t₄

t₅

t₂

CS

t₉

t₃

t₈

WR

t₁₅

t₆

t₇

DB11...DB0

BUSY

t₁₀

t₁₁

t₁₃

t₁₂

t₁₈

1

LDAC

t₁₄

t₁₆

VOUT1

2

LDAC

t₁₃

t₁₈

t₁₇

VOUT2

CLR

t₁₉

t₂₀

VOUT

1

2

LDAC ACTIVE DURING BUSY.

LDAC ACTIVE AFTER BUSY.

Figure 7. Parallel Interface Timing Diagram

Rev. D | Page 12 of 40

Data Sheet

AD5381

ABSOLUTEMAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.¹

Stresses abovethoselisted under AbsoluteMaximumRatings

may cause permanent damageto the device. This is a stress

rating only; functionaloperation of the device at these orany

other conditions above thoselisted in the operationalsections

of this specification is not implied. Exposure to absolute maxi-

mum rating conditions for extendedperiodsmay affect device

reliability.

Table 8.

Parameter

Rating

AVDD to AGND

–0.3 V to +7 V

DVDD to DGND

–0.3 V to +7 V

Digital Inputs to DGND

SDA/SCL to DGND

–0.3 V to DVDD + 0.3 V

–0.3 V to +7 V

Digital Outputs to DGND

REFIN/REFOUT to AGND

AGND to DGND

–0.3 V to DVDD + 0.3 V

–0.3 V to AVDD + 0.3 V

–0.3 V to +0.3 V

VOUTx to AGND

–0.3 V to AVDD + 0.3 V

Analog Inputs to AGND

Operating Temperature Range

Commercial (B Version)

Storage Temperature Range

JunctionTemperature (T_{J MAX}

100-Lead LQFP Package

θ_JAThermal Impedance

Reflow Soldering

–40°C to +85°C

–65°C to +150°C

150°C

)

44°C/W

230°C

Peak Temperature

Reflow Soldering (Pb-free)

Peak Temperature

260(0/-5)°C

Time at Peak Temperature

ESD

10 sec to 40 sec

HBM

FICDM

6.5 kV

2 kV

¹Transient currents of up to 100 mA will not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

this product features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

Rev. D | Page 13 of 40

AD5381

Data Sheet

PIN CONFIGURATIONAND FUNCTION DESCRIPTIONS

1

FIFO EN

CLR

VOUT24

VOUT25

VOUT26

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

RESET

DB5

DB4

DB3

DB2

DB1

DB0

NC

PIN 1

IDENTIFIER

2

3

4

5

6

VOUT27

SIGNAL_GND4

DAC_GND4

AGND4

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

AVDD4

VOUT28

VOUT29

VOUT30

REG0

REG1

VOUT23

VOUT22

VOUT21

VOUT20

AVDD3

AGND3

DAC_GND3

SIGNAL_GND3

VOUT19

VOUT18

VOUT17

VOUT16

AVDD2

AGND2

AD5381

TOP VIEW

(Not to Scale)

VOUT31

REFGND

REFOUT/REFIN

SIGNAL_GND1

DAC_GND1

AVDD1

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

AGND1

54

53

52

51

NC = NO CONNECT

Figure 8. 100-Lead LQFP Pin Configuration

Table 9. Pin Function Descriptions

Mnemonic

Function

Buffered Analog Outputs forChannel x. Each analogoutput is driven by a rail-to-rail output amplifier operating at a

gain of 2. Each output is capable of driving an output load of5 kΩ to ground. Typical output impedance is 0.5 Ω.

VOUTx

Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together

internally and should be connected to the AGND plane as close as possible to the AD5381.

Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 12-bit DAC.

These pins shound be connected to the AGND plane.

Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be

connected externally to the AGND plane.

SIGNAL_GND(1–5)

DAC_GND(1–5)

AGND(1–5)

Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are shorted internallyand

should be decoupled with a 0.1 µF ceramic capacitor and 10 µF tantalum capacitor. Operating range for the

AD5381-5 is 4.5 V to 5.5 V; operating range for the AD5381-3 is 2.7 V to 3.6 V.

AVDD(1–5)

DGND

DVDD

Ground for All Digital Circuitry.

Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled

with a 0.1 µF ceramic and a 10 µF tantalum capacitors to DGND.

REFGND

Ground Reference Point for the Internal Reference.

Rev. D | Page 14 of 40

Data Sheet

AD5381

Mnemonic

Function

The AD5381 contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference

output. If the application requires an external reference, it can be applied to this pin and the internal reference can

be disabled via the control register. The default for this pin is a reference input.

REFOUT/REFIN

This pin has a dual function. It acts as a buffered output for Channel 39 in default mode. However, when the monitor

function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to

multiplex one of Channels 0 to 38 to the MON_OUT pin. The MON_OUT pin’s output impedance is typically 500 Ω

and is intended to drive a high input impedance like that exhibited by SAR ADC inputs.

VOUT39/MON_OUT

SER/

PAR

Interface Select Input. This pin allows the user to select whether the serial or parallel interface is used. If it is tied high,

the serial interface mode is selected and Pin 97 ( /I²C) is used to determine if the interface mode is SPI or I²C.

SPI

Parallel interface mode is selected when SER/

PAR

is low.

/(

CS SYNC

/AD0)

In parallel interface mode, this pin acts as chip select input (level sensitive, active low). When low, the AD5381

is selected.

Serial Interface Mode. This is the frame synchronizationinput signal for the serialclock and data.

I²C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address

for the device on the I²C bus.

/(DCEN/AD1)

Multifunction Pin. In parallel interface mode, this pin acts as write enable. In serial interface mode, this pin acts as a

daisy-chain enable in SPI mode and as a hardware address pin in I²C mode.

WR

Parallel Interface Write Input (edge sensitive). The rising edge of

address bus inputs to write to the selected device registers.

is used in conjunction with low, and the

CS

WR

Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction

with SER/ high to enable the SPI serial interface daisy-chain mode.

PAR

I²C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address

for this device on the I²C bus.

DB11–DB0

A5–A0

Parallel Data Bus. DB11 is the MSB and DB0 is the LSB of the input data-word onthe AD5381.

Parallel Address Inputs. A5 to A0 are decoded to address one of the AD5381’s 40 input channels. Used in conjunction

with the REG1 and REG0 pins to determine the destination register for the input data.

In parallel interface mode, REG1 and REG0 are used in decoding the destination registers for the input data. REG1

and REG0 are decoded to address the input data register, offset register, or gain register for the selected channel and

are also used to decide the special function registers.

REG1, REG0

SDO/( /B)

A

Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a

number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the fallingedge

of SCLK.

When operating in parallel interface mode, this pin acts as the A or B data register select when writing data to the

AD5381’s data registers with toggle mode selected (see the Toggle Mode Function section). In toggle mode, the

LDAC is used to switch the output between the data contained in the A and B data registers. All DAC channels

contain two data registers. In normal mode, Data Register A is the default for data transfers.

Digital CMOS Output.

goes low during internal calculations ofthe data (x2) loaded to the DAC data register.

BUSY

LDAC

BUSY

During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the

DAC registers and DAC outputs can take place. If

is taken low while

is low, this event is stored.

also

LDAC

RESET

BUSY

pin is low. During this time, the interface is disabled andany

BUSY

goes low during power-on reset, and when the

events on are ignored. A

operation also brings low.

BUSY

LDAC

CLR

Load DAC Logic Input (Active Low). If

registers are transferred to the DAC registers and the DAC outputs are updated. If

active and internal calculations are taking place, the

goes inactive. However any events on

BUSY

Asynchronous Clear Input. The

with the data contained in the

is taken low while

is inactive (high), the contents of the input

LDAC

BUSY

is taken low while

is

LDAC

event is stored and the DAC registers are updated when

BUSY

LDAC

during power-on reset or on

are ignored.

LDAC

RESET

input is falling edge sensitive. When is activated, all channels are updated

CLR

code register.

is low for a duration of35 µs while all channels are being

BUSY

updated with the code.

CLR

Asynchronous Digital Reset Input (Falling Edge Sensitive). The function ofthis pin is equivalent to that of the power-

on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1,

RESET

m, c, and x2 registers to their default power-on values. This sequence typically takes270 µs. The falling edge of

RESET

is complete. While

RESET BUSY

initiates the

is low, all interfaces are disabled and all

process and

goes low forthe duration, returning high when

RESET

BUSY

pulses are ignored. When

returns high, the part resumes normal

LDAC

BUSY

operation and the status of the

pin is ignored untilthe next falling edge is detected.

RESET

Rev. D | Page 15 of 40

AD5381

Data Sheet

Mnemonic

Function

Power-Down (Level Sensitive, Active High). PD is used to place the device in low power mode, where the analog

current consumption is reduced to 2 µA and the digital current consumption is reduced to 20 µA. In power-down

mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high

impedance output or provides a 100 kΩ load to ground, depending on how the power-down mode is configured.

The serial interface remains active during power-down.

PD

FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user

to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO EN pin is

sampled on power-up, and also followinga CLEAR or RESET, to determine if the FIFO is enabled. In either serial or

I²C interface modes, the FIFO EN pin should be tied low.

FIFO EN

DB9/( /I²C)

SPI

Multifunction Input Pin. In parallel interface mode, this pin acts as DB9 of the parallel input data-word. In serial

interface mode, this pin acts as serial interface mode select. When serial interface mode is selected (SER/

= 1) and

PAR

this input is low, SPI mode is selected. In SPI mode, DB12 is the serial clock (SCLK) input and DB11 is the serial data

(DIN) input.

When serial interface mode is selected (SER/

PAR

= 1) and this input is high I²C Mode is selected.

In this mode, DB12 is the serial clock (SCL) input and DB11 is the serial data (SDA) input.

Multifunction Input Pin. In parallel interface mode, this pin acts as DB10 of the parallel input data-word. In serial

interface mode, this pin acts as a serial clock input.

Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the fallingedge of SCLK.

This operates at clock speeds up to 50 MHz.

I²C Mode. In I²C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in

I²C mode is compatible with both 100 kHz and 400 kHz operating modes.

DB10/(SCLK/SCL)

DB11/(DIN/SDA)

Multifunction Data Input Pin. In parallel interface mode, this pin acts as DB11 of the parallel input data-word.

Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling

edge of SCLK.

I²C Mode. In I²C mode, this pin is the serial data pin (SDA) operating as an open-draininput/output.

Rev. D | Page 16 of 40

Data Sheet

AD5381

TERMINOLOGY

Relative Accuracy

DC Output Impedance

Relative accuracy, or endpoint linearity, is a measure of the

maximum deviation from a straight line passing through the

endpoints of the DAC transfer function. It is measuredafter

adjusting for zero-scale error and full-scale error, and is

expressedin LSB.

This is the effective output source resistance.It is dominated by

package lead resistance.

Output Voltage Settling Time

This is the amount of time it takes for the output of a DAC to

settle to a specified levelfor a ¼ to ¾ full-scale input change,

and is measuredfrom the

rising edge.

Differential Nonlinearity

BUSY

Differentialnonlinearity is the difference betweenthe measured

change and the ideal1 LSB change between any two adjacent

codes. A specified differential nonlinearity of 1 LSB maximum

ensures monotonicity.

Digital-to-Analog Glitch Energy

This is the amount of energy injected into the analog output at

the major code transition. It is specified as the area of the glitch

in nV-s. It is measuredby toggling the DAC registerdata

between 0x7FF and 0x800.

Zero-Scale Error

Zero-scale error is the errorin the DAC output voltagewhen all

0s are loaded into the DAC register. Ideally, with all0s loaded

to the DAC and m = all 1s, c = 2^{n – 1}

DAC-to-DAC Crosstalk

DAC-to-DACcrosstalkis the glitch impulse that appearsat the

output of one DAC due to both the digitalchange and the

subsequent analog output change at another DAC. The victim

channel is loaded with midscale. DAC-to-DACcrosstalkis

specified in nV-s.

VOUT_(Zero-Scale)= 0 V

Zero-scale error is a measureof the difference between VOUT

(actual) and VOUT (ideal), expressed in mV. It is mainly due to

offsets in the output amplifier.

Digital Crosstalk

The glitch impulse transferred to the output of one converter

due to a change in the DAC register code of another converter

is defined as the digital crosstalk and is specified in nV-s.

Offset Error

Offset error is a measure of the differencebetween VOUT

(actual) and VOUT (ideal) in the linear region of the transfer

function, expressed in mV. Offset error is measured on the

AD5381-5with Code 32loaded into the DAC register, and on

the AD5381-3 with Code 64.

Digital Feedthrough

When the device is not selected, high frequency logicactivity

on the device’s digital inputs can be capacitively coupled both

across and through the device to show up as noise on the

VOUT pins. It can also be coupled along the supply and

ground lines. This noise is digital feedthrough.

Gain Error

Gain Error is specified in the linear region of the output range

between VOUT= 10 mV and VOUT = AVDD – 50 mV. It is

the deviation in slope of the DAC transfer characteristicfrom

the idealand is expressedin %FSR with the DAC output

unloaded.

Output Noise Spectral Density

This is a measure of internally generatedrandomnoise.

Random noise is characterized as a spectraldensity (voltageper

√Hertz). It is measured by loading allDACs to midscaleand

measuring noise at the output. It is measured in nV/√Hz in a

1 Hz bandwidth at 10 kHz.

DC Crosstalk

This is the dc change in the output levelof one DAC at

midscale in response to a full-scale code (all 0s to all 1s, and

vice versa)and output change of allother DACs.It is expressed

in LSB.

Rev. D | Page 17 of 40

AD5381

Data Sheet

TYPICAL PERFORMANCECHARACTERISTICS

1.00

0.75

0.50

0.25

0

AVDD = 5V

AVDD = 3V

REFIN = 1.25V

REFIN = 2.5V

= 25°C

0.75

T

T = 25°C

A

0.50

0.25

0

–0.25

–0.50

–0.75

–1.00

–0.25

–0.50

–0.75

–1.00

0

512

1024

1536

2048

2560

3072

3584

4096

0

512

1024

1536

2048

2560

3072

3584

4096

INPUT CODE

Figure 9. Typical AD5381-5 INL Plot

Figure 12. Typical AD5381-3 INL Plot

1.254

1.253

1.252

1.251

1.250

1.249

1.248

1.247

1.246

1.245

2.510

2.505

2.500

2.995

2.990

AVDD = DVDD = 3V

V

= 1.25V

REF

= 25°C

T

A

14ns/SAMPLE NUMBER

1 LSB CHANGE AROUND MIDSCALE

GLITCH IMPULSE = 5nV-s

0

50 100 150 200 250 300 350 400 450 500 550

SAMPLE NUMBER

0

2

4

6

8

10

12

TIME (µs)

Figure 13. AD5381-3 Glitch Impulse

Figure 10. AD5381-5 Glitch Impulse

LDAC

VOUT

AVDD = DVDD = 5V

= 2.5V

AVDD = DVDD = 5V

VREF = 2.5V

V

REF

T

= 25°C

A

T

= 25°C

A

Figure 11. Slew Rate with Boost Off

Figure 14. Slew Rate with Boost On

Rev. D | Page 18 of 40

Data Sheet

AD5381

14

12

10

8

AVDD = 5.5V

= 2.5V

V

REF

= 25°C

T

A

AVDD = DVDD = 5V

VREF = 2.5V

T

= 25°C

A

VDD

6

4

VOUT

2

8

9

10

AI (mA)

11

DD

Figure 15. AI_DDHistogram with Boost Off

Figure 18. Power-Up Transient

40

35

30

25

20

15

10

5

DVDD = 5.5V

V

= DVDD

= DGND

= 25°C

IH

IL

A

10

8

T

6

4

2

0

–5.0 –4.0 –3.0 –2.0 –1.0

0

1.0 2.0 3.0 4.0 5.0

0.5

0.6

0.7

DI

0.8

0.9

1.0

–4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5

REFERENCE DRIFT (ppm/°C)

(mA)

DD

Figure 19. REFOUT Temperature Coefficient

Figure 16. DI_DDHistogram

PD

BUSY

VOUT

AVDD = DVDD = 5V

= 2.5V

AVDD = DVDD = 5V

= 2.5V

V

REF

V

REF

T

= 25°C

A

T

= 25°C

A

Figure 20. Exiting Hardware Power-Down

Figure 17. Exiting Soft Power-Down

Rev. D | Page 19 of 40

AD5381

Data Sheet

6

5

AVDD = DVDD = 3V

= 1.25V

FULL SCALE

V

REF

T

= 25°C

5

4

A

AVDD = DVDD = 5V

V

= 2.5V

= 25°C

3/4 SCALE

REF

T

4

A

3/4 SCALE

FULL SCALE

MIDSCALE

3

MIDSCALE

2

1/4 SCALE

1

ZERO SCALE

0

ZERO SCALE

–5

1/4 SCALE

–1

–40 –20 –10

–5

–2

0

2

5

10

20

40

–40 –20 –10

–2

0

2

5

10

20

–40

CURRENT (mA)

Figure 21. AD5381-5 Output Amplifier Source and Sink Capability

Figure 24. AD5381-3 Output Amplifier Source and Sink Capability

0.20

2.456

AVDD = 5V

AVDD = DVDD = 5V

V

= 2.5V

REF

= 25°C

V

T

= 2.5V

REF

= 25°C

0.15

0.10

0.05

0

T

A

2.455

2.454

2.453

2.452

2.451

2.450

2.449

A

14ns/SAMPLE NUMBER

ERROR AT ZERO SINKING CURRENT

–0.05

–0.10

–0.15

–0.20

(VDD–VOUT) AT FULL-SCALE SOURCING CURRENT

0

0.25

0.50

0.75

I

1.00

/I

1.25

1.50

1.75

2.00

0

50 100 150 200 250 300 350 400 450 500 550

SAMPLE NUMBER

(mA)

SOURCE SINK

Figure 22. Headroom at Rails vs. Source/Sink Current

Figure 25. Adjacent Channel DAC-to-DAC Crosstalk

600

500

400

300

200

100

0

AVDD = 5V

T

= 25°C

A

REFOUT DECOUPLED

WITH 100nF CAPACITOR

AVDD = DVDD = 5V

= 25°C

T

A

DAC LOADED WITH MIDSCALE

EXTERNAL REFERENCE

Y AXIS = 5µV/DIV

X AXIS = 100ms/DIV

REFOUT = 2.5V

REFOUT = 1.25V

AV = DV = 5V

DD DD

V

= 2.5V

REF

T

= 25°C

A

EXITS SOFT PD

TO MIDSCALE

100

1k

10k

100k

FREQUENCY (Hz)

Figure 23. REFOUT Noise Spectral Density

Figure 26. 0.1 Hz to 10 Hz Noise Plot

Rev. D | Page 20 of 40

Data Sheet

AD5381

FUNCTIONALDESCRIPTION

DAC ARCHITECTURE—GENERAL

The complete transfer function for thesedevices can be

represented as

The AD5381 is a complete, single-supply, 40-channel voltage

output DACthat offers12-bit resolution. The part is available

in a 100-lead LQFPpackage and features both a paralleland

a serial interface. This product includes an internal, software

selectable, 1.25 V/2.5 V, 1 0 ppm/°C reference that can be used

to drive the bufferedreference inputs; alternatively, an external

referencecan be used to drive theseinputs. Internal/external

referenceselection is via the CR8bit in the controlregister;

CR10selects the referencemagnitude if the internalreference

is selected. All channels have an on-chip output amplifier with

rail-to-rail outputcapable of driving 5 kΩ in parallel with a

200 pF load.

VOUT = 2 × V_REF× x2/2ⁿ

where:

x2 is the data-word loaded to the resistor string DAC. V_REF

is externally applied to the DACREFOUT/REFINpin. For

specified performance, an externalreference voltageof 2.5 V is

recommendedfor the AD5381-5, and 1.25 V for the AD5381-3.

DATA DECODING

The AD5381 contains a 12-bit data bus, DB11 to DB0. Depend-

ing on the value of REG1 and REG0 (see Table 10), this data is

loaded into the addressedDAC input registers, offset (c)

registers, or gain (m)registers. The format data, offset (c), and

gain (m) register contents are shown in Table 11 to Table 13.

VREF

AVDD

×1 INPUT

REG

DAC

REG

12-BIT

DAC

Table 10. Register Selection

INPUT DATA m REG ×2

c REG

VOUT

REG1

REG0

Register Selected

R

1

0

1

0

1

0

Input Data Register (x1)

Offset Register (c)

Gain Register (m)

Special Function Registers (SFRs)

Figure 27. Single-Channel Architecture

Table 11. DAC Data Format(REG1 = 1, REG0 = 1)

The architecture of a single DACchannelconsists ofa 12-bit

resistor-string DACfollowed by an outputbuffer amplifier

operating at a gain of 2. This resistor-string architecture

guaranteesDAC monotonicity. The 12-bit binary digital code

loaded to the DAC registerdetermines at whatnode on the

string the voltage is tapped off beforebeing fed to the output

amplifier. Each channelon these devices contains independent

offset and gain control registers that allow theuser to digitally

trim offset and gain. These registers give the userthe ability to

calibrate out errors in the complete signal chain, including the

DAC, using the internal m and cregisters, which hold the

correction factors. Allchannels are double buffered, allow-

DB11 to DB0

DAC Output (V)

2 V_REF× (4095/4096)

2 V_REF× (4094/4096)

2 V_REF× (2049/4096)

2 V_REF× (2048/4096)

2 V_REF× (2047/4096)

2 V_REF× (1/4096)

0

1111

1000

0111

0000

1111

1110

0001

0000

1111

0001

0000

1111

0000

1111

0000

Table 12. Offset Data Format (REG1 = 1, REG0 = 0)

DB11 to DB0

Offset (LSB)

+2048

+2047

+1

1111

1000

0111

0000

1111

0000

1111

1110

0001

0000

1111

0001

0000

ing synchronous updating of all channels using the

pin.

LDAC

Figure 27 shows a blockdiagram of a single channelon the

AD5381. The digital input transfer function for each DAC

can be represented as

0

1111

0000

–1

–2047

–2048

x2 = [(m + 2)/ 2ⁿ× x1] + (c – 2^{n – 1}

)

where:

Table 13. GainData Format(REG1 = 0, REG0 = 1)

x2 = the data-wordloadedto the resistorstring DAC.

x1 = the 12-bit data-wordwritten to the DACinput register.

m = the gain coefficient (default is 0xFFE). The gain coefficient

is written to the 11 most significant bits (DB11 to DB1), the LSB

(DB0) of the data-word is a 0.

n = DAC resolution (n = 12 for AD5381).

c = the12-bit offset coefficient (default is 0x800).

DB11 to DB0

Gain Factor

1111

1011

0111

0011

0000

1111

1110

0000

1

0.75

0.5

0.25

0

1111

0000

Rev. D | Page 21 of 40

AD5381

Data Sheet

ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)

Soft CLR

The AD5381 contains a number of special function registers

(SFRs), as outlined in Table 14. SFRs are addressed with

REG1 = REG0 = 0 and are decoded using Address Bits

A5 to A0.

REG1 = REG0 = 0, A5 to A0 = 000010

DB11 to DB0= Don’t Care

Executing this instruction performs the CLR, which is func-

tionally the same as that provided by the external pin. The

DAC outputs areloaded with the data in the CLR code register.

It takes 35 µs to fully execute the SOFT CLR, as indicated by the

CLR

Table 14. SFR Register Functions (REG1 = 0, REG0 = 0)

R/

A5 A4 A3 A2 A1 A0 Function

W

low time.

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NOP (No Operation)

Write CLR Code

Soft CLR

Soft Power-Down

Soft Power-Up

Control Register Write

Control Register Read

Monitor Channel

Soft Reset

BUSY

Soft Power-Down

REG1 = REG0 = 0, A5 to A0 = 001000

DB11 to DB0= Don’t Care

Executing this instruction performs a global power-down

feature that puts allchannels into a low powermodethat

reduces the analog supply current to 2 µA max and the digi-

tal current to 20 µA max. In power-down mode, the output

amplifier can be configured as a high impedance output or

provide a 100 kΩ load to ground. The contentsof all internal

registers are retained in power-down mode. No registercan be

written to while in power-down.

SFR COMMANDS

NOP (No Operation)

REG1 = REG0 = 0, A5 to A0 = 000000

Performs no operation but is usefulin serial readbackmodeto

Soft Power-Up

clock out data on D_OUTfor diagnosticpurposes.

low during a NOP operation.

pulses

BUSY

REG1 = REG0 = 0, A5 to A0 = 001001

DB11 to DB0= Don’t Care

Write CLR Code

This instruction is used to power up the output amplifiers and

the internalreference. The time to exit power-down is 8µs.

The hardware power-downand softwarefunction are internally

combined in a digital OR function.

REG1 = REG0 = 0, A5 to A0 = 000001

DB11 to DB0= Contain the CLR data

Bringing the

line low or exercising the soft clear function

CLR

Soft RESET

will load the contents of the DACregisters with the data con-

tained in the user configurable CLR register, and will set

VOUT0 to VOUT39 accordingly. This can be very useful for

setting up a specific output voltage in a clear condition. It is also

beneficial for calibration purposes; the user can load full scale

or zero scale to the clear code register and then issue a hard-

ware or software clear to load this code to allDACs, removing

the need for individual writes to each DAC.Default on power-

up is all zeros.

REG1 = REG0 = 0, A5 to A0 = 001111

DB11 to DB0= Don’t Care

This instruction is used to implement a softwarereset. All

internalregisters arereset to their default values, which corre-

spond to m at full scale and c at zero scale. The contents of the

DAC registers arecleared, setting allanalog outputsto 0 V. The

soft reset activation time is 135 µs.

Rev. D | Page 22 of 40

Data Sheet

AD5381

Table 15. Control Register Contents

MSB

LSB

CR11

Control Register Write/Read

REG1 = REG0 = 0, A5 to A0 = 001100, R/ status determines

CR10

CR9

CR8

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

CR7= 0: Monitor Disabled (default on power-up). When the

monitor is disabled, the MON_OUT pin assumes its normal

DAC output function.

W

if the operation is a write (R/ = 0) or a read (R/ = 1). DB11

W

to DB0contains the controlregisterdata.

CR6: Thermal Monitor Function. When enabled, this function

is used to monitor the internaldie temperature of the AD5381.

The thermalmonitorpowersdown the output amplifiers when

the temperature exceeds130°C. This function can be used to

protect the device in cases where power dissipation may be

exceeded if a number of outputchannels aresimultaneously

short-circuited. A soft power-up will re-enable the output

amplifiers if the die temperature hasdroppedbelow 130°C.

Control Register Contents

CR11: Power-Down Status. This bit is used to configure the

output amplifier state in power-down.

CR11= 1. Amplifier output is high impedance (default on

power-up).

CR11 = 0. Amplifier output is 100 kΩ to ground.

CR6= 1: Thermal MonitorEnabled.

CR6= 0: Thermal MonitorDisabled (default on power-up).

CR5: Don’t Care.

CR10: REF Select. This bit selects the operating internal

referencefor the AD5381. CR10is programmed as follows:

CR10= 1: Internalreference is 2.5V (AD5381-5 default), the

recommendedoperating reference for AD5381-5.

CR4 to CR0: Toggle Function Enable. This function allows the

user to toggle the output between two codes loaded to the A

and B registers for each DAC.ControlRegister Bits CR4to CR0

are used to enable individual groups of eight channels for

operation in toggle mode. A Logic1written to any bit enables

CR10= 0: Internal reference is 1.25 V (AD5381-3default),

the recommendedoperating reference for AD5381-3.

CR9: Current Boost Control. This bit is used to boost the

current in the output amplifier, thereby altering its slew rate.

This bit is configured as follows:

a group of channels; a Logic 0 disables a group.

to toggle between the two registers.

is used

LDAC

CR9= 1: Boost Mode On. This maximizes the bias current

in the output amplifier, optimizing its slew rate but increasing

the power dissipation.

Table 16.

CR Bit

Group

Channels

32–39

24–31

16–23

8–15

CR4

CR3

CR2

4

3

2

1

0

CR9= 0: Boost Mode Off (default on power-up). This

reduces the bias current in the output amplifier and reduces

the overallpower consumption.

CR1

CR0

0–7

CR8: Internal/ExternalReference. This bit determines if the

DAC uses its internalreference or an externally applied

reference.

Channel Monitor Function

REG1 = REG0 = 0, A5 to A0 = 001010

CR8= 1: InternalReference Enabled. The reference output

depends on data loaded to CR10.

DB11–DB6= Contain data to address the monitoredchannel.

A channel monitor function is providedon the AD5381. This

feature, which consists of a multiplexeraddressed via the inter-

face, allows any channeloutput to be routed to the MON_OUT

pin for monitoring using an external ADC. In channel monitor

mode, VOUT39becomes the MON_OUT pin, to which all

monitored pins arerouted. The channel monitor function must

be enabled in the controlregisterbeforeany channels arerouted

to MON_OUT. On the AD5381, DB11 to DB6contain the

channel address forthe monitored channel. Selecting Channel

Address 63 three-states M ON _O UT.

CR8= 0: ExternalReference Selected(defaulton power-up).

CR7: Channel Monitor Enable(see Channel Monitor Function

section).

CR7= 1: Monitor Enabled. This enablesthe channel monitor

function. After a write to the monitor channel in the SFR

register, the selected channeloutput is routed to the

MON_OUT pin. VOUT39operates at the MON_OUT pin.

Rev. D | Page 23 of 40

AD5381

Data Sheet

Table 17. AD5381 Channel Monitor Decoding

REG1

0

•

REG0

0

•

A5

0

•

A4

0

•

A3

1

•

A2

0

•

A1

1

•

A0

0

•

DB11

0

1

•

DB10

0

1

0

•

DB9

0

1

0

1

0

•

DB8

0

1

0

1

0

1

0

1

0

1

•

DB8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

•

DB6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

•

DB5–DB0

MON_OUT

VOUT0

X

•

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

VOUT8

VOUT9

VOUT10

VOUT11

VOUT12

VOUT13

VOUT14

VOUT15

VOUT16

VOUT17

VOUT18

VOUT19

VOUT20

VOUT21

VOUT22

VOUT23

VOUT24

VOUT25

VOUT26

VOUT27

VOUT28

VOUT29

VOUT30

VOUT31

VOUT32

VOUT33

VOUT34

VOUT35

VOUT36

VOUT37

VOUT38

Undefined

•

0

1

0

1

0

1

0

1

X

Undefined

Three-State

REG1 REG0A5 A4 A3 A2 A1 A0

0

1

0

1

0

VOUT0

VOUT1

AD5381

CHANNEL

MONITOR

DECODING

VOUT39/MON_OUT

VOUT37

VOUT38

CHANNEL ADDRESS

DB11–DB6

Figure 28. Channel Monitor Decoding

Rev. D | Page 24 of 40

Data Sheet

AD5381

HARDWAREFUNCTIONS

RESET FUNCTION

FIFO OPERATION IN PARALLEL MODE

Bringing the

line low resets the contents of allinternal

The AD5381 contains a FIFO to optimize operation when

operating in parallelinterface mode. The FIFO Enable (level

sensitive, active high)is used to enable the internalFIFO. When

connected to DVDD, the internal FIFO is enabled, allowing the

user to write to the device at fullspeed. FIFO is only available in

parallel interface mode. The status of the FIFO EN pin is sam-

RESET

registers to their power-onreset state. Reset is a negative edge-

sensitive input. The default corresponds to m at full-scale and

to c at zero scale. The contents of the DACregistersarecleared,

setting VOUT0to VOUT39 to 0 V. This sequence takes 270 µs.

The falling edge of

RESET

low for the duration, returning high when

initiates the resetprocess;

goes

BUSY

is complete.

pled on power-up, and after a

or , to determine if

CLR RESET

RESET

is low, all interfaces are disabledand allLDAC

the FIFO is enabled. In either serialor I²C interface modes,

FIFO EN should be tied low. Up to 128successive instructions

can be written to the FIFO at maximum speedin parallel mode.

When the FIFO is full, any further writes to the device are

ignored. Figure 29 shows a comparison between FIFO mode

and non-FIFO mode in terms ofchannelupdate time. Figure 29

also outlines digital loading time.

While

BUSY

pulses are ignored.When

returns high, the part resumes

BUSY

normaloperation and the status of the

until the next falling edge is detected.

pin is ignored

RESET

ASYNCHRONOUS CLEAR FUNCTION

Bringing the

line low clears the contents of the DAC

CLR

25

registers to the data contained in the user configurable CLR

register and sets VOUT0to VOUT39 accordingly. This func-

tion can be used in system calibrationto load zero-scale and

full-scale to all channels. The execution time for a CLR is 35µs.

WITHOUT FIFO

20

(CHANNEL UPDATE TIME)

15

AND

FUNCTIONS

LDAC

BUSY

is a digital CMOS output thatindicates the status of the

BUSY

10

AD5381. The value of x2, the internaldata loaded to the DAC

data register, is calculated each time the user writes newdata to

the corresponding x1, c, or m registers. During the calculation

WITH FIFO

(CHANNEL UPDATE TIME)

5

WITH FIFO

(DIGITAL LOADING TIME)

of x2, the

output goeslow. While

is low, the user

BUSY

can continue writing new data to the x1, m, or c registers, but

no DAC outputupdatescan take place. The DACoutputsare

0

1

4

7

10 13 16 19 22 25 28 31 34 37 40

NUMBER OF WRITES

updated by taking the

input low. If

goes low while

LDAC

event is stored and the DACoutputs

Figure 29. Channel Update Rate (FIFO vs. NON-FIFO)

is active, the

BUSY

LDAC

BUSY

input permanently low, in which case the DAC

update immediatelyafter

goes high. The user may hold

POWER-ONRESET

the

LDAC

outputs update immediately after

The AD5381 contains a power-on reset generator and state

machine. The power-on reset resetsallregisters to a predefined

state and configures the analog outputsas high impedance.The

pin goes low during the power-on reset sequencing, pre-

venting data writes to the device.

goes high.

BUSY

also goes low during power-on reset and when a falling edge is

detected on the pin. During this time, allinterfaces are

BUSY

RESET

disabled and any eventson

BUSY

are ignored.

LDAC

The AD5381 contains an extra featurewhereby a DAC register

is not updated unless its x2register has been written to since

POWER-DOWN

The AD5381 contains a globalpower-down featurethat putsall

channels into a low power modeand reduces the analog power

consumption to 2 µA max and digital power consumption to

20 µA max. In power-down mode, the output amplifier can be

configured as a high impedance outputor can providea 100 kΩ

load to ground. The contents ofallinternalregisters are retained

in power-down mode. When exiting power-down,the settling

time of the amplifier willelapse beforethe outputs settleto their

correct values.

the last time

was brought low. Normally, when

LDAC

is brought low, the DAC registers arefilled with the contents

of the x2 registers. However, the AD5381 will only update the

DAC registerif the x2data has changed, thereby removing

unnecessary digitalcrosstalk.

Rev. D | Page 25 of 40

AD5381

Data Sheet

INTERFACES

The AD5381 contains both paralleland serialinterfaces.

Furthermore, the serialinterface can be programmed to be

either SPI-, DSP-, MICROWIRE-, or I²C-compatible. The

Figure 3and Figure 5 show timing diagrams for a serialwrite

to the AD5381 in standalone anddaisy-chain modes. The 24-bit

data-word format for the serialinterface is shown in Table 18.

SER/

PAR

pin selects paralleland serialinterface modes. In

/B This pin selects whether the data write is to the A or B

A

serial mode, the /I²C pin is used to select DSP-, SPI-,

SPI

register when toggle modeis enabled. With toggle disabled, this

bit should be set to 0to select the A data register.

MICROWIRE-, or I²C-interface mode.

The devices use an internalFIFO memoryto allow high speed

successive writes in parallelinterface mode. Theuser can con-

tinue writing new data to the device while write instructions are

R/ is the read or write controlbit.

W

A5 to A0 are used to address the inputchannels.

being executed. The

signalindicates the current statusof

BUSY

REG1 and REG0 select the registerto which data is written,

as shown in Table 10.

the device, going low while instructions in the FIFO are being

executed. In parallel mode,up to 128successive instructions

can be written to the FIFO at maximum speed. When the FIFO

is full, any further writes to the device areignored.

DB11 to .DB0 contain the input data-word.

X is a don’t care condition.

To minimize both the power consumption of the device and the

on-chip digital noise, the active interface only powersup fully

when the device is being written to, that is, on the falling edge

Standalone Mode

By connecting the DCEN (daisy-chain enable) pin low, stand-

alone mode is enabled. The serialinterface works with both a

continuous and a noncontinuous serial clock. The first falling

of

or the falling edge of

.

WR

SYNC

DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL

INTERFACES

The serialinterface can be operated with a minimum of three

wires in standalone mode orfour wiresin daisy-chain mode.

Daisy chaining allows many devices to be cascaded together to

edge of

starts the write cycle and resetsa counter that

SYNC

counts the number of serialclocks to ensure the correct number

of bits are shifted into the serialshift register. Any further edges

on

, except for a falling edge, are ignored until 24 bits are

SYNC

clocked in. Once 24 bits are shifted in, the SCLK is ignored. In

order for anotherserialtransfer to take place,the countermust

be reset by the falling edge of

increase system channel count. The SER/

pin must be tied

PAR

high and the /I²C pin (Pin 97) should be tied low to enable

SPI

.

SYNC

the DSP-/SPI-/MICROWIRE-compatible serial interface. In

serialinterface mode, the user doesnot need to drivethe paral-

lel input data pins. The serial interface’s control pins are

, DIN, SCLK—Standard 3-wire interface pins.

SYNC

DCEN—Selects standalone mode or daisy-chain mode.

SDO—Data out pin for Daisy-chain mode.

Table 18. 40-Channel, 12-bitDAC Serial InputRegister Configuration

MSB

LSB

X

A5

A4

A3

A2

A1

A0

REG1

REG0

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

X

A/B

R/W

Rev. D | Page 26 of 40

Data Sheet

AD5381

Daisy-Chain Mode

Readback Mode

Readbackmodeis invoked by settingthe R/ bit = 1 in the

For systemsthat contain severaldevices, theSDO pin can be

used to daisy-chain severaldevices together. This daisy-chain

mode can be useful in system diagnostics and in reducing the

number of serialinterfacelines.

W

serial input register write. With R/ = 1, Bits A5 to A0, in

W

association with Bits REG1 and REG0, select theregister tobe

read. The remainingdata bitsin the write sequence are don’t

cares. Duringthe next SPIwrite,the data appearing on the

SDO output willcontain thedata fromthe previously

addressedregister.

By connecting the DCEN (daisy-chain enable) pin high, daisy-

chain mode is enabled. Thefirst falling edge of

starts the

SYNC

write cycle. The SCLK is continuously applied to the input shift

register when is low. If more than 24 clock pulses are

SYNC

For a read of a single register, the NOPcommandcan be used

in clocking out the data from the selected register on SDO.

Figure 30 shows the readbacksequence. For example, to read

back the m register of Channel 0 on the AD5381, the following

sequence shouldbe implemented. First, write 0x404XXX to the

AD5381 input register. This configures the AD5381 for read

mode with the m register of Channel 0selected. Notethat Data

Bits DB11 to DB0are don’t cares. Follow this with a second

write, a NOPcondition, 0x000000.

applied, the data ripplesout of the shift register and appears

on the SDO line. This data is clocked out on the rising edge of

SCLK and is valid on the falling edge. By connecting the SDO

of the first device to the DIN input on the next device in the

chain, a multidevice interface is constructed. Twenty-four clock

pulses are requiredfor each device in the system.Therefore, the

totalnumber of clockcycles must equal24N, where N is the

totalnumber of AD538x devices in the chain.

When the serialtransferto alldevices is complete,

is

During this write, the data from the m registeris clocked out on

the DOUT line, that is, data clocked out will contain the data

from the m register in Bit DB11 to Bit DB0, and the top 10bits

contain the address information as previously written. In

SYNC

taken high. This latches the input data in each device in the

daisy-chain and prevents further datafrombeing clocked

into the input shift register.

readbackmode,the

signalmust frame the data. Data is

SYNC

If

is taken high before 24 clocks are clocked into the part,

SYNC

clocked out on the rising edge of SCLK and is valid on the

falling edge of the SCLK signal. If the SCLK idles high between

the write and read operationsof a readbackoperation, the first

this is considered a bad frameand the data is discarded.

The serial clock can be either a continuous or a gated clock. A

continuous SCLK sourcecan only be used if it can be arranged

bit of data is clocked out on the falling edge of

.

SYNC

that

is held low for the correct number of clock cycles. In

SYNC

gated clock mode, a burst clock containing the exact number of

clock cycles must be used and

must betaken high after

SYNC

the final clock to latch the data.

SCLK

SYNC

24

48

DB23

DB0

DB23

DB0

DIN

INPUT WORD SPECIFIES REGISTER TO BE READ

NOP CONDITION

DB23

DB0

DB23

DB0

SDO

UNDEFINED

SELECTED REGISTER DATA CLOCKED OUT

Figure 30. Serial Readback Operation

Rev. D | Page 27 of 40

AD5381

Data Sheet

I²C SERIAL INTERFACE

The AD5381 features an I²C-compatible 2-wire interface

consisting of a serialdata line (SDA)and a serial clock line

(SCL). SDA and SCL facilitate communication between the

AD5381 and the master at ratesup to 400 kHz. Figure 6 shows

the 2-wire interface timing diagrams that incorporate three

different modes of operation. In selecting the I²C operating

AD5381 Slave Addresses

A bus masterinitiates communication with a slave device by

issuing a START condition followed by the 7-bit slave address.

When idle, the AD5381 waits for a START condition followed

by its slave address. TheLSB of the addresswordis the Read/

Write (R/ ) bit. The AD5381 is a receive only device; when

W

mode, first configure serialoperating mode (SER/

= 1)

communicating with the AD5381, R/ = 0. After receiving the

W

proper address 1010 1(AD1)(AD0), the AD5381 issues an ACK

by pulling SDA low for one clock cycle.

PAR

and then select I²C mode by configuring the /I²C pin to a

SPI

Logic 1. The device is connected to the I²C bus as a slave device

(that is, no clock is generated by the AD5381). The AD5381 has

a 7-bit slave address 1010 1(AD1)(AD0). The 5MSB are hard-

coded and the 2 LSB are determinedby the stateof the AD1

and AD0 pins. The facility to hardware configure AD1and AD0

allows four of these devices to be configured on the bus.

The AD5381 has four different user programmable addresses

determined by the AD1and AD0bits.

Write Operation

There are threespecificmodes in which data can be written to

the AD5381 DAC.

I²C Data Transfer

One data bit is transferred during each SCL clock cycle. The

data on SDA must remain stable during the high period of the

SCL clock pulse. Changesin SDA while SCL is high are control

signals that configure START and STOP conditions. Both SDA

and SCL are pulled high by the externalpull-up resistors when

the I²C bus is not busy.

4-Byte Mode

When writing to the AD5381 DACs, the user must begin

with an address byte(R/ = 0) after which the DAC acknowl-

W

edges that it is prepared to receive databy pulling SDA low.

The address byteis followed by the pointer byte; this addresses

the specific channel in the DAC to be addressed andis also

acknowledged by the DAC. Twobytesof data are then written

to the DAC, as shown in Figure 31. A STOPcondition follows.

This allows the user to update a single channelwithin the

AD5381 at any time and requires fourbytes of datato be

transferred fromthe master.

START and STOP Conditions

A master device initiates communication by issuing a START

condition. A START condition is a high-to-low transition on

SDA with SCL high. A STOP condition is a low-to-high

transition on SDA while SCL is high. A START condition

from the mastersignals the beginning of a transmission to

the AD5381. The STOPcondition frees the bus. If a repeated

START condition (Sr) is generatedinsteadof a STOP condition,

the bus remains active.

3-Byte Mode

In 3-byte mode,the user can update morethan one channel in a

write sequence without having to write the device addressbyte

each time. The device address byte is only required once;sub-

sequent channelupdates requirethe pointer byteand the data

bytes. In 3-byte mode, the userbegins with an address byte

Repeated START Conditions

A repeated START (Sr)condition may indicate a change of data

direction on the bus. Sr can be used when the bus masteris

writing to several I²C devices and wants to maintain controlof

the bus.

(R/ = 0), after which the DAC willacknowledge that it is pre-

W

pared to receive databy pulling SDA low. The addressbyteis

followed by the pointer byte. This addresses thespecificchannel

in the DAC to be addressed and is also acknowledged by the

DAC. This is then followed by the two databytes. REG1and

REG0 determine the register to be updated.

Acknowledge Bit (ACK)

The acknowledge bit (ACK)is the ninth bit attached to any

8-bit data-word. ACKis always generatedby the receiving

device. The AD5381 devices generatean ACK whenreceiving

an address or data by pulling SDA low during the ninth clock

period. Monitoring ACK allowsfor detection of unsuccess-

ful data transfers. An unsuccessfuldata transfer occurs if a

receiving device is busy or if a system fault has occurred.

In the event of an unsuccessful data transfer, the busmaster

should reattempt communication.

If a STOPcondition doesnot follow thedatabytes, another

channel can be updated by sending a newpointerbyte followed

by the data bytes. Thismode only requires threebytes tobe

sent to updateany channel oncethe device hasbeen initially

addressed, andreduces the software overhead in updating the

AD5381 channels.A STOP condition atany time exitsthis mode.

Figure 32 showsa typical configuration.

Rev. D | Page 28 of 40

Data Sheet

AD5381

SCL

1

0

1

0

1

AD1

AD0

R/W

0

A5

A4

A3

A2

A1

A0

SDA

START COND

BY MASTER

ACK BY

AD538x

MSB

ACK BY

AD538x

ADDRESS BYTE

POINTER BYTE

SCL

SDA

REG1 REG0

MSB

LSB

MSB

LSB

ACK BY

AD538x

ACK BY

AD538x

STOP

COND

BY

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

MASTER

Figure 31. 4-Byte AD5381, I²C Write Operation

SCL

SDA

1

0

1

0

1

AD1

AD0

R/W

0

A5

A4

A3

A2

A1

A0

START COND

BY MASTER

ACK BY

AD538x

MSB

ACK BY

AD538x

ADDRESS BYTE

POINTER BYTE FOR CHANNEL "N"

SCL

SDA

REG1 REG0

MSB

LSB

MSB

LSB

ACK BY

AD538x

ACK BY

AD538x

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

DATA FOR CHANNEL "N"

SCL

SDA

0

A5

A4

A3

A2

A1

A0

MSB

ACK BY

AD538x

POINTER BYTE FOR CHANNEL "NEXT CHANNEL"

SCL

SDA

REG1 REG0

MSB

LSB

MSB

LSB

ACK BY

AD538x

ACK BY STOP COND

AD538x BY MASTER

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

DATA FOR CHANNEL "NEXT CHANNEL"

Figure 32. 3-Byte AD5381, I²C Write Operation

Rev. D | Page 29 of 40

AD5381

Data Sheet

2-Byte Mode

PARALLEL INTERFACE

Following initialization of 2-byte mode, the usercan update

channels sequentially. The device address byte is only required

once and the pointer address pointeris configured for auto-

increment or burst mode.

The SER/

PAR

pin must be tied low to enable the parallel

interface and disable the serialinterfaces.Figure 7shows the

timing diagram for a parallelwrite. The parallelinterface is

controlled by the following pins.

The user must begin with an addressbyte(R/ = 0), after

W

CS

Active low device select pin.

which the DAC acknowledges that it is preparedto receive

data by pulling SDA low. The addressbyteis followed by a

specific pointer byte (0xFF)that initiates the burst mode of

operation. The address pointer initializes to Channel 0, the data

following the pointer is loaded to Channel 0, and the address

pointer automatically incrementsto the next address.

WR

On the rising edge of

to Pin A0 are latched; data present on the data bus is loaded into

the selected input registers.

, with low, the addresseson Pin A5

WR CS

REG0, REG1 Pins

The REG0 and REG1 bits in the data byte determinewhich

register will be updated. In this mode, following the initializa-

tion, only the two data bytes are required to updatea channel.

The channeladdressautomatically increments fromAddress 0

to Channel 39 and then returns to the normal 3-byte mode of

operation. This modeallows transmission of datato all

channels in one block and reduces the software overhead in

configuring all channels. A STOP condition at any time exits

this mode. Toggle mode is not supported in 2-byte mode.

Figure 33 shows a typical configuration.

The REG0 and REG1 pins determine the destination registerof

the data being written to the AD5381. See Table 10.

Pin A5 to Pin A0

Each of the 40 DAC channels can be individually addressed.

Pin DB11 to Pin DB0

The AD5381 accepts a straight 12-bit parallel word on DB11 to

DB0, where DB11 is the MSB and DB0is the LSB.

SCL

SDA

1

0

1

0

1

AD1

AD0

R/W

A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1

START COND

BY MASTER

ACK BY

CONVERTER

MSB

ACK BY

CONVERTER

ADDRESS BYTE

POINTER BYTE

SCL

SDA

REG1 REG0 MSB

LSB

MSB

LSB

ACK BY

AD538x

ACK BY

AD538x

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

CHANNEL 0 DATA

SCL

SDA

REG1 REG0 MSB

LSB

MSB

LSB

ACK BY

CONVERTER

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

CHANNEL 1 DATA

SCL

SDA

REG1 REG0 MSB

LSB

MSB

LSB

ACK BY

STOP

CONVERTER

CONVERTER COND

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

BY

MASTER

CHANNEL N DATA FOLLOWED BY STOP

Figure 33. 2-Byte, 1²C Write Operation

Rev. D | Page 30 of 40

Data Sheet

AD5381

MICROPROCESSOR INTERFACING

Parallel Interface

When data is being transmitted to the AD5381, the

line

SYNC

The AD5381 can be interfaced to a variety of 16-bit microcon-

trollers or DSPprocessors. Figure 35 shows the AD5381 family

interfaced to a generic16-bit microcontroller/DSPprocessor.

The lower address lines fromthe processor areconnected to A0

to A5 on the AD5381. The upper address lines aredecoded to

is taken low (PC7). Data appearing on the MOSIoutput is valid

on the falling edge of SCK. Serialdata from the MC68HC11 is

transmitted in 8-bit bytes with only eight falling clock edges

occurring in the transmit cycle.

DVDD

MC68HC11

AD5381

provide a

,

signal for the AD5381. The fast interface

CS LDAC

SER/PAR

RESET

timing of the AD5381 allows direct interface to a wide variety

of microcontrollersand DSPs, as shown in Figure 35.

MISO

MOSI

SCK

PC7

SDO

DIN

AD5381 to MC68HC11

SCLK

SYNC

The serialperipheralinterface (SPI)on the MC68HC11is

configured for master mode (MSTR = 1), clock polarity bit

(CPOL) = 0, and the clock phase bit (CPHA)= 1. The SPI is

configured by writing to the SPI controlregister (SPCR)—see

the MC68HC11 user manual. SCK of the MC68HC11 drives the

SCLK of the AD5381, the MOSIoutput drivesthe serialdata

line (D_IN) of the AD5381, and the MISO input is driven from

D_OUT. The SYNC signal is derived from a port line (PC7).

2

SPI/I C

Figure 34. AD5381-to-MC68HC11 Interface

µCONTROLLER/

DSP PROCESSOR

AD5381

1

D15

REG1

REG0

D11

DATA

BUS

D0

CS

UPPER BITS OF

ADDRESS BUS

ADDRESS

DECODE

LDAC

A5

A4

A5

A4

A3

A2

A1

A0

WR

A3

A2

A1

A0

R/W

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 35. AD5381-to-Parallel Interface

Rev. D | Page 31 of 40

AD5381

Data Sheet

DVDD

8XC51

AD5381 to PIC16C6x/7x

AD5381

SER/PAR

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the ClockPolarity Bit = 0. This is done

by writing to the synchronousserial port control register

(SSPCON). See the PIC16/17 microcontroller user manual.

RESET

RxD

SDO

DIN

TxD

P1.1

SCLK

SYNC

In this example I/O, Port RA1is being used to pulse

SYNC

2

and enable the serialport of the AD5381. This microcontroller

transfers only eight bits of dataduring each serialtransfer

operation; therefore,threeconsecutiveread/write operations

may be needed depending on the mode. Figure 36 showsthe

connection diagram.

SPI/I C

Figure 37. AD5381-to-8051 Interface

AD5381 to ADSP-2101/ADSP-2103

Figure 38 shows a serialinterface between the AD5381 and the

ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should

be set up to operate in SPORT transmit alternateframing mode.

The ADSP-2101/ADSP-2103 SPORT is programmedthrough

the SPORT controlregisterand configuredas follows: internal

clock operation, active low framing, and 16-bit word length.

Transmission is initiated by writing a word to the Tx register

after the SPORT has been enabled.

DVDD

PIC16C6X/7X

AD5381

SER/PAR

RESET

SDI/RC4

SDO/RC5

SCK/RC3

RA1

SDO

DIN

SCLK

SYNC

2

SPI/I C

Figure 36. AD5381-to-PIC16C6x/7x Interface

DVDD

ADSP-2101/

AD5381

ADSP-2103

SER/PAR

AD5381 to 8051

RESET

The AD5381 requires a clocksynchronized to the serialdata.

The 8051 serialinterface must thereforebe operated in Mode 0.

In this mode, serialdata enters and exits through RxD, and a

shift clock is output on TxD. Figure 37 shows howthe 8051 is

connected to the AD5381. Because the AD5381 shifts data out

on the rising edge of the shift clock and latches data in on the

falling edge, the shift clock must be inverted.The AD5381

requires its data to be MSBfirst. Since the 8051outputs the

LSB first, the transmit routine must take this into account.

DR

DT

SDO

DIN

SCK

TFS

RFS

SCLK

SYNC

2

SPI/I C

Figure 38. AD5381-to-ADSP-2101/ADSP-2103 Interface

Rev. D | Page 32 of 40

Data Sheet

AD5381

APPLICATION INFORMATION

externally from eitheran ADR421 or ADR431 2.5 V reference.

Suitable externalreferences for the AD5381-3include the

ADR280 1.2 V reference. The reference should be decoupledat

the REFOUT/REFIN pin of the device with a 0.1 µF capacitor.

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful considera-

tion of the power supply and ground return layout helps to

ensure the ratedperformance. The printed circuit board on

which the AD5381 is mounted should be designed so that the

analog and digitalsections are separatedand confined to

certain areas of the board. If the AD5381 is in a system where

multiple devices requirean AGND-to-DGND connection, the

connection should be made at onepoint only, a star ground

point established as close to the device as possible.

AVDD

0.1µF

DVDD

10µF

0.1µF

ADR431/

ADR421

AVDD

DVDD

VOUT0

REFOUT/REFIN

For supplies with multiple pins (AVDD, DVDD), these pins

should be tied together. TheAD5381 should haveample supply

bypassing of 10 µF in parallel with 0.1 µF on each supply,

located as close to the package as possibleand ideally right

up against the device. The 10µF capacitors are the tantalum

bead type. The 0.1 µF capacitor should havelow effective series

resistance (ESR) and effective series inductance (ESI), like the

common ceramictypes that providea low impedance path to

ground at high frequencies, to handletransient currents dueto

internal logic switching.

0.1µF

AD5381-5

REFGND

VOUT39

DGND

DAC_GND SIGNAL_GND AGND

Figure 39. Typical Configuration with External Reference

Figure 40 shows a typical configuration when using the internal

reference. On power-up, the AD5381 defaults to an external

reference; therefore, the internalreference needs to be config-

ured and turned on via a write to the AD5381 controlregister.

ControlRegister Bit CR10 allows the user to choosethe

referencevalue; Bit CR8is used to select the internalreference.

It is recommended to use the 2.5 V reference when AVDD =

5 V, and the 1.25 V reference when AVDD= 3V.

The power supplylines of the AD5381 should use as largea

trace as possible to providelow impedance paths and reduce

the effects of glitches on the power supply line. Fast switching

signals such as clocks should be shielded with digitalground

to avoid radiating noise to other partsof the board, andshould

never be run near the reference inputs.A ground line routed

between the D_INand SCLK lines will help reduce crosstalk

between them(this is not required on a multilayerboard

because therewillbe a separate ground plane, butseparat-

ing the lines will help). It is essential to minimize noise on

the REFOUT/REFIN line.

AVDD

0.1µF

DVDD

10µF

0.1µF

Avoid crossover of digitaland analog signals. Traceson

opposite sides of the board should run at right angles to

each other. This reduces the effects of feedthrough through

the board. A micro-strip technique is by far the best, but is

not always possible with a double-sided board. In this tech-

nique, the component side of the boardis dedicated to the

ground plane while signaltraces are placed on the solder side.

AVDD

DVDD

VOUT0

REFOUT/REFIN

0.1µF

AD5381

REFGND

VOUT39

DGND

DAC_GND SIGNAL_GND AGND

TYPICAL CONFIGURATION CIRCUIT

Figure 39 shows a typicalconfiguration for the AD5381-5

when configured for use with an externalreference. In the

circuit shown, all AGND, SIGNAL_GND, and DAC_GND pins

are tied together to a common AGND. AGNDand DGNDare

connected togetherat the AD5381 device. On power-up, the

AD5381 defaults to externalreference operation. All AVDD

lines are connected together and driven from the same5V

source. It is recommended to decoupleclose to the device

with a 0.1 µF ceramicand a 10 µF tantalum capacitor. In this

application, the referencefor the AD5381-5 is provided

Figure 40. Typical Configuration with Internal Reference

Digital connections have been omitted forclarity. The AD5381

contains an internal power-on reset circuit with a 10 ms brown-

out time. If the power supply ramp rate exceeds10ms, the user

should reset the AD5381 as part of the initialization process to

ensure the calibration datais loaded correctly into the device.

Rev. D | Page 33 of 40

AD5381

Data Sheet

Note that B registers can only be loadedwhen toggle mode is

enabled. The sequence of events whenconfiguring the AD5381

for toggle mode is

MONITOR FUNCTION

The AD5381 channel monitor function consists of a multiplexer

addressedvia the interface, allowing any channel output to be

routed to this pin for monitoring using an external ADC. In

channel monitor mode, VOUT39 becomes the MON_OUTpin,

to which all monitoredsignals are routed. The channel monitor

function must be enabled in the control register before any

channels are routed to MON_OUT. Table 17 contains the

decoding information required to route anychannel to

MON_OUT.Selecting Channel Address 63 three-states

MON_OUT.Figure 41 shows a typical monitoring circuit

implemented using a 12-bit SAR ADC in a 6-lead SOT-23

package. The controller output port selects the channelto be

monitored, and the input port readsthe converteddata from

the ADC.

1. Enable toggle mode for the required channels via the

controlregister.

2. Load data to the A registers.

3. Load data to the B registers.

4. Apply

.

LDAC

is used to switch between the A and B registers in

LDAC

determining the analog output. Thefirst

configuresthe

LDAC

output to reflect data in the A registers. This modeofferssignif-

icant advantages if the user wants to generatea square waveat

the output of all 40 channels, as might be required to drive a

liquid crystal-based variableopticalattenuator.

In this case, the user writes to the controlregister and enables

the toggle function by setting CR4to CR2= 0, thus enabling the

five groups of eight for toggle modeoperation. The user must

LDAC

the output values to reflect the data in the A and B registers.

AVDD

then load data to all40 A and B registers. Toggling

sets

DIN

VOUT0

SYNC

SCLK

OUTPUT PORT

The frequency of the

square waveoutput.

determines the frequency of the

LDAC

VDD

CS

AD5381

AD7476

VOUT39/MON_OUT

VIN

SCLK

INPUT PORT

Toggle mode is disabled via the controlregister. The first

LDAC

SDATA

following the disabling of the toggle mode will update the out-

puts with the data contained in the A registers.

GND

CONTROLLER

AGND

VOUT38

THERMAL MONITOR FUNCTION

DAC_GND SIGNAL_GND

The AD5381contains a temperature shutdown function to

protect the chip if multiple outputs areshorted. The short-

circuit current of each output amplifier is typically 40 mA.

Operating the AD5381 at 5 V leads to a power dissipation of

200 mW per shorted amplifier. Withfive channels shorted, this

leads to an extra watt of powerdissipation. Forthe 100-lead

LQFP, the θ_JAis typically 44°C/W.

Figure 41. Typical Channel Monitoring Circuit

TOGGLE MODE FUNCTION

The toggle mode function allows an output signalto be gener-

ated using the

controlsignalthat switches between two

LDAC

DAC data registers. This function is configured using the SFR

controlregister as follows. A write with REG1 = REG0 = 0 and

A5 to A0 = 001100 specifies a control register write. The toggle

mode function is enabled in groups of eight channels using Bit

CR4to Bit CR0in the controlregister. See the AD5381 control

register description. Figure 42 shows a blockdiagram of toggle

mode implementation. Each of the 40DAC channels on the

AD5381 contain an A and B data register.

The thermalmonitoris enabledby the user via CR6in the

controlregister. The outputamplifiers on the AD5381 are

automatically powered down if the die temperatureexceeds

approximately 130°C. After a thermalshutdown hasoccurred,

the user can re-enable the part by executing a soft power-up if

the temperature has droppedbelow130°C or by turning off the

thermalmonitorfunction via the controlregister.

Rev. D | Page 34 of 40

Data Sheet

AD5381

DATA

REGISTER

A

DAC

REGISTER

VOUT

12-BIT DAC

DATA

REGISTER

B

INPUT

DATA REGISTER

INPUT

LDAC

CONTROL INPUT

A/B

Figure 42. Toggle Mode Function

UTILIZING FIFO

OPTICAL ATTENUATORS

The AD5381FIFO mode optimizes totalsystemupdate rates

in applications where a largenumber of channels needto be

updated. FIFO modeis only available when parallelinterface

mode is selected. The FIFO EN pin is used to enable the FIFO.

The status of FIFO EN is sampled during the initialization

sequence. Therefore,the FIFO statuscan only be changed by

resetting the device.

Based on its high channel count, high resolution, monotonic

behavior, and high levelof integration,the AD5381 is ideally

targeted at opticalattenuation applications used in dynamic

gain equalizers, variable opticalattenuators (VOAs), and optical

add-drop multiplexers(OADMs). In these applications, each

wavelength is individually extracted using an arrayed wave

guide; its power is monitoredusing a photodiode, transimped-

ance amplifier and ADC in a closed-loop controlsystem. The

AD5381 controls the opticalattenuator for each wavelength,

ensuring that the power is equalized in allwavelengthsbefore

being multiplexed ontothe fiber. This preventsinformation loss

and saturation fromoccurring at amplification stages further

along the fiber.

In a telescope that provides for the cancel-lation of atmospheric

distortion, for example, a large numberof channels need to be

updated in a short period of time. In such systems, as manyas

400 channels need to be updated within 40 µs. Four-hundred

channels require the useof 10 AD5381s. With FIFO mode

enabled, the data writecycle time is 40 ns; therefore, each group

consisting of 40 channels can be fully loaded in 1.6 µs. In FIFO

mode, a completegroupof 40chan-nels will update in 14.4 µs.

The time taken to update all 400 channels is

14.4 µs + 9 × 1.6 µs = 28.8 µs.

Figure 44 shows the FIFO operation scheme.

ADD

DROP

PORTS

OPTICAL

SWITCH

PHOTODIODES

11

12

ATTENUATOR

DWDM

IN

DWDM

OUT

ATTENUATOR

FIBRE

AWG FIBRE

AWG

1n–1

1n

ATTENUATOR

TIA/LOG AMP

(AD8304/AD8305)

ADG731

(40:1 MUX)

N:1 MULTIPLEXER

AD5381,

40-CHANNEL,

12-BIT DAC

AD7671

(0V TO 5V, 1MSPS)

CONTROLLER

16-BIT ADC

Figure 43. OADM Using the AD5381 as Part of an Optical Attenuator

Rev. D | Page 35 of 40

AD5381

Data Sheet

GROUP A

CHNLS 0–39 CHNLS 40–79

GROUP B

GROUP C

CHNLS

GROUP D

CHNLS

GROUP E

CHNLS

GROUP F

CHNLS

GROUP G

CHNLS

GROUP H

CHNLS

GROUP I

CHNLS

GROUP J

CHNLS

80–119

120–159

160–199

200–239

240–279

280–319

320–359

360–399

FIFO DATA LOAD

GROUP A

FIFO DATA LOAD

GROUP B

FIFO DATA LOAD

GROUP J

1.6µs

OUTPUT UPDATE

TIME FOR GROUP A

OUTPUT UPDATE

TIME FOR GROUP J

14.4µs

OUTPUT UPDATE

TIME FOR GROUP B

14.4µs

TIME TO UPDATE 400 CHANNELS = 28.8µs

Figure 44. Using FIFO Mode 400 Channels Updated in Under 30 µs

Rev. D | Page 36 of 40

Data Sheet

AD5381

OUTLINEDIMENSIONS

16.20

16.00 SQ

15.80

1.60 MAX

0.75

0.60

0.45

100

1

76

75

PIN 1

14.20

14.00 SQ

13.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

0.08

COPLANARITY

25

51

50

0.15

0.05

26

SEATING

PLANE

0.27

0.22

0.17

VIEW A

0.50

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BED

Figure 45. 100-Lead Low Profile Quad Flat Package [LQFP]

(ST-100-1)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Range

Output

Channels

Linearity

Error (LSB)

Package

Description

Package

Option

Model¹

Resolution

AVDD Range

AD5381BSTZ-3

AD5381BSTZ-3-REEL

AD5381BSTZ-5

AD5381BSTZ-5-REEL

EVAL-AD5380EBZ

12 Bits

–40°C to +85°C

2.7 V to 3.6 V

4.5 V to 5.5 V

40

1

100-Lead LQFP

Evaluation Kit

ST-100-1

¹Z = RoHS Compliant Part.

Rev. D | Page 37 of 40

AD5381

NOTES

Data Sheet

Rev. D | Page 38 of 40

Data Sheet

NOTES

AD5381

Rev. D | Page 39 of 40

AD5381

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D03732-0-9/12(D)

Rev. D | Page 40 of 40


型号：	AD5392BSTZ-5
厂家：	ADI
描述：	40-Channel, 3 V/5 V, Single-Supply 12-Bit, denseDAC 40通道， 3 V / 5 V单电源，12位， denseDAC
文件：	总40页 (文件大小：1170K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5392BSTZ-5 [ADI]

相关型号：

AD5392_15

AD5398

AD5398A

AD5398A-WAFER

AD5398ABCBZ-REEL

AD5398ABCBZ-REEL7

AD5398ABCPZ-U2

AD5398BCBZ-REEL7

AD5398BCPZ-REEL

AD5398BCPZ-REEL7

AD5398BCPZ-WP

AD5398ZCSURF