AD5398ABCPZ-U2 [ADI]
120 mA, Current Sinking, 10-Bit, I<sup>2</sup>C DAC;
| 型号： | AD5398ABCPZ-U2 |
| 厂家： | 
ADI |
| 描述： | 120 mA, Current Sinking, 10-Bit, I<sup>2</sup>C DAC 转换器 |
| 文件： | 总17页 (文件大小：600K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
120 mA, Current Sinking,
10-Bit, I2C DAC
AD5398A
Industrial
FEATURES
Heater control
Fan control
Current sink: 120 mA
2-wire, (I2C-compatible) 1.8 V serial interface
10-bit resolution
Integrated current sense resistor
Power supply: 2.7 V to 5.5 V
Guaranteed monotonic over all codes
Power down to: 0.5 μA typical
Internal reference
Cooler (Peltier) control
Solenoid control
Valve control
Linear actuator control
Light control
Current loop control
Ultralow noise preamplifier
Power-down function
Power-on reset
GENERAL DESCRIPTION
The AD5398A is a single, 10-bit digital-to-analog converter
(DAC) with a current sink output capability of 120 mA. This
device features an internal reference and operates from a
single 2.7 V to 5.5 V supply. The DAC is controlled via a
2-wire (1.8 V, I2C®-compatible) serial interface that operates
at clock rates up to 400 kHz.
Available in 3 × 3 array WLCSP package
APPLICATIONS
Consumer
Lens autofocus
Image stabilization
Optical zoom
Shutters
Iris/exposure
Neutral density (ND) filters
Lens covers
The AD5398A incorporates a power-on reset circuit, which
ensures the DAC output powers up to 0 V and remains there
until a valid write takes place. It has a power-down feature
that reduces the current consumption of the device to 0.5 μA
typically.
Camera phones
The AD5398A is designed for autofocus, image stabilization,
and optical zoom applications in camera phones, digital still
cameras, and camcorders. The AD5398A is also suitable for
many industrial applications, such as controlling temperature,
light, and movement without derating, over temperatures
ranging from −30°C to +85°C. The I2C address range for the
AD5398A is 0x18 to 0x1F inclusive.
Digital still cameras
Camera modules
Digital video cameras/camcorders
Camera-enabled devices
Security cameras
Web/PC cameras
FUNCTIONAL BLOCK DIAGRAM
V
DD
POWER-ON
RESET
REFERENCE
AD5398A
V
DD
D1
SDA
SCL
10-BIT
2
I C SERIAL
I
CURRENT
SINK
INTERFACE
OUTPUT DAC
R
SENSE
3.3Ω
R
PD
DGND
DGND
AGND
Figure 1.
Rev. 0
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Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
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AD5398A
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
Terminology.......................................................................................9
Theory of Operation ...................................................................... 10
Serial Interface............................................................................ 10
I2C Bus Operation ...................................................................... 10
Data Format ................................................................................ 11
Power Supply Bypassing and Grounding................................ 12
Applications Information.............................................................. 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Consumer Applications ................................................................... 1
Industrial Applications .................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Specifications.......................................................................... 4
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD5398A
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance (RL) = 25 Ω connected to VDD; all specifications TMIN to TMAX
,
unless otherwise noted.
Table 1.
B Version1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC PERFORMANCE
VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V
with reduced performance
Resolution
10
1.5
Bits
LSB
LSB
mA
mA
117 μA/LSB
Relative Accuracy2
Differential Nonlinearity2, 3
Zero Code Error2, 4
Offset Error @ Code 162
Gain Error2
4
1
Guaranteed monotonic over all codes
All 0s loaded to DAC
0
0.5
0.5
1
0.6
0.5
% of FSR at 25°C
μA/°C
LSB/°C
Offset Error Drift2, 4, 5
Gain Error Drift2, 5
10
0.2
OUTPUT CHARACTERISTICS
Minimum Sink Current4
Maximum Sink Current
3
120
mA
mA
VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V;
specified maximum sink current may not be achieved
PD = 1
Output voltage range over which maximum 120 mA
sink current is available
Output voltage range over which 90 mA sink current
is available
Output Current During PD5
Output Compliance5
80
nA
V
0.6
VDD
VDD
Output Compliance5
0.48
V
Power-Up Time5
20
μs
To 10% of FS, coming out of power-down mode; VDD = 5 V
LOGIC INPUT (PD)5
Input Current
1
0.54
μA
V
V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
VDD = 2.7 V to 5.5 V
VDD = 2.7 V to 5.5 V
1.26
3
pF
LOGIC INPUTS (SCL, SDA)5
Input Low Voltage, VINL
Input High Voltage, VINH
Input Low Voltage, VINL
Input High Voltage, VINH
Input Leakage Current, IIN
Input Hysteresis, VHYST
Digital Input Capacitance, CIN
Glitch Rejection6
−0.3
1.26
−0.3
1.4
+0.54
VDD + 0.3
+0.54
VDD + 0.3
1
V
V
V
V
μA
V
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.6 V to 5.5 V
VIN = 0 V to VDD
0.05 VDD
6
pF
ns
50
Pulse width of spike suppressed
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
2.7
5.5
1
V
mA
0.5
0.5
IDD specification is valid for all DAC codes;
VIH = VDD, VIL = GND, VDD = 5.5 V
VIH = VDD, VIL = GND, VDD = 3 V
IDD (Power-Down Mode)7
μA
1 Temperature range for the B version is −30°C to +85°C.
2 See the Terminology section.
3 Linearity is tested using a reduced code range: Code 32 to Code 1023.
4 To achieve near zero output current, use the power-down feature.
5 Guaranteed by design and characterization; not production tested. PD is active high. SDA and SCL pull-up resistors are tied to 1.8 V.
6 Input filtering on both the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.
7 PD is active high. When PD is taken high, the AD5389A enters power-down mode.
Rev. 0 | Page 3 of 16
AD5398A
AC SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, RL = 25 Ω connected to VDD, unless otherwise noted.
Table 2.
B Version1, 2
Parameter
Min Typ
Max Unit
Test Conditions/Comments
Output Current Settling Time
250
μs
VDD = 5 V, RL = 25 Ω, LL = 680 μH
¼ scale to ¾ scale change (0x100 to 0x300)
Slew Rate
0.3
mA/μs
Major Code Change Glitch Impulse
Digital Feedthrough3
0.15
0.06
nA-sec
nA-sec
1 LSB change around major carry
1 Temperature range for the B version is –30°C to +85°C.
2 Guaranteed by design and characterization; not production tested.
3 See the Terminology section.
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Version
Parameter1
Unit
Description
Limit at TMIN, TMAX
fSCL
t1
t2
t3
t4
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns max
ns min
pF max
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD, STA, start/repeated start condition hold time
tSU, DAT, data setup time
tHD, DAT, data hold time
t5
t6
2
t7
t8
t9
t10
tSU, STA, setup time for repeated start
tSU, STO, stop condition setup time
tBUF, bus free time between a stop condition and a start condition
tR, rise time of both SCL and SDA when receiving
Can be CMOS driven
t11
250
300
20 + 0.1 Cb
tF, fall time of SDA when receiving
tF, fall time of both SCL and SDA when transmitting
3
Cb
400
Capacitive load for each bus line
1 Guaranteed by design and characterization; not production tested.
2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) to bridge the undefined region of the SCL
falling edge.
3 Cb is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD
.
Timing Diagram
SDA
t3
t4
t9
t10
t11
SCL
t2
t7
t1
t8
t4
t6
t5
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. 0 | Page 4 of 16
AD5398A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
Table 4.
Parameter
Rating
VDD to AGND
−0.3 V to +7 V
VDD to DGND
AGND to DGND
−0.3 V to VDD + 0.3 V
−0.3 V to +0.3 V
SCL, SDA to DGND
PD to DGND
ISINK to AGND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
ESD CAUTION
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature (TJ max)
θJA Thermal Impedance2
Mounted on 2-Layer Board
Mounted on 4-Layer Board
Lead Temperature, Soldering
Maximum Peak Reflow Temperature3
−40°C to +85°C
−65°C to +150°C
150°C
84°C/W
48°C/W
260°C ( 5°C)
1 Transient currents of up to 100 mA do not cause SCR latch-up.
2 To achieve the optimum θJA, it is recommended that the AD5398A be
soldered onto a 4-layer board.
3 As per Jedec J-STD-020C.
Rev. 0 | Page 5 of 16
AD5398A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
3
2
1
A
B
C
VIEW FROM BALL SIDE
Figure 3. 9-Ball WLCSP Pin Configuration
Table 5. 9-Ball WLCSP Pin Function Description
Pin Number
Mnemonic
Description
A1
A2
A3
B1
B2
B3
C1
C2
C3
ISINK
NC
PD
AGND
DGND
SDA
DGND
VDD
Output Current Sink.
No Connection.
Power-Down. Asynchronous power-down signal.
Analog Ground Pin.
Digital Ground Pin.
I2C Interface Signal.
Digital Ground Pin.
Digital Supply Voltage.
I2C Interface Signal.
SCL
1400µm
PD
1
I
SINK
8
AGND
7
DGND
2
1690µm
SDA
3
V
DD
6
SCL
4
DGND
5
Figure 4. Metallization Photograph
Dimensions shown in μm
Contact Factory for Latest Dimensions
Rev. 0 | Page 6 of 16
AD5398A
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
VERT = 50µs/DIV
INL V = 3.8V
DD
TEMP = 25°C
1.5
1.0
0.5
0
3
HORIZ = 468µA/DIV
–0.5
CH3
M50.0ms
CODE
Figure 5. Typical INL vs. Code Plot
Figure 8. Settling Time for a 4-LSB Step (VDD = 3.6 V)
0.6
0.5
0.4
0.3
0.2
0.1
0
DNL V = 3.8V
DD
TEMP = 25°C
VERT = 2µA/DIV
4.8µA p-p
1
–0.1
–0.2
–0.3
HORIZ = 2s/DIV
CH1
M2.0s
CODE
Figure 9. 0.1 Hz to 10 Hz Noise Plot (VDD = 3.6 V)
Figure 6. Typical DNL vs. Code Plot
0.14
92.0
91.5
91.0
90.5
90.0
89.5
89.0
88.5
88.0
I
@ +25°C
OUT
0.12
0.10
0.08
0.06
0.04
0.02
0
I
@ –40°C
OUT
I
@ +85°C
OUT
–6
–6
–6
–6
–6
250.0
–6 –6
300.0 333.1
53.5
100.0
150.0
200.0
TIME
CODE
Figure 10. Sink Current vs. Code vs. Temperature (VDD = 3.6 V)
Figure 7. ¼ to ¾ Scale Settling Time (VDD = 3.6 V)
Rev. 0 | Page 7 of 16
AD5398A
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
2000
1800
1600
1400
1200
1000
800
V
= 3.6V
DD
V
= 4.5V
DD
V
= 3.8V
DD
600
400
200
0
10
–40 –30 –20 –10
0
15 25 35 45 55 65 75 85
100
1k
10k
100k
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 14. Zero Code Error vs. Temperature vs. Supply Voltage
Figure 11. AC Power Supply Rejection Ratio (VDD = 3.6 V)
3.5
1.5
V
= 4.5V
DD
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.5
POSITIVE INL (V = 3.8V) POSITIVE INL (V = 4.5V)
DD DD
V
= 3.8V
DD
0
POSITIVE INL (V = 3.6V)
DD
–0.5
–1.0
–1.5
–2.0
NEGATIVE INL (V = 3.6V)
DD
NEGATIVE INL (V = 3.8V)
DD
–0.5
–1.0
V
= 3.6V
DD
NEGATIVE INL (V = 4.5V)
DD
–40 –30 –20 –10
0
15 25 35 45 55 65 75 85
–40 –30 –20 –10
0
15 25 35 45 55 65 75 85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. INL vs. Temperature vs. Supply Voltage
Figure 15. Full-Scale Error vs. Temperature vs. Supply Voltage
1.0
0.8
0.6
POSITIVE DNL (V = 3.6V)
DD
0.4
POSITIVE DNL (V = 4.5V)
DD
0.2
0
POSITIVE DNL (V = 3.8V)
DD
NEGATIVE DNL (V = 3.8V)
DD
–0.2
–0.4
–0.6
–0.8
–1.0
NEGATIVE DNL (V = 4.5V)
DD
NEGATIVE DNL (V = 3.6V)
DD
–40 –30 –20 –10
0
15 25 35 45 55 65 75 85
TEMPERATURE (°C)
Figure 13. DNL vs. Temperature vs. Supply Voltage
Rev. 0 | Page 8 of 16
AD5398A
TERMINOLOGY
Relative Accuracy
Gain Error Drift
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSB, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 5.
This is a measurement of the change in gain error with changes
in temperature. It is expressed in LSB/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nA-sec
and is measured when the digital input code is changed by
1 LSB at the major carry transition.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot is shown in Figure 6.
Digital Feedthrough
Digital feedthrough is a measurement of the impulse injected
into the analog output of the DAC from the digital inputs of
the DAC, however is measured when the DAC output is not
updated. It is specified in nA-sec and measured with a full-
scale code change on the data bus, that is, from all 0s to all 1s
and vice versa.
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output is 0 mA. The zero-code error is always positive in the
AD5398A because the output of the DAC cannot go below
0 mA. This is due to a combination of the offset errors in the
DAC and output amplifier. Zero-code error is expressed in mA.
Offset Error
Offset error is a measurement of the difference between ISINK
(actual) and IOUT (ideal) in the linear region of the transfer
function, expressed in mA. Offset error is measured on the
AD5398A with Code 16 loaded into the DAC register.
Gain Error
This is a measurement of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percent of the full-scale range.
Offset Error Drift
This is a measurement of the change in offset error with a
change in temperature. It is expressed in μV/°C.
Rev. 0 | Page 9 of 16
AD5398A
THEORY OF OPERATION
V
DD
The AD5398A is a fully integrated 10-bit DAC with 120 mA
output current sink capability and is intended for driving voice
coil actuators in applications such as lens autofocus, image sta-
bilization, and optical zoom. The circuit diagram is shown in
Figure 16. A 10-bit current output DAC coupled with Resistor R
generates the voltage that drives the noninverting input of the
operational amplifier. This voltage also appears across the RSENSE
resistor and generates the sink current required to drive the
voice coil.
R
R
P
P
SDA
SCL
2
2
2
I C MASTER
DEVICE
I C SLAVE
I C SLAVE
AD5398A
DEVICE
DEVICE
Figure 17. Typical I2C Bus
When the bus is idle, SCL and SDA are both high. The master
device initiates a serial bus operation by generating a start
condition, which is defined as a high-to-low transition on the
SDA line while SCL is high. The slave device connected to the
bus responds to the start condition and shifts in the next eight
data bits under the control of the serial clock. These eight data
bits consist of a 7-bit address, plus a read/write bit, which is 0 if
data is to be written to a device, and 1 if data is to be read from a
device. Each slave device on an I2C bus must have a unique
address. The address of the AD5398A is 0001100; however,
0001101, 0001110, and 0001111 address the part because the
last two bits are unused/don’t care (see Figure 18 and Figure 19).
The R and RSENSE resistors are interleaved and matched. There-
fore, the temperature coefficient and any nonlinearities over
temperature are matched and the output drift over temperature
is minimized. Diode D1 is an output protection diode.
V
BAT
VOICE COIL
ACTUATOR
V
DD
POWER-ON
RESET
REFERENCE
AD5398A
V
DD
W
Because the address plus R/ bit always equals eight bits of data,
D1
SDA
SCL
10-BIT
2
another way of looking at it is that the write address of the
AD5398A is 0001 1000 (0x18) and the read address is 0001 1001
(0x19). Again, Bit 6 and Bit 7 of the address are unused, and,
therefore, the write addresses can also be 0x1A, 0x1C, and 0x1E,
and the read address can be 0x1B, 0x1D, and 0x1F (see Figure 18
and Figure 19).
I C SERIAL
CURRENT
INTERFACE
I
OUTPUT DAC
SINK
R
SENSE
3.3Ω
R
PD
DGND
DGND
AGND
W
At the end of the address data, after the R/ bit, the slave
Figure 16. Circuit Diagram Showing Connection to
Voice Coil
device that recognizes its own address responds by generating
an acknowledge (ACK) condition. This is defined as the slave
device pulling SDA low while SCL is low before the ninth clock
pulse, and keeping it low during the ninth clock pulse. Upon
receiving an ACK, the master device can clock data into the
AD5398A in a write operation, or it can clock it out in a read
operation. Data must change either during the low period of the
clock, because SDA transitions during the high period define a
start condition as described previously, or during a stop condi-
tion as described in the Data Format section.
SERIAL INTERFACE
The AD5398A is controlled using the industry-standard I2C
2-wire serial protocol. Data can be written to or read from
the DAC at data rates up to 400 kHz. After a read operation,
the contents of the input register are reset to all zeros.
I2C BUS OPERATION
An I2C bus operates with one or more master devices that
generate the serial clock (SCL), and read/write data on the serial
data line (SDA) to/from slave devices such as the AD5398A. On
all devices on an I2C bus, the SCL pin is connected to the SCL
line and the SDA pin is connected to the SDA line. I2C devices
can only pull the bus lines low; pulling high is achieved by the
pull-up resistors, RP. The value of RP depends on the data rate,
bus capacitance, and the maximum load current that the I2C
device can sink (3 mA for a standard device).
I2C data is divided into blocks of eight bits, and the slave
generates an ACK at the end of each block. The AD5398A
requires 10 bits of data; two data-words must be written to it
when a write operation occurs, or read from it when a read
operation occurs. At the end of a read or write operation, the
AD5398A acknowledges the second data byte. The master
generates a stop condition, defined as a low-to-high transition
on SDA while SCL is high, to end the transaction.
Rev. 0 | Page 10 of 16
AD5398A
DATA FORMAT
Data is written to the AD5398A high byte first, MSB first, and is
shifted into the 16-bit input register. After all data is shifted in,
data from the input register is transferred to the DAC register.
The data format is shown in Table 6. When referring to this table,
note that Bit 14 is unused; Bit 13 to Bit 4 correspond to the DAC
data bits, D9 to D0; and Bit 3 to Bit 0 are unused.
Because the DAC requires only 10 bits of data, not all bits of the
input register data are used. The MSB is reserved for an active-
high, software-controlled, power-down function.
During a read operation, data is read in the same bit order.
1
0
9
1
1
9
SCL
SDA
0
0
1
1
X
X
R/W
PD
X
D9 D8 D7 D6 D5 D4
D3 D2 D1 D0
X
X
X
X
START BY
MASTER
ACK BY
AD5398A
ACK BY
AD5398A
ACK BY STOP BY
AD5398A MASTER
FRAME 1
FRAME 2
MOST SIGNIFICANT
DATA BYTE
FRAME 3
LEAST SIGNIFICANT
DATA BYTE
SERIAL BUS
ADDRESS BYTE
Figure 18. Write Operation
1
0
9
1
1
9
SCL
SDA
0
0
1
1
X
X
R/W
PD
X
D9 D8 D7 D6 D5 D4
D3 D2 D1 D0
X
X
X
X
START BY
MASTER
ACK BY
AD5398A
ACK BY
AD5398A
ACK BY STOP BY
AD5398A MASTER
FRAME 1
FRAME 2
MOST SIGNIFICANT
DATA BYTE
FRAME 3
LEAST SIGNIFICANT
DATA BYTE
SERIAL BUS
ADDRESS BYTE
Figure 19. Read Operation
Table 6. Data Format
High Byte
Low Byte
Serial Data-
Words
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Serial Data Bits
Input Register
Function1
SD7 SD6
R15 R14
SD5
R13
D9
SD4
R12
D8
SD3
R11
D7
SD2
R10
D6
SD1 SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
R9
R8
R7
R6
R5
R4
R3
X
R2
X
R1
X
R0
X
PD
X
D5
D4
D3
D2
D1
D0
1 PD = soft power-down; X = unused/don’t care; and D7 to D0 = DAC data.
Rev. 0 | Page 11 of 16
AD5398A
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in an application, it is beneficial
to consider power supply and ground return layout on the PCB.
The PCB for the AD5398A should have separate analog and
digital power supply sections. Where shared AGND and DGND
is necessary, the connection of grounds should be made at only
one point, as close as possible to the AD5398A.
When the maximum sink current is flowing through the motor,
the resistive elements, RT and RG, may have an impact on the
voltage headroom of Q1 and may, in turn, limit the maximum
value of RC because of voltage compliance.
For example, if
V
BAT = 3.6 V
Pay special attention to the layout of the AGND return path
and track it between the voice coil motor and ISINK to minimize
any series resistance. Figure 20 shows the output current sink
of the AD5398A and illustrates the importance of reducing the
effective series impedance of AGND, and the track resistance
between the motor and ISINK. The voice coil is modelled as
Inductor LC and Resistor RC. The current through the voice
coil is effectively a dc current that results in a voltage drop, VC,
when the AD5398A is sinking current; the effect of any series
inductance is minimal. The maximum voltage drop allowed
across RSENSE is 400 mV, and the minimum drain to source
voltage of Q1 is 200 mV. This means that the AD5398A output
has a compliance voltage of 600 mV. If VDROP falls below
600 mV, the output transistor, Q1, can no longer operate
properly and ISINK might not be maintained as a constant.
RG = 0.5 Ω
RT = 0.5 Ω
I
SINK = 120 mA
DROP = 600 mV (the compliance voltage)
V
then the largest value of resistance of the voice coil, RC, is
VBAT −[VDROP +(ISINK ×RT )+(ISINK ×RG )]
RC
=
=
ISINK
3.6 V −[600 mV + 2×(120 mA×0.5 ꢀ)]
= 24 ꢀ
120 mA
For this reason, it is important to minimize any series impedance
on both the ground return path and interconnect between the
AD5398A and the motor.
V
BAT
VOICE
COIL
The power supply of the AD5398A should be decoupled with
0.1 μF and 10 μF capacitors. These capacitors should be kept as
physically close as possible, with the 0.1 μF capacitor serving as
a local bypass capacitor, and therefore should be located as close
as possible to the VDD pin. The 10 μF capacitor should be a
tantalum bead-type; the 0.1 μF capacitor should be a ceramic
type with a low effective series resistance and effective series
inductance. The 0.1 μF capacitor provides a low impedance path
to ground for high transient currents.
L
C
ACTUATOR
V
C
R
C
V
DD
TRACE
RESISTANCE
R
D1
Q1
T
V
V
T
I
SINK
R
SENSE
3.3Ω
DROP
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by digital
ground. Avoid crossover of digital and analog signals if possible.
AGND
GROUND
RESISTANCE
R
G
V
G
GROUND
INDUCTANCE
L
G
Figure 20. Effect of PCB Trace Resistance and Inductance
When traces cross on opposite sides of the board, ensure that
they run at right angles to each other to reduce feedthrough
effects through the board. The best board layout technique is to
use a multilayer board with ground and power planes, where
the component side of the board is dedicated to the ground
plane only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.
As the current increases through the voice coil, VC increases
and VDROP decreases and eventually approaches the minimum
specified compliance voltage of 600 mV. The ground return
path is modelled by the RG and LG components. The track resis-
tance between the voice coil and the AD5398A is modelled as
RT. The inductive effects of LG influence RSENSE and RC equally,
and because the current is maintained as a constant, it is not as
critical as the purely resistive component of the ground return path.
Rev. 0 | Page 12 of 16
AD5398
APPLICATIONS INFORMATION
The AD5398A is designed to drive both spring preloaded
and nonspring linear motors used in applications such as lens
autofocus, image stabilization, or optical zoom. The operating
principle of the spring-preloaded motor is that the lens position
is controlled by the balancing of a voice coil and a spring. Figure 21
shows the transfer curve of a typical spring preloaded linear
motor for autofocus. The key points of this transfer function are
displacement or stroke, which is the actual distance the lens
moves in millimeters (mm), and the current through the motor
in milliamps (mA).
0.5
0.4
0.3
0.2
0.1
0
START
CURRENT
A start current is associated with spring-preloaded linear motors,
which is effectively a threshold current that must be exceeded for
any displacement in the lens to occur. The start current is usually
20 mA or greater; the rated stroke or displacement is usually
0.25 mm to 0.4 mm; and the slope of the transfer curve is approxi-
mately 10 μm/mA or less.
0
10
20
30
40
50
60
70
80
90 100 110 120
SINK CURRENT (mA)
Figure 21. Spring Preloaded Voice Coil Stroke vs. Sink Current
The AD5398A is designed to sink up to 120 mA, which is
more than adequate for available commercial linear motors or
voice coils. Another factor that makes the AD5398A the ideal
solution for these applications is the monotonicity of the device,
which ensures that lens positioning is repeatable for the applica-
tion of a given digital word.
Figure 22 shows a typical application circuit for the AD5398A.
V
V
CC
DD
+
+
0.1µF
10µF
10µF
0.1µF
V
DD
POWER-DOWN
RESET
VOICE
POWER-ON
RESET
REFERENCE
COIL
AD5398A
ACTUATOR
V
PD
DD
V
DD
R
R
P
P
SDA
SCL
D1
SDA
SCL
10-BIT
2
I C SERIAL
CURRENT
INTERFACE
I
OUTPUT DAC
SINK
2
2
2
R
I C MASTER
DEVICE
I C SLAVE
I C SLAVE
DEVICE
SENSE
3.3Ω
R
DEVICE
DGND
DGND
AGND
Figure 22. Typical Application Circuit
Rev. 0 | Page 13 of 16
AD5398A
OUTLINE DIMENSIONS
0.65
0.59
0.53
1.575
1.515
1.455
SEATING
PLANE
3
2
1
A
B
C
0.35
0.32
0.29
BALL 1
IDENTIFIER
1.750
1.690
1.630
0.50 BSC
BALL PITCH
TOP VIEW
(BALL SIDE DOWN)
0.28
0.24
0.20
BOTTOM VIEW
(BALL SIDE UP)
Figure 23. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-9-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5398ABCBZ-REEL71
AD5398ABCBZ-REEL1
AD5398A-WAFER
EVAL-AD5398AEBZ1
Temperature Range
Package Description
Package Option
CB-9-1
CB-9-1
Branding
−30°C to +85°C
−30°C to +85°C
−40°C to +85°C
9-Ball Wafer Level Chip Scale (WLCSP)
9-Ball Wafer Level Chip Scale (WLCSP)
Bare Die Wafer
1Z
1Z
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 14 of 16
AD5398A
NOTES
Rev. 0 | Page 15 of 16
AD5398A
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07795-0-10/08(0)
Rev. 0 | Page 16 of 16
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