AD5405YCPZ-REEL [ADI]
Dual 12-Bit, High Bandwidth, Multiplying DAC with 4 Quadrant Resistors and Parallel Interface;
| 型号： | AD5405YCPZ-REEL |
| 厂家： | 
ADI |
| 描述： | Dual 12-Bit, High Bandwidth, Multiplying DAC with 4 Quadrant Resistors and Parallel Interface 转换器 |
| 文件： | 总25页 (文件大小：863K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 12-Bit, High Bandwidth, Multiplying DAC with
4-Quadrant Resistors and Parallel Interface
Data Sheet
AD5405
FEATURES
GENERAL DESCRIPTION
The AD54051 is a CMOS, 12-bit, dual-channel, current output
10 MHz multiplying bandwidth
On-chip 4-quadrant resistors allow flexible output ranges
INL of 1 LSB
40-lead LFCSP package
digital-to-analog converter (DAC). This device operates from a
2.5 V to 5.5 V power supply, making it suited to battery-powered
and other applications.
2.5 V to 5.5 V supply operation
10 V reference input
21.3 MSPS update rate
Extended temperature range: −40°C to +125°C
4-quadrant multiplication
Power-on reset
0.5 μA typical current consumption
Guaranteed monotonic
As a result of manufacturing with a CMOS submicron process the
device offers excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor (RFB)
provides temperature tracking and full-scale voltage output when
combined with an external I to V precision amplifier. This device
also contains the 4-quadrant resistors necessary for bipolar
operation and other configuration modes.
Readback function
APPLICATIONS
This DAC uses data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches fill with 0s, and the DAC outputs
are at zero scale.
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
The AD5405 has a 6 mm × 6 mm, 40-lead LFCSP package.
1 U.S. Patent Number 5,689,257.
Ultrasound
Gain, offset, and voltage trimming
FUNCTIONAL BLOCK DIAGRAM
V
A
R1A
R3A
R2_3A
R2A
REF
R3
2R
R2
2R
R1
2R
RFB
2R
AD5405
V
R
A
DD
FB
DATA
INPUTS
DB0
I
1A
2A
OUT
INPUT
BUFFER
12-BIT
R-2R DAC A
LATCH
DB11
I
OUT
DAC A/B
CONTROL
LOGIC
CS
R/W
I
I
1B
2B
OUT
12-BIT
R-2R DAC B
LATCH
OUT
LDAC
R
B
FB
POWER-ON
RESET
GND
CLR
R1
2R
RFB
2R
R3
2R
R2
2R
R3B
R2_3B
R2B
V
B R1B
REF
Figure 1.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5405* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
REFERENCE MATERIALS
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
• Multiplying DACs Flexible Building Blocks
EVALUATION KITS
• AD5405 Evaluation Board
DESIGN RESOURCES
• AD5405 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Application Notes
• AN-1085: Multiplying DACs—AC/Arbitrary Reference
Applications
• AN-137: A Digitally Programmable Gain and Attenuation
Amplifier Design
DISCUSSIONS
View all AD5405 EngineerZone Discussions.
• AN-320A: CMOS Multiplying DACs and Op Amps Combine
to Build Programmable Gain Amplifier, Part 1
• AN-320B: CMOS Multiplying DACs and Op Amps Combine
to Build Programmable Gain Amplifiers, Part 2
SAMPLE AND BUY
Visit the product page to see pricing options.
• AN-912: Driving a Center-Tapped Transformer with a
Balanced Current-Output DAC
TECHNICAL SUPPORT
Data Sheet
Submit a technical question or find your regional support
number.
• AD5405: Dual 12-Bit, High Bandwidth, Multiplying DAC
with 4-Quadrant Resistors and Parallel Interface Data
Sheet
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
AD5405
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Operation....................................................................... 14
Single-Supply Applications ....................................................... 15
Adding Gain................................................................................ 15
Divider or Programmable Gain Element................................ 16
Reference Selection .................................................................... 16
Amplifier Selection .................................................................... 16
Parallel Interface......................................................................... 18
Microprocessor Interfacing....................................................... 18
PCB Layout and Power Supply Decoupling ........................... 19
Overview of the AD5424 to AD5547 Devices............................ 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 13
General Description....................................................................... 14
DAC Section................................................................................ 14
REVISION HISTORY
1/16—Rev. B to Rev. C
7/05—Rev. 0 to Rev. A
Changed Pin DAC A/B to DAC /B ...............................Universal
Deleted Positive Output Voltage Section and Figure 35............ 15
Changes to Adding Gain Section ................................................. 15
Changes to ADSP-21xx Processors to AD5405 Interface Section
Title, ADSP-BF504 to ADSP-BF592 Device Family to AD5405
Interface Section Title, and Figure 39 Caption........................... 19
Deleted Evaluation Board for the DACs Section and Power
Supplies for the Evaluation Board Section.................................. 19
Changes to Table 10........................................................................ 22
Updated Outline Dimensions....................................................... 23
Changes to Ordering Guide .......................................................... 23
A
Changes to Features List...................................................................1
Changes to Specifications.................................................................3
Changes to Timing Characteristics.................................................5
Change to Absolute Maximum Ratings .........................................6
Change to Figure 7 and Figure 8 .....................................................8
Change to Figure 12 ..........................................................................9
Change to Figure 26 Through Figure 28..................................... 11
Changes to General Description Section .................................... 14
Change to Figure 31 ....................................................................... 14
Changes to Table 5 Through Table 10 ......................................... 14
Changes to Figure 34 and Figure 35 ............................................ 15
Changes to Figure 36 and Figure 37 ............................................ 16
Changes to Microprocessor Interfacing Section ........................ 18
Added Figure 38 Through Figure 40 ........................................... 18
Change to Power Supplies for the Evaluation Board Section... 19
Updated Outline Dimensions....................................................... 23
Changes to Ordering Guide.......................................................... 23
12/09—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
Changes to Table 2 and Figure 2..................................................... 5
Changes to Table 4 and Figure 4..................................................... 7
Updated Outline Dimensions....................................................... 23
Changes to Ordering Guide .......................................................... 23
7/04—Revision 0: Initial Version
Rev. C | Page 2 of 24
Data Sheet
AD5405
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted.
Table 1.1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Guaranteed monotonic
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
12
1
Bits
LSB
−1/+2 LSB
25
mV
Gain Error Temperature Coefficient
Bipolar Zero-Code Error
Output Leakage Current
5
ppm FSR/°C
25
1
15
mV
nA
nA
Data = 0x0000, TA = 25°C, IOUT
Data = 0x0000, TA = −40°C to +125°C, IOUT1
1
REFERENCE INPUT
Reference Input Range
VREFA, VREFB Input Resistance
VREFA to VREFB Input Resistance
Mismatch
10
10
1.6
V
kΩ
%
8
13
2.5
Input resistance TC = −50 ppm/°C
Typ = 25°C, max = 125°C
R1, RFB Resistance
R2, R3 Resistance
R2 to R3 Resistance Mismatch
Input Capacitance
Code 0
17
17
20
20
25
25
kΩ
kΩ
%
Input resistance TC = −50 ppm/°C
Input resistance TC = −50 ppm/°C
Typ = 25°C, max = 125°C
0.06 0.18
3.5
3.5
pF
pF
Code 4095
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH
1.7
1.7
V
V
VDD = 3.6 V to 5.5 V
VDD = 2.5 V to 3.6 V
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
0.8
0.7
V
V
V
V
V
V
µA
pF
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD = 4.5 V to 5.5 V, ISOURCE = 200 µA
VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA
VDD = 4.5 V to 5.5 V, ISINK = 200 µA
VDD = 2.5 V to 3.6 V, ISINK = 200 µA
VDD − 1
VDD − 0.5
0.4
0.4
1
Input Leakage Current, IIL
Input Capacitance
4
10
DYNAMIC PERFORMANCE
Reference Multiplying BW
Output Voltage Settling Time
10
MHz
VREF = 3.5 V p-p, DAC loaded all 1s
RLOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V
DAC latch alternately loaded with 0s and 1s
Measured to 1 mV of FS
Measured to 4 mV of FS
Measured to 16 mV of FS
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
80
35
30
20
15
3
120
70
60
40
30
ns
ns
ns
ns
ns
nV-sec
Interface time delay
Rise and fall times
1 LSB change around major carry, VREF = 0 V
DAC latch loaded with all 0s, VREF = 3.5 V
1 MHz
10 MHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
70
48
17
30
dB
dB
pF
pF
Output Capacitance
12
25
Rev. C | Page 3 of 24
AD5405
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Digital Feedthrough
1
nV-sec
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
At 1 kHz
VREF = 3. 5 V p-p, all 1s loaded, f = 1 kHz
Clock = 10 MHz, VREF = 3.5 V
Output Noise Spectral Density
Analog THD
Digital THD
25
81
nV/√Hz
dB
100 kHz fOUT
50 kHz fOUT
61
66
dB
dB
SFDR Performance (Wideband)
Clock = 10 MHz
500 kHz fOUT
VREF = 3.5 V
55
63
65
dB
dB
dB
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50
60
62
dB
dB
dB
50 kHz fOUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz fOUT
VREF = 3.5 V
73
80
87
dB
dB
dB
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
70
75
80
dB
dB
dB
50 kHz fOUT
Intermodulation Distortion
f1 = 40 kHz, f2 = 50 kHz
f1 = 40 kHz, f2 = 50 kHz
POWER REQUIREMENTS
Power Supply Range
IDD
VREF = 3.5 V
Clock = 10 MHz
Clock = 25 MHz
72
65
dB
dB
2.5
5.5
0.7
10
0.001
V
µA
µA
%/%
TA = 25°C, logic inputs = 0 V or VDD
TA = −40°C to +125°C, logic inputs = 0 V or VDD
∆VDD = 5%
0.5
Power Supply Sensitivity
1 Guaranteed by design and characterization, not subject to production test.
Rev. C | Page 4 of 24
Data Sheet
AD5405
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
REF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
V
Table 2.1
Parameter
Limit at TMIN, TMAX
Unit
Test Conditions/Comments
Write Mode
t1
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
R/W to CS setup time
R/W to CS hold time
CS low time
t2
0
t3
10
10
0
6
0
t4
t5
t6
t7
Address setup time
Address hold time
Data setup time
Data hold time
R/W high to CS low
CS min high time
t8
5
t9
7
t14
10
12
10
10
CS rising to LDAC falling time
LDAC pulse width
t15
t16
CS rising to LDAC rising time
LDAC falling to CS rising time
t17
Data Readback Mode
t10
t11
t12
0
0
5
35
5
ns typ
ns typ
ns typ
ns max
ns typ
ns max
MSPS
Address setup time
Address hold time
Data access time
t13
Bus relinquish time
10
21.3
Update Rate
Consists of CS min high time, CS low time, and output voltage settling time
1 Guaranteed by design and characterization, not subject to production test.
t8
t2
t2
t1
R/W
CS
t9
t3
t4
t11
t10
t5
DACA/DACB
DATA
t6
t12
t13
t7
DATA VALID
DATA VALID
t14
t15
LDAC1
LDAC2
t17
t16
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Timing Diagram
I
200
µ
A
OL
V
+ V
2
TO
OUTPUT
PIN
OH (MIN)
OL (MAX)
C
50pF
L
I
200
µ
A
OH
Figure 3. Load Circuit for Data Timing Specifications
Rev. C | Page 5 of 24
AD5405
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 3.
Parameter
Rating
VDD to GND
VREFA, VREFB, RFBA, RFBB to GND
IOUT1, IOUT2 to GND
Logic Inputs and Output1
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
−0.3 V to +7 V
−12 V to +12 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
40-lead LFCSP, θJA Thermal Impedance
Lead Temperature, Soldering (10 sec)
30°C/W
300°C
Infrared (IR) Reflow, Peak Temperature
(<20 sec)
235°C
1
LDAC CS
W
Overvoltages at DBx,
,
, and R/ are clamped by internal diodes.
Rev. C | Page 6 of 24
Data Sheet
AD5405
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
R1A
R2A
R2_3A
1
2
3
4
5
6
7
8
9
30 R1B
29 R2B
28 R2_3B
27 R3B
R3A
AD5405
V
A
26 V
25 V
B
REF
REF
DD
DGND
LDAC
DAC A/B
NIC
TOP VIEW
(Not to Scale)
24 CLR
23 R/W
22 CS
DB11 10
21 DB0
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. EXPOSED PAD MUST BE CONNECTED TO GROUND.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 4
R1A, R2B,
R2_3B, R3A
DAC A 4-Quadrant Resistors. Allow a number of configuration modes, including bipolar operation with
minimum of external components.
5, 26
6
7
VREFA, VREF
DGND
LDAC
B
DAC Reference Voltage Input Terminals.
Digital Ground Pin.
Load DAC Input. Allows asynchronous or synchronous updates to the DAC output. The DAC is
asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an
automatic or synchronous update mode is selected whereby the DAC is updated on the rising edge of CS.
8
A
Selects DAC A or B. Low selects DAC A, and high selects DAC B.
DAC /B
9, 34 to 37
10 to 21
22
NIC
DB11 to DB0
CS
Not internally connected.
Parallel Data Bits 11 through 0.
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to
read data from the DAC register. Edge sensitive; when pulled high, the DAC data is latched.
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction
with CS to read back contents of DAC register.
23
R/W
24
CLR
VDD
Active Low Control Input. Clears DAC output and input and DAC registers.
25
Positive Power Supply Input. These devices can be operated from a supply of 2.5 V to 5.5 V.
27 to 30
R3B, R2_3B,
R2B, R1B
DAC B 4-Quadrant Resistors. Allow a number of configuration modes, including bipolar operation with a
minimum of external components.
31, 40
32
RFBB, RFBA
IOUT2B
External Amplifier Output.
DAC A Analog Ground. This pin typically ties to the analog ground of the system, but can be biased to
achieve single-supply operation.
33
38
39
IOUT1B
IOUT1A
IOUT2A
DAC B Current Outputs.
DAC A Current Outputs.
DAC A Analog Ground. This pin typically ties to the analog ground of the system, but can be biased to
achieve single-supply operation.
EPAD
Exposed pad must be connected to ground.
Rev. C | Page 7 of 24
AD5405
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
–0.40
–0.45
–0.50
–0.55
–0.60
–0.65
–0.70
T
V
= 25°C
= 5V
A
T
V
V
= 25°C
A
0.8
DD
= 10V
REF
= 5V
DD
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
MIN DNL
0
0
2
500
1000
1500
2000
2500
3000
3500
4000
2
3
4
5
6
7
8
9
10
CODE
REFERENCE VOLTAGE
Figure 8. Differential Nonlinearity (DNL) vs. Reference Voltage
Figure 5. Integral Nonlinearity (INL) vs. Code (12-Bit DAC)
5
1.0
0.8
T
V
V
= 25°C
A
4
3
= 10V
REF
= 5V
V
= 5V
DD
DD
0.6
2
0.4
1
0.2
0
0
V
= 2.5V
DD
–1
–2
–3
–4
–5
–0.2
–0.4
–0.6
–0.8
–1.0
V
= 10V
REF
500
1000
1500
2000
2500
3000
3500
4000
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
CODE
Figure 6. DNL vs. Code (12-Bit DAC)
Figure 9. Gain Error vs. Temperature
0.6
0.5
8
7
6
5
4
3
2
1
0
T
= 25°C
A
0.4
MAX INL
0.3
V
= 5V
DD
0.2
T
V
= 25°C
= 5V
A
0.1
DD
0
MIN INL
–0.1
–0.2
–0.3
V
= 3V
DD
V
= 2.5V
DD
3
4
5
6
7
8
9
10
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
REFERENCE VOLTAGE
INPUT VOLTAGE (V)
Figure 7. INL vs. Reference Voltage
Figure 10. Supply Current vs. Logic Input Voltage
Rev. C | Page 8 of 24
Data Sheet
AD5405
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6
0
–6
T
= 25°C
ALL ON
DB11
DB10
DB9
DB8
DB7
A
LOADING
ZS TO FS
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
I
I
1 V = 5V
DD
OUT
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1 V = 3V
DD
OUT
T
V
= 25°C
DD
= ±3.5V
= 1.8pF
A
= 5V
V
REF
C
ALL OFF
COMP
AMP = AD8038
1
10
100
1k
10k
100k
1M 10M 100M
–40
–20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 14. Reference Multiplying Bandwidth vs. Frequency and Code
Figure 11. IOUT1 Leakage Current vs. Temperature
0.2
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
= 5V
DD
0
–0.2
–0.4
ALL 0s
ALL 1s
V
= 2.5V
DD
ALL 1s
ALL 0s
T
V
V
C
= 25°C
A
–0.6
–0.8
= 5V
DD
= ±3.5V
REF
= 1.8pF
COMP
AMP = AD8038
1
10 100
1k
10k
100k
1M
10M
100M
–60 –40 –20
0
20
40
60
80
100 120 140
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 12. Supply Current vs. Temperature
Figure 15. Reference Multiplying Bandwidth—All 1s Loaded
14
12
10
8
3
T
V
= 25°C
A
T
= 25°C
A
= 5V
DD
LOADING ZS TO FS
V
= 5V
DD
0
–3
–6
–9
6
V
V
= 3V
DD
DD
4
V
V
V
V
V
= ±2V, AD8038 C 1.47pF
C
REF
REF
REF
REF
REF
= 2.5V
= ±2V, AD8038 C 1pF
C
= ±0.15V, AD8038 C 1pF
C
2
= ±0.15V, AD8038 C 1.47pF
C
= ±3.51V, AD8038 C 1.8pF
C
0
1
10
100
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. Supply Current vs. Update Rate
Figure 16. Reference Multiplying Bandwidth vs. Frequency
and Compensation Capacitor
Rev. C | Page 9 of 24
AD5405
Data Sheet
–60
–65
–70
–75
–80
–85
–90
0.045
0x7FF TO 0x800
T
V
= 25°C
= 0V
T = 25°C
A
A
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
V
= 3V
REF
AMP = AD8038
= 1.8pF
DD
V
= 5V
V
= 3.5V p-p
DD
REF
C
COMP
V
= 3V
DD
0x800 TO 0x7FF
= 3V
V
DD
–0.005
–0.010
V
= 5V
DD
0
20
40
60
80
100 120 140 160 180 200
TIME (ns)
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 17. Midscale Transition, VREF = 0 V
Figure 20. THD and Noise vs. Frequency
–1.68
–1.69
–1.70
–1.71
–1.72
–1.73
–1.74
–1.75
–1.76
–1.77
100
80
60
40
20
0
T
V
= 25°C
= 3.5V
A
0x7FF TO 0x800
= 5V
MCLK = 1MHz
REF
AMP = AD8038
= 1.8pF
V
DD
C
COMP
MCLK = 200kHz
MCLK = 0.5MHz
V
= 3V
DD
V
= 5V
V
DD
= 3V
DD
T
V
= 25°C
= 3.5V
A
REF
AMP = AD8038
0x800 TO 0x7FF
20 40 60
0
20
40
60
80
100 120 140 160 180 200
0
80
100 120 140 160 180 200
TIME (ns)
fOUT (kHz)
Figure 21. Wideband SFDR vs. fOUT Frequency
Figure 18. Midscale Transition, VREF = 3.5 V
90
80
70
60
50
40
30
20
10
0
20
0
T
V
= 25°C
A
= 3V
DD
AMP = AD8038
MCLK = 5MHz
MCLK = 10MHz
–20
–40
–60
–80
–100
–120
FULL SCALE
ZERO SCALE
MCLK = 25MHz
T
V
= 25°C
= 3.5V
A
REF
AMP = AD8038
1
100
1k
10k
100k
1M
10M
0
100 200 300 400 500 600 700 800 900 1000
fOUT (kHz)
10
FREQUENCY (Hz)
Figure 22. Wideband SFDR vs. fOUT Frequency
Figure 19. Power Supply Rejection Ratio vs. Frequency
Rev. C | Page 10 of 24
Data Sheet
AD5405
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
V
= 25°C
DD
T = 25°C
A
DD
AMP = AD8038
65k CODES
A
= 5V
V
= 3V
AMP = AD8038
65k CODES
0
2
4
6
8
10
12
250 300 350 400 450 500 550 600 650 700 750
FREQUENCY (MHz)
FREQUENCY (kHz)
Figure 23. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
Figure 26. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
= 25°C
DD
T = 25°C
A
DD
AMP = AD8038
65k CODES
A
= 5V
V
= 3V
AMP = AD8038
65k CODES
0
–20
–40
–60
–80
–100
–120
50
60
70
80
90
100 110 120 130 140 150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (kHz)
FREQUENCY (MHz)
Figure 27. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
Figure 24. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
V
= 25°C
DD
T
V
= 25°C
DD
A
A
= 3V
= 5V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
AMP = AD8038
65k CODES
AMP = AD8038
65k CODES
70
75
80
85
90
95
100 105 110 115 120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (kHz)
FREQUENCY (MHz)
Figure 28. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
Figure 25. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
Rev. C | Page 11 of 24
AD5405
Data Sheet
300
250
200
150
100
50
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
= 25°C
T
V
= 25°C
DD
A
A
ZERO SCALE LOADED TO DAC
MIDSCALE LOADED TO DAC
FULL SCALE LOADED TO DAC
AMP = AD8038
= 5V
AMP = AD8038
65k CODES
0
–100
0
100
1k
10k
FREQUENCY (Hz)
100k
50
100
150
200
250
300
350
400
FREQUENCY (kHz)
Figure 29. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
Figure 30. Output Noise Spectral Density
Rev. C | Page 12 of 24
Data Sheet
AD5405
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
Multiplying Feedthrough Error
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is measured after adjusting for zero and full scale and is normally
expressed in LSBs or as a percentage of the full-scale reading.
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Digital Crosstalk
Differential Nonlinearity
The glitch impulse transferred to the outputs of a DAC in
response to a full-scale code change (all 0s to all 1s, or vice
versa) in the input register of another DAC. It is expressed in
nV-sec.
The difference in the measured change and the ideal 1 LSB change
between two adjacent codes. A specified differential nonlinearity of
−1 LSB maximum over the operating temperature range ensures
monotonicity.
Analog Crosstalk
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For this DAC, ideal maximum output is
The glitch impulse transferred to the output of one DAC due to
a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s, or vice versa) while keeping LDAC high and
then pulsing LDAC low and monitoring the output of the DAC
whose digital code has not changed. The area of the glitch is
expressed in nV-sec.
V
REF − 1 LSB. The gain error of the DAC is adjustable to zero
with an external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when they
are turned off. For the IOUT1 terminal, it can be measured by
loading all 0s to the DAC and measuring the IOUT1 current.
Minimum current flows into the IOUT2 line when the DAC is
loaded with all 1s.
Channel to Channel Isolation
The portion of input signal from a DAC reference input that
appears at the output of the other DAC. It is expressed in decibels.
Total Harmonic Distortion (THD)
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as the second to the fifth harmonics.
Output Current Settling Time
The amount of time for the output to settle to a specified level
for a full-scale input change. For this device, it is specified with
a 100 Ω resistor to ground.
2
2
2
2
V2 + V3 + V4 + V5
THD = 20 log
V1
Digital-to-Analog Glitch Impulse
Intermodulation Distortion (IMD)
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is typically
specified as the area of the glitch in either pA-sec or nV-sec,
depending on whether the glitch is measured as a current or
voltage signal.
The DAC is driven by two combined sine wave references
of frequencies fa and fb. Distortion products are produced
at sum and difference frequencies of mfa nfb, where m, n = 0,
1, 2, 3 ... Intermodulation terms are those for which m or n is
not equal to 0. The second-order terms include (fa + fb) and
(fa − fb), and the third-order terms are (2fa + fb), (2fa − fb),
(f + 2fa + 2fb), and (fa − 2fb). IMD is defined as
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs is capacitively coupled through the
device and produces noise on the IOUT pins and, subsequently,
on the following circuitry. This noise is digital feedthrough.
(rms sum of the sum and diff distortion products)
IMD = 20 log
rms amplitude of the fundamental
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Rev. C | Page 13 of 24
AD5405
Data Sheet
GENERAL DESCRIPTION
When an output amplifier is connected in unipolar mode, the
output voltage is given by
DAC SECTION
The AD5405 is a 12-bit, dual-channel, current-output DAC
consisting of a standard inverting R-2R ladder configuration.
Figure 31 shows a simplified diagram for a single channel of the
AD5405. The feedback resistor RFBA has a value of 2R. The value of
R is typically 10 kΩ (with a minimum of 8 kΩ and a maximum
of 13 kΩ). If IOUT1A and IOUT2A are kept at the same potential, a
constant current flows into each ladder leg, regardless of digital
input code. Therefore, the input resistance presented at VREFA is
always constant.
VOUT = −VREF × D 2n
where:
D is the fractional representation, in the range of 0 to 4,095, of
the digital word loaded to the DAC.
n is the resolution of the DAC.
With a fixed 10 V reference, the circuit shown in Figure 32 gives
a unipolar 0 V to −10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
R
R
R
V
REFA
Table 5 shows the relationship between digital code and the
expected output voltage for unipolar operation.
2R
S1
2R
S2
2R
S3
2R
2R
S12
R
R
A
FB
I
I
Table 5. Unipolar Code
OUT1A
OUT2A
Digital Input
Analog Output (V)
−VREF (4,095/4,096)
−VREF (2,048/4,096) = −VREF/2
−VREF (1/4,096)
DAC DATA LATCHES
AND DRIVERS
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
Figure 31. Simplified Ladder Configuration
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of
the DAC, making the device extremely versatile and allowing it
to be configured for several operating modes, such as unipolar
output, bipolar output, or single-supply mode.
−VREF (0/4,096) = 0
Bipolar Operation
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier, as shown in Figure 33.
CIRCUIT OPERATION
Unipolar Mode
Using a single operational amplifier, this DAC can easily be
configured to provide 2-quadrant multiplying operation or a
unipolar output voltage swing, as shown in Figure 32.
V
DD
R1A
R
2R
FB
R1
2R
R
A
FB
R2A
C1
V
IN
I
I
1A
2A
R2
2R
OUT
V
DD
R1A
AD5405
A1
R2_3A
R3A
OUT
12-Bit DAC A
R
R1
2R
R
FB
2R
V
= –V TO +V
IN IN
OUT
R
A
FB
R3
2R
A1
C1
R2A
I
1A
2A
OUT
AGND
R2
2R
V
A
AD5405
GND
REF
A1
I
12-Bit DAC A
R
OUT
R2_3A
AGND
V
= 0V TO –V
IN
OUT
AGND
R3
2R
NOTES
1. SIMILAR CONFIGURATION FOR DAC B.
R3A
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
AGND
AGND
V
A
REF
GND
Figure 33. Bipolar Operation (4-Quadrant Multiplication)
When in bipolar mode, the output voltage is given by
VOUT = (VREF ×D 2n −1 ) −VREF
where:
AGND
NOTES
1. SIMILAR CONFIGURATION FOR DAC B.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 32. Unipolar Operation
D is the fractional representation, in the range of 0 to 4095, of
the digital word loaded to the DAC.
n is the number of bits.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication.
Table 6 shows the relationship between the digital code and the
expected output voltage for bipolar operation.
Rev. C | Page 14 of 24
Data Sheet
AD5405
Note that VIN is limited to low voltages because the switches in the
DAC ladder no longer have the same source drain drive voltage.
As a result, their on resistance differs and degrades the integral
linearity of the DAC. Also, VIN must not go negative by more
than 0.3 V, or an internal diode turns on, causing the device to
exceed the maximum ratings. In this type of application, the full
range of multiplying capability of the DAC is lost.
Table 6. Bipolar Code
Digital Input
Analog Output (V)
+VREF (4,095/4,096)
0
−VREF (4,095/4,096)
−VREF (4,096/4,096)
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
Stability
ADDING GAIN
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the operational amplifier must be connected as close as
possible, and proper printed circuit board (PCB) layout techniques
must be used. Because every code change corresponds to a step
function, gain peaking may occur if the operational amplifier has
limited gain bandwidth product (GBP) and there is excessive
parasitic capacitance at the inverting node. This parasitic cap-
acitance introduces a pole into the open-loop response, which can
cause ringing or instability in the closed-loop applications circuit.
In applications where the output voltage must be greater than VIN,
gain can be added with an additional external amplifier, or it can be
achieved in a single stage. Consider the effect of temperature
coefficients of the thin film resistors of the DAC. Simply placing
a resistor in series with the RFB resistor causes mismatches in the
temperature coefficients, resulting in larger gain temperature
coefficient errors. Instead, the circuit of Figure 35 shows the
recommended method for increasing the gain of the circuit. R1,
R2, and R3 can have similar temperature coefficients, but they need
not match the temperature coefficients of the DAC. This
approach is recommended in circuits where gains of greater than
1 are required. Note that RFB ≫ R2//R3 and a gain error percentage
of 100 × (R2//R3)/RFB must be taken into consideration.
An optional compensation capacitor, C1, can be added in parallel
with RFBA for stability, as shown in Figure 32 and Figure 33. Too
small a value of C1 can produce ringing at the output, whereas
too large a value can adversely affect the settling time. C1 can be
found empirically, but 1 pF to 2 pF is generally adequate for the
compensation.
V
DD
C
1
V
R
A
FB
SINGLE-SUPPLY APPLICATIONS
Voltage Switching Mode of Operation
DD
R
1
I
1A
2A
OUT
V
12-BIT
DAC
V
A
IN
V
OUT
REF
I
OUT
R
R
3
2
Figure 34 shows the DAC operating in the voltage switching
mode. The reference voltage, VIN, is applied to the IOUT1A pin,
GND
GAIN = R2 + R3
R2
IOUT2A is connected to AGND, and the output voltage is available at
R1 = R2R3
R2 + R3
NOTES
1. SIMILAR CONFIGURATION FOR DAC B.
the VREFA terminal. In this configuration, a positive reference
voltage results in a positive output voltage, making single-supply
operation possible. The output from the DAC is voltage at a
constant impedance (the DAC ladder resistance). Therefore, an
operational amplifier is necessary to buffer the output voltage.
The reference input no longer sees a constant input impedance,
but one that varies with code. Therefore, the voltage input must
be driven from a low impedance source.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 35. Increasing Gain of Current Output DAC
V
DD
R
R
1
2
R
A
V
FB
DD
V
I
I
1A
IN
OUT
V
OUT
V
A
REF
2A
OUT
GND
NOTES
1. SIMILAR CONFIGURATION FOR DAC B.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 34. Single-Supply Voltage-Switching Mode
Rev. C | Page 15 of 24
AD5405
Data Sheet
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
REFERENCE SELECTION
Current steering DACs are very flexible and lend themselves to
many applications. If this type of DAC is connected as the feedback
element of an operational amplifier and RFBA is used as the
input resistor, as shown in Figure 36, the output voltage is
inversely proportional to the digital input fraction, D.
When selecting a reference for use with the AD5405 and other
devices in this series of current output DACs, pay attention to the
reference’s output voltage temperature coefficient specification.
This parameter not only affects the full-scale error, but also can
affect the linearity (INL and DNL) performance. The reference
temperature coefficient must be consistent with the system
accuracy specifications. For example, an 8-bit system required to
hold its overall specification to within 1 LSB over the temperature
range 0°C to 50°C dictates that the maximum system drift with
temperature must be less than 78 ppm/°C. A 12-bit system with
the same temperature range to overall specification within 2 LSBs
requires a maximum drift of 10 ppm/°C. Choosing a precision
reference with low output temperature coefficient minimizes
this error source. Table 7 lists some references available from
Analog Devices, Inc., that are suitable for use with this range of
current output DACs.
For D = 1 − 2−n, the output voltage is
VOUT = −VIN D = −VIN
1− 2−n
V
DD
V
IN
R
A
V
FB
DD
I
1A
OUT
V
A
REF
I
2A
OUT
GND
AMPLIFIER SELECTION
V
OUT
The primary requirement for the current steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code dependent output resistance of the DAC, the
input offset voltage of an operational amplifier is multiplied by the
variable gain of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed on the desired change in output
between the two codes and gives rise to a differential linearity
error, which, if large enough, could cause the DAC to be
nonmonotonic.
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 36. Current Steering DAC Used as a Divider or
Programmable Gain Element
As D is reduced, the output voltage increases. For small values of
the digital fraction D, it is important to ensure that the amplifier
does not saturate and that the required accuracy is met. For
example, an 8-bit DAC driven with the binary code 0x10 (0001
0000)—that is, 16 decimal—in the circuit of Figure 36 can cause
the output voltage to be 16 times VIN. However, if the DAC has a
linearity specification of 0.5 LSB, D can have a weight in the range
of 15.5/256 to 16.5/256 so that the possible output voltage is in
the range of 15.5 VIN to 16.5 VIN—an error of 3%, even though
the DAC itself has a maximum error of 0.2%.
The input bias current of an operational amplifier also generates
an offset at the voltage output as a result of the bias current flowing
in the feedback resistor, RFB. Most operational amplifiers have input
bias currents low enough to prevent significant errors in 12-bit
applications.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the operational amplifier through
the DAC. Because only a fraction, D, of the current into the
Common-mode rejection of the operational amplifier is
important in voltage switching circuits, because it produces a
code dependent error at the voltage output of the circuit. Most
operational amplifiers have adequate common-mode rejection
for use at 12-bit resolution.
V
REF terminal is routed to the IOUT1 terminal, the output voltage
changes as follows:
Provided that the DAC switches are driven from true wideband,
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-switching
DAC circuit is determined largely by the output operational
amplifier. To obtain minimum settling time in this configuration,
minimize capacitance at the VREF node (the voltage output node
in this application) of the DAC. This is done by using low input
capacitance buffer amplifiers and careful board design.
Output Error Voltage Due to DAC Leakage = (Leakage × R)/D
where R is the DAC resistance at the VREF terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that
is, 1/D) of 16, the error voltage is 1.6 mV.
Most single-supply circuits include ground as part of the analog
signal range, which in turn requires an amplifier that can handle
rail-to-rail signals. Analog Devices offers a wide range of single-
supply amplifiers, as listed in Table 8 and Table 9.
Rev. C | Page 16 of 24
Data Sheet
AD5405
Table 7. Suitable Analog Devices Precision References
Part No. Output Voltage (V)
Initial Tolerance (%)
Temp Drift (ppm/°C)
ISS (mA)
Output Noise (µV p-p) Package
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR431
ADR435
ADR391
ADR395
10
10
5
0.05
0.05
0.06
0.06
0.10
0.10
0.10
0.10
0.04
0.04
0.16
0.10
3
9
3
9
3
9
3
9
3
3
9
9
1
1
1
1
1
1
1
1
0.8
0.8
0.12
0.12
20
20
10
10
6
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
SOIC-8
TSOT-23
TSOT-23
5
2.5
2.5
3
3
2.5
5
6
10
10
3.5
8
5
8
2.5
5
Table 8. Suitable Analog Devices Precision Operational Amplifiers
0.1 Hz to 10 Hz
Noise (µV p-p)
Part No.
OP97
OP1177
AD8551
AD8603
AD8628
Supply Voltage (V)
2 to 20
2.5 to 15
2.7 to 5
1.8 to 6
2.7 to 6
VOS (Max) (µV)
IB (Max) (nA)
Supply Current (µA)
Package
25
60
5
50
5
0.1
2
0.05
0.001
0.1
0.5
0.4
1
2.3
0.5
600
500
975
50
SOIC-8
MSOP, SOIC-8
MSOP, SOIC-8
TSOT
850
TSOT, SOIC-8
Table 9. Suitable Analog Devices High Speed Operational Amplifiers
Part No.
AD8065
AD8021
AD8038
AD9631
Supply Voltage (V)
BW at ACL (MHz)
Slew Rate (V/µs)
VOS (Max) (µV) IB (Max) (nA)
Package
5 to 24
2.5 to 12
3 to 12
145
490
350
320
180
120
425
1,300
1,500
1,000
3,000
10,000
6,000
10,500
750
SOIC-8, SOT-23, MSOP
SOIC-8, MSOP
SOIC-8, SC70-5
SOIC-8
3 to 6
7,000
Rev. C | Page 17 of 24
AD5405
Data Sheet
8xC51 to AD5405 Interface
PARALLEL INTERFACE
Figure 38 shows the interface between the AD5405 and the
8xC51 family of DSPs. To facilitate external data memory access,
the address latch enable (ALE) mode is enabled. The low byte of
the address is latched with this output pulse during access to the
external memory. AD0 to AD7 are the multiplexed low order
addresses and data bus; they require strong internal pull-ups when
emitting 1s. During access to external memory, A8 to A15 are
the high order address bytes. Because these ports are open
drained, they also require strong internal pull-ups when
emitting 1s.
Data is loaded into the AD5405 in a 12-bit parallel word format.
Control lines and R/ allow data to be written to or read from
CS
W
the DAC register. A write event takes place when
and R/
W
CS
are brought low, data available on the data lines fills the shift
register, and the rising edge of latches the data and transfers
CS
the latched data-word to the DAC register. The DAC latches are
not transparent; therefore, a write sequence must consist of a
falling and rising edge on
to ensure that data is loaded into
CS
the DAC register and that its analog equivalent is reflected on
the DAC output. A read event takes place when R/ is held high
W
A8 TO A15
ADDRESS BUS
and is brought low. Data is loaded from the DAC register, goes
CS
back into the input register, and is output onto the data line, where
it can be read back to the controller for verification or diagnostic
purposes. The input and DAC registers of these devices are not
AD54051
1
8051
ADDRESS
DECODER
transparent; therefore, a falling and rising edge of
is required
CS
CS
to load each data-word.
WR
R/W
MICROPROCESSOR INTERFACING
ADSP-21xx Processors to AD5405 Interface
DB0 TO DB11
8-BIT
LATCH
ALE
Figure 37 shows the AD5405 interfaced to the ADSP-21xx series
of DSPs as a memory-mapped device. A single wait state may be
necessary to interface the AD5405 to the ADSP-21xx, depending
on the clock speed of the DSP. The wait state can be programmed
via the data memory wait state control register of the ADSP-21xx
(see the ADSP-21xx family user manual for details).
AD0 TO AD7
DATA BUS
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 38. 8xC51 to AD5405 Interface
ADSP-BF504 to ADSP-BF592 Device Family to AD5405
Interface
ADDR TO
ADRR
0
ADDRESS BUS
13
Figure 39 shows a typical interface between the AD5405 and the
ADSP-BF504 to ADSP-BF592 family of DSPs. The asynchronous
memory write cycle of the processor drives the digital inputs of
AD54051
1
ADSP-21xx
ADDRESS
DECODER
DMS
WR
the DAC. The
x line is actually four memory select lines.
CS
AMS
Internal ADDR lines are decoded into
3–0; these lines are
AMS
R/W
then inserted as chip selects. The rest of the interface is a
standard handshaking operation.
DB0 TO DB11
ADDR TO
1
ADDRESS BUS
ADRR
19
DATA 0 TO
DATA 23
DATA BUS
AD54051
1
ADSP-BF5xx
1
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS
DECODER
AMSx
CS
Figure 37. ADSP-21xx to AD5405 Interface
AWE
R/W
DB0 TO DB11
DATA 0 TO
DATA 23
DATA BUS
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 39. ADSP-BF504 to ADSP-BF592 Device Family to AD5405 Interface
Rev. C | Page 18 of 24
Data Sheet
AD5405
Components, such as clocks, that produce fast switching signals
must be shielded with digital ground to avoid radiating noise to
other parts of the board, and they must never run near the
reference inputs.
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. The PCB on which the AD5405 is mounted
must be designed so the analog and digital sections are separated
and confined to certain areas of the board. If the DAC is in a system
where multiple devices require an AGND to DGND connection,
the connection must be made at one point only. The star ground
point must be established as close as possible to the device.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board must run at right angles to each
other. This reduces the effects of feedthrough on the board.
A microstrip technique is by far the best, but its use is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to the ground
plane, and signal traces are placed on the soldered side.
These DACs must have ample supply bypassing of 10 µF in parallel
with 0.1 µF on the supply located as close as possible to the
package, ideally right up against the device. The 0.1 µF capacitor
must have low effective series resistance (ESR) and low effective
series inductance (ESI), like the common ceramic types of cap-
acitors that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors must also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
It is good practice to use compact, minimum lead length PCB
layout design. Leads to the input must be as short as possible to
minimize IR drops and stray inductance.
The PCB metal traces between VREF and RFB must also be
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier must be located as close as
possible to the device.
Figure 40. Schematic of AD5405 Evaluation Board
Rev. C | Page 19 of 24
AD5405
Data Sheet
Figure 41. Component Side Artwork
Figure 42. Silkscreen—Component Side View (Top Layer)
Rev. C | Page 20 of 24
Data Sheet
AD5405
Figure 43. Solder Side Artwork
Rev. C | Page 21 of 24
AD5405
Data Sheet
OVERVIEW OF THE AD5424 TO AD5547 DEVICES
Table 10.
Part No.
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5405
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
Resolution
No. DACs
INL (LSB)
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package1
RU-16, CP-20
RM-10
RU-20
Features
8
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
0.25
0.25
0.25
0.25
0.25
0.5
0.5
0.5
0.5
0.25
1
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
8
8
8
8
RU-10
UJ-8
RM-10
RU-20, CP-20
RU-16
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
RU-24
UJ-8
RM-10
RM-8
0.5
1
1
RU-24
10 MHz BW, 50 MHz serial
CP-40-9
RU-20, CP-20
RU-24
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
1
1
1
0.5
1
2
1
RU-16
UJ-8, RM-8
RM-8
UJ-8, RM-8
RM-8
RU-28
10 MHz BW, 50 MHz serial
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
1
1
1
RM-8
RU-38
2
2
RM-8
RU-28
2
2
RU-16
RU-38
1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
Rev. C | Page 22 of 24
Data Sheet
AD5405
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
31
30
40
1
0.50
BSC
4.25
4.10 SQ
3.95
EXPOSED
PAD
21
20
10
11
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 44. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.75 Package Height
(CP-40-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Resolution INL (LSB) Temperature Range
Package Description
Package Option
CP-40-9
CP-40-9
AD5405YCPZ
AD5405YCPZ–REEL
12
12
1
1
1
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
AD5405YCPZ–REEL7 12
CP-40-9
1 Z = RoHS Compliant Part
Rev. C | Page 23 of 24
AD5405
NOTES
Data Sheet
©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04463-0-1/16(C)
Rev. C | Page 24 of 24
相关型号：
AD5405YCPZ-REEL7
Dual 12-Bit, High Bandwidth, Multiplying DAC with 4 Quadrant Resistors and Parallel Interface
ADI
AD5410ACPZ-REEL7
SERIAL INPUT LOADING, 40 us SETTLING TIME, 12-BIT DAC, QCC40, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40
ROCHESTER
AD5410ACPZ-REEL7
Single-Channel, 12-Bit, Serial Input, 4 mA to 20 mA, Current Source DAC, HART Connectivity
ADI
©2020 ICPDF网 联系我们和版权申明