AD5442ABCPZ-1-RL7 [ADI]
SERIAL INPUT LOADING, 1us SETTLING TIME, 16-BIT DAC, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-220WEED, LFCSP-10;
| 型号： | AD5442ABCPZ-1-RL7 |
| 厂家： | 
ADI |
| 描述： | SERIAL INPUT LOADING, 1us SETTLING TIME, 16-BIT DAC, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-220WEED, LFCSP-10 输入元件 光电二极管 转换器 |
| 文件： | 总24页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.7 V to 5.5 V, Serial-Input,
Voltage-Output, 12-/16-Bit DAC
AD5512A/AD5542A
FEATURES
12-/16-bit resolution
FUNCTIONAL BLOCK DIAGRAM
V
DD
1 LSB INL
11.8 nV/√Hz noise spectral density
1 µs settling time
1.1 nV-sec glitch energy
0.05 ppm/°C temperature drift
5 kV HBM ESD classification
0.375 mW power consumption at 3 V
2.7 V to 5.5 V single-supply operation
R
FB
R
FB
INV
V
REFF
REFS
R
INV
16-BIT DAC
OUT
AGNDF
AGNDS
V
LOGIC
CS
16-BIT DAC LATCH
CONTROL
LOGIC
LDAC
SCLK
DIN
CLR
LDAC
functions
Hardware
and
SERIAL INPUT REGISTER
50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface
Power-on reset clears DAC output to midscale
Available in 3 mm × 3 mm, 10-/16-lead LFCSP and
16-lead TSSOP
AD5512A/
AD5542A
CLR
DGND
Figure 1. 16-Lead TSSOP and 16-Lead LFCSP
APPLICATIONS
Automatic test equipment
Precision source-measure instruments
Data acquisition systems
Medical and aerospace instrumentation
Communication equipment
GND
10
8
7
R
FB
AD5542A-1
R
FB
INV
V
R
INV
1
2
6
16-BIT DAC
REF
OUT
16-BIT DAC LATCH
CS
CLR
5
3
4
CONTROL
LOGIC
SCLK
DIN
SERIAL INPUT REGISITER
9
GENERAL DESCRIPTION
V
DD
The AD5512A/AD5542A are single, 12-/16-bit, serial input,
unbuffered voltage output digital-to-analog converters (DAC)
that operate from a single 2.7 V to 5.5 V supply. The DAC
output range extends from 0 V to VREF and is guaranteed
monotonic, providing 1 LSB INL accuracy at 16 bits without
adjustment over the full specified temperature range of −40°C
to +85°C (AD5542A) or −40°C to +125°C (AD5512A).
Figure 2. 10-Lead LFCSP
Table 1. Related Devices
Part No. Description
AD5040/AD5060 2.7 V to 5.5 V 14-/16-bit buffed output DACs
2.7 V to 5.5 V 16-bit voltage output DACs
18-/20-bit voltage output DACs
16-bit 12 V/ 15 V bipolaꢀ output DAC
4.5 V to 5.5 V, 12-/16-bit quad channel DAC
16-bit, bipolaꢀ, voltage output DAC
AD5541/AD5542
AD5781/AD5791
AD5570
AD5024/AD5064
AD5764
Offering unbuffered outputs, the AD5512A/AD5542A achieve
a 1 μs settling time with low offset errors ideal for high speed
open loop control.
The AD5512A/AD5542A incorporate a bipolar mode of operation
PRODUCT HIGHLIGHTS
that generates a
VREF output swing. The AD5512A/AD5542A
1. 16-bit performance without adjustment.
2. 2.7 V to 5.5 V single supply operation.
3. Low 11.8 nV/√Hz noise spectral density.
4. Low 0.05 ppm/°C temperature drift.
5. 3 mm × 3 mm LFCSP and TSSOP packaging.
also include Kelvin sense connections for the reference and
analog ground pins to reduce layout sensitivity.
The AD5512A/AD5542A are available in a 16-lead LFCSP with
the AD5542A also available in a 10-lead LFCSP and a 16-lead
TSSOP. The AD5512A/AD5542A use a versatile 3-wire interface
that is compatible with 50 MHz SPI, QSPI™, MICROWIRE™, and
DSP interface standards.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010-2011 Analog Devices, Inc. All rights reserved.
AD5512A/AD5542A
TABLE OF CONTENTS
Features .............................................................................................. 1
Unipolar Output Operation...................................................... 15
Bipolar Output Operation......................................................... 16
Output Amplifier Selection....................................................... 17
Force Sense Amplifier Selection............................................... 17
Reference and Ground............................................................... 17
Power-On Reset.......................................................................... 17
Power Supply and Reference Bypassing .................................. 17
Applications Information .............................................................. 18
Microprocessor Interfacing....................................................... 18
AD5512A/AD5542A to ADSP-BF531 Interface .................... 18
AD5512A/AD5542A to SPORT Interface .............................. 18
AD5512A/AD5542A to 68HC11/68L11 Interface .................... 18
AD5512A/AD5542A to ADSP-2101 Interface....................... 18
AD5512A/AD5542A to MICROWIRE Interface .................. 18
Layout Guidelines....................................................................... 19
Galvanically Isolated Interface ................................................. 19
Decoding Multiple DACs.......................................................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 21
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD5512A....................................................................................... 3
AD5542A....................................................................................... 4
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Digital-to-Analog Section ......................................................... 15
Serial Interface ............................................................................ 15
REVISION HISTORY
5/11—Rev. 0 to Rev. A
Changes to Table 3, Power Dissipation Value and Endnote 1 .... 4
Changes to Table 5............................................................................ 6
Changes to Ordering Guide .......................................................... 21
10/10—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD5512A/AD5542A
SPECIFICATIONS
AD5512A
VDD = 2.7 V to 5.5 V, VLOGIC = 2.7 V to 5.5 V, VREF = 2.5 V, AGND = DGND = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter1
Min
Typ
Max
Unit
Test Condition
STATIC PERFORMANCE
Resolution
12
Bits
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Gain Error
Gain Error Temperature Coefficient
Unipolar Zero-Code Error
Unipolar Zero-Code Temperature Coefficient
Bipolar Resistor Matching
0.5
0.5
+0.5
0.1
0.03
0.05
1.0
1.0
2
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
Ω/Ω
%
Guaranteed monotonic
0.5
1
RFB/RINV, typically RFB = RINV = 28 kΩ
Ratio error
0.02
0.07
0.2
0.02
0.07
0.1
±0.08
2
Bipolar Zero Offset Error
Bipolar Zero Temperature Coefficient
Bipolar Zero-Code Offset Error
Bipolar Gain Error
Bipolar Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Voltage Range
LSB
ppm/°C
LSB
LSB
ppm/°C
0.5
2
0
VREF − 1 LSB
+VREF − 1 LSB
V
V
Unipolar operation
Bipolar operation
Tolerance typically 20%
ΔVDD 10%
DAC code = 0x840 (AD5512A) or
0x8400 (AD5542A), frequency = 1 kHz,
unipolar mode
−VREF
DAC Output Impedance
Power Supply Rejection Ratio
Output Noise Spectral Density
6.25
11.8
kΩ
LSB
nV/√Hz
1.0
Output Noise
0.134
μV p-p
0.1 Hz to 10 Hz, unipolar mode
DAC REFERENCE INPUT2
Reference Input Range
Reference Input Resistance3
2.0
9
7.5
VDD
V
kΩ
kΩ
pF
pF
Unipolar operation
Bipolar operation
Code 0x0000
Reference Input Capacitance
26
26
Code 0x3FFF
LOGIC INPUTS
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Input Capacitance2
Hysteresis Voltage2
POWER REQUIREMENTS
VDD
1
0.8
μA
V
V
pF
V
VDD = 2.7 V to 5.5 V
VDD = 2.7 V to 5.5 V
2.4
10
0.15
125
2.7
1.8
5.5
150
5.5
24
V
µA
V
µA
mW
All digital inputs at 0 V, VLOGIC, or VDD
VIH = VLOGIC or VDD and VIL = GND
IDD
VLOGIC
ILOGIC
15
1.5
All digital inputs at 0 V, VLOGIC, or VDD
Power Dissipation
6.05
1 Temperatures are as follows: A version −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
3 Reference input resistance is code-dependent, minimum at 0x855.
Rev. A | Page 3 of 24
AD5512A/AD5542A
AD5542A
VDD = 2.7 V to 5.5 V, VLOGIC = 2.7 V to 5.5 V, VREF = 2.5 V, AGND = DGND = 0 V, −40°C < TA < +85°C, unless otherwise noted.
Table 3.
Parameter1
Min
Typ
Max
Unit
Test Condition
STATIC PERFORMANCE
Resolution
Relative Accuracy (INL)
16
Bits
LSB
0.5
1.0
2.0
1.0
2
B grade
A grade
Guaranteed monotonic
TA = 25°C
Differential Nonlinearity (DNL)
Gain Error
0.5
+0.5
LSB
LSB
3
LSB
Gain Error Temperature Coefficient
Unipolar Zero-Code Error
0.1
0.3
ppm/°C
LSB
LSB
0.7
1.5
TA = 25°C
Unipolar Zero-Code Temperature Coefficient
Bipolar Resistor Matching
0.05
1.000
0.0015
ppm/°C
Ω/Ω
%
RFB/RINV, typically RFB = RINV = 28 kΩ
Ratio error
0.0076
Bipolar Zero Offset Error
1
5
6
LSB
LSB
TA = 25°C
Bipolar Zero Temperature Coefficient
Bipolar Zero-Code Offset Error
0.2
1
ppm/°C
LSB
LSB
LSB
LSB
5
6
5
6
TA = 25°C
TA = 25°C
Bipolar Gain Error
1
Bipolar Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Voltage Range
0.1
ppm/°C
0
VREF − 1 LSB
+VREF − 1 LSB
V
V
Unipolar operation
Bipolar operation
Tolerance typically 20%
ΔVDD 10%
−VREF
DAC Output Impedance
Power Supply Rejection Ratio
Output Noise Spectral Density
6.25
11.8
kΩ
LSB
nV/√Hz
1.0
DAC code = 0x840 (AD5512A) or
0x8400 (AD5542A), frequency = 1 kHz,
unipolar mode
Output Noise
0.134
μV p-p
0.1 Hz to 10 Hz
DAC REFERENCE INPUT2
Reference Input Range
Reference Input Resistance3
2.0
9
7.5
VDD
V
kΩ
kΩ
pF
pF
Unipolar operation
Bipolar operation
Code 0x0000
Reference Input Capacitance
26
26
Code 0xFFFF
LOGIC INPUTS
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Input Capacitance2
Hysteresis Voltage2
POWER REQUIREMENTS
VDD
1
0.8
μA
V
V
VDD = 2.7 V to 5.5 V
VDD = 2.7 V to 5.5 V
2.4
10
pF
V
0.15
125
2.7
1.8
5.5
150
5.5
V
µA
V
All digital inputs at 0 V, VLOGIC, or VDD
VIH = VLOGIC or VDD and VIL = GND
IDD
VLOGIC
ILOGIC
15
0.625
24
0.825
µA
mW
All digital inputs at 0 V, VLOGIC, or VDD
Power Dissipation
1 For 2.7 V ≤ VLOGIC ≤ 5.5 V, temperatures are as follows: A, B versions −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
3 Reference input resistance is code-dependent, minimum at 0x8555.
Rev. A | Page 4 of 24
AD5512A/AD5542A
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VLOGIC = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = D GN D = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 4.
Parameter
Min Typ
Max Unit
Test Condition
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Reference −3 dB Bandwidth
Reference Feedthrough
Digital Feedthrough
Signal-to-Noise Ratio
Spurious Free Dynamic Range
Total Harmonic Distortion
To 1/2 LSB of FS, CL = 10 pF
CL = 10 pF, measured from 0% to 63%
1 LSB change around major carry
All 1s loaded
1
μs
V/µs
nV-sec
MHz
17
1.1
2.2
1
0.2
92
80
74
mV p-p All 0s loaded, VREF = 1 V p-p at 100 kHz
nV-sec
dB
dB
dB
Digitally generated sine wave at 1 kHz
DAC code = 0x3FFF (AD5512A) or 0xFFFF (AD5542A), frequency 10 kHz,
VREF = 2.5 V ± 1 V p-p
Rev. A | Page 5 of 24
AD5512A/AD5542A
TIMING CHARACTERISTICS
VDD = 5 V, 2.5 V ≤ VREF ≤ VDD, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V, unless otherwise noted.
Table 5.
Parameter1, 2 Limit 1.8 ≤ VLOGIC ≤ 2.7 V3 Limit 2.7 V ≤ VLOGIC ≤ 5.5 V4
Unit
Description
fSCLK
t1
t2
14
70
35
35
5
50
20
10
10
5
MHz max SCLK cycle frequency
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns
SCLK cycle time
SCLK high time
t3
SCLK low time
t4
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
t5
5
5
t6
5
5
t7
10
35
5
5
t8
10
4
t9
Data hold time (VINH = 90% of VDD, VINL = 10% of VDD)
Data hold time (VINH = 3 V, VINL = 0 V)
LDAC pulsewidth
t9
5
5
t10
t11
t12
t13
20
10
15
15
20
10
15
15
CS high to LDAC low setup
CS high time between active periods
CLR pulsewidth
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
3 −40°C < TA < +105°C.
4 −40°C < TA < +125°C.
t1
SCLK
t2
t3
t6
t5
t7
t4
CS
t12
t8
t9
1
DB15
DB11
DIN
2
t11
t10
LDAC
t13
CLR
NOTES
1. FOR AD5542A = DB15.
2. FOR AD5512A = DB11.
Figure 3. Timing Diagram
Rev. A | Page 6 of 24
AD5512A/AD5542A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
Rating
VDD to AGND
Digital Input Voltage to DGND
VOUT to AGND
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +0.3 V
10 mA
AGNDF, AGNDS to DGND
Input Current to Any Pin Except Supplies
Operating Temperature Range
AD5512A Industrial (A Version)
AD5542A Industrial (A, B Versions)
Storage Temperature Range
Maximum Junction Temperature (TJ max)
Package Power Dissipation
Thermal Impedance, θJA
TSSOP (RU-16)
ESD CAUTION
−40°C to +125°C
−40°C to +85°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
113°C/W
73°C/W
74°C/W
LFCSP (CP-16-22)
LFCSP (CP-10-9)
Lead Temperature, Soldering
Peak Temperature1
ESD2
260°C
5 kV
1 As per JEDEC Standard 20.
2 HBM classification.
Rev. A | Page 7 of 24
AD5512A/AD5542A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REF
CS
1
2
3
4
5
10 GND
9
8
7
6
V
DD
V
1
2
3
4
12 DGND
11 LDAC
10 CLR
OUT
AD5542A-1
TOP VIEW
Not to Scale
SCLK
DIN
R
FB
AGNDF
AGNDS
REFS
TOP
VIEW
INV
CLR
V
OUT
9
DIN
NOTES
NC = NO CONNECT
(Not to Scale)
1. THE EXPOSED PADDLE SHOULD BE
TIED TO THE POINT OF LOWEST
POTENTIAL, IN THIS CASE, GND.
Figure 4. AD5512A/AD5542A 16-Lead LFCSP Pin Configuration
Figure 5. AD5542A-1 10-Lead LFCSP Pin Configuration
Table 7. AD5512A/AD5542A Pin Function Descriptions
Pin No.
16-Lead
LFCSP
10-Lead
LFCSP
Mnemonic
VOUT
AGNDF
AGNDS
REFS
Description
1
2
3
4
6
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can
range from 2 V to VDD.
5
REFF
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can
range from 2 V to VDD.
6
7
8
2
CS
Logic Input Signal. The chip select signal is used to frame the serial data input.
No Connect.
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be
between 40% and 60%.
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the
rising edge of SCLK.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses
are ignored. When CLR is activated, the DAC register is cleared to the model selectable midscale.
NC
SCLK
3
4
5
9
DIN
CLR
10
11
LDAC
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the
contents of the input register.
12
13
DGND
INV
Digital Ground. Ground reference for digital circuitry.
Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op
amps inverting input in bipolar mode.
7
14
15
16
VLOGIC
VDD
RFB
Logic Power Supply.
Analog Supply Voltage, 5 V 10%.
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
Voltage Reference Input for the DAC. Connect this pin to an external 2.5 V reference. Reference can
range from 2 V to VDD.
9
8
1
REF
10
GND
Ground.
EPAD
Exposed Pad The exposed pad should be tied to the point of lowest potential, in this case, GND.
Rev. A | Page 8 of 24
AD5512A/AD5542A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
V
DD
FB
V
V
LOGIC
OUT
AGNDF
INV
AD5542A
TOP VIEW
(Not to Scale)
AGNDS
REFS
REFF
NC
DGND
LDAC
CLR
DIN
CS
SCLK
NC = NO CONNECT
Figure 6. AD5542A 16-Lead TSSOP Pin Configuration
Table 8. AD5542A Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
RFB
VOUT
AGNDF
AGNDS
REFS
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from
2 V to VDD.
6
REFF
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from
2 V to VDD.
7
8
9
NC
CS
No Connect.
Logic Input Signal. The chip select signal is used to frame the serial data input.
SCLK
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40%
and 60%.
10
11
DIN
CLR
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the DAC register is cleared to the model selectable midscale.
12
LDAC
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
input register.
13
14
DGND
INV
Digital Ground. Ground reference for digital circuitry.
Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amps inverting
input in bipolar mode.
15
16
VLOGIC
VDD
Logic Power Supply.
Analog Supply Voltage, 5 V 10%.
Rev. A | Page 9 of 24
AD5512A/AD5542A
TYPICAL PERFORMANCE CHARACTERISTICS
0.50
0.50
V
V
= 5V
V
V
= 5V
DD
DD
= 2.5V
= 2.5V
REF
REF
0.25
0
0.25
0
–0.25
–0.50
–0.25
–0.50
–0.75
0
8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE
0
8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE
Figure 7. AD5542A Integral Nonlinearity vs. Code
Figure 10. AD5542A Differential Nonlinearity vs. Code
0.25
0.75
V
V
= 5V
V
= 5V
DD
DD
= 2.5V
V
= 2.5V
REF
REF
0
–0.25
–0.50
–0.75
0.50
0.25
0
–0.25
–1.00
–0.50
–60 –40 –20
0
20
40
60
80
100 120 140
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. AD5542A Integral Nonlinearity vs. Temperature
Figure 11. AD5542A Differential Nonlinearity vs. Temperature
0.50
0.75
V
T
= 5V
V
T
= 2.5V
DD
= 25°C
REF
= 25°C
A
A
0.25
0
0.50
0.25
0
DNL
DNL
–0.25
–0.50
INL
–0.25
INL
–0.75
–0.50
2
3
4
5
6
7
0
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 9. AD5542A Linearity Error vs. Supply Voltage
Figure 12. AD5542A Linearity Error vs. Reference Voltage
Rev. A | Page 10 of 24
AD5512A/AD5542A
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
0.15
0.10
0.05
0
V
V
= 5V
V
= 5V
DD
DD
= 2.5V
V
= 2.5V
REF
REF
T
= 25°C
T = 25°C
A
A
–0.05
–0.10
–0.15
–40
25
85
–40
25
TEMPERATURE (°C)
85
TEMPERATURE (°C)
Figure 13. AD5512A/AD5542A Gain Error vs. Temperature
Figure 16. AD5512A/AD5542A Zero-Code Error vs. Temperature
2.0
132
T
= 25°C
A
V
V
= 5V
DD
= 2.5V
REF
130
128
126
124
122
120
118
116
T
= 25°C
A
1.5
1.0
0.5
0
REFERENCE VOLTAGE
= 5V
V
DD
SUPPLY VOLTAGE
= 2.5V
V
REF
0
1
2
3
VOLTAGE (V)
4
5
6
–40
25
85
TEMPERATURE (°C)
Figure 17. AD5512A/AD5542A Supply Current vs. Reference Voltage or
Supply Voltage
Figure 14. AD5512A/AD5542A Supply Current vs. Temperature
200
200
180
160
140
120
100
80
V
V
= 5V
DD
= 2.5V
REF
T
= 25°C
A
150
100
50
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
0
10,000 20,000 30,000 40,000 50,000 60,000 70,000
CODE (Decimal)
DIGITAL INPUT VOLTAGE (V)
Figure 15. AD5512A/AD5542A Supply Current vs. Digital Input Voltage
Figure 18. AD5512A/AD5542A Reference Current vs. Code
Rev. A | Page 11 of 24
AD5512A/AD5542A
V
V
= 2.5V
REF
= 5V
V
V
= 2.5V
REF
= 5V
DD
= 25°C
DD
= 25°C
T
A
T
A
100
100
90
V
(1V/DIV)
DIN (5V/DIV)
OUT
90
V
(50mV/DIV)
OUT
V
(50mV/DIV)
OUT
GAIN = –216
1LSB = V
N
/(2 )–1
10
0
10
0
REF
2µs/DIV
0.5µs/DIV
Figure 19. AD5512A/AD5542A Digital Feedthrough
Figure 22. AD5512A/AD5542A Small Signal Settling Time
5
1.236
1.234
1.232
1.230
1.228
1.226
1.224
5
+125°C
+25°C
–55°C
CS
0
4
3
2
–5
–10
–15
–20
–25
–30
V
OUT
1
0
90
100
110
120
–0.5
0
0.5
TIME (ns)
1.0
1.5
2.0
I
SUPPLY (µA)
DD
Figure 20. AD5512A/AD5542A Digital-to-Analog Glitch Impulse
Figure 23. AD5512A/AD5542A Analog Supply Current Histogram
6
5
4
3
2
+125°C
+25°C
–55°C
V
V
= 2.5V
REF
= 5V
2µs/DIV
DD
= 25°C
T
A
CS (5V/DIV)
100
90
10pF
50pF
100pF
200pF
1
0
10
0
V
(0.5V/DIV)
15
16
17
18
19
OUT
I
AT RAILS (µA)
LOGIC
Figure 21. AD5512A/AD5542A Large Signal Settling Time
Figure 24. AD5512A/AD5542A Digital Supply Current Histogram
Rev. A | Page 12 of 24
AD5512A/AD5542A
40
20
10
V
V
T
= 5V
= 5V
= 25°C
DD
V
V
= 5V
DD
REF
= 2.5V
REF
A
T
= 25°C
A
DATA = 0x0000
0
5
–20
–40
–60
0
–80
–5
–100
0
20
40
60
80
100
120
0
10,000 20,000 30,000 40,000 50,000 60,000 70,000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. AD5512A/AD5542A 0.1 Hz to 10 Hz Output Noise
Figure 28. AD5512A/AD5542A Total Harmonic Distortion
40
35
30
25
20
15
10
V
V
= 5V
DD
= 2.5V
0
–10
–20
–30
–40
REF
T
= 25°C
A
10
5
V
V
= 5V
DD
–50
–60
= 2.5V ± 0.2V
REF
0
600
700
800
900
1000
1100
1200
1300
1400
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 26. AD5512A/AD5542A Noise Spectral Density vs. Frequency,1 kHz
Figure 29. AD5512A/AD5542A Multiplying Bandwidth
14
12
10
8
6
4
V
V
= 5V
DD
2
= 2.5V
REF
T
= 25°C
A
0
9600
9700
9800
9900 10,000 10,100 10,200 10,300 10,400
FREQUENCY (Hz)
Figure 27. AD5512A/AD5542A Noise Spectral Density vs. Frequency, 10 kHz
Rev. A | Page 13 of 24
AD5512A/AD5542A
TERMINOLOGY
Digital-to-Analog Glitch Impulse
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or INL is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL vs. code plot is shown in Figure 7.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by
1 LSB at the major carry transition. A digital-to-analog glitch
impulse plot is shown in Figure 20.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of 1 LSB maximum ensures mono-
tonicity. A typical DNL vs. code plot is shown in Figure 10.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but it is measured when the DAC output is not updated.
Gain Error
CS
is held high while the SCLK and DIN signals are toggled. It
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range.
It is the deviation in slope of the DAC transfer characteristic
from ideal.
is specified in nV-sec and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice
versa. A typical digital feedthrough plot is shown in Figure 19.
Power Supply Rejection Ratio (PSRR)
Gain Error Temperature Coefficient
PSRR indicates how the output of the DAC is affected by changes
in the power supply voltage. The power supply rejection ratio is
quoted in terms of percent change in output per percent change
in VDD for full-scale output of the DAC. VDD is varied by 10%.
Gain error temperature coefficient is a measure of the change
in gain error with changes in temperature. It is expressed in
ppm/°C.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code is loaded to the DAC register.
Reference Feedthrough
Reference feedthrough is a measure of the feedthrough from the
V
REF input to the DAC output when the DAC is loaded with all 0s.
Zero-Code Temperature Coefficient
A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in mV/°C.
expressed in mV p-p.
Rev. A | Page 14 of 24
AD5512A/AD5542A
THEORY OF OPERATION
The AD5512A/AD5542A are single, 12-/16-bit, serial input,
voltage output DACs. They operate from a single supply
ranging from 2.7 V to 5 V and consume typically 125 µA
with a supply of 5 V. Data is written to these devices in a
12-bit (AD5512A) or 16-bit (AD5542A) word format, via a
3- or 4-wire serial interface. To ensure a known power-up
state, these parts are designed with a power-on reset function.
In unipolar mode, the output is reset to midscale; in bipolar
mode, the output is set to 0 V. Kelvin sense connections for the
reference and analog ground are included on the AD5512A/
AD5542A.
SERIAL INTERFACE
The AD5512A/AD5542A are controlled by a versatile 3- or 4-
wire serial interface that operates at clock rates of up to 50 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards. The timing diagram is shown in Figure 3.
CS
Input data is framed by the chip select input, . After a high-
CS
to-low transition on , data is shifted synchronously and
latched into the input register on the rising edge of the serial
clock, SCLK. Data is loaded MSB first in 12-bit (AD5512A)
or 16-bit (AD5542A) words. After 12 (AD5512A) or 16
(AD5542A) data bits have been loaded into the serial input
DIGITAL-TO-ANALOG SECTION
CS
register, a low-to-high transition on transfers the contents
of the shift register to the DAC. Data can be loaded to the part
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 30. The DAC
architecture of the AD5512A/AD5542A is segmented. The four
MSBs of the 16-bit (AD5542A)/12-bit (AD5512A) data-word
are decoded to drive 15 switches, E1 to E15. Each switch
CS
only while
The AD5512A/AD5542A have an
the DAC latch to be updated asynchronously by bringing
CS LDAC
is low.
LDAC
function that allows
LDAC
should be maintained high while
LDAC
low after
data is written to the shift register. Alternatively,
tied permanently low to update the DAC synchronously. With
LDAC CS
goes high.
connects one of 15 matched resistors to either AGND or VREF
The remaining 12 bits of the data-word drive the S0 to S11
switches of a 12-bit voltage mode R-2R ladder network.
.
can be
tied permanently low, the rising edge of loads the data to
R
R
V
OUT
the DAC.
2R
2R
S0
2R . . . . .
S1 . . . . .
2R
2R
E1
2R . . . . .
E2 . . . . .
2R
E15
UNIPOLAR OUTPUT OPERATION
These DACs are capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low supply current, typically
300 μA, and a low offset error. The AD5512A/AD5542A
S11
V
REF
provide a unipolar output swing ranging from 0 V to VREF
.
FOUR MSBs DECODED
INTO 15 EQUAL SEGMENTS
12-BIT R-2R LADDER
The AD5512A/AD5542A can be configured to output both
unipolar and bipolar voltages. Figure 31 shows a typical
unipolar output voltage circuit. The code table for this
mode of operation is shown in Table 9.
Figure 30. DAC Architecture
With this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by
5V
2.5V
the reference is heavily code dependent. The output voltage is
dependent on the reference voltage, as shown in the following
equation:
10µF
0.1µF
0.1µF
VREF × D
SERIAL
INTERFACE
V
REFF
REFS
VOUT
where:
=
DD
2N
AD820/
OP196
CS
UNIPOLAR
OUTPUT
DIN
AD5512A/
AD5542A
V
OUT
SCLK
LDAC
D is the decimal data-word loaded to the DAC register.
N is the resolution of the DAC.
EXTERNAL
OP AMP
DGND AGNDF AGNDS
For a reference of 2.5 V, the equation simplifies to the following:
Figure 31. Unipolar Output
2.5 × D
Table 9. AD5542A Unipolar Code Table
DAC Latch Contents
VOUT
=
65,536
MSB
LSB
Analog Output
VREF × (65,535/65,536)
VREF × (32,768/65,536) = ½ VREF
VREF × (1/65,536)
0 V
This gives a VOUT of 1.25 V with midscale loaded, and 2.5 V
with full scale loaded to the DAC.
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
The LSB size is VREF/65,536.
Rev. A | Page 15 of 24
AD5512A/AD5542A
2.5 V reference and the AD8628 low offset and zero-drift
reference buffer.
Assuming a perfect reference, the unipolar worst-case output
voltage can be calculated from the following equation:
D
Table 10. AD5542A Bipolar Code Table
DAC Latch Contents
VOUT−UNI
=
×
(
VREF + VGE + VZSE + INL
)
2N
MSB
LSB
Analog Output
where:
OUT−UNI is the unipolar mode worst-case output.
D is the code loaded to DAC.
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
+VREF × (32,767/32,768)
+VREF × (1/32,768)
0 V
−VREF × (1/32,768)
−VREF × (32,768/32,768) = −VREF
V
N is the resolution of the DAC.
V
V
V
REF is the reference voltage applied to the part.
GE is the gain error in volts.
ZSE is the zero-scale error in volts.
Assuming a perfect reference, the worst-case bipolar output
voltage can be calculated from the following equation:
INL is the integral nonlinearity in volts.
BIPOLAR OUTPUT OPERATION
[(VOUT− + VOS )(2 + RD) −VREF (1 + RD)]
UNI
V OUT−BIP
=
With the aid of an external op amp, the AD5512A/AD5542A
can be configured to provide a bipolar voltage output. A typical
circuit is shown in Figure 32. The matched bipolar offset resistors,
RFB and RINV, are connected to an external op amp to achieve
this bipolar output swing, typically RFB = RINV = 28 kΩ. Table 10
shows the transfer function for this output operating mode.
Also provided on the AD5542A are a set of Kelvin connections
to the analog ground inputs. The example includes the ADR421
1 + (2 + RD)
A
where:
VOUT−BIP is the bipolar mode worst-case output
VOUT−UNI is the unipolar mode worst-case output.
VOS is the external op amp input offset voltage.
RD is the RFB and RINV resistor matching error.
A is the op amp open-loop gain.
+5V +2.5V
10µF
0.1µF
0.1µF
R
+5V
FB
SERIAL
INTERFACE
V
REFF REFS
DD
R
FB
V
CS
INV
OUT
DIN
R
INV
BIPOLAR
OUTPUT
AD5512A/
AD5542A
SCLK
LDAC
–5V
EXTERNAL
OP AMP
DGND AGNDF AGNDS
Figure 32. Bipolar Output
Rev. A | Page 16 of 24
AD5512A/AD5542A
REFERENCE AND GROUND
OUTPUT AMPLIFIER SELECTION
Because the input impedance is code-dependent, the refer-
ence pin should be driven from a low impedance source. The
AD5512A/AD5542A operate with a voltage reference ranging
from 2 V to VDD. References below 2 V result in reduced accuracy.
The full-scale output voltage of the DAC is determined by the
reference. Table 9 and Table 10 outline the analog output voltage
or particular digital codes. For optimum performance, Kelvin
sense connections are provided on the AD5512A/AD5542A.
For bipolar mode, a precision amplifier should be used and
supplied from a dual power supply. This provides the VREF
output. In a single-supply application, selection of a suitable op
amp may be more difficult because the output swing of the ampli-
fier does not usually include the negative rail, in this case,
AGND. This can result in some degradation of the specified
performance unless the application does not use codes near zero.
The selected op amp must have a very low-offset voltage (the
DAC LSB is 38 μV for the AD5542A with a 2.5 V reference)
to eliminate the need for output offset trims. Input bias current
should also be very low because the bias current, multiplied by
the DAC output impedance (approximately 6 kΩ), adds to the
zero-code error. Rail-to-rail input and output performance is
required. For fast settling, the slew rate of the op amp should
not impede the settling time of the DAC. Output impedance
of the DAC is constant and code-independent, but to minimize
gain errors, the input impedance of the output amplifier should
be as high as possible. The amplifier should also have a 3 dB
bandwidth of 1 MHz or greater. The amplifier adds another
time constant to the system, thus increasing the settling time
of the output. A higher 3 dB amplifier bandwidth results in a
shorter effective settling time of the combined DAC and amplifier.
If the application doesn’t require separate force and sense lines,
tie the lines close to the package to minimize voltage drops
between the package leads and the internal die.
POWER-ON RESET
The AD5512A/AD5542A have a power-on reset function to
ensure that the output is at a known state on power-up. On
power-up, the DAC register contains all 0s until the data is
loaded from the serial register. However, the serial register is
not cleared on power-up; therefore, its contents are undefined.
When loading data initially to the DAC, 16 bits or more should
be loaded to prevent erroneous data appearing on the output.
If more than 16 bits are loaded, the last 16 are kept, and if less
than 16 bits are loaded, bits remain from the previous word.
If the AD5512A/AD5542A must be interfaced with data shorter
than 16 bits, the data should be padded with 0s at the LSBs.
FORCE SENSE AMPLIFIER SELECTION
Use single-supply, low-noise amplifiers. A low-output impedance
at high frequencies is preferred because the amplifiers must be
able to handle dynamic currents of up to 20 mA.
POWER SUPPLY AND REFERENCE BYPASSING
For accurate high-resolution performance, it is recommended
that the reference and supply pins be bypassed with a 10 μF
tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.
Rev. A | Page 17 of 24
AD5512A/AD5542A
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
AD5512A/AD5542A TO 68HC11/68L11 INTERFACE
Microprocessor interfacing to the AD5512A/AD5542A is via
a serial bus that uses standard protocol that is compatible with
DSP processors and microcontrollers. The communications
channel requires a 3- or 4-wire interface consisting of a clock
signal, a data signal, and a synchronization signal. The
AD5512A/AD5542A require a 16-bit data-word with data
valid on the rising edge of SCLK. The DAC update can be
done automatically when all the data is clocked in, or it can
Figure 35 shows a serial interface between the AD5512A/
AD5542A and the 68HC11/68L11 microcontroller. SCK of
the 68HC11/68L11 drives the SCLK of the DAC, and the
CS
MOSI output drives the serial data line serial DIN. The
signal is driven from one of the port lines. The 68HC11/68L11 is
configured for master mode: MSTR = 1, CPOL = 0, and CPHA =
0. Data appearing on the MOSI output is valid on the rising
edge of SCK.
LDAC
be done under the control of the
.
PC6
PC7
LDAC
CS
AD5512A/AD5542A TO ADSP-BF531 INTERFACE
68HC11/
68L11*
AD5512A/
MOSI
SCK
DIN
AD5542A*
The SPI interface of the AD5512A/AD5542A is designed to be
easily connected to industry-standard DSPs and micro-
controllers. Figure 33 shows how the AD5512A/AD5542A
can be connected to the Analog Devices, Inc., Blackfin® D SP.
The Blackfin has an integrated SPI port that can be connected
directly to the SPI pins of the AD5512A/AD5542A.
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 35. AD5512A/AD5542A to 68HC11/68L11 Interface
AD5512A/AD5542A TO ADSP-2101 INTERFACE
Figure 36 shows a serial interface between the AD5512A/
AD5542A and the ADSP-2101. The ADSP-2101 should be
set to operate in the SPORT transmit alternate framing mode.
The ADSP-2101 is programmed through the SPORT control
register and should be configured as follows: internal clock
operation, active low framing, 16-bit word length. Transmission
is initiated by writing a word to the Tx register after the SPORT
has been enabled. As the data is clocked out on each rising edge
of the serial clock, an inverter is required between the DSP and
the DAC, because the AD5512A/AD5542A clock data in on the
falling edge of the SCLK.
AD5512A/
AD5542A
SPISELx
SCK
CS
SCLK
DIN
MOSI
ADSP-BF531
PF9
LDAC
Figure 33. AD5512A/AD5542A to ADSP-BF531 Interface
AD5512A/AD5542A TO SPORT INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 34 shows how one SPORT interface can be used to
control the AD5512A/AD5542A.
FO
TFS
LDAC
CS
AD5512A/
ADSP-2101
DT
DIN
AD5542A*
AD5512A/
AD5542A
SCLK
SCLK
SPORT_TFS
SPORT_TSCK
SPORT_DTO
CS
SCLK
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 36. AD5512A/AD5542A to ADSP-2101 Interface
AD5512A/AD5542A TO MICROWIRE INTERFACE
ADSP-BF527
GPIO0
LDAC
Figure 37 shows an interface between the AD5512A/AD5542A
and any MICROWIRE-compatible device. Serial data is shifted
out on the falling edge of the serial clock and into the AD5512A/
AD5542A on the rising edge of the serial clock. No glue logic
is required because the DAC clocks data into the input shift
register on the rising edge.
Figure 34. AD5512A/AD5542A to ADSP-BF527 Interface
CS
SO
CS
AD5512A/
AD5542A*
MICROWIRE*
DIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 37. AD5512A/AD5542A to MICROWIRE Interface
Rev. A | Page 18 of 24
AD5512A/AD5542A
LAYOUT GUIDELINES
DECODING MULTIPLE DACS
In any circuit where accuracy is important, careful consider-
ation of the power supply and ground return layout helps to
ensure the rated performance. Design the printed circuit board
(PCB) on which the AD5512A/AD5542A is mounted so that
the analog and digital sections are separated and confined to
certain areas of the board. If the AD5512A/AD5542A are in a
system where multiple devices require an analog ground-to-
digital ground connection, make the connection at one point
only. Establish the star ground point as close as possible to the
device.
CS
pin of the AD5512A/AD5542A can be used to select
The
one of a number of DACs. All devices receive the same serial
CS
clock and serial data, but only one device receives the
at any one time. The DAC addressed is determined by the
signal
decoder. There is some digital feedthrough from the digital
input lines. Using a burst clock minimizes the effects of digital
feedthrough on the analog signal channels. Figure 39 shows a
typical circuit.
AD5512A/
SCLK
AD5542A
CS
V
OUT
OUT
OUT
OUT
The AD5512A/AD5542A should have ample supply bypassing
of 10 μF in parallel with 0.1 μF on each supply located as close
to the package as possible, ideally right up against the device.
The 10 μF capacitors are the tantalum bead type. The 0.1 μF
capacitor should have low effective series resistance (ESR)
and low effective series inductance (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching.
DIN
DIN
V
DD
SCLK
ENABLE
AD5512A/
AD5542A
EN
CS
CODED
ADDRESS
V
DECODER
DGND
DIN
SCLK
AD5512A/
AD5542A
CS
V
GALVANICALLY ISOLATED INTERFACE
DIN
SCLK
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry
from any hazardous common-mode voltages that may occur.
iCoupler® products from Analog Devices provide voltage
isolation in excess of 2.5 kV. The serial loading structure
of the AD5512A/AD5542A makes the parts ideal for isolated
interfaces because the number of interface lines is kept to a
minimum. Figure 38 shows a 4-channel isolated interface to
the AD5512A/AD5542A using an ADuM1400. For further
information, visit http://www.analog.com/icouplers.
AD5512A/
AD5542A
CS
V
DIN
SCLK
Figure 39. Addressing Multiple DACs
ADuM14001
CONTROLLER
V
V
V
V
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
TO
SERIAL
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
SCLK
CLOCK IN
TO
DIN
SERIAL
DATA OUT
TO
CS
SYNC OUT
LOAD DAC
OUT
TO
LDAC
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 38. Isolated Interface
Rev. A | Page 19 of 24
AD5512A/AD5542A
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 40. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. A | Page 20 of 24
AD5512A/AD5542A
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
6
10
PIN 1 INDEX
AREA
EXPOSED
PAD
1.74
1.64
1.49
0.50
0.40
0.30
5
1
PIN 1
INDICATOR
TOP VIEW
BOTTOM VIEW
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 42. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Power On
Reset to Code
1 LSB Midscale
Model1
INL
1 LSB
DNL
Package Description
16-Lead LFCSP
16-Lead LFCSP
Package Option Branding
AD5512AACPZ-REEL7
AD5512AACPZ-500RL7
AD5542ABRUZ
AD5542ABRUZ-REEL7
AD5542AARUZ
AD5542AARUZ-REEL7
AD5542ABCPZ-REEL7
AD5542AACPZ-REEL7
AD5442ABCPZ-1-RL7
AD5542ABCPZ-500RL7
EVAL-AD5542ASDZ
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
CP-16-22
CP-16-22
RU-16
DFQ
DFQ
1 LSB
1 LSB
1 LSB
2 LSB
2 LSB
1 LSB
2 LSB
1 LSB
1 LSB
1 LSB Midscale
1 LSB Midscale
1 LSB Midscale
1 LSB Midscale
1 LSB Midscale
1 LSB Midscale
1 LSB Midscale
1 LSB Midscale
1 LSB Midscale
16-Lead TSSOP
16-Lead TSSOP
RU-16
16-Lead TSSOP
RU-16
16-Lead TSSOP
RU-16
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
10-Lead LFCSP_WQ
16-Lead LFCSP
CP-16-22
CP-16-22
CP-10-9
CP-16-22
DFL
DFK
DFM
DFL
AD5541A Evaluation Board
1 Z = RoHS Compliant Part.
Rev. A | Page 21 of 24
AD5512A/AD5542A
NOTES
Rev. A | Page 22 of 24
AD5512A/AD5542A
NOTES
Rev. A | Page 23 of 24
AD5512A/AD5542A
NOTES
©2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09199-0-5/11(A)
Rev. A | Page 24 of 24
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