AD5520JSTZ-REEL1 [ADI]
Per Pin Parametric Measurement Unit/Source Measure Unit; 每个引脚参数测量单元/源测量单元
| 型号： | AD5520JSTZ-REEL1 |
| 厂家： | 
ADI |
| 描述： | Per Pin Parametric Measurement Unit/Source Measure Unit |
| 文件： | 总24页 (文件大小：514K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Per Pin Parametric
Measurement Unit/Source Measure Unit
AD5520
FEATURES
GENERAL DESCRIPTION
Force/measure functions
FIMV, FVMI, FVMV, FIMI, FNMV
Force/measure voltage range 11 V
4 user programmable force/measure current ranges
4 ꢀA, 40 ꢀA, 400 ꢀA, 4 mA (external resistors)
2 user programmable extended current ranges
Up to 6 mA without external driver
Higher currents with external driver
Clamp circuitry and window comparators on board
Guard amplifier
The AD5520 is a single-channel, per pin parametric measure-
ment unit (PPMU) for use in semiconductor automatic
test equipment. The part is also suited for use as a source
measurement unit for instrumentation applications. It
contains programmable modes to force a pin voltage and
measure the corresponding current, or force a current and
measure the voltage. The AD5520 can force/measure over a
±±± ꢀ range or user-programmable currents up to ±ꢁ mA
with its on-board force amplifier. An external amplifier is
required for wider current ranges. The device provides a force
sense capability to ensure accuracy at the tester pin. A guard
output is also available to drive the shield of a force/sense pair.
The AD5520 is available in a 6ꢁ-lead LQFP package.
64-lead LQFP package
APPLICATIONS
Automatic test equipment
Per pin PMU, shared pin PMU, device power supply
instrumentation
Source measure, parametric measurement,
precision measurement
FUNCTIONAL BLOCK DIAGRAM
AV
EE
AV
CC
AD5520
FOH
BW SELECT
FOH3
FOH2
FOH1
FOH0
FIN
MEASI5H
CLAMP
DETECT
MEASI4H
MEASI3H
MEASI2H
MEASI1H
CLH
CLL
MEASI0H
REFGND
G = 16
MEASIOUT
MEASIL
I
SENSE
INST AMP
GUARDIN
GUARD
V
MEASOUT
SENSE
G = 1
INST AMP
MEASVH
MEASVL
G = 1
MEASVOUT
COMPARATOR
CPH
CPOH
AGND
QM5
LOGICS
CPOL
CPL
QM4
CPCK
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices.Trademarks and registered trademarks are theproperty of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD5520
TABLE OF CONTENTS
Features .............................................................................................. ±
Force Control Amplifier............................................................ ±5
Comparator Function and Strobing ........................................ ±5
Clamp Function.......................................................................... ±5
High Current Ranges................................................................. ±5
Circuit Operation ........................................................................... ±6
Force ꢀoltage............................................................................... ±6
Measure Current......................................................................... ±6
Force Current.............................................................................. ±7
Measure ꢀoltage ......................................................................... ±7
Short Circuit Protection ............................................................ ±7
Settling Time Considerations ....................................................... ±8
PCB Layout and Power Supply Decoupling................................ ±9
Typical Connection Circuit for the AD5520 .............................. 20
Typical Application Circuit ........................................................... 2±
Evaluation Board for the AD5520................................................ 22
Outline Dimensions....................................................................... 2ꢁ
Ordering Guide .......................................................................... 2ꢁ
Applications....................................................................................... ±
General Description......................................................................... ±
Functional Block Diagram .............................................................. ±
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... ±0
Theory of Operation ...................................................................... ±3
Interface ........................................................................................... ±ꢁ
Standby Mode ............................................................................. ±ꢁ
Force ꢀoltage or Force Current ................................................ ±ꢁ
Measured Parameter .................................................................. ±ꢁ
Current Ranges ........................................................................... ±ꢁ
RS Selection.................................................................................. ±ꢁ
REVISION HISTORY
9/05—Rev. A to Rev. B
10/03—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Features.......................................................................... ±
Changes to Figure ±.......................................................................... ±
Changes to Specifications................................................................ 3
Changes to Force Current Section................................................ ±7
Changes to Figure 26 ..................................................................... 20
Updated Outline Dimensions....................................................... 2ꢁ
Changes to Ordering Guide .......................................................... 2ꢁ
Changes to Specifications.................................................................3
Updated Ordering Guide .................................................................5
9/03—Revision 0: Initial Version
Rev. B | Page 2 of 24
AD5520
SPECIFICATIONS
AꢀCC = +±5 ꢀ ± 5%, AꢀEE = −±5 ꢀ ± 5%, DꢀDD = 5 ꢀ ± ±0%, AGND = 0 ꢀ, REFGND = 0 ꢀ, DGND = 0 ꢀ. All specifications 0°C to 70°C,
unless otherwise noted.
Table 1.
Parameter
Min
Typ1
Max
Unit
Test Conditions/Comments
VOLTAGE FORCE MODE
Force Control Output Voltage Range
FOH Output Impedance
FOH0
±±±
V
Ω
kΩ
kΩ
Ω
RLOAD = ±0 kΩ, CLOAD = 50 pF
70
2.5
3
500
60
FOH±
FOH2
FOH3
Ω
Input Offset Error
Input Offset Error Temperature Coefficient
Gain Error
±±
±±0
±5
mV
μV/°C
%
±
Clamp Current Error2
CURRENT MEASURE/FORCE
FOH0
FOH±
FOH2
±±
% FS
of FIN
Suggested values; set with external sense resistors
MODE0, RS = ±25 kΩ
MODE±, RS = ±2.5 kΩ
MODE2, RS = ±2.5 kΩ
MODE3, RS = ±25 Ω
±4
μA
μA
μA
mA
±40
±400
±4
FOH3
CURRENT MEASURE MODE
High Sense Input Range, VMEASIxH
Linearity3
Input Bias Current
Input Bias Current Drift±
Output Offset Error
±±±
±0.0±
±3
V
% FSR
nA
pA/°C
mV
mV
mV
+±± V > VFOL > −±± V
±±
50
±±00
±±00
±±00
±±00
MODE0 (±4 μA)
MODE± (±40 μA)
MODE2 (±400 μA)
MODE3 (±4 mA)
mV
Output Offset Error Temperature Coefficient
Gain Error
Gain Error Temperature Coefficient4
MEASIOUT Output Load Current
CMRR
±±0
±0.±
30
±4
95
μV/°C
%
ppm/°C
mA
±0.35
Gain of ±6
dB
@ DC
CURRENT FORCE MODE
Input Offset Error
Gain Error
Clamp Voltage Error2
±±0
±
±±
mV
%
% FS
with MODE0, MODE±, MODE2, MODE3
of FIN
VOLTAGE MEASURE MODE
Differential Input Range
Low Sense Input Voltage Range
Linearity3
Input Offset Error
Input Offset Error Temperature Coefficient±
Gain Error
Gain Error Temperature Coefficient4
Input Bias Current
Input Bias Current Drift4
MEASVOUT Output Load Current
CMRR4
±±±
V
mV
±±00
MEASVL
+0.005 % FSR
+±± V > VMEASVH to VMEASVL > −±± V
FIN = 0 V, measured @ MEASVOUT
±5
±±0
±0.±5
±3
mV
μV/°C
%
ppm/°C
nA
pA/°C
mA
±±5
±0.03
2
±±
50
Gain of ±
@ DC
±4
73
dB
Rev. B | Page 3 of 24
AD5520
Parameter
AMPLIFIER SETTLING TIME4, 5
Min
Typ1
Max
Unit
Test Conditions/Comments
VSENSE Amp
ISENSE Amp
20
±2
μs
μs
to 0.2%
to 0.2%
LOOP SETTLING4, 5
Settling to within 0.024% of 8 V step
MODE0
COMPIN2 = ±00 pF
450
285
±70
2
600
390
240
2.5
ꢀs
ꢀs
MODE±
ꢀs
MODE2, MODE3
MODE0
COMPIN± = ±000 pF
ms
±.8
5.75
50
4.3
±.28
2.4
ms
MODE±, MODE2, MODE3
MODE0, MODE±, MODE2, MODE3
COMPIN2 = ±00 pF
COMPIN± = ±000 pF
COMPIN0 = 3000 pF
COMPIN0 = 3000 pF
SLEW RATE4, 5
8.7
ms
mV/ꢀs
mV/ꢀs
mV/ꢀs
COMPARATOR
CPH, CPL Input Range
Input Offset
±±±
±7
V
mV
VCPH > VCPL
GUARD DRIVER
Output Voltage
±±±
V
Output Impedance
±30
400
±4
Ω
Capacitive load only
Output Offset Voltage
mV
mA
ꢀs
Load Current4
Output Settling Time4
0.5
2
±00 pF capacitive load
ANALOG REFERENCE INPUTS
Force Control Input Range
Force Control Input Impedance
Clamp Control Input Range
Clamp Control Input Impedance
Comparator Threshold Input Range
Comparator Threshold Input Impedance
Input Capacitance4
±±±
±±±
±±±
V
MΩ
V
MΩ
V
MΩ
pF
±
±
VCLH > VCLL
±
3
LEAKAGE CURRENT
MEASIxx, MEASVx, MEASOUT Leakage
ANALOG MEASUREMENT OUTPUTS
Voltage Measure Output Impedance
Current Measure Output Impedance
Multiplexed Sense Output Impedance
Input Capacitance
±3
±20
nA
2
3
±
Ω
Ω
kΩ
MEASIxH, MEASVH, FOHx
LOGIC INPUTS
8
pF
Input Current
±±
0.8
ꢀA
V
V
All digital inputs together
Input Low Voltage, VINL
Input High Voltage, VIHL
Input Capacitance4
2.0
2.4
3
pF
LOGIC OUTPUTS
4
Output Low Voltage, VOL
Output High Voltage, VOH
0.4
V
V
ISINK = 2 mA
ISOURCE = 2 mA
4
Rev. B | Page 4 of 24
AD5520
Parameter
Min
Typ1
Max
Unit
Test Conditions/Comments
POWER REQUIREMENTS
AVCC
AVEE
±4.25
−±4.25 −±5
±5
±5.75
+±5.75
V
V
for specific performance6
Power Supply Rejection Ratio, PSRR±
FOH
−25
−±6
−±5
−55
−±0
90
dB
dB
dB
dB
dB
dB
V
mA
mA
mA
±00 kHz
500 kHz
± MHz
±00 kHz
500 kHz
MEASOUT
DC PSR
DVDD
IAVCC
IAVEE
IDVDD
5
±2
±2
0.5
Digital inputs at supply rails
± Typical values are at 25°C and nominal supply, unless otherwise noted.
2 Full-scale = ±± V.
3 Full-scale range = 22 V.
4 Guaranteed by design and characterization, but not subject to production test.
5 Force control amplifier dominates slew rate and settling time.
6 Operational with ±±2 V supplies, force/measure range is reduced to ±8.5 V.
Rev. B | Page 5 of 24
AD5520
TIMING CHARACTERISTICS
AꢀCC = +±5 ꢀ ± 5%, AꢀEE = −±5 ꢀ ± 5%, AGND = 0 ꢀ, REFGND = 0 ꢀ, DGND = 0 ꢀ. All specifications 0°C to 70°C, unless otherwise
noted.±, 2
Table 2.
DVDD
Parameter
5 V 10%
0
3.3 V
0
Unit
Conditions/Comments
t±
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ꢀs min
ns min
ns min
ns min
CS falling edge to STB falling edge setup time
STB pulse width
t2
30
200
70
t3
40
STB rising edge to CS rising edge setup time
Data setup time
CS falling edge to CPCK rising edge setup time
CPCK pulse width
CPCK to STB falling edge setup time
STB rising edge to QMx, CLxDETECT valid
STB rising edge to CPOH, CPOL valid
Comparator setup time, MODE2, MODE3 settling
Comparator hold time
t4
t5
0
40
550
320
450
±50
±00
240
±50
±00
320
560
320
500
800
440
240
500
440
320
t6
t7
t8
t9
t±0
t±±
t±2
t±3
Comparator output delay time
Comparator strobe pulse width
± See Figure 2.
2 All input signals are specified with tr = tf = ± ns (±0% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
CS
t1
t2
t3
STB
t4
AMx, ACx, FSEL,
MSEL, CPSEL
t5
t6
t7
CPCK
t6
t9
QM4, QM5,
CLHDETECT,
CLLDETECT
CPOL, CPOH
Figure 2. Timing Diagram
t11
MEASVOUT
OR MEASIOUT
CPCK
CPOH, CPOL
t13
t10
t12
Figure 3. Comparator Timing
Rev. B | Page 6 of 24
AD5520
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
AVCC to AVEE
34 V
AVCC to AGND
−0.3 V, +±7 V
AVEE to AGND
+0.3 V, −±7 V
DVDD
−0.3 V to +6 V
Digital Inputs to DGND
Analog Inputs to AGND
CLH to CLL
−0.3 V to DVDD + 0.3 V
AVCC + 0.3 V to AVEE – 0.3 V
−0.3 V to +34 V
−0.3 V to +34 V
AVCC + 0.3 V to AVEE – 0.3 V
CPH to CPL
REFGND, DGND
Operating Temperature Range
Commercial (J Version)
0°C to 70°C
−65°C to +±50°C
±50°C
Storage Temperature Range
Maximum Junction Temperature,
(TJ max)
Package Power Dissipation
Thermal Impedance θJA
(TJ max – TA)/θJA
47.8°C /W
300°C
Lead Temperature
(Soldering ±0 sec)
IR Reflow, Peak Temperature
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 24
AD5520
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CPH
AV
EE_B
PIN 1
2
CPL
MEASI5H
MEASI4H
FOH3
3
4
DV
DD
CPOH
CPOL
5
MEASI3H
FOH2
6
CPCK
AD5520
TOP VIEW
(Not to Scale)
7
DGND
CLHDETECT
CLLDETECT
QM4
MEASI2H
FOH1
8
9
MEASI1H
FOH0
10
11
12
13
14
15
16
QM5
MEASI0H
MEASIL
MEASVH
GUARD(NC)
MEASVL
MOE
CS
STB
AC0
AC1
AV
CC_G
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC = NO CONNECT
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
±
2
3, ±8
CPH
CPL
DVDD
Upper Comparator Threshold Voltage Input, CPH > CPL.
Lower Comparator Threshold Voltage Input, CPL < CPH.
Digital Supply Voltage.
4
5
CPOH
CPOL
Logic Output. When high, indicates MEASVOUT or MEASIOUT > CPH.
Logic Output. When high, indicates MEASVOUT or MEASIOUT < CPL.
6
7, ±7
8
9
±0
CPCK
Logic Input. Used to initiate comparator sampling and update CPOH and CPOL.
Digital Ground.
Logic Output. When high, indicates upper clamp active. See the Clamp Function section.
Logic Output. When high, indicates lower clamp active. See the Clamp Function section.
Logic Output. When high, indicates current range Mode 4 is enabled. May be used to drive external relay or
switch. See the High Current Ranges section.
DGND
CLHDETECT
CLLDETECT
QM4
±±
QM5
Logic Output. When high, indicates current range Mode 5 is enabled. May be used to drive external relay or
switch. See the High Current Ranges section.
±2
±3
±4
MOE
CS
Active Low MEASOUT Enable.
Active Low Logic Input. The device is selected when this pin is low. See the Interface section.
STB
Active Low Logic Input. Used in conjunction with CPCK and CS to configure the device for different
configurations. Rising edge of STB triggers sequence inputs. See the Interface section.
±5
±6
±9
20
2±
22
AC0
Logic Input. Used in conjunction with AC± to select one of three external compensation capacitors.
See the Force Control Amplifier section.
Logic Input. Used in conjunction with AC0 to select one of three external compensation capacitors.
See the Force Control Amplifier section.
Logic Input. Used in conjunction with AM± and AM0 to select one of six current ranges or to enable standby
mode. See the Current Ranges section.
Logic Input. Used in conjunction with AM2 and AM0 to select one of six current ranges or to enable standby
mode. See the Current Ranges section.
AC±
AM2
AM±
AM0
Logic Input. Used in conjunction with AM2 and AM± to select one of six current ranges or to enable standby
mode. See the Current Ranges section.
Logic Input. When high, device is in standby mode of operation. See the Standby Mode section.
STANDBY
Rev. B | Page 8 of 24
AD5520
Pin No. Mnemonic
Description
23
24
25
FSEL
Logic Input. Force mode select. Used to select between current or voltage force operation. See the
Force Voltage or Force Current section.
Logic Input. Measure mode select. Used to connect MEASOUT to either MEASIOUT when high or MEASVOUT
when low.
Logic Input. Comparator select. Used to compare CPL, CPH to MEASVOUT when low, or to MEASIOUT when
high. See the Comparator Function and Strobing section.
MSEL
CPSEL
26
27
28
29
30
3±
32
33
34
35
36
37
38
39
40
4±
42
43
44
45
46
47
48
49
50
5±
52
53
54
55
56
57, 59
58
60
6±
62
63
64
AVEE
AVCC
AGND
AVEE_G
Most Negative Supply Voltage.
Most Positive Supply Voltage.
MEASx Input Ground.
Most Negative Supply Voltage.
Guard Output.
No Connect.
GUARD
NC
GUARDIN
AVCC_G
MEASVL
GUARD(NC)
MEASVH
MEASIL
MEASI0H
FOH0
MEASI±H
FOH±
MEASI2H
FOH2
MEASI3H
FOH3
MEASI4H
MEASI5H
AVEE_B
Guard Input.
Most Positive Supply Voltage.
DUT Voltage Sense Inputs (Low Sense).
No Connect.
DUT Voltage Sense Inputs (High Sense).
DUT Current Sense Inputs (Low Sense).
DUT Current Sense Inputs (High Sense).
Force Control Voltage Output.
DUT Current Sense Inputs (High Sense).
Force Control Voltage Output.
DUT Current Sense Inputs (High Sense).
Force Control Voltage Output.
DUT Current Sense Inputs (High Sense).
Force Control Voltage Output.
DUT Current Sense Inputs (High Sense).
DUT Current Sense Inputs (High Sense).
Most Negative Supply Voltage.
External Force Driver Control Voltage Output.
Most Positive Supply Voltage.
Compensation Capacitor 0 Output.
Compensation Capacitor ± Output.
Compensation Capacitor 2 Output.
Compensation Capacitor 0 Input.
Compensation Capacitor ± Input.
Compensation Capacitor 2 Input.
Analog Input/Output Reference Ground.
Multiplexed DUT Voltage/Current Sense Output. See the Measured Parameter section.
DUT Current Sense Output.
FOH
AVCC_B
COMPOUT0
COMPOUT±
COMPOUT2
COMPIN0
COMPIN±
COMPIN2
REFGND
MEASOUT
MEASIOUT
MEASVOUT
FIN
DUT Voltage Sense Output.
Force Control Voltage Input.
Upper Clamp Voltage Input CLH > CLL.
Lower Clamp Voltage CLL < CLH.
CLH
CLL
Rev. B | Page 9 of 24
AD5520
TYPICAL PERFORMANCE CHARACTERISTICS
0.0030
0.0030
0.0025
0.0020
V
V
= +15V
= –15V
V
V
= +15V
= –15V
DD
DD
SS
SS
MODE 3
MODE 3
0.0025
0.0020
0.0015
0.0010
0.0015
0.0010
0.0005
0
0.0005
0
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Voltage Sense Amplifier Linearity vs. Temperature
Figure 8. Current Sense Linearity vs. Temperature
80
140
120
V
V
T
= +15V
= –15V
= 25°C
I
CMRR
SENSE
DD
SS
V
V
= +15V
= –15V
= 25°C
DD
SS
70
60
50
40
A
T
A
100
80
60
40
30
20
20
0
10
0
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Voltage Sense Amplifier CMRR vs. Frequency
Figure 9. Current Sense Amplifier CMRR vs. Frequency
10
5
0
–5
C
= 0.1nF
0
COMP
–10
–20
C
= 0.1nF
COMP
–10
–15
–20
C
= 1.0nF
COMP
C
= 1.0nF
COMP
–30
–40
–25
–30
C
= 3.3nF
10k
COMP
C
= 3.3nF
10k
COMP
V
V
= +15V
= –15V
= 25°C
V
V
= +15V
= –15V
–50
–60
DD
SS
DD
SS
–35
–40
T
T = 25°C
A
A
100
1k
100k
100
1k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Force Amplifier Bandwidth, Mode 0 (4 μA)
Figure 10. Force Amplifier Bandwidth, Mode 1 (40 μA)
Rev. B | Page ±0 of 24
AD5520
0
0
V
V
= +15V
= –15V
= 25°C
V
V
= +15V
= –15V
DD
SS
DD
SS
–5
–10
–15
–20
–25
–30
–35
–5
–10
–15
–20
–25
–30
–35
T
T = 25°C
A
A
C
= 0.1nF
C
= 0.1nF
COMP
COMP
C
= 1.0nF
C
= 1.0nF
COMP
COMP
C
= 3.3nF
C
= 3.3nF
COMP
COMP
–40
–45
–40
–45
100
1k
10k
FREQUENCY (Hz)
100k
100
1k
10k
FREQUENCY (Hz)
100k
Figure 11. Force Amplifier Bandwidth, Mode 2 (400 μA)
Figure 14. Force Amplifier Bandwidth, Mode 3 (4 mA)
5
0
30
20
10
0
V
V
= +15V
= –15V
= 25°C
DD
SS
T
A
I
SENSE
–5
–10
–15
–20
–25
–30
–10
V
SENSE
–20
–30
V
V
= +15V
= –15V
= 25°C
DD
SS
–35
–40
T
A
1
10
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12. Guard Amplifier Bandwidth
Figure 15. Voltage Sense and Current Sense Amplifier Bandwidths
20
10
0
V
V
= +15V
= –15V
= 25°C
V
V
= +15V
= –15V
DD
SS
DD
SS
T
T = 25°C
A
A
–5
–10
–15
–20
0
–10
–20
–30
–40
–50
–60
–25
–30
100k
1M
10M
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. Current Sense Amplifier AC PSRR
Figure 16. Force Amplifier AC PSRR, Mode 3, CCOMP = 100 pF
Rev. B | Page ±± of 24
AD5520
20
16
V
V
= +15V
= –15V
= 25°C
DD
SS
14
12
10
8
10
T
A
V
CC
0
–10
–20
–30
–40
6
4
V
2
DUT
–50
–60
0
–2
100k
1M
10M
0
5
10
15
20
25
30
35
40
45
FREQUENCY (Hz)
TIME (ms)
Figure 17. Voltage Sense Amplifier AC PSRR
Figure 19. Power Up
700
9
8
7
6
5
4
COMPIN2 = 100pF
COMPIN1 = 1000pF
600
500
GUARD
400
300
200
COMPIN2 = 3000pF
V
SENSE
3
2
1
FOH
100
0
0
I
SENSE
100
–1
10
1k
FREQUENCY (Hz)
10k
100k
0
0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008
TIME (s)
Figure 18. Noise Spectral Density
Figure 20. Settling Time, Mode 2
Rev. B | Page ±2 of 24
AD5520
THEORY OF OPERATION
The AD5520 is a single-channel per pin parametric measure-
ment unit (PPMU) for use in semiconductor automatic test
equipment. It contains programmable modes to force a pin
voltage and measure the corresponding current (FꢀMI), force
current measure voltage (FIMꢀ), force current measure current
(FIMI), force voltage measure voltage (FꢀMꢀ), and force
nothing measure voltage (FNMꢀ). The PPMU can force or
measure a voltage from −±± ꢀ to +±± ꢀ. It can force or measure
currents up to 6 mA using the internal amplifier, while the
addition of an external amplifier enables higher current ranges.
External resistors allow users to choose the optimum ranges for
their needs.
The AD5520 has an on-board window comparator that
provides two bits of useful information, DUT too low or too
high. Also provided on the chip is clamp circuitry that flags via
CLHDETECT and CLLDETECT if the voltage applied to FIN
or across the DUT exceeds the voltage applied to CLL and CLH.
On-chip is clamp circuitry that clamps the output of the force
amplifier if the voltage at MEASIOUT and MEASꢀOUT
exceeds CLL or CLH.
The device provides a force sense capability to ensure accuracy
at the tester pin. A guard output is also available to drive the
shield of a force/sense pair.
Rev. B | Page ±3 of 24
AD5520
INTERFACE
The AD5520 PPMU is controlled via a number of digital inputs,
which are discussed in detail in the following sections. All
MEASURED PARAMETER
MEASOUT is a muxed output that tracks the sensed parameter.
MSEL (digital input) connects the MEASOUT to the output of
the current sense amplifier or the voltage sense amplifier,
depending on which is the measured parameter of interest.
CS
inputs are TTL-compatible.
is used to select the device while
(active low input) latches data available on the other digital
inputs and updates any required digital outputs. The rising edge
STB
STB
of
triggers sequence inputs. The remaining digital inputs
The MEASOUT pin is connected back to an ADC to allow the
measured value to be converted to a digital code.
control the function of the PMU. They also determine which
measure mode the PMU is in, the compensation capacitor used,
and the selected current range.
Table 7. MEASOUT Connected to Voltage or Current
MSEL
Function
STANDBY MODE
Low
High
MEASOUT = DUT Voltage
MEASOUT = DUT Current
The AD5520 can be placed into standby mode via the standby
logic input. In this mode, the force amplifier is disconnected
from the force input (FIN). In addition, the switch in series with
the force output pins (FOHx) is opened, and the current
measure amplifier is disconnected from the sense resistors. The
voltage measure amplifier is still connected across the DUT;
therefore, DUT voltage measurements may still be made while
in standby mode. Figure 2± shows the configuration of the
PMU while in standby mode.
The MEASOUT pin can also be made high impedance through
the MOEB logic input.
Table 8. MOEB Allows MEASOUT to Go High Impedance
MOEB
Function
Low
High
Enable MEASOUT Output
Hi-Z MEASOUT Output
CURRENT RANGES
Table 5. Standby Mode
Standby
A number of current ranges are possible with the AD5520. The
AM0, AM±, and AM2 pins are digital inputs used to establish
full-scale current range of the PMU.
Function
Low
High
Normal Force Mode
Standby Mode
Table 9. Selection of Current Range
AM0 AM1 AM2 Function
DAC
Low
High Low
Low
High High Low
Low Low
Low
Low
Low
Current Range MODE0 (4 ꢀA)
Current Range MODE± (40 ꢀA)
Current Range MODE2 (400 ꢀA)
Current Range MODE3 (4 mA)
FIN
FOHx
High Low
High Current Range MODE4
MEASIHx
MEASIL
G = 16
G = 1
MEASIOUT
MEASVOUT
R
(External Buffer Mode)
S
High Low
High Current Range MODE5
(External Buffer Mode)
MEASVH
MEASVL
Low
High High Standby (Same as STANDBY = High)
DUT
High High High Standby (Same as STANDBY = High)
RS SELECTION
Figure 21. PMU in Standby Mode
The AD5520 is designed to ensure the voltage drop across each
of the RS resistors is less than ±500 mꢀ when maximum current
is flowing through them. To support other current ranges, these
sense resistor values can be changed. The force amplifier can
drive a maximum of 6 mA. It is not recommended to increase
the maximum current above the nominal range.
FORCE VOLTAGE OR FORCE CURRENT
FSEL is an input that determines whether the PPMU forces a
voltage or current.
Table 6. FSEL Function
FSEL Function
Low
Voltage Force and Current Clamp with MEASIOUT Voltage
The two external current ranges use an external buffer to drive
higher current. The example in Figure 26 uses ꢁ0 mA and
±60 mA ranges. These ranges can be changed to suit user
requirements for a high current range.
High Current Force and Voltage Clamp with MEASVOUT Voltage
Rev. B | Page ±4 of 24
AD5520
FORCE CONTROL AMPLIFIER
CLAMP FUNCTION
The force control amplifier requires external capacitors
connected between the COMPOUTx and COMPINx pins.
For stability with large capacitance at the DUT, the largest
capacitance value (3000 pF) should be selected. The force
control amplifier should always contribute the dominant
pole in the control loop. Settling times increase with
larger capacitances. ACx inputs select which external
compensation capacitor is used.
Clamp circuitry, which is also included on-chip, clamps the
force amplifier’s output if the voltage or current applied to the
DUT exceeds the clamp levels, CLL and CLH. The clamp
circuitry also comes into play in the event of a short or open
circuit. When in force current range, the voltage clamps protect
the DUT from an open circuit. Likewise, when forcing a voltage
and a short circuit occurs, the current clamps protect the DUT.
The clamps also function to protect the DUT if a transient
voltage or current spike occurs when changing to a different
operating mode, or when programming the device to a different
current range.
Table 10. AC0, AC1 Compensation Capacitor Selection
AC0
Low
High
Low
AC1
Low
Low
High
Function
Select External Compensation Capacitor 0
Select External Compensation Capacitor ±
Select External Compensation Capacitor 2
The digital output flags, which indicate a clamp limit has been
hit, are CLHDETECT for the upper clamp, and CLLDETECT
output for the lower clamp.
COMPARATOR FUNCTION AND STROBING
Table 13. Clamp Detect Outputs
The AD5520 has an on-board window comparator that
provides two bits of useful information, DUT too low or
DUT too high. CPSEL is the digital input that controls
this function, selecting whether it should compare to the
voltage sense or the current sense amplifier.
CLHDETECT
Function
Low
High
Upper Clamp Inactive
Upper Clamp Active
Function
CLLDETECT
Low
High
Lower Clamp Inactive
Lower Clamp Active
Table 11. Comparator Function Select
CPSEL
Function
Low
High
Compare CPL, CPH to MEASVOUT
Compare CPL, CPH to MEASIOUT
HIGH CURRENT RANGES
With the use of an external high current amplifier, two high
current ranges are possible. The current range values can be set
as required in the application through appropriate selection of
the sense resistors connected between MEASI5H, MEASIꢁH,
and MEASIL. When one of these high current ranges (Mode ꢁ
or Mode 5) is selected via the AMx control lines, the appro-
priate QMꢁ or QM5 output is enabled. As a result, these outputs
can be used to control relays connected in series with the high
current amplifier, as shown in Figure 26.
After CPSEL has selected which amplifier output is of interest,
logic input CPCK is used to initiate comparator sampling and
update the logic outputs CPOH and CPOL. This indicates
whether the voltages at MEASIOUT or MEASꢀOUT have
exceeded voltages set at CPL or CPH (thus providing DUT too
STB
high or DUT too low information). A rising edge on
required to clock the CPOH and CPOL data out.
is
Table 12. CPCK Synchronous Logic Outputs
Table 14. High Current Range Logic Outputs
CPOH
Function
QM4
High
Low
QM5
Function
Low
High
MEASVOUT or MEASIOUT < CPH MEASVOUT or
MEASIOUT > CPH
Low
High
Current Range Mode 4 Enable Output
Current Range Mode 5 Enable Output
CPOL
Function
Low
High
MEASVOUT or MEASIOUT > CPL MEASVOUT or
MEASIOUT < CPL
Rev. B | Page ±5 of 24
AD5520
CIRCUIT OPERATION
FORCE VOLTAGE
MEASURE CURRENT
Most PMU measurements are performed while in force voltage
and measure current modes; for example, when the device is
used as a device power supply, or in continuity or leakage
testing. In the force voltage mode, the voltage at analog input
FIN is mapped directly to the voltage forced at the DUT.
Figure 23 shows a simplified diagram of the PMU when in force
voltage mode. The control loop consists of the force amplifier
with the voltage sense amplifier making up the feedback path.
Current flowing through the DUT is measured by sensing the
current flowing through a selectable sense resistor, which is in
series with the DUT. The current sense amplifier (Gain = ±6)
generates a voltage at its output, which is proportional to the
current flowing through the DUT. This voltage is compared to
the CLL and CLH levels to ensure the clamp voltages have not
When in force voltage and measure current modes, the
maximum voltage applied to the input corresponds to the
maximum current outputs. Figure 22 shows the transfer
function when forcing a voltage.
STB
been exceeded. Strobing CPCK and
provides information
V
about the voltage level with respect to the comparator levels,
CPH and CPL.
DUT
FIN
R
S
DUT
V
×
CLH
R
× 16
FOHx
MEASIHx
G = 16
G = 1
VFIN
R
R
CLH
CLL
S
V
FIN
MEASIL
MEASVH
R
S
DUT
V
×
CLL
DUT
R
× 16
VCLL
VCLH
MEASVL
REFGNDI/V
V
V
VMEASVOUT
VMEASIOUT
I
DUT
V
V
> I
< I
× R × 16
V
V
< I
< I
× R × 16
V
V
> I
> I
× R × 16
S
CLH
CLL
DUT
DUT
S
CLH
CLL
DUT
DUT
S
CLH
CLL
DUT
DUT
CONDITION
OUTPUT
× R × 16
× R × 16
× R × 16
S
S
S
V
= V
V
= V
V
= V
DUT CLL
DUT
FIN
DUT
CLH
V
S
Figure 23. Force Voltage, Measure Current Mode
CLH
R
× 16
V
CLH
V
FIN
V
CLH
V
S
CLL
R
× 16
Figure 22. Force Voltage Transfer Function
Rev. B | Page ±6 of 24
AD5520
FORCE CURRENT
SHORT CIRCUIT PROTECTION
In force current mode, the voltage at FIN is now converted to a
current through the following relationship:
The AD5520 is designed to withstand a direct short circuit on
any of the amplifier outputs.
Force Current = VFIN/(RSENSE × ±6)
Figure 25 illustrates the transfer function of the current force
mode.
Figure 2ꢁ shows a simplified diagram of the PMU when in force
current mode. The control loop consists of the force amplifier
with the current sense amplifier making up the feedback path.
In this case, voltage at the DUT is sensed across the voltage
measure amplifier (Gain = ±) and presented at the MEASꢀOUT
output.
I
DUT
V
R
CLH
DUT
FIN
V
FIN
FOHx
MEASIHx
V
CLL
R
DUT
G = 16
G = 1
VFIN
R
R
CLH
CLL
S
MEASIL
MEASVH
DUT
VCLL
VCLH
MEASVL
REFGNDI/V
V
DUT
V
V
VMEASVOUT
VMEASIOUT
V
CLH
V
V
> V
< V
V
V
< V
< V
V
V
> V
> V
CLH
CLL
DUT
DUT
CLH
CLL
DUT
DUT
CLH
CLL
DUT
DUT
CONDITION
OUTPUT
V
V
V
FIN
CLH
CLL
I
=
I
=
I
DUT
=
DUT
DUT
R
R
R
S
S
S
V
CLH
V
Figure 24. Current Force, Voltage Measure Mode
FIN
V
CLH
MEASURE VOLTAGE
V
CLH
A DUT voltage is tested via the voltage measure amplifier by a
window comparator to ensure that CPH and CPL levels are not
exceeded. In addition, the DUT voltage is automatically tested
against the voltage levels at the clamp, and clamp flags are
enabled if the DUT voltage exceeds either of the levels.
Figure 25. Current Force Transfer Function
Rev. B | Page ±7 of 24
AD5520
SETTLING TIME CONSIDERATIONS
Fast throughput is a key requirement in automatic test
equipment because it relates directly to the cost of manufac-
turing the DUT; thus reducing the time required to make a
measurement is of greatest importance. When taking
measurements using a PMU, the limiting factor is usually the
time it takes the output to settle to the required accuracy so a
measurement can be taken. DUT capacitance, measurement
accuracy, and the design of the PMU are the major contributors
to this time.
When selecting a faster settling time, there is a trade-off.
A small compensation value results in faster settling, but
may incur penalties in overshoots or ringing at the DUT.
Compensation capacitor selection should be optimized to
ensure minimum overshoots while still giving decent settling
time performance.
While careful selection of the compensation capacitor is
required to minimize the settling time, another factor can
greatly contribute to the overall settling of the loop if the
feedback loop is broken in some manner, and the force control
amplifier goes to either the positive or negative rails. There is a
finite amount of time required for the amplifier to recover from
this condition, typically 85 μs, which adds to the settling of the
loop. Ensuring that the force control amplifier never goes into
saturation is the best solution. This solution can be helped by
putting the device into standby mode any time the operating
mode or range selection is changed. In addition, ensure that the
selected output range can supply the required current needed by
the DUT.
Figure 26 shows a simplified block diagram of the AD5520
PMU. In brief, the device consists of a force control amplifier,
access to a number of selectable sense resistors, a voltage
measure instrumentation amplifier, and a current measure
instrumentation amplifier. To optimize the performance of the
device, there are also nodes provided where external compensa-
tion capacitors are added. As mentioned, making an accurate
measurement in the fastest time while avoiding overshoots and
ringing is the key requirement in any automatic test equipment
(ATE) system. Doing so provides challenges, however. The
external compensation capacitors set up different settling times
or bandwidths on the force control amplifier, and while one
compensation capacitor value may suit one range, it may not
suit other ranges. To optimize measurement performance and
speed, differences in signal behavior on each range and
frequency of use of each range need to be taken into account.
Rev. B | Page ±8 of 24
AD5520
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful considera-
tion to the power supply and the ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5520 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the PMU is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other parts of the
board and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best but not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to the ground plane
while signal traces are placed on the solder side.
This PMU should have ample supply bypassing of ±0 μF in
parallel with 0.± μF on the supply and should be located as close
as possible to the package, ideally right up against the device. The
0.± μF capacitor should have low effective series resistance (ESR)
and effective series inductance (ESI), such as the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal
logic switching. Low ESR (± μF to ±0 μF) tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
It is good practice to use compact, minimum lead length PCB
layout design. Leads to the input should be as short as possible
to minimize IR drops and stray inductance.
Rev. B | Page ±9 of 24
AD5520
TYPICAL CONNECTION CIRCUIT FOR THE AD5520
Figure 26 shows the AD5520 as connected in a typical applica-
tion. The external components required are three compensation
capacitors and six sense resistors, depending on the number of
ranges required. If high current ranges >6 mA are required, an
external amplifier must be used with relays (or some form of
high current switch) to switch in the different current ranges to
the DUT. Other components are also required to make the
PMU function.
The PMU requires a number of discrete voltage levels: five DAC
levels for each PMU used in the system, two levels each for the
comparator and clamps, and one voltage level for the AD5520
force input voltage. To use the information measured at the
DUT, an ADC such as the AD7665 (a ±6-bit ADC), must be
connected to the MEASOUT pin to convert the measured
current or voltage to digital for analysis.
3000pF
1000pF
100pF
+15V –15V
AV
AV
CC
EE
AD5520
AD815
FOH
BW SELECT
RELAY
FOH3
FOH2
FOH1
FOH0
FIN
FORCE
AMPLIFIER
<±11.5V
3.126Ω
MEASI5H
CLAMP
DETECT
MEASI4H
MEASI3H
MEASI2H
12.5Ω
125Ω
CLH
CLL
MEASI1H
MEASI0H
1.25kΩ
12.5kΩ
REFGND
125kΩ
G = 16
MEASIOUT
MEASIL
I
SENSE
INST AMP
GUARDIN
GUARD
MEASOUT
V
G = 1
SENSE
±≥ 11V
INST AMP
MEASVH
MEASVL
G = 1
DUT
MEASVOUT
COMPARATOR
CPH
AGND
QM5
<±100mV
CPOH
LOGICS
QM4
CPOL
CPL
CPCK
Figure 26. Typical Configuration of the AD5520 as Used in an ATE Circuit
Rev. B | Page 20 of 24
AD5520
TYPICAL APPLICATION CIRCUIT
Figure 27 shows the AD5520 as in an ATE system. This device
can used as a per pin parametric unit in order to speed up the
rate at which testing can be done. It can also be used as a DUT
power supply, as shown in the application circuit.
The flexible function of the AD5520 also makes it suited for use
in instrumentation applications such as source measure units.
Source measure units are programmable instruments capable of
sourcing and measuring voltage or current simultaneously. The
AD5520 provides a more integrated solution in such
equipment.
The central PMU shown in the block diagram (Figure 27) is
usually a highly accurate PMU and is shared among a number
of pins in the tester. In general, many discrete levels are required
in an ATE system for the pin drivers, comparators, clamps, and
active loads. DAC devices, such as the AD5379, offer a highly
integrated solution for a number of these levels. The AD5379 is
a dense ꢁ0-channel DAC designed with high channel
requirements, such as ATE.
CENTRAL PMU
DAC
GUARD AMP
PPMU
DAC
ADC
VCH
DAC
ADC
VTERM
DAC
VH
TIMING DATA
MEMORY
DEVICE UNDER
TEST (DUT)
DAC
RELAYS
50Ω COAX
TIMING
GENERATOR
DLL, LOGIC
FORMATTER
DE-SKEW
DRIVER
VL
VCL
GUARD
AMP
DAC
DAC
DAC
GND SENSE
DEVICE POWER
SUPPLIES
VTH
VTL
DAC
COMPARE
MEMORY
FORMATTER
DE-SKEW
COMP
ADC
DAC
ACTIVE LOAD
IOL
DAC
DAC
VCOM
DAC
IOH
Figure 27. Typical Application ATE Circuit
Rev. B | Page 2± of 24
AD5520
EVALUATION BOARD FOR THE AD5520
A full-featured evaluation kit is available for the AD5520. It
includes an evaluation board with direct hookup via a 36-way
Centronics connector to a PC. PC-based software to control the
AD5520 is also part of the evaluation kit. The evaluation board
schematic is shown in Figure 28.
Both AGND and DGND inputs are provided on the board. The
AGND and DGND planes are connected at one location close
to the AD5520. It is recommended not to connect AGND and
DGND elsewhere in the system to avoid ground loop problems.
REFGND is routed back to AGND at the power block to
maintain a clean ground reference for accurate measurements.
Note that ꢀDD and ꢀSS must provide sufficient headroom for the
force and measure voltage range. In addition to the supply
voltages for the evaluation board, it is necessary to provide the
voltage levels for the clamp, comparator, and the force input
pins (CLL, CLH, CPL, CPH, and FIN). SMB connections are
provided for these voltage inputs. To use the evaluation board, it
is also necessary to provide a DUT connected via the gold pins.
Each supply is decoupled to the relevant ground plane with
±0 μF and 0.± μF capacitors. The device supply pin is again
decoupled with a ±0 μF and 0.± μF capacitor pair to the relevant
ground plane.
Care should be taken when replacing devices to ensure that the
pins line up correctly with the PCB pads.
Rev. B | Page 22 of 24
AD5520
R L 2
– G Y 6 L H A R E
R L 1
R 7
R 6
– G Y 6 L H A R E
Ω 4 1 2 . R 5 ,
Ω
1 2 4 R 4 ,
Ω
2 4 k 1 . R 3 ,
Ω 4 k 1 2 . R 2 ,
Ω
1 2 4 R k 1 ,
D [ 0 : 7 ]
Figure 28. Evaluation Board Schematic
Rev. B | Page 23 of 24
AD5520
Preliminary Technical Data
OUTLINE DIMENSIONS
0.75
0.60
0.45
12.00
BSC SQ
1.60
MAX
64
49
48
1
PIN 1
10.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
16
33
32
0.15
0.05
SEATING
PLANE
17
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 29. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5520JST
AD5520JST-REEL
AD5520JSTZ-REEL±
EVAL-AD5520EB
Temperature Range
0°C to 70°C
0°C to 70°C
Package Description
Package Option
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board and Software
ST-64-2
ST-64-2
ST-64-2
0°C to 70°C
± Z = Pb-free part.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03701-0-9/05(B)
Rev. B | Page 24 of 24
相关型号：
AD5530BRUZ-REEL
SERIAL INPUT LOADING, 20us SETTLING TIME, 12-BIT DAC, PDSO16, LEAD FREE, MO-153AB, TSSOP-16
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