AD5533ABC-1REEL [ADI]
IC SAMPLE AND HOLD AMPLIFIER, PBGA74, 12 X 12 MM, LFBGA-74, Sample and Hold Circuit;
| 型号： | AD5533ABC-1REEL |
| 厂家： | 
ADI |
| 描述： | IC SAMPLE AND HOLD AMPLIFIER, PBGA74, 12 X 12 MM, LFBGA-74, Sample and Hold Circuit 放大器 |
| 文件： | 总16页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32-Channel Infinite
Sample-and-Hold
a
AD5533*
GENERAL DESCRIPTION
FEATURES
The AD5533 combines a 32-channel voltage translation function
with an infinite output hold capability. An analog input voltage
on the common input pin, VIN, is sampled and its digital repre-
sentation transferred to a chosen DAC register. VOUT for this
DAC is then updated to reflect the new contents of the DAC
register. Channel selection is accomplished via the parallel address
inputs A0–A4 or via the serial input port. The output voltage
range is determined by the offset voltage at the OFFS_IN pin
and the gain of the output amplifier. It is restricted to a range
from VSS + 2 V to VDD – 2 V because of the headroom of the
output amplifier.
Infinite Sample-and-Hold Capability to ؎0.018% Accuracy
High Integration: 32-Channel SHA in 12
؋
12 mm2 LFBGA Per Channel Acquisition Time of 16 s max
Adjustable Voltage Output Range
Output Voltage Span 10 V
Output Impedance 0.5 ⍀
Readback Capability
DSP-/Microcontroller-Compatible Serial Interface
Parallel Interface
Temperature Range –40؇C to +85؇C
APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
The device is operated with AVCC = 5 V 5%, DVCC = 2.7 V to
5.25 V, VSS = –4.75 V to –16.5 V and VDD = 8 V to 16.5 V and
requires a stable 3 V reference on REF_IN as well as an offset
voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
1. Infinite Droopless Sample-and-Hold Capability.
Low Cost I/O
2. The AD5533 is available in a 74-lead LFBGA package with a
body size of 12 mm × 12 mm.
FUNCTIONAL BLOCK DIAGRAM
DV
CC
AV
OFFS IN
V
V
SS
REF IN REF OUT
CC
DD
V
0
OUT
V
ADC
DAC
IN
TRACK/RESET
BUSY
V
31
OUT
AD5533
DAC
DAC
DAC GND
AGND
OFFS OUT
DGND
INTERFACE
CONTROL
LOGIC
SER/PAR
WR
ADDRESS INPUT REGISTER
OFFSET SEL
A4–A0
CAL
SCLK
D
D
SYNC/CS
IN
OUT
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V
to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from
VSS + 2 V to VDD – 2 V. All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
AD5533–SPECIFICATIONS
Parameter1
A Version2
Unit
Conditions/Comments
ANALOG CHANNEL
V
IN to VOUT Nonlinearity
0.018
0.006
3.46/3.6
50
% max
% typ
min/max
mV max
Input Range 100 mV to 2.96 V
After Gain and Offset Adjustment
3.52 typ
Gain
Offset Error
ANALOG INPUT (VIN)
Input Voltage Range
Input Lower Deadband
0 to 3
70
V
Nominal Input Range
50 mV typ. Referred to VIN.
See Figure 5
mV max
Input Upper Deadband
Input Current
40
1
mV max
µA max
pF typ
12 mV typ. Referred to VIN.
See Figure 5
100 nA typ. VIN Being Acquired on
One Channel
Input Capacitance3
20
ANALOG INPUT (OFFS_IN)
Input Current
1
µA max
100 nA typ
<1 nA typ
VOLTAGE REFERENCE
REF_IN
Nominal Input Voltage
Input Voltage Range3
Input Current
3.0
2.85/3.15
1
V
V min/max
µA max
REF_OUT
Output Voltage
3
280
60
V typ
kΩ typ
ppm/°C typ
Output Impedance3
Reference Temperature Coefficient3
ANALOG OUTPUTS (VOUT 0–31)
Output Temperature Coefficient3, 4
DC Output Impedance
Output Range
20
0.5
ppm/°C typ
Ω typ
V min/max
kΩ min
pF max
mA typ
dB typ
VSS + 2 /VDD – 2
5
500
10
–70
–70
250
100 µA Output Load
Resistive Load3, 5
Capacitive Load3, 5
Short-Circuit Current3
DC Power Supply Rejection Ratio3
VDD = +15 V 5%
VSS = –15 V 5%
dB typ
µV max
DC Crosstalk3
ANALOG OUTPUT (OFFS_OUT)
Output Temperature Coefficient3, 4
DC Output Impedance3
Output Range
20
1.3
ppm/°C typ
kΩ typ
mV typ
50 to REF_IN – 12
Output Current
Capacitive Load
10
100
µA max
pF max
Source Current
DIGITAL INPUTS3
Input Current
Input Low Voltage
10
0.8
0.4
2.4
2.0
200
10
µA max
V max
V max
V min
V min
mV typ
5 µA typ
DVCC = 5 V 5%
DVCC = 3 V 10%
DVCC = 5 V 5%
DVCC = 3 V 10%
Input High Voltage
Input Hysteresis (SCLK and CS Only)
Input Capacitance
pF max
DIGITAL OUTPUTS (BUSY, DOUT)3
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
0.4
4.0
0.4
2.4
1
V max
V min
V max
V min
µA max
pF typ
DVCC = 5 V. Sinking 200 µA
DVCC = 5 V. Sourcing 200 µA
DVCC = 3 V. Sinking 200 µA
DVCC = 3 V. Sourcing 200 µA
High Impedance Leakage Current
High Impedance Output Capacitance
D
OUT Only
15
DOUT Only
REV. 0
–2–
AD5533
Parameter1
A Version2
Unit
Conditions/Comments
POWER REQUIREMENTS
Power-Supply Voltages
VDD
VSS
AVCC
8/16.5
V min/max
V min/max
V min/max
V min/max
–4.75/–16.5
4.75/5.25
2.7/5.25
DVCC
Power-Supply Currents6
IDD
ISS
AICC
15
15
33
1.5
mA max
mA max
mA max
mA max
mW typ
10 mA typ. All Channels Full Scale
10 mA typ. All Channels Full Scale
26 mA typ
1 mA typ
VDD = +10 V, VSS = –5 V
DICC
Power Dissipation6
280
NOTES
1See Terminology.
2A Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
3Guaranteed by design and characterization, not production tested.
4AD780 as reference for the AD5533.
5Ensure that you do not exceed TJ (max). See maximum ratings.
6Outputs unloaded.
Specifications subject to change without notice.
(VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND =
DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from VSS + 2 V to VDD – 2 V. All outputs unloaded.
All specifications TMIN to TMAX unless otherwise noted.)
AC CHARACTERISTICS
Parameter
A Version1
Unit
Conditions/Comments
Output Settling Time2
Acquisition Time
3
µs max
16
10
0.2
400
5
µs max
OFFS_IN Settling Time2
Digital Feedthrough2
µs max
500 pF, 5 kΩ Load; 0 V–3 V Step
nV-s typ
nV/(√Hz) typ
nV-s typ
Output Noise Spectral Density @ 1 kHz2
AC Crosstalk2
NOTES
1A version: Industrial temperature range –40°C to +85°C; typical at 25°C.
2Guaranteed by design and characterization, not production tested
Specifications subject to change without notice.
REV. 0
–3–
AD5533
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Limit at TMIN, TMAX
Parameter1, 2
(A Version)
Unit
Conditions/Comments
t1
t2
t3
t4
t5
t6
0
0
50
50
20
0
ns min
ns min
ns min
ns min
ns min
ns min
CS to WR Setup Time
CS to WR Hold Time
CS Pulsewidth Low
WR Pulsewidth Low
A4–A0, CAL, OFFS_SEL to WR Setup Time
A4–A0, CAL, OFFS_SEL to WR Hold Time
NOTES
1See Interface Timing Diagram.
2Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACE
Limit at TMIN, TMAX
Parameter1, 2
(A Version)
Unit
Conditions/Comments
fCLKIN
t1
t2
t3
t4
t5
t6
t73
t83
t9
20
20
20
10
50
10
5
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
DIN Setup Time
DIN Hold Time
SYNC Falling Edge to SCLK Rising Edge Setup Time
SCLK Rising Edge to DOUT Valid
SCLK Falling Edge to DOUT High Impedance
10th SCLK Falling Edge to SYNC Falling Edge for Readback
5
20
60
400
t10
NOTES
1See Serial Interface Timing Diagrams.
2Guaranteed by design and characterization, not production tested.
3These numbers are measured with the load circuit of Figure 2.
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAM
CS
I
OL
200A
TO
OUTPUT
PIN
1.6V
WR
C
50pF
L
I
200A
OH
A4–A0, CAL,
OFFS SEL
Figure 1. Parallel Write (SHA Mode Only)
Figure 2. Load Circuit for DOUT Timing Specifications
REV. 0
–4–
AD5533
SERIAL INTERFACE TIMING DIAGRAMS
t1
SCLK
1
2
3
4
5
6
7
8
9
10
t2
t3
SYNC
t4
t5
t6
D
IN
MSB
LSB
Figure 3. 10-Bit Write (SHA Mode and Both Readback Modes)
t1
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
10
t7
t2
SYNC
t10
t4
t8
t9
D
OUT
MSB
LSB
Figure 4. 14-Bit Read (Both Readback Modes)
REV. 0
–5–
AD5533
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted)
AGND to DGND. . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C
74-Lead LFBGA Package, θJA Thermal Impedance . . . 41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
V
SS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AVCC to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVCC + 0.3 V
Digital Outputs to DGND . . . . . . . . . –0.3 V to DVCC + 0.3 V
REF_IN to AGND, DAC_GND . . . . . . . . . . . –0.3 V to +7 V
VIN to AGND, DAC_GND . . . . . . . . . . . . . . . –0.3 V to +7 V
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
V
OUT0–31 to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
VOUT0–31 toVSS . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +24 V
OFFS_IN to AGND . . . . . . . . . . SS – 0.3 V to VDD + 0.3 V
OFFS_OUT to AGND . . . . AGND – 0.3 V to AVCC + 0.3 V
V
ORDERING GUIDE
Output
Impedance
Output
Voltage Span
Package
Description
Package
Option
Model
Function
AD5533ABC-1
32-Channel SHA Only
0.5 Ω typ
10 V
74-Lead LFBGA
BC-74
AD5532ABC-1*
AD5532ABC-2*
AD5532ABC-3*
AD5532ABC-5*
32 DACs, 32-Channel SHA
32 DACs, 32-Channel SHA
32 DACs, 32-Channel SHA
32 DACs, 32-Channel SHA
0.5 Ω typ
0.5 Ω typ
500 Ω typ
1 kΩ typ
10 V
20 V
10 V
10 V
74-Lead LFBGA
74-Lead LFBGA
74-Lead LFBGA
74-Lead LFBGA
BC-74
BC-74
BC-74
BC-74
EVAL-AD5532EB
AD5532/AD5533 Evaluation Board
*Separate Data Sheet.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5533 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–6–
AD5533
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
1
2
3
4
5
6
7
8
9
10 11
74-Lead LFBGA Ball Configuration
LFBGA
Number
Ball
Name
LFBGA
Number
Ball
Name
LFBGA
Number
Ball
Name
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C6
N/C
A4
A2
A0
CS/SYNC
DVCC
SCLK
OFFSET_SEL
BUSY
TRACK/RESET
N/C
VO16
N/C
A3
A1
WR
DGND
DIN
C10
C11
D1
AVCC1
REF_OUT
VO20
DAC_GND2
AVCC2
OFFS_OUT
VO26
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
VO9
VO11
VO17
VO15
VO27
VSS3
VSS1
VSS4
VDD2
VO2
VO10
VO13
VO12
N/C
VO28
VO29
VO30
VDD3
VDD1
VDD4
VO31
VO0
D2
D10
D11
E1
E2
VO14
E10
E11
F1
AGND1
OFFS_IN
VO25
VO21
AGND2
VO6
VO24
VO8
VO5
VO3
VO23
VIN
VO4
VO7
VO22
VO19
VSS2
F2
F10
F11
G1
G2
G10
G11
H1
H2
H10
H11
J1
CAL
SER/PAR
DOUT
REF_IN
VO18
DAC_GND1
N/C
L10
L11
VO1
N/C
J2
J6
REV. 0
–7–
AD5533
PIN FUNCTION DESCRIPTIONS
Pin
Function
AGND(1–2)
AVCC (1–2)
Analog GND Pins.
Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
VDD Supply Pins. Voltage range from 8 V to 16.5 V.
VSS Supply Pins. Voltage range from –4.75 V to –16.5 V.
Digital GND Pins.
V
V
DD (1–4)
SS (1–4)
DGND
DVCC
DAC_GND(1–2)
REF_IN
Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
Reference GND Supply for All the DACs.
Reference Voltage for Channels 0–31.
REF_OUT
Reference Output Voltage.
V
OUT (0–31)
Analog Output Voltages from the 32 Channels.
VIN
Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
Parallel Interface: 5-Address Pins for 32 Channels. A4 = MSB of Channel Address. A0 = LSB.
Parallel Interface: Control input that allows all 32 channels to acquire VIN simultaneously.
A4–A11, A02
CAL1
CS/SYNC
This pin is both the active low Chip Select pin for the parallel interface and the Frame Synchronization pin
for the serial interface.
Parallel Interface: Write pin. Active low. This is used in conjunction with the CS pin to address the device
WR1
using the parallel interface.
OFFSET_SEL1
SCLK2
Parallel Interface: Offset Select Pin. Active high. This is used to select the offset channel.
Serial Clock Input for Serial Interface. This operates at clock speeds up to 20 MHz.
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK.
2
DIN
DOUT
Output from the DAC Registers for readback. Data is clocked out on the rising edge of SCLK and is valid
on the falling edge of SCLK.
SER/PAR1
OFFS_IN
OFFS_OUT
BUSY
This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low,
the parallel interface will be used. If it is tied high, the serial interface will be used.
Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to
this pin if the user wants to drive this pin with the Offset Channel.
Offset Output. This is the acquired/programmed offset voltage which can be tied to the OFFS_IN pin
to offset the span.
This output tells the user when the input voltage is being acquired. It goes low during acquisition and
returns high when the acquisition operation is complete.
If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the
gain/offset stage is switched directly to VIN. The addressed channel begins to acquire VIN on the rising edge
of TRACK. See TRACK Input section for further information. This input can also be used as a means of
resetting the complete device to its power-on-reset conditions. This is achieved by applying a low-going
pulse of between 50 ns and 150 ns to this pin. See section on RESET Function for further details.
TRACK/RESET2
NOTES
1Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.
2Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
REV. 0
–8–
AD5533
TERMINOLOGY
DC Crosstalk
VIN to VOUT Nonlinearity
This the dc change in the output level of one channel in response
to a full-scale change in the output of all other channels. It is
expressed in µV.
This is a measure of the maximum deviation from a straight line
passing through the endpoints of the VIN versus VOUT transfer
function. It is expressed as a percentage of the full-scale span.
Output Settling Time
Offset Error
This is the time taken from when BUSY goes high to when the
output has settled to 0.018%.
This is a measure of the output error when VIN = 70 mV. Ideally,
with VIN = 70 mV:
Acquisition Time
V
OUT = (Gain × 70) – ((Gain – 1) × VOFFS_IN) mV
This is the time taken for the VIN input to be acquired. It is the
length of time that BUSY stays low.
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal). It is expressed in mV and can be positive or
negative. See Figure 5.
OFFS_IN Settling Time
This is the time taken from a 0 V–3 V step change in input volt-
age on OFFS_IN until the output has settled to within 0.35%.
Gain Error
This is a measure of the span error of the analog channel. It is
the deviation in slope of the transfer function. See Figure 5. It
is calculated as:
Digital Feedthrough
This is a measure of the impulse injected into the analog outputs
from the digital control inputs when the part is not being written
to, i.e., CS/SYNC is high. It is specified in nV-secs and is mea-
sured with a worst-case change on the digital input pins, e.g.,
from all 0s to all 1s and vice versa.
Gain Error = Actual Full-Scale Output – Ideal Full-Scale Output –
Offset Error
where
Output Noise Spectral Density
Ideal Full-Scale Output = Ideal Gain × 2.96 – ((Ideal Gain-1) × VOFFS_IN
Ideal Gain = 3.52
)
This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per root Hertz).
It is measured by loading all DACs to midscale and measuring
Output Temperature Coefficient
This is a measure of the change in analog output with changes
in temperature. It is expressed in ppm/°C.
noise at the output. It is measured in nV/(√Hz)1/2
.
AC Crosstalk
This is the area of the glitch that occurs on the output of one
channel while another channel is acquiring. It is expressed in
nV-secs.
DC Power-Supply Rejection Ratio
DC Power-Supply Rejection Ratio (PSRR) is a measure of the
change in analog output for a change in supply voltage (VDD
and VSS). It is expressed in dBs. VDD and VSS are varied 5%.
V
OUT
GAIN ERROR +
OFFSET ERROR
IDEAL
TRANSFER
FUNCTION
ACTUAL
TRANSFER
FUNCTION
OFFSET
ERROR
70mV
2.96
0V
3V
V
IN
LOWER
DEADBAND
UPPER
DEADBAND
Figure 5. SHA Transfer Function
REV. 0
–9–
AD5533–Typical Performance Characteristics
3.535
3.530
3.525
3.520
0.0024
20
15
10
5
3.56
3.54
3.52
3.50
3.48
T
V
V
= 25؇C
A
T
= 25؇C
0.0020
A
= 3V
REFIN
V
= 3V
REFIN
0.0016
0.0012
= 0V
OFFS_IN
V
= 1V
IN
GAIN
0.0008
0.0004
0.0000
–0.0004
–0.0008
–0.0012
–0.0016
–0.0020
–0.0024
OFFSET ERROR
0
6
4
2
0
–2
–4
–6
–40
0
40
80
0.1
2.96
SINK/SOURCE CURRENT – mA
V
– V
IN
TEMPERATURE – ؇C
Figure 8. VOUT Source and Sink
Capability
Figure 6. VIN to VOUT Accuracy after
Offset and Gain Adjustment
Figure 7. Offset Error and Gain vs.
Temperature
70k
63791
T
= 25؇C
A
60k
50k
40k
30k
20k
10k
0
V
V
V
= 3V
5V
REFIN
= 1.5V
IN
OFFS_IN
100
= 0V
90
BUSY
V
OUT
T
V
V
= 25؇C
A
= 3V
REFIN
= 0 1.5V
IN
10
0%
2s
1V
1545
5.2682
200
5.2670
5.2676
– V
V
OUT
Figure 9. Acquisition Time and
Output Settling Time
Figure 10. SHA Mode Repeatability
(64K Acquisitions)
REV. 0
–10–
AD5533
FUNCTIONAL DESCRIPTION
ADDRESSED CHANNEL
The AD5533 can be thought of as consisting of an ADC and 32
DACs in a single package. The input voltage VIN is sampled
and converted into a digital word. The digital result is loaded
into one of the DAC registers and is converted (with gain and
offset) into an analog output voltage (VOUT0–VOUT31). Since
the channel output voltage is effectively the output of a DAC
there is no droop associated with it. As long as power to the
device is maintained, the output voltage will remain constant
until this channel is addressed again.
V
IN
C2
C1
20pF
7.5pF
Figure 11. Analog Input Circuit
Large source impedances will significantly affect the performance
of the ADC. This may necessitate the use of an input buffer
amplifier.
To update a single channel’s output voltage, the required new
voltage level is set up on the common input pin, VIN. The desired
channel is then addressed via the parallel port or the serial port.
When the channel address has been loaded, provided TRACK is
high, the circuit begins to acquire the correct code to load to the
DAC in order that the DAC output matches the voltage on VIN.
The BUSY pin goes low and remains so until the acquisition is
complete. The noninverting input to the output buffer is tied to
VIN during the acquisition period to avoid spurious outputs while
the DAC acquires the correct code. The acquisition is completed
in 16 µs max. The BUSY pin goes high and the updated DAC
output assumes control of the output voltage. The output voltage
of the DAC is connected to the noninverting input of the output
buffer. The held voltage will remain on the output pin indefinitely,
without drooping, as long as power to the device is maintained.
Output Buffer Stage—Gain and Offset
The function of the output buffer stage is to translate the 0 V–3 V
output of the DAC to a wider range. This is done by gaining up
the DAC output by 3.52 and offsetting the voltage by the volt-
age on OFFS_IN pin.
V
OUT = 3.52 × VDAC – 2.52 × VOFFS_IN
V
V
DAC is the output of the DAC.
OFFS_IN is the voltage at the OFFS_IN pin.
Table I shows how the output range on VOUT relates to the offset
voltage supplied by the user.
Table I. Sample Output Voltage Ranges
VOFFS_IN (V)
VDAC (V)
VOUT (V)
On power-on, all the DACs, including the offset channel, are
loaded with zeros. The outputs of the DACs are at 50 mV typical
(negative full-scale). If the OFFS_IN pin is driven by the on-board
offset channel, the outputs VOUT0 to VOUT31 are also at 50 mV on
power-on since OFFS_IN = 50 mV (VOUT = 3.52 × VDAC – 3.52
× VOFFS_IN = 176 mV – 126 mV = 50 mV).
0.5
1
0 to 3
0 to 3
–1.26 to +9.3
–2.52 to +8.04
VOUT is limited only by the headroom of the output amplifiers.
VOUT must be within maximum ratings.
Offset Voltage Channel
Analog Input
The offset voltage can be externally supplied by the user at
OFFS_IN or it can be supplied by an additional offset voltage
channel on the device itself. The required offset voltage is set up
on VIN and acquired by the offset DAC. This offset channel’s
DAC output is directly connected to OFFS_OUT. By connect-
ing OFFS_OUT to OFFS_IN this offset voltage can be used as
the offset voltage for the 32-output amplifiers. It is important to
choose the offset so that VOUT is within maximum ratings.
The equivalent analog input circuit is shown in Figure 11. The
Capacitor C1 is typically 20 pF and can be attributed to pin
capacitance and 32 off-channels. When a channel is selected, an
extra 7.5 pF (typ) is switched in. This Capacitor C2 is charged to
the previously acquired voltage on that particular channel so
it must charge/discharge to the new level. It is essential that the
external source can charge/discharge this additional capaci-
tance within 1 µs–2 µs of channel selection so that VIN can be
acquired accurately. For this reason a low impedance source is
recommended.
PIN
DRIVER
V
1
OUT
OUTPUT
STAGE
DEVICE
UNDER
TEST
V
IN
ACQUISITION
CIRCUIT
CONTROLLER
DAC
BUSY
TRACK
AD5533
THRESHOLD
VOLTAGE
ONLY ONE CHANNEL SHOWN FOR SIMPLICITY
Figure 12. Typical ATE Circuit Using TRACK Input
REV. 0
–11–
AD5533
Reset Function
1. SHA Mode
The reset function on the AD5533 can be used to reset all nodes
on this device to their power-on-reset condition. This is imple-
mented by applying a low-going pulse of between 50 ns and 150 ns
to the TRACK/RESET pin on the device. If the applied pulse
is less than 50 ns it is assumed to be a glitch and no operation
takes place. If the applied pulse is wider than 150 ns this pin adopts
its track function on the selected channel, VIN is switched to the
output buffer and an acquisition on the channel will not occur
until a rising edge of TRACK.
In this standard mode a channel is addressed and that channel
acquires the voltage on VIN. This mode requires a 10-bit write
to address the relevant channel (VOUT0–VOUT31, offset channel
or all channels). MSB is written first.
2. Acquire and Readback Mode
This mode allows the user to acquire VIN and read back the data
in a particular DAC register. The relevant channel is addressed
(10-bit write, MSB first) and VIN is acquired in 16 µs (max).
Following the acquisition, after the next falling edge of SYNC
the data in the relevant DAC register is clocked out onto the
DOUT line in a 14-bit serial format. During readback DIN is
ignored. The full acquisition time must elapse before the DAC
register data can be clocked out.
TRACK Function
Normally in SHA mode of operation, TRACK is held high and
the channel begins to acquire when it is addressed. However, if
TRACK is low when the channel is addressed, VIN is switched
to the output buffer and an acquisition on the channel will not
occur until a rising edge of TRACK. At this stage the BUSY pin
will go low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and
VIN is free to change again without affecting this output value.
3. Readback Mode
Again, this is a readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of SYNC, the data in the relevant DAC
register is clocked out onto the DOUT line in a 14-bit serial format.
The user must allow 400 ns (min) between the last SCLK fall-
ing edge in the 10-bit write and the falling edge of SYNC in
the 14-bit readback. The serial write and read words can be seen in
Figure 13.
This is useful in an application where the user wants to ramp up
V
IN until VOUT reaches a particular level (Figure 12). VIN does
not need to be acquired continuously while it is ramping up.
TRACK can be kept low and only when VOUT has reached its
desired voltage is TRACK brought high. At this stage, the
acquisition of VIN begins.
This feature allows the user to read back the DAC register code
of any of the channels. Readback is useful if the system has been
calibrated and the user wants to know what code in the DAC
In the example shown, a desired voltage is required on the out-
put of the pin driver. This voltage is represented by one input to
a comparator. The microcontroller/microprocessor ramps up
the input voltage on VIN through a DAC. TRACK is kept low
while the voltage on VIN ramps up so that VIN is not continu-
ally acquired. When the desired voltage is reached on the output of
the pin driver, the comparator output switches. The µC/µP then
knows what code is required to be input in order to obtain the
desired voltage at the DUT. The TRACK input is now brought
high and the part begins to acquire VIN. BUSY goes low until VIN
has been acquired. When BUSY goes high, the output buffer
is switched from VIN to the output of the DAC.
corresponds to a desired voltage on VOUT
.
INTERFACES
SERIAL INTERFACE
The SER/PAR pin is tied high to enable the serial interface and
to disable the parallel interface. The serial interface is controlled
by four pins as follows:
SYNC, DIN, SCLK
Standard 3-wire interface pins. The SYNC pin is shared
with the CS function of the parallel interface.
DOUT
Data Out pin for reading back the contents of the DAC regis-
ters. The data is clocked out on the rising edge of SCLK and
is valid on the falling edge of SCLK.
MODES OF OPERATION
The AD5533 can be used in three different modes. These modes
are set by two mode bits, the first two bits in the serial word.
The 01 option (DAC Mode) is not available for the AD5533.
To avail of this mode refer to the AD5532 data sheet. If you
attempt to set up DAC mode, the AD5533 will enter a test-mode
and a 24-clock write will be necessary to clear this.
Cal Bit
When this is high all 32 channels acquire VIN simultaneously.
The acquisition time is then 45 µs (typ) and accuracy may be
reduced.
Offset_Sel Bit
Table II. Modes of Operation
If this bit is set high, the offset channel is selected and Bits
A4–A0 are ignored.
Mode Bit 1
Mode Bit 2
Operating Mode
Test Bit
0
0
1
1
0
1
0
1
SHA Mode
This must be set low for correct operation of the part.
DAC Mode (Not Available)
Acquire and Readback
Readback
A4–A0
Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).
REV. 0
–12–
AD5533
MSB
LSB
0
0
CAL
0
OFFSET SEL
A4–A0
MODE BIT 1 MODE BIT 2
MODE BITS
TEST BIT
a. 10-Bit Input Serial Write Word (SHA Mode)
MSB
LSB
A4–A0
MSB
LSB
1
0
CAL
OFFSET SEL
0
DB13–DB0
TEST BIT
MODE BITS
14-BIT DATA
10-BIT
READ FROM PART AFTER
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
SERIAL WORD
WRITTEN TO PART
b. Input Serial Interface (Acquire and Readback Mode)
MSB
LSB
A4–A0
MSB
LSB
1
1
0
0
OFFSET SEL
DB13–DB0
TEST BIT
MODE BITS
14-BIT DATA
10-BIT
READ FROM PART AFTER
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
SERIAL WORD
WRITTEN TO PART
c. Input Serial Interface (Readback Mode)
Figure 13. Serial Interface Formats
DB13–DB0
falling edge of the SYNC signal and on subsequent SCLK falling
edges. The serial interface will not shift data in or out until it
receives the falling edge of the SYNC signal.
These are used in both readback modes to read a 14-bit word
from the addressed DAC register.
The serial interface is designed to allow easy interfacing to most
microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI, SPI,
DSP56000, TMS320, and ADSP-21xx, without the need for
any glue logic. When interfacing to the 8051, the SCLK must
be inverted. The Microprocessor/Microcontroller Interface
section explains how to interface to some popular DSPs and
microcontrollers.
Parallel Interface
The SER/PAR bit must be tied low to enable the parallel inter-
face and disable the serial interface. The parallel interface is
controlled by nine pins.
CS
Active low package select pin. This pin is shared with the SYNC
function for the serial interface.
Figures 3 and 4 show the timing diagram for a serial read and
write to the AD5533. The serial interface works with both a
continuous and a noncontinuous serial clock. The first falling
edge of SYNC resets a counter that counts the number of serial
clocks to ensure the correct number of bits are shifted in and
out of the serial shift registers. Any further edges on SYNC are
ignored until the correct number of bits are shifted in or out.
Once the correct number of bits have been shifted in or out, the
SCLK is ignored. In order for another serial transfer to take
place the counter must be reset by the falling edge of SYNC.
In readback, the first rising SCLK edge after the falling edge
of SYNC causes DOUT to leave its high impedance state and
data is clocked out onto the DOUT line and also on subsequent
SCLK rising edges. The DOUT pin goes back into a high imped-
ance state on the falling edge of the 14th SCLK. Data on the
DIN line is latched in on the first SCLK falling edge after the
WR
Active low write pin. The values on the address pins are latched
on a rising edge of WR.
A4–A0
Five address pins (A4 = MSB of address, A0 = LSB). These are
used to address the relevant channel (out of a possible 32).
Offset_Sel
Offset select pin. This has the same function as the Offset_Sel
bit in the serial interface. When it is high, the offset channel is
addressed and the address on A4–A0 is ignored.
Cal
Same functionality as the Cal bit in the serial interface. When this
pin is high, all 32 channels acquire VIN simultaneously.
REV. 0
–13–
AD5533
MICROPROCESSOR INTERFACING
AD5533 to ADSP-21xx Interface
The ADSP-21xx family of DSPs are easily interfaced to the
AD5533 without the need for extra logic.
data in the SPDR register. PC7 must be pulled low to start a
transfer. It is taken high and pulled low again before any further
read/write cycles can take place. A connection diagram is shown in
Figure 15.
A data transfer is initiated by writing a word to the TX register
after the SPORT has been enabled. In a write sequence data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5533 on the falling edge of its SCLK. In
readback 16 bits of data are clocked out of the AD5533 on each
rising edge of SCLK and clocked into the DSP on the rising edge
of SCLK. DIN is ignored. The valid 14 bits of data will be cen-
tered in the 16-bit RX register when using this configuration.
The SPORT control register should be set up as follows:
AD5533*
MC68HC11*
MISO
PC7
D
OUT
SYNC
SCK
MOSI
SCLK
D
IN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 15. AD5533 to MC68HC11 Interface
AD5533 to PIC16C6x/7x
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
The PIC16C6x Synchronous Serial Port (SSP) is configured
as an SPI Master with the Clock Polarity bit = 0. This is done
by writing to the Synchronous Serial Port Control Register
(SSPCON). See user PIC16/17 Microcontroller User Manual.
In this example I/O port RA1 is being used to pulse SYNC and
enable the serial port of the AD5533. This microcontroller trans-
fers only eight bits of data during each serial transfer operation;
therefore, two consecutive read/write operations are needed for
a 10-bit write and a 14-bit readback. Figure 16 shows the con-
nection diagram.
ISCLK = 1, Internal Serial Clock
TFSR
IRFS
ITFS
= RFSR = 1, Frame Every Word
= 0, External Framing Signal
= 1, Internal Framing Signal
SLEN = 1001, 10-Bit Data Words (SHA Mode Write)
SLEN = 1111, 16-Bit Data Words (Readback Mode)
Figure 14 shows the connection diagram.
ADSP-2101/
AD5533*
PIC16C6x/7x*
AD5533*
ADSP-2103*
DR
D
OUT
SCK/RC3
SCLK
TFS
RFS
DT
SYNC
SDO/RC5
SDI/RC4
RA1
D
OUT
D
IN
D
IN
SYNC
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. AD5533 to PIC16C6x/7x Interface
AD5533 TO 8051
Figure 14. AD5533 to ADSP-2101/ADSP-2103 Interface
AD5533 to MC68HC11
The AD5533 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode
0. In this mode serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 17 shows how the 8051 is
connected to the AD5533. Because the AD5533 shifts data
out on the rising edge of the shift clock and latches data in on
the falling edge, the shift clock must be inverted. The AD5533
requires its data with the MSB first. Since the 8051 outputs
the LSB first, the transmit routine must take this into account.
The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 User Manual. SCK of the 68HC11 drives the SCLK of
the AD5533, the MOSI output drives the serial data line (DIN)
of the AD5533 and the MISO input is driven from DOUT. The
SYNC signal is derived from a port line (PC7). When data is
being transmitted to the AD5533, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the fall-
ing edge of SCK. Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. In order to trans-
mit 10-data bits in SHA mode it is important to left-justify the
8051*
AD5533*
SCLK
TxD
RxD
D
OUT
D
IN
SYNC
P1.1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. AD5533 to 8051 Interface
REV. 0
–14–
AD5533
APPLICATION CIRCUITS
POWER SUPPLY DECOUPLING
AD5533 in a Typical ATE System
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5533 is mounted should be designed so that the analog and
digital sections are separated, and confined to certain areas of
the board. If the AD5533 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device. For supplies with
multiple pins (VSS, VDD, AVCC) it is recommended to tie those pins
together. The AD5533 should have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low Effective Series Resistance (ESR) and Effective
Series Inductance (ESI), like the common ceramic types that
provide a low impedance path to ground at high frequencies, to
handle transient currents due to internal logic switching.
The AD5533 Infinite Sample-and-Hold is ideally suited for use
in Automatic Test Equipment. Several SHAs are required to
control pin drivers, comparators, active loads, and signal timing.
Traditionally, sample-and-hold devices with droop were used in
this application. These required refreshing to prevent the volt-
age from drifting.
The AD5533 has several advantages: no refreshing is required,
there is no droop, pedestal error is eliminated, and there is no
need for extra filtering to remove glitches. Overall, a higher level
of integration is achieved in a smaller area, see Figure 18.
PARAMETRIC
MEASUREMENT
UNIT
SYSTEM BUS
SHA
SHA
SHA
ACTIVE
LOAD
The power supply lines of the AD5533 should use as large a trace
as possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiat-
ing noise to other parts of the board, and should never be run
near the reference inputs. A ground line routed between the
DIN and SCLK lines will help reduce crosstalk between them (not
required on a multilayer board as there will be a separate ground
plane, but separating the lines will help). It is essential to mini-
mize noise on VIN and REFIN lines.
STORED
DATA
DRIVER
AND INHIBIT
PATTERN
SHA
FORMATTER
DUT
SHA
PERIOD
GENERATION
AND
DELAY
TIMING
SHA
SHA
COMPARE
REGISTER
COMPARATOR
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is by far the best, but not always possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground plane while signal traces are placed on
the solder side.
SYSTEM BUS
SHAs
Figure 18. AD5533 in an ATE System
Typical Application Circuit
The AD5533 can be used to set up voltage levels on 32 channels
as shown in the circuit below. An AD780 provides the 3 V refer-
ence for the AD5533, and for the AD5541 16-bit DAC. A simple
3-wire interface is used to write to the AD5541. The DAC out-
put is buffered by an AD820. It is essential to minimize noise on
VIN and REFIN when laying out this circuit.
AV
CC
AV
CC
V
SS
DV
CC
V
DD
V
AD820
IN
AD5541*
REF
CS
DIN
V
0–31
OUT
AD5533*
SCLK
OFFS_IN
OFFS_OUT
REFIN
AD780*
V
OUT
SCLK DIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. Typical Application Circuit
REV. 0
–15–
AD5533
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
74-Lead LFBGA
(BC-74)
0.394 (10.00) BSC
0.472 (12.00) BSC
A1
11 10
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
0.472
(12.00)
BSC
0.394
(10.00)
BSC
BOTTOM
VIEW
TOP VIEW
0.039
(1.00)
BSC
K
L
0.039 (1.00) BSC
DETAIL A
DETAIL A
0.067
(1.70)
MAX
0.033
(0.85)
MIN
0.010
(0.25)
MIN
CONTROLLING DIMENSIONS
ARE IN MILLIMETERS
0.024 (0.60)
BSC
SEATING
PLANE
BALL DIAMETER
REV. 0
–16–
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