AD5535BKBC [ADI]
32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V; 32通道， 14位DAC，满量程输出电压可编程范围为50 V至200 V
| 型号： | AD5535BKBC |
| 厂家： | 
ADI |
| 描述： | 32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V |
| 文件： | 总16页 (文件大小：322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32-Channel, 14-Bit DAC with Full-Scale Output
Voltage Programmable from 50 V to 200 V
Data Sheet
AD5535B
FEATURES
GENERAL DESCRIPTION
High integration
The AD5535B is a 32-channel, 14-bit denseDAC® with an on-chip
32-channel, 14-bit denseDAC® with integrated high
voltage output amplifier
Guaranteed monotonic
Housed in 15 mm × 15 mm CSP_BGA package
Full-scale output voltage programmable from 50 V to 200 V
via reference input
high voltage output amplifier. This device is targeted for optical
micro-electromechanical systems. The output voltage range is
programmable via the REF_IN pin. The output range is 0 V to
50 V when REF_IN = 1 V, and 0 V to 200 V when REF_IN = 4 V.
Each amplifier can source 550 µA, which is ideal for the deflection
and control of optical MEMS mirrors.
550 µA drive capability
The selected digital-to-analog converter (DAC) register is written
to via the 3-wire interface. The serial interface operates at clock
rates of up to 30 MHz and is compatible with DSP and micro-
controller interface standards.
Integrated silicon diode for temperature monitoring
DSP-/microcontroller-compatible serial interface
1.2 MHz channel update rate
Asynchronous
facility
RESET
The device is operated with AVCC = 4.75 V to 5.25 V, DVCC
=
–10°C to +85°C temperature range
2.7 V to 5.25 V, V+ = 4.75 V to 5.25 V, and VPP of up to 225 V.
REF_IN is buffered internally on the AD5535B and should be
driven from a stable reference source.
APPLICATIONS
Optical microelectromechanical systems (MEMS)
Optical crosspoint switches
Micropositioning applications using piezoelectric actuators
Level setting in automotive test and measurement
FUNCTIONAL BLOCK DIAGRAM
DV
AV
V
V
+
CC
CC
REF_IN
PP
PGND
ANODE
RESET
AD5535B
CATHODE
DAC
DAC
R1
R1
V
0
OUT
RF
14-BIT BUS
V
1
OUT
DAC_GND
AGND
RF
DAC
DAC
R1
R1
V
V
30
31
OUT
RF
RF
OUT
INTERFACE
CONTROL
LOGIC
DGND
D
SCLK
SYNC
IN
Figure 1.
Rev. A
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Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
AD5535B
Data Sheet
TABLE OF CONTENTS
Features ......................................................................................1
DAC Section........................................................................12
Applications...............................................................................1
General Description .................................................................1
Functional Block Diagram ......................................................1
Revision History .......................................................................2
Specifications.............................................................................3
Timing Characteristics ........................................................5
Absolute Maximum Ratings....................................................6
ESD Caution..........................................................................6
Pin Configuration and Function Descriptions.....................7
Typical Performance Characteristics .....................................9
Terminology ............................................................................11
Functional Description..........................................................12
Reset Function ....................................................................12
Serial Interface ....................................................................12
Microprocessor Interfacing...............................................12
Applications.............................................................................14
MEMS Mirror Control Application.................................14
IPC-2221-Compliant Board Layout.................................14
Power Supply Decoupling Recommendations.....................15
Guidelines for Printed Circuit Board Layout......................15
Outline Dimensions ...............................................................16
Ordering Guide...................................................................16
REVISION HISTORY
4/13—Rev. 0 to Rev. A
Change to General Description Section.........................................1
Changes to DAC Section ................................................................12
Changes to MEMS Mirror Control Application Section ...........14
1/13—Revision 0: Initial Version
Rev. A | Page 2 of 16
Data Sheet
AD5535B
SPECIFICATIONS
VPP = 215 V; V+ = 5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; PGND = AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V;
all outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
K Grade2
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
DC PERFORMANCE3
Resolution
14
Bits
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero Code Voltage
Output Offset Error
Offset Drift
0.1
0.5
0.5
% of FSR
LSB
V
–1
–1
49
+1
1
+1
Guaranteed monotonic
V
0.5
50
mV/°C
V/V
Voltage Gain
51
Gain Temperature Coefficient
5
–200
ppm/°C
ppm/°C
%
Due to DAC
Due to DAC and amplifier
Channel-to-Channel Gain Match4
OUTPUT CHARACTERISTICS
Output Voltage Range3
Output Impedance
Resistive Load4, 5
Capacitive Load4
Short-Circuit Current
DC Crosstalk4
DC Power Supply Rejection (PSRR), VPP
Long-Term Drift
–5
1
+5
VPP − 1
V
Ω
50
1
MΩ
pF
mA
LSB
dB
LSB
200
4
0.55
3
70
0.25
Outputs at midscale,
measured over 30 days at 25°C
AC CHARACTERISTICS4
Settling Time
¼ to ¾ Scale Step
60
60
5
5
10
3
µs
µs
µs
µs
V/µs
V/µs
kHz
µV/√Hz
mV p-p
No load
200 pF load
No load
200 pF load
No load
200 pF load
1 LSB Step
Slew Rate
–3 dB Bandwidth
30
Output Noise Spectral Density
0.1 Hz to 10 Hz Output Noise Voltage
Digital-to-Analog Glitch Impulse
4.5
1
Measured at 10 kHz
1 LSB change around major
carry
Positive Transition
Negative Transition
Analog Crosstalk
Digital Feedthrough
VOLTAGE REFERENCE, REF_IN6
15
8
2.5
2
nV-sec
nV-sec
µV-sec
nV-sec
AVCC and V+ must exceed REF_IN
by 1.15 V minimum
Input Voltage Range4
Input Impedance
1
4.096
60
V
kΩ
Rev. A | Page 3 of 16
AD5535B
Data Sheet
K Grade2
Typ
Parameter1
Min
Max
Unit
Test Conditions/Comments
TEMPERATURE MEASUREMENT DIODE4
Peak Inverse Voltage, PIV
Forward Diode Drop, VF
Forward Diode Current, IF
VF Temperature Coefficient, TC
DIGITAL INPUTS4
5
0.8
100
V
V
Cathode to anode
IF = 100 µA, anode to cathode
Anode to cathode
0.65
−2.20
5
µA
mV/°C
Anode to cathode
Input Current
Input Low Voltage
10
0.8
µA
V
Input High Voltage
2.0
V
Input Hysteresis (SCLK and SYNC Only)
Input Capacitance
200
mV
pF
10
POWER SUPPLY VOLTAGES
VPP
(50 ×
225
V
REF_IN) + 1
V+
AVCC
DVCC
4.75
4.75
2.7
5.25
5.25
5.25
V
V
V
POWER SUPPLY CURRENTS7
IPP
All Channels at Full-Scale
All Channels at Zero-Scale
50
25
1.2
17.5
0.25
60
35
1.7
20
0.6
µA/channel
µA/channel
mA
mA
mA
I+
AICC
DICC
1 See the Terminology section.
2 K Grade temperature range: −10°C to +85°C; typical = +25°C.
3 Linear output voltage range: 7 V to VPP − 1 V.
4 Guaranteed by design and characterization, not production tested.
5 Ensure that TJ max is not exceeded. See the Absolute Maximum Ratings section.
6 Reference input determines output voltage range. Using a 4.096 V reference (REF198) gives an output voltage range of 2.50 V to 200 V. The output range is
programmable via the reference input. The full-scale output range is programmable from 50 V to 200 V. The linear output voltage range is restricted from 7
V to VPP − 1 V.
7 Outputs unloaded.
Rev. A | Page 4 of 16
Data Sheet
AD5535B
TIMING CHARACTERISTICS
VPP = 210 V; V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V. All specifications TMIN
to TMAX, unless otherwise noted.
Table 2.
Parameter1, 2, 3
A Grade
1.2
30
13
13
Unit
Test Conditions/Comments
Channel update rate
SCLK frequency
SCLK high pulse width
SCLK low pulse width
SYNC falling edge to SCLK falling edge setup time
SYNC low time
fUPDATE
fCLKIN
t1
t2
t3
MHz max
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
15
t4
50
t5
10
SYNC high time
t6
t7
t8
10
5
200
20
DIN setup time
DIN hold time
19th SCLK falling edge to SYNC falling edge for next write
t9
RESET pulse width
1 See Figure 2.
2 Guaranteed by design and characterization, not production tested.
3 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.
t1
SCLK
1
2
3
4
5
16
17
18
19
1
t3
t2
t5
SYNC
t4
t6
t8
t7
D
IN
MSB
LSB
RESET
t9
Figure 2. Serial Interface Timing Diagram
Rev. A | Page 5 of 16
AD5535B
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
VPP to AGND
V+ to AGND
AVCC to AGND, DAC_GND
DVCC to DGND
Digital Inputs to DGND
REF_IN to AGND, DAC_GND
VOUT0 to VOUT31 to AGND
ANODE/CATHODE to AGND, DAC_GND
AGND to DGND
Rating
0.3 V to 240 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V
−0.3 V to AVCC + 0.3 V
–0.3 V to VPP + 0.3 V
−0.3 V to +7 V
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
−0.3 V to +0.3 V
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
−10°C to +85°C
−65°C to +150°C
150°C
124-Lead CSP_BGA Package,
θJA Thermal Impedance
40°C/W
Lead Temperature
Soldering
JEDEC industry standard
J-STD-020
ESD
Human Body Model
Machine Model
Field Induced Charged Device Model
2.5 kV
250 V
400 V
Rev. A | Page 6 of 16
Data Sheet
AD5535B
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
5
9
11 12 13 14
10
1
2
3
4
6
7
8
A
B
C
D
A
B
C
D
E
F
E
F
G
G
H
J
H
J
K
L
K
L
M
N
P
M
N
P
5
9
11 12 13 14
10
1
2
3
4
6
7
8
Figure 3. Pin Configuration
Table 4. Pin Assignments
Pin No.
Mnemonic
Pin No.
H1
Mnemonic
VPP
A1
NC
A2
A4
A6
A8
A10
A12
A14
B1
B3
B5
VOUT
VOUT
1
7
H2
H4 to H11
H13
J3 to J12
K1
K2
K3 to K14
L1
L2
L3 to L13
L14
M1 to M12
M13
M14
N1
N2
N3
N4
N5 to N14
P1
P2
P3
P4
VPP
AGND
VOUT27
AGND
V+
V+
AGND
NC
VOUT11
VOUT16
VOUT20
VOUT25
NC
VOUT
VOUT
VOUT
VOUT13
VOUT17
VOUT21
VOUT26
0
4
9
NC
AGND
DAC_GND
AGND
AVCC
B7
B9
B11
B13
C2
C12
C14
D1
D13
E2
E4
E6
E8
E10
E12
E14
F3
AVCC
VOUT
VOUT22
VOUT29
3
PGND
PGND
CATHODE
ANODE
AGND
NC
REF_IN
DAC_GND
RESET
DVCC
VOUT
VOUT23
VOUT
VOUT
VOUT12
VOUT15
VOUT19
VOUT24
VOUT31
2
5
8
P5
P6
P7
P8
DGND
TEST
DIN
VOUT
6
F5
F7
F9
F13
G14
VOUT10
VOUT14
VOUT18
VOUT30
VOUT28
P9
P10
SCLK
SYNC
AGND
NC
P11 to P13
P14
Rev. A | Page 7 of 16
AD5535B
Data Sheet
Table 5. Pin Function Descriptions
Mnemonic
AGND
AVCC
VPP
V+
PGND
DGND
DVCC
DAC_GND
REF_IN
Description
Analog GND Pins.
Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
Output Amplifier High Voltage Supply. Voltage range from (REF_IN × 50) + 1 V to 225 V.
V+ Amplifier Supply Pins. Voltage range from 4.75 V to 5.25 V.
Output Amplifier Ground Reference Pins.
Digital GND Pins.
Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
Reference GND Supply for All DACs.
Reference Voltage for Channel 0 to Channel 31. Reference input range is 1 V to 4 V and can be used to program the full-
scale output voltage from 50 V to 200 V.
VOUT0 to VOUT31 Analog Output Voltages from the 32 Channels.
ANODE
CATHODE
SYNC
Anode of Internal Diode for Diode Temperature Measurement.
Cathode of Internal Diode for Diode Temperature Measurement.
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in
upon the falling edge of SCLK.
SCLK
Serial Clock Input. Data is clocked into the shift register upon the falling edge of SCLK. The pin operates at clock speeds of
up to 30 MHz. Internal pull-up device on logic input; therefore, it can be left floating and defaults to a logic high
condition.
DIN
TEST
RESET
Serial Data Input. Data must be valid upon the falling edge of SCLK.
For normal operation, tie this pin low.
Active Low Input. This pin can also be used to reset the complete device to its power-on reset conditions. Zero code is
loaded to the DACs.
NC
No Connect. Do not connect to these pins.
Rev. A | Page 8 of 16
Data Sheet
AD5535B
TYPICAL PERFORMANCE CHARACTERISTICS
16
1.00
0.75
0.50
0.25
0
V
V
= 60V
V
V
= 210V
PP
PP
= AV = +5V
REF_IN = 1V
= 25°C
= AV = +5.25V
+
CC
+
CC
12
8
REF_IN = 4.096V
T
T
= 25°C
A
A
4
0
–4
–8
–12
–16
–0.25
–0.50
–0.75
–1.00
0
2048
4096
6144
8192 10240 12288 14336 16384
0
2048
4096
6144
8192 10240 12288 14336 16384
INPUT CODE
INPUT CODE
Figure 4. Integral Nonlinearity (INL) with Full-Scale Range = 50 V
Figure 7. DNL with Full-Scale Range = 200 V
1.00
1.00
0.
V
V
= 60V
PP
CHANNEL 2
CHANNEL 1
= AV = +5V
+
CC
0.75
0.50
0.25
0
REF_IN = 1V
10kΩ
T
= 25°C
A
DAC
AMP
0.
0.
CHANNEL 2
–0.25
–0.50
–0.75
–1.00
–0.
–0.
T
CHANNEL 1
–0.
–1.00
0
2048
4096
6144
8192 10240 12288 14336 16384
CH1 5V
0 2048
CH2 5V
4096 6144
M 500ns
CH1
21.6V
8192 10240 12288 14336 16384
INPUT CODE
INPUT CODE
Figure 5. Differential Nonlinearity (DNL) with Full-Scale Range = 50 V
Figure 8. Short-Circuit Current Limit Timing
16
1.00
0.75
0.50
0.25
V
V
= 210V
T
PP
= AV = +5.25V
+
CC
12
8
REF_IN = 4.096V
T
= 25°C
A
CHANNEL 2 AREA
11 µV-sec
4
0
0
2
–4
–8
–12
–16
–0.25
V
V
= 210V
PP
= AV = +5.25V
+
CC
REF_IN = 4.096V
V
1
–0.50
= 100V
OUT
T
= 25°C
A
–0.75
–1.00
CHANNEL 1: CHANNEL OUTPUT SLEW
CHANNEL 2: AC CROSSTALK
0
2048
4096
6144
8192 10240 12288 14336 16384
CH1 50V
2 48
CH2 200mV
M 10µs
CH1
0
4096 144 8192 10240 12288 14336 16384
INPUT CODE
INPUT CODE
Figure 6. INL with Full-Scale Range = 200 V
Figure 9. Worst-Case Adjacent Channel Crosstalk
Rev. A | Page 9 of 16
AD5535B
Data Sheet
0.04
0.03
0.02
0.01
0
V
V
= 210V
PP
140
120
100
80
= AV = +5.25V
+
CC
REF_IN = 4.096V
T
= 25°C
A
60
–0.01
–0.02
–0.03
–0.04
40
V
V
= 210V
PP
= AV = +5.25V
+
CC
VICTIM CHANNEL = 31
31 = MIDSCALE
REF_IN = 4.096V
V
20
0
V
OUT
= 70V
OUT
FULL-SCALE TRANSITION ON
OTHER CHANNELS IN SEQUENCE.
T
= 25°C
A
–5
–4
–3
–2
–1
0
1
2
0
5
10
15
20
25
30
SOURCE/SINK CURRENT (mA)
CHANNEL NUMBER
Figure 10. Output Amplifier Source and Sink Capability
Figure 13. Cumulative DC Crosstalk Effects on a Single-Channel Output,
Switching All Other Channels in Sequence
180
12.0
11.5
11.0
10.5
10.0
9.5
V
V
= 210V
PP
0pF
= AV = +5.25V
+
CC
160
REF_IN = 4.096V
140
100pF
120
100
200pF
80
60
V
V
= 210V
PP
9.0
= AV = +5.25V
+
CC
40
20
0
REF_IN = 4.096V
T
= 25°C
A
8.5
1/4 FULL-SCALE TO
3/4 FULL-SCALE STEP
8.0
–10
0
0.02
0.04
0.06
0.08
0.10
0
10
20
30
40
50
60
70
80
TIME (ms)
TEMPERATURE (°C)
Figure 11. Offset Error vs. Temperature
Figure 14. Settling Time vs. Capacitive Load
–1.0
–1.1
–1.2
–1.3
–1.4
–1.5
V
V
= 210V
PP
= AV = +5.25V
+
CC
REF_IN = 4.096V
–10
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
Figure 12. Gain Error vs. Temperature
Rev. A | Page 10 of 16
Data Sheet
AD5535B
TERMINOLOGY
Integral Nonlinearity (INL)
DC Crosstalk
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function.
It is expressed as a percentage of full-scale range.
The dc change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s and vice
versa) and the output change of all other DACs. It is expressed
in LSB.
Differential Nonlinearity (DNL)
The difference between the measured change and the ideal
1 LSB change between any two adjacent codes. A specified
DNL of 1 LSB maximum ensures monotonicity.
Output Voltage Settling Time
The time taken from when the last data bit is clocked into the
DAC until the output has settled to within 0.5 LSB of its final
value. Measured for a step change of ¼ to ¾ full scale.
Zero Code Voltage
A measure of the output voltage present at the device output
with all 0s loaded to the DAC. It includes the offset of the
DAC and the output amplifier and is expressed in V.
Digital-to-Analog Glitch Impulse
The area of the glitch injected into the analog output when
the code in the DAC register changes state. It is specified as
the area of the glitch in nV-sec when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00
or 100 . . . 00 to 011 . . . 11).
Offset Error
Calculated by taking two points in the linear region of the
transfer function, drawing a line through these points, and
extrapolating back to the y-axis. It is expressed in V.
Analog Crosstalk
The area of the glitch transferred to the output (VOUT) of one DAC
due to a full-scale change in the output (VOUT) of another DAC.
The area of the glitch is expressed in nV-sec.
Voltage Gain
Calculated from the change in output voltage for a change in
code, multiplied by 16,384, and divided by the REF_IN voltage.
This is calculated between two points in the linear section of the
transfer function.
Digital Feedthrough
A measure of the impulse injected into the analog outputs from
the digital control inputs when the part is not being written to
Gain Error
(
is high). It is specified in nV-sec and measured with a
SYNC
A measure of the output error with all 1s loaded to the DAC,
and the difference between the ideal and actual analog output
range. Ideally, the output should be 50 × REF_IN. It is expressed
as a percentage of full-scale range.
worst-case change on the digital input pins, for example, from
all 0s to all 1s and vice versa.
Output Noise Spectral Density
A measure of internally generated random noise. Random noise
is characterized as a spectral density (voltage per √Hz). It is
measured by loading all DACs to midscale and measuring noise
at the output. It is measured in μV/√Hz.
DC Power Supply Rejection Ratio (PSRR)
A measure of the change in analog output for a change in VPP
supply voltage. It is expressed in dB, and VPP is varied 5%.
Rev. A | Page 11 of 16
AD5535B
Data Sheet
FUNCTIONAL DESCRIPTION
The AD5535B consists of a 32-channel, 14-bit DAC with 200 V
high voltage amplifiers in a single 15 mm × 15 mm CSP_BGA
package. The output voltage range is programmable via the
REF_IN pin. The output range is 0 V to 50 V when REF_IN =
1 V, and 0 V to 200 V when REF_IN = 4 V. Communication to
the device is through a serial interface operating at clock rates of
up to 30 MHz, which is compatible with DSP and microcontroller
interface standards. A 5-bit address and a 14-bit data-word are
loaded into the AD5535B input register via the serial interface.
The channel address is decoded, and the data-word is converted
into an analog output voltage for this channel.
A4 to A0 Bits
The A4 to A0 bits can address any one of the 32 channels. A4 is
the MSB of the address, while A0 is the LSB.
DB13 to DB0 Bits
The DB13 to DB0 bits are used to write a 14-bit data-word into
the addressed DAC register.
Figure 2 is the timing diagram for a serial write to the
AD5535B. The serial interface works with both a continuous
and a discontinuous serial clock. The first falling edge of
resets the serial clock counter to ensure that the correct number
of bits are shifted into the serial shift register. Any further edges
SYNC
At power-on, all the DAC registers are loaded with 0s.
on
are ignored until the correct number of bits are
SYNC
DAC SECTION
shifted in. After 19 bits are shifted in, the SCLK is ignored. For
another serial transfer to take place, the counter must be reset
by the falling edge of
The architecture of each DAC channel consists of a resistor
string DAC, followed by an output buffer amplifier operating
with a nominal gain of 50. The voltage at the REF_IN pin
provides the reference voltage for the corresponding DAC. The
input coding to the DAC is straight binary, and the ideal DAC
output voltage is given by
. The user must allow 200 ns
SYNC
(minimum) between successive writes.
LSB
DB13 TO DB0
MSB
A4
A3
A2
A1
A0
Figure 15. Serial Data Format
50×VREF _ IN ×D
VOUT
=
214
MICROPROCESSOR INTERFACING
AD5535B-to-ADSP-BF527 Interface
where D is the decimal equivalent (0 to 16,383) of the binary
The Blackfin® DSP is easily interfaced to the AD5535B without
the need for extra logic. A data transfer is initiated by writing a
word to the TX register after SPORT is enabled. In a write
sequence, data is clocked out on each rising edge of the serial
clock of the DSP and clocked into the AD5535B on the falling
edge of its SCLK. The SPORT can be configured to transmit 19
SCLKs while TFS is low. Figure 16 shows the connection diagram.
code, which is loaded to the DAC register.
The output buffer amplifier is specified to drive a load of 1 MΩ
and 200 pF. The linear output voltage range for the output amplifier
is from 7 V to VPP − 1 V. The amplifier output bandwidth is
typically 30 kHz, and is capable of sourcing 550 µA and sinking
2.8 mA. Settling time for a ¼ to ¾ full-scale step change is
typically 60 µs with a load of up to 200 pF.
AD5535B
RESET FUNCTION
The reset function on the AD5535B can be used to reset all
nodes on the device to their power-on reset condition. All the
DACs are loaded with 0s, and all registers are cleared. Take
ADSP-BF527
SPORT_TFS
SPORT_TSCK
SPORT_DTO
SYNC
SCLK
SDIN
the
pin low to implement the reset function.
RESET
SERIAL INTERFACE
GPIO0
RESET
The serial interface is controlled by the three following pins:
Figure 16. AD5535B-to-ADSP-BF527 Interface
•
, which is the frame synchronization pin for the serial
SYNC
interface.
•
•
SCLK, which is the serial clock input that operates at clock
speeds of up to 30 MHz.
DIN, which is the serial data input and data must be valid
upon the falling edge of SCLK.
To update a single DAC channel, a 19-bit data-word is written
to the AD5535B input register.
Rev. A | Page 12 of 16
Data Sheet
AD5535B
AD5535B-to-MC68HC11 Interface
necessary to transmit 19 bits of data. Data is transmitted MSB
first. It is important to left justify the data in the SPDR register
so that the first 19 bits transmitted contain valid data. RA1 must
be pulled low to start a transfer. RA1 must then be brought high
and pulled low again before any further write cycles can take
place. Figure 18 shows the connection diagram.
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), clock polarity bit (CPOL)
= 0, and clock phase bit (CPHA) = 1. The SPI is configured by
writing to the SPI control register (SPCR). SCK of the MC68HC11
drives the SCLK of the AD5535B and the MOSI output drives
the serial data line (DIN) of the AD5535B. The
signal is
SYNC
derived from a port line (PC7). When data is being transmitted
to the AD5535B, the pin is taken low (PC7).
PIC16C6x/7x*
AD5535B*
SCK/RC3
SCLK
SYNC
SDI/RC4
RA1
D
IN
SYNC
Data appearing on the MOSI output is valid on the falling edge
of SCK. The MC68HC11 transfers only eight bits of data during
each serial transfer operation; therefore, three consecutive write
operations are necessary to transmit 19 bits of data. Data is
transmitted MSB first. It is important to left justify the data in
the SPDR register so that the first 19 bits transmitted contain
valid data. PC7 must be pulled low to start a transfer. PC7 is then
taken high and pulled low again before any further write cycles
can take place. Figure 17 shows the connection diagram.
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 18. AD5535B-to-PIC16C6x/7x Interface
AD5535B-to-8051 Interface
The AD5535B requires a clock synchronized to the serial data.
Therefore, the 8051 serial interface must operate in Mode 0. In
this mode, serial data exits the 8051 through RxD, and a shift
clock is output on TxD. The
signal is derived from a port
SYNC
line (P1.1). Figure 19 shows how the 8051 is connected to the
AD5535B. Because the AD5535B shifts data out upon the rising
edge of the shift clock and latches data in upon the falling edge,
the shift clock must be inverted. Note that the AD5535B also
requires its data to be MSB first. Because the 8051 outputs LSB
first, the transmit routine must take this into account.
MC68HC11*
AD5535B*
SCK
SCLK
MOSI
PC7
D
IN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 17. AD5535B-to-MC68HC11 Interface
8051*
AD5535B*
AD5535B-to-PIC16C6x/7x Interface
TxD
RxD
P1.1
SCLK
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit = 0. This is done by
writing to the synchronous serial port control register (SSPCON).
D
IN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
In this example, I/O port RA1 is being used to pulse
and
SYNC
Figure 19. AD5535B-to-8051 Interface
to enable the serial port of the AD5535B. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
Rev. A | Page 13 of 16
AD5535B
Data Sheet
APPLICATIONS INFORMATION
REF198
(4.096V)
+5V +210V
MEMS MIRROR CONTROL APPLICATION
OUTPUT RANGE
0V TO 200V
The AD5535B is targeted to all optical switching control systems
based on MEMS technology. The AD5535B is a 32-channel,
14-bit DAC with integrated high voltage amplifiers. The output
amplifiers are capable of generating an output range of 0 V to
200 V when using a 4 V reference. The full-scale output voltage
is programmable from 50 V to 200 V using reference voltages
from 1 V to 4 V. Each amplifier can output 550 µA and directly
drives the control actuators, which determine the position of
MEMS mirrors in optical switch applications.
V
V
REF_IN
+
PP
SENSOR
+
14-BIT DAC
8-CHANNEL
V
0
OUT
ADC (AD7856)
4-TO-1 MUX
(ADG739)
ACTUATORS
FOR
OR
MEMS
OR
MIRROR
ARRAY
V
31
OUT
SINGLE-
14-BIT DAC
CHANNEL
32-TO-1 MUX
(ADG732)
ADC (AD7671)
AD5535B
ADSP-21065L
The AD5535B is generally used in a closed-loop feedback system,
as shown in Figure 20, with a high resolution ADC and DSP.
The exact position of each mirror is measured using capacitive
sensors. The sensor outputs are multiplexed using an ADG739
4-to-1 multiplexer to an 8-channel, 14-bit ADC (AD7856). An
alternative solution is to multiplex using a 32-to-1 multiplexer
(ADG732) into a single-channel ADC (AD7671). The control
loop is driven by an ADSP-21065L, a 32-bit SHARC® DSP with
an SPI-compatible SPORT interface. With 14-bit monotonic
behavior and a 0 V to 200 V output range, coupled with its fast
serial interface, the AD5535B is ideally suited for controlling a
cluster of MEMS-based mirrors.
Figure 20. AD5535B in a MEMS-Based Optical Switch
IPC-221-COMPLIANT BOARD LAYOUT
The diagram in Figure 21 is a typical 2-layer printed circuit board
(PCB) layout for the AD5535B that complies with the specifications
outlined in IPC-221. Do not connect to the four corner balls
labeled as original no connects. Connect balls labeled as
additional no connects to AGND.
The routing shown in Figure 21 shows the feasibility of
connecting to the high voltage balls while complying with
the spacing requirements of IPC-221. Figure 21 also shows
the physical distances that are available.
A1 BALL PAD CORNER
1
2 4
3
5
9
11 12 13 14
10
1
6
7
8
A
B
C
D
1.414mm
DETAIL A
E
F
ORIGINAL
NO CONNECTS
G
250µm RAD
H
J
ADDITIONAL
NO CONNECTS
SPACE = 433µm
100µm
K
L
2mm
SPACE = 433µm
100µm
M
N
P
SPACE = 433µm
250µm RAD
1
1
1
Figure 21. Layout Guidelines to Comply with IPC-221
Rev. A | Page 14 of 16
Data Sheet
AD5535B
A microstrip technique is by far the best, but it is not always
POWER SUPPLY DECOUPLING RECOMMENDATIONS
possible to use with a double-sided board. In this technique,
the component side of the board is dedicated to ground planes,
and signals are placed on the solder side. Multilayer printed
circuit boards with dedicated ground, power, and tracking
layers offer the optimum solution in terms of obtaining analog
performance, but at increased manufacturing costs.
On the AD5535B, it is recommended to tie all grounds together
as close to the device as possible. If the number of supplies must be
reduced, bring all supplies back separately and make a provision
on the board via a link option to drive the AVCC and V+ pins
from the same supply. Decouple all power supplies adequately
with 10 µF tantalum capacitors and 0.1 µF ceramic capacitors.
Good decoupling is vitally important when using high resolu-
tion converters. Decouple all analog supplies with 10 µF tantalum
capacitors in parallel with 0.1 µF ceramic capacitors to analog
ground. To achieve the best results from the decoupling components,
place them as close to the device as possible, ideally right up
against the IC or the IC socket. The main aim of a bypassing
element is to maximize the charge stored in the bypass loop
while simultaneously minimizing the inductance of this loop.
Inductance in the loop acts as an impedance to high frequency
transients and results in power supply spiking. By keeping the
decoupling as close to the device as possible, the loop area is
kept as small as possible, thereby reducing the possibility of
power supply spikes. Decouple digital supplies of high resolution
converters with 10 µF tantalum capacitors and 0.1 µF ceramic
GUIDELINES FOR PCB LAYOUT
Design printed circuit boards such that the analog and digital
sections are separated and confined to the designated analog
and digital sections of the board. This facilitates the use of ground
planes that can be separated easily. A minimum etch technique
is generally the best for ground planes because it optimizes
shielding of sensitive signal lines. Join digital and analog ground
planes in one place only, at the AGND and DGND pins of the
high resolution converter. To isolate the high frequency bus of
the processor from the bus of the high resolution converters, buffer
or latch data and address buses on the board. These act as a
Faraday shield and increase the signal-to-noise performance of
the converters by reducing the amount of high frequency digital
coupling. Avoid running digital lines under the device because
they couple noise onto the die. Allow the ground plane to run
under the IC to avoid noise coupling.
capacitors to the digital ground plane. Decouple the V
+ supply
with a 10 µF tantalum capacitor and a 0.1 µF ceramic capacitor
to AGND.
Use as large a trace as possible for the supply lines of the device
to provide low impedance paths and reduce the effects of glitches
on the power supply line. Shield components, such as clocks with
fast-switching signals, with digital ground to avoid radiating noise
to other sections of the board. Never run clock signals near the
analog inputs of the device. Avoid crossovers of digital and analog
signals. Keep traces for analog inputs as wide and short as possible
and shield with analog ground if possible. Run traces on opposite
sides of the 2-layer PCB at right angles to each other to reduce the
effects of feedthrough through the board.
Decouple all logic chips with 0.1 µF ceramic capacitors to digital
ground to decouple high frequency effects associated with
digital circuitry.
Rev. A | Page 15 of 16
AD5535B
Data Sheet
OUTLINE DIMENSIONS
15.10
15.00 SQ
14.90
A1 BALL
CORNER
14 13 12 11 10
7 1
9 8 6
4 2
5 3
A
B
C
D
E
F
BALL A1
PAD CORNER
13.00
REF
G
H
J
K
L
M
N
P
1.00
BSC
BOTTOM VIEW
TOP VIEW
DETAIL A
*
1.70 MAX
1.25 MAX
0.85 MIN
DETAIL A
*
0.41
0.36
0.31
COPLANARITY
0.12
*
0.46 NOM
BALL DIAMETER
SEATING
PLANE
*
COMPLIANT WITH JEDEC STANDARDS MO-192-AAE-1
WITH EXCEPTION TO DIMENSIONS INDICATED BY AN ASTERISK.
NOMINAL BALL SIZE IS REDUCED FROM 0.60mm TO 0.46mm.
Figure 22. 124-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-124-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Function Output Voltage Span
Temperature Range
−10°C to +85°C
−10°C to +85°C
Package Description
124-Lead CSP_BGA
124-Lead CSP_BGA
Evaluation Board
Package Option
BC-124-2
BC-124-2
AD5535BKBC
AD5535BKBCZ
EVAL-AD5535BEBZ
32 DACs
32 DACs
0 V to 200 V maximum
0 V to 200 V maximum
1 Z = RoHS Compliant Part.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10852-0-4/13(A)
Rev. A | Page 16 of 16
相关型号：
AD5535BKBCZ
32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V
ADI
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