AD5535ABC [ADI]
32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V; 32通道， 14位DAC，满量程输出电压可编程范围为50 V至200 V
| 型号： | AD5535ABC |
| 厂家： | 
ADI |
| 描述： | 32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V |
| 文件： | 总16页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32-Channel, 14-Bit DAC with Full-Scale Output
Voltage Programmable from 50 V to 200 V
Preliminary Technical Data
AD5535
GENERAL DESCRIPTION
FEATURES
The AD5535 is a 32-channel, 14-bit DAC with an on-chip high
High integration: 32-channel, 14-bit DAC with integrated,
high voltage output amplifier
voltage output amplifier. This device is targeted for optical
micro-electromechanical systems. The output voltage range is
programmable via the REFIN pin. Output range is 0 V to 50 V
with REFIN = 1 V and is 0 V to 200 V with REFIN = 4 V. Each
amplifier can source 700 µA, which is ideal for the deflection
and control of optical MEMS mirrors.
Guaranteed monotonic
Housed in 15 × 15 mm CSP-BGA package
Full-scale output voltage programmable from 50 V to 200 V
via reference input
700 µA drive capability
The selected DAC register is written to via the 3-wire interface.
The serial interface operates at clock rates of up to 30 MHz and
is compatible with DSP and microcontroller interface standards.
Integrated silicon diode for temperature monitoring
DSP-/microcontroller-compatible serial interface
Channel update rate: 1.2 MHz
The device is operated with AVCC = 4.75 to 5.25 V, DVCC = 2.7 V
to 5.25 V, V– = −4.75 V to −5.25 V, V+ = +4.75 V to +5.25 V, VPP
= 210 V. REF_IN is buffered internally on the AD5535 and
should be driven from a stable reference source.
RESET
Asynchronous
facility
Temperature range: –10°C to +85°C
APPLICATIONS
Optical micro-electromechanical systems (MEMS)
Optical cross-point switches
Micropositioning applications using Piezo Flextures
Level setting in automotive test and measurement
FUNCTIONAL BLOCK DIAGRAM
DV
REF_IN
AV
V
PGND
V
–
V
CC
CC
PP
+
ANODE
RESET
AD5535
CATHODE
DAC
DAC
R1
R1
V
0
OUT
RF
RF
14-BIT BUS
V
1
OUT
DAC_GND
AGND
DAC
DAC
R1
R1
V
V
30
31
OUT
RF
RF
OUT
INTERFACE
CONTROL
LOGIC
DGND
D
SCLK
SYNC
IN
Figure 1.
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5535
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Microprocessor Interfacing....................................................... 11
Applications Information.............................................................. 13
MEMS Mirror Control Application......................................... 13
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Functional Description .................................................................. 11
Digital-to-Analog Section ......................................................... 11
Reset Function ............................................................................ 11
Serial Interface ............................................................................ 11
AD5535 Board Layout to Ensure Compliance with IPC-221
Specification................................................................................ 13
Power Supply Sequencing and Decoupling Recommendations
....................................................................................................... 14
Guidelines for Printed Circuit Board Layout ......................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
10/04—Revision PrE: Preliminary Version
Rev. PrE | Page 2 of 16
Preliminary Technical Data
SPECIFICATIONS
AD5535
VPP = 210 V, V− = −5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V;
all outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A Grade2
Parameter1
Unit
Conditions/Comments
Min
Typ
Max
DC PERFORMANCE
Resolution
14
Bits
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero Code Voltage
Offset Error
±±.1
±±.ꢀ
% of FSR
LSB
V
±1
2
+4ꢀ
Guaranteed monotonic
–4ꢀ
mV
Offset Drift
Voltage Gain
±.±9
ꢀ±
TBD
ꢀ
LSB/°C
V/V
ppm/°C
%
47.ꢀ
ꢀ2.ꢀ
Gain Temperature Coefficient
Channel-to-Channel Gain Match
Full-Scale Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage Range3
Output Impedance
Resistive Load4, ꢀ
Capacitive Load4
Short-Circuit Current
DC Crosstalk4
8
ppm/°C
±
1
VPP – 1±
V
Ω
ꢀ±
MΩ
pF
mA
LSB
dB
2±±
3
±.7
7±
DC Power Supply Rejection (PSRR), VPP
AC CHARACTERISTICS
Settling Time
1/4 to 3/4 Scale Step
3±
1±±
1±
1±
1±
3
µs
µs
µs
µs
V/µs
V/µs
No load
2±± pF load
No load
2±± pF load
No load
2±± pF load
1 LSB Step
Slew Rate
–3 dB Bandwidth
ꢀ
kHz
Output Noise Spectral Density
±.1 Hz to 1± Hz Output Noise Voltage
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk
Digital Feedthrough
TBD
TBD
TBD
TBD
13
Measured at 1 kHz
nV/√Hz
µV p-p
nV–s typ
nV–s typ
µV–s typ
nV–s typ
1 LSB change around major carry
TBD
VOLTAGE REFERENCE, REF_IN6
Input Voltage Range4
Input Current
AVCC must exceed REFIN by 1.2ꢀ V min
1
4.±96
1
V
µA
TEMPERATURE MEASUREMENT DIODE4
Peak Inverse Voltage, PIV
Forward Diode Drop, VF
Forward Diode Current, IF
VF Temperature Coefficient, TC
ꢀ
V
Cathode to anode
IF = 2 mA, anode to cathode
Anode to cathode
IF = 2ꢀ± µA
±.8
2
V
mA
mV/°C
–1.44
Rev. PrE | Page 3 of 16
AD5535
Preliminary Technical Data
A Grade2
Typ
Parameter1
DIGITAL INPUTS4
Unit
Conditions/Comments
Min
Max
Input Current
Input Low Voltage
±ꢀ
±1±
±.8
µA
V
DVCC = 3 V to ꢀ V
DVCC = 3 V to ꢀ V
Input High Voltage
2.±
V
SYNC
2±±
mV
pF
Input Hysteresis (SCLK and
Input Capacitance
only)
1±
POWER-SUPPLY VOLTAGES
VPP
V–
V+
AVCC
(ꢀ± × REF_IN) +1±
21±
22ꢀ
V
V
V
V
V
–ꢀ.2ꢀ
4.7ꢀ
4.7ꢀ
2.7
–4.7ꢀ
ꢀ.2ꢀ
ꢀ.2ꢀ
ꢀ.2ꢀ
DVCC
POWER-SUPPLY CURRENTS7
IPP
7ꢀ
11±
3.ꢀ
3.ꢀ
2±
µA/channel
mA
2.ꢀ
2.ꢀ
16
±.1
6±9
I−
I+
AICC
DICC
mA
mA
mA
±.ꢀ
POWER DISSIPATION
7
mW
1 See Terminology.
2 A Grade temperature range: −1±°C to +8ꢀ°C; typically +2ꢀ°C.
3 Linear output voltage range: +7 V to VPP − 1± V.
4 Guaranteed by design and characterization, not production tested.
ꢀ Ensure that TJ max is not exceeded. See the Absolute Maximum Ratings section.
6 Reference input determines output voltage range. Using a 4.±96 V reference (REF 198) gives an output voltage range of ± V to 2±± V. Output range is programmable
via the reference input. The full-scale output range is programmable from ꢀ± V to 2±± V. The linear output voltage range is restricted from 7 V to VPP − 1± V.
7 Outputs unloaded.
Rev. PrE | Page 4 of 16
Preliminary Technical Data
AD5535
TIMING CHARACTERISTICS
VPP = 210 V, V− = –5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V.
All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1, 2, 3
A Grade
1.2
3±
13
13
Unit
Conditions/Comments
Channel Update Rate
SCLK Frequency
SCLK High Pulse Width
SCLK Low Pulse Width
fUPDATE
fCLKIN
t1
t2
t3
MHz max
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
1ꢀ
SYNC
SYNC
SYNC
Falling Edge to SCLK Falling Edge Setup Time
t4
ꢀ±
Low Time
High Time
tꢀ
1±
t6
t7
t8
1±
ꢀ
2±±
2±
DIN Setup Time
DIN Hold Time
SYNC
19th SCLK Falling Edge to Falling Edge for Next Write
RESET
Pulse Width
t9
1 See timing diagrams in Figure 2.
2 Guaranteed by design and characterization, not production tested.
3 All input signals are specified with tr = tf = ꢀ ns (1±% to 9±% of DVCC) and timed from a voltage level of (VIL + VIH)/2.
t1
SCLK
1
2
3
4
5
16
17
18
19
1
t3
t2
t5
SYNC
t4
t6
t8
t7
D
IN
MSB
LSB
RESET
t9
Figure 2. Serial Interface Timing Diagram
Rev. PrE | Page ꢀ of 16
AD5535
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
±.3 V to 22ꢀ V
VPP to AGND
+±.3 V to −6 V
−±.3 V to +7 V
−±.3 V to +7 V
−±.3 V to +7 V
−±.3 V to DVCC + ±.3 V
−±.3 V to AVCC + ±.3 V
V– to VPP
V− to AGND
V+ to AGND
AVCC to AGND, DAC_GND
DVCC to DGND
Digital Inputs to DGND
REF_IN to AGND, DAC_GND
VOUT ±–31 to AGND
Transient currents up to 100 mA do not cause SCR latch-up.
This device is a voltage-integrated circuit with an ESD rating of
<2 kV and it is ESD sensitive. Proper precautions should be
taken for handling and assembly.
Anode/Cathode to AGND, DAC_GND
AGND to DGND
−±.3 V to +7 V
−±.3 V to +±.3 V
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
−1±°C to +8ꢀ°C
−6ꢀ°C to +1ꢀ±°C
1ꢀ±°C
124-Lead CSP-BGA Package,
4±°C/W
θJA Thermal Impedance
Reflow Soldering
Peak Temperature
22±°C
Time at Peak Temperature
1± s to 4± s
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrE | Page 6 of 16
Preliminary Technical Data
AD5535
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
9
10
11 12 13 14
7
8
1
2
3
4
5
6
A
B
C
D
A
B
C
D
E
F
E
F
G
G
H
J
H
J
K
L
K
L
M
N
P
M
N
P
3
4
5
9
11 12 13
10 14
1
2
6
7
8
Figure 3. Pin Configuration
Table 4. 124-Lead CSP-BGA Ball Configuration
CSP-BGA
Number
CSP-BGA
Number
CSP-BGA
Number
CSP-BGA
Number
Ball Name
Ball Name
Ball Name
VPP
VOUT 27
AGND
V+
V+
AGND
V–
Ball Name
CATHODE
ANODE
AGND
N/C
REF_IN
DAC_GND
RESET
DVCC
DGND
TEST
DIN
SCLK
SYNC
A1
A2
A4
A6
N/C
C14
D1
D13
E2
E4
E6
VOUT 29
H2
N3
N4
Nꢀ–N14
P1
P2
VOUT
VOUT
1
7
H13
J3–J12
K1
K2
K3–K14
L1
L2
L3–L13
L14
M1
M2
VOUT
2
VOUT 23
VOUT 11
VOUT 16
VOUT 2±
VOUT 2ꢀ
N/C
VOUT
VOUT
ꢀ
8
A8
A1±
A12
A14
B1
B3
Bꢀ
B7
B9
B11
B13
C2
P3
P4
VOUT 12
VOUT 1ꢀ
VOUT 19
VOUT 24
VOUT 31
E8
V–
E1±
E12
E14
F3
Fꢀ
F7
Pꢀ
P6
P7
P8
VOUT
VOUT
VOUT
±
4
9
AGND
DAC_GND
AGND
AGND
AGND
AVCC
AVCC
PGND
PGND
VOUT
6
VOUT 13
VOUT 17
VOUT 21
VOUT 26
VOUT 1±
VOUT 14
VOUT 18
VOUT 3±
VOUT 28
VPP
P9
M3–12
M13
M14
N1
P1±
P11–P13
P14
F9
AGND
N/C
F13
G14
H1
VOUT
3
C12
VOUT 22
N2
Rev. PrE | Page 7 of 16
AD5535
Preliminary Technical Data
Table 5. Pin Function Descriptions
Pin
Function
AGND
AVCC
Analog GND Pins.
Analog Supply Pins. Voltage range from 4.7ꢀ V to ꢀ.2ꢀ V.
VPP
V+
V–
PGND
DGND
DVCC
DAC_GND
REF_IN
Output Amplifier High Voltage Supply. Voltage range from (REF_IN × ꢀ±) + 1± V to 22ꢀ V.
V+ Amplifier Supply Pins. Voltage range from 4.7ꢀ V to ꢀ.2ꢀ V.
V– Amplifier Supply Pins. Voltage range from −4.7ꢀ V to −ꢀ.2ꢀ V.
Output Amplifier Ground Reference Pins.
Digital GND Pins.
Digital Supply Pins. Voltage range from 2.7 V to ꢀ.2ꢀ V.
Reference GND Supply for All the DACs.
Reference Voltage for Channels ±–31. Reference input range is 1 V to 4 V and can be used to program the full-scale
output voltage from ꢀ± V to 2±± V.
VOUT (±–31)
ANODE
CATHODE
SYNC
Analog Output Voltages from the 32 Channels.
Anode of Internal Diode for Diode Temperature Measurement.
Cathode of Internal Diode for Diode Temperature Measurement.
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While
on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds of up to
3± MHz.
is low, data is transferred in
SCLK1
1
DIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
TEST
Allows the same data to be simultaneously loaded to all channels of the ADꢀꢀ3ꢀ. This pin is used for calibration purposes
when loading zero scale and full scale to all channels. To invoke this feature, take the TEST pin high. In normal operation,
TEST should be tied low.
RESET1
Active Low Input. This pin can also be used to reset the complete device to its power-on reset conditions. Zero code is
loaded to the DACs.
1 Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.
Rev. PrE | Page 8 of 16
Preliminary Technical Data
TERMINOLOGY
AD5535
Output Temperature Coefficient
Integral Nonlinearity (INL)
A measure of the change in analog output with changes in
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is expressed as a percentage of full-scale range.
temperature. It is expressed in ppm/°C.
Output Voltage Settling Time
The time taken from when the last data bit is clocked into the
DAC until the output has settled to within 0.5 LSB of its final
value.
Differential Nonlinearity (DNL)
The difference between the measured change and the ideal
1 LSB change between any two adjacent codes. A specified DNL
of 1 LSB maximum ensures monotonicity.
Digital-to-Analog Glitch Impulse
The area of the glitch injected into the analog output when the
code in the DAC register changes state. It is specified as the area
of the glitch in nV–s, when the digital code is changed by 1 LSB
at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . .
00 to 011 . . . 11).
Zero-Code Voltage
A measure of the output voltage present at the device output
with all 0s loaded to the DAC. It includes the offset of the DAC
and the output amplifier. It is expressed in V.
Offset Error
Digital Crosstalk
Calculated by taking two points in the linear region of the
transfer function, drawing a line through these points, and
extrapolating back to the Y axis. It is expressed in mV.
The glitch impulse transferred to the output of one DAC at
midscale while a full-scale code change (all 1s to all 0s and
vice versa) is being written to another DAC. It is expressed
in nV–s.
Voltage Gain
Calculated from the change in output voltage for a change in
code multiplied by 16,384 and divided by the REF_IN voltage.
This is calculated between two points in the linear section of the
transfer function.
Analog Crosstalk
The area of the glitch transferred to the output (VOUT) of one
DAC due to a full-scale change in the output (VOUT) of another
DAC. The area of the glitch is expressed in nV–s.
Gain Error
Digital Feedthrough
A measure of the impulse injected into the analog outputs from
the digital control inputs when the part is not being written to
A measure of the output error with all 1s loaded to the DAC,
and is the difference between the ideal and actual analog output
range. Ideally, the output should be 50 × REF_IN. It is expressed
as a percentage of full-scale range.
SYNC
(
is high). It is specified in nV–s and is measured with a
worst-case change on the digital input pins, for example, from
all 0s to all 1s and vice versa.
DC Power-Supply Rejection Ratio (PSRR)
A measure of the change in analog output for a change in VPP
supply voltage. It is expressed in dB. VPP is varied 5ꢀ.
Output Noise Spectral Density
A measure of internally generated random noise. Random noise
is characterized as a spectral density (voltage per √Hz). It is
measured by loading all DACs to midscale and measuring noise
at the output. It is measured in nV/(Hz)1/2.
DC Crosstalk
The dc change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s and vice
versa) and the output change of all other DACs. It is expressed
in LSB.
Rev. PrE | Page 9 of 16
AD5535
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
16
1.00
0.75
0.50
V
= 50V
V
= 200V
OUT
OUT
12
8
4
0
0.25
0
–4
–8
–0.25
–0.50
–12
–16
–0.75
–1.00
0
2048
4096
6144 8192 10240 12288 14336 16384
CODE
0
2048
4096
6144 8192 10240 12288 14336 16384
INPUT CODE
Figure 4. Integral Linearity with VPP = 60 V, VOUT Full Scale = 50 V
Figure 7. DNL with VPP = 210 V, VOUT Full Scale = 200 V
1.00
1.00
0.
0.
V
= 50V
OUT
0.75
0.50
0.25
0
0.
–0.25
–0.50
–0.
–0.
T
–0.75
–1.00
–0.
–1.00
CH1 5V
0 2048
CH2 5V
4096
M 500ns
CH1
21.6V
0
2048
4096
6144 8192 10240 12288 14336 16384
INPUT CODE
6144 8192 10240 12288 14336 16384
INPUT CODE
Figure 5.DNL with VPP = 60 V, VOUT Full Scale = 50 V
Figure 8. Short-Circuit Current Limit Timing
1.00
0.
0.
0.
16
12
8
V
= 200V
OUT
T
T
4
0
2
–4
–8
–0.
1
–0.
–0.
–1.00
–12
–16
CH1 50V
0 2 48
CH2 200mV
4096
M 10
µ
s
CH1
83V
0
2048
4096
6144 8192 10240 12288 14336 16384
INPUT CODE
6144 8192 10240 12288 14336 16384
INPUT CODE
Figure 6. Integral Linearity with VPP = 210 V, VOUT Full Scale = 200 V
Figure 9. Worst-Case Adjacent Channel Crosstalk
Rev. PrE | Page 1± of 16
Preliminary Technical Data
FUNCTIONAL DESCRIPTION
AD5535
A4 to A0 Bits
The AD5535 consists of 32 14-bit DACs with 200 V high voltage
amplifiers in a single 15 mm × 15 mm CSP-BGA package. The
output voltage range is programmable via the REFIN pin.
Output range is 0 V to 50 V with REFIN = 1 V, and 0 V to 200 V
with REFIN = 4 V. Communication to the device is through a
serial interface operating at clock rates of up to 30 MHz and is
compatible with DSP and microcontroller interface standards. A
5-bit address and a 14-bit data-word are loaded into the
AD5535 input register via the serial interface. The channel
address is decoded, and the data-word is converted into an
analog output voltage for this channel.
These bits can address any one of the 32 channels. A4 is the
MSB of the address; A0 is the LSB.
DB13 to DB0 Bits
These bits are used to write a 14-bit word into the addressed
DAC register.
Figure 2 is the timing diagram for a serial write to the AD5535.
The serial interface works with both a continuous and a discon-
SYNC
tinuous serial clock. The first falling edge of
resets a
counter that counts the number of serial clocks to ensure that
the correct number of bits are shifted into the serial shift
At power-on, all the DAC registers are loaded with 0s.
SYNC
register. Any further edges on
are ignored until the
DIGITAL-TO-ANALOG SECTION
correct number of bits are shifted in. Once 19 bits have been
shifted in, the SCLK is ignored. For another serial transfer to
take place, the counter must be reset by the falling edge of
The architecture of each DAC channel consists of a resistor
string DAC followed by an output buffer amplifier operating
with a nominal gain of 50. The voltage at the REF_IN pin
provides the reference voltage for the corresponding DAC. The
input coding to the DAC is straight binary and the ideal DAC
output voltage is given by
SYNC
successive writes.
. The user must allow 200 ns (minimum) between
LSB
MSB
A4
A3
A2
A1
A0
DB13–DB0
50×VREF _ IN ×D
Figure 10. Serial Data Format
VOUT
=
214
MICROPROCESSOR INTERFACING
AD5535 to ADSP-21xx Interface
where D is the decimal equivalent of the binary code, which is
loaded to the DAC register (0 to 16,383).
The ADSP-21xx family of DSPs is easily interfaced to the
AD5535 without the need for extra logic. A data transfer is
initiated by writing a word to the TX register after the SPORT
has been enabled. In a write sequence, data is clocked out on
each rising edge of the DSP’s serial clock and clocked into the
AD5535 on the falling edge of its SCLK. The easiest way to
provide the 19-bit data-word required by the AD5535, is to
transmit two 10-bit data-words from the ADSP-21xx. Ensure
that the data is positioned correctly in the TX register so that
the first 19 bits transmitted contain valid data.
The output buffer amplifier is specified to drive a load of 1 MΩ
and 200 pF. The linear output voltage range for the output
amplifier is from 7 V to VPP − 10V. The amplifier output band-
width is typically 5 kHz, and is capable of sourcing 700 µA and
sinking 2.8mA. Settling time for a full-scale step is typically
30 µs with no load and 110 µs with a 200 pF load.
RESET FUNCTION
The reset function on the AD5535 can be used to reset all nodes
on the device to their power-on reset condition. All the DACs
are loaded with 0s and all registers are cleared. The reset
Set up the SPORT control register as follows:
TFSW = 1, Alternate Framing
RESET
function is implemented by taking the
pin low.
SERIAL INTERFACE
INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = 1, Frame Every Word
The serial interface is controlled by three pins:
SYNC
interface.
•
•
•
is the frame synchronization pin for the serial
SCLK is the serial clock input. This pin operates at clock
speeds of up to 30 MHz.
ITFS = 1, Internal Framing Signal
SLEN = 1001, 10-Bit Data Word
Figure 11 shows the connection diagram.
DIN is the serial data input. Data must be valid on the falling
edge of SCLK.
To update a single DAC channel, a 19-bit data-word is written
to the AD5535 input register.
Rev. PrE | Page 11 of 16
AD5535
Preliminary Technical Data
AD5535 to PIC16C6X/7X
ADSP-2101/
ADSP-2103*
AD5535*
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit = 0. This is done by
writing to the synchronous serial port control register
SCLK
SCLK
D
DT
IN
TFS
SYNC
(SSPCON). See the PIC16/17 Microcontroller User Manual. In
*ADDITIONAL PINS OMITTED FOR CLARITY
SYNC
this example, I/O port RA1 is being used to pulse
and
enable the serial port of the AD5535. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
necessary to transmit 19 bits of data. Data is transmitted MSB
first. It is important to left-justify the data in the SPDR register
so that the first 19 bits transmitted contain valid data. RA1 must
be pulled low to start a transfer. It is taken high and pulled low
again before any further write cycles can take place. Figure 13
shows the connection diagram.
Figure 11. AD5535 to ADSP-2101/ADSP-2103 Interface
AD5535 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), clock polarity bit
(CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5535 and the MOSI output drives the serial data line
SYNC
(DIN) of the AD5535. The
line (PC7). When data is being transmitted to the AD5535, the
SYNC
signal is derived from a port
PIC16C6x/7x*
AD5535*
SCLK
SCK/RC3
line is taken low (PC7).
D
SDI/RC4
RA1
IN
SYNC
Data appearing on the MOSI output is valid on the falling edge
of SCK. The 68HC11 transfers only eight bits of data during
each serial transfer operation; therefore, three consecutive write
operations are necessary to transmit 19 bits of data. Data is
transmitted MSB first. It is important to left-justify the data in
the SPDR register so that the first 19 bits transmitted contain
valid data. PC7 must be pulled low to start a transfer. It is taken
high and pulled low again before any further write cycles can
take place. See Figure 12.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. AD5535 to PIC16C6x/7x Interface
AD5535 to 8051
The AD5535 requires a clock synchronized to the serial data.
The 8051 serial interface must, therefore, be operated in
Mode 0. In this mode, serial data exits the 8051 through RxD,
SYNC
and a shift clock is output on TxD. The
signal is derived
from a port line (P1.1). Figure 14 shows how the 8051 is
connected to the AD5535. Because the AD5535 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. Note also that the
AD5535 requires its data with the MSB first. Because the 8051
outputs the LSB first, the transmit routine must take this into
account.
MC68HC11*
AD5535*
SCLK
SCK
D
MOSI
PC7
IN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. AD5535 to MC68HC11 Interface
8051*
AD5535*
SCLK
TxD
RxD
P1.1
D
IN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. AD5535 to 8051 Interface
Rev. PrE | Page 12 of 16
Preliminary Technical Data
AD5535
APPLICATIONS INFORMATION
MEMS MIRROR CONTROL APPLICATION
REF198
(4.096V)
+5V +210V
OUTPUT RANGE
0V TO 200V
The AD5535 is targeted to all optical switching control systems
based on micro-electromechanical systems (MEMS)
technology. The AD5535 is a 32-channel, 14-bit DAC with
integrated high voltage amplifiers. The output amplifiers are
capable of generating an output range of 0 V to 200 V when
using a 4 V reference. The full-scale output voltage is
programmable from 50 V to 200 V using reference voltages
from 1 V to 4V. Each amplifier can output 700 µA and directly
drives the control actuators, which determine the position of
MEMS mirrors in optical switch applications.
V
V
REF_IN
+
PP
SENSOR
+
14-BIT DAC
8-CHANNEL
V
1
O
ADC (AD7856)
4 TO 1 MUX
(ADG739)
ACTUATORS
FOR
OR
MEMS
OR
MIRROR
ARRAY
V
32
O
SINGLE
CHANNEL
ADC (AD7671)
14-BIT DAC
32 TO 1 MUX
(ADG732)
AD5535
V
–
–5V
ADSP21065L
The AD5535 is generally used in a closed-loop feedback system,
as shown in Figure 15, with a high resolution ADC and DSP.
The exact position of each mirror is measured using capacitive
sensors. The sensor outputs are multiplexed using an ADG739
to an 8-channel 14-bit ADC (AD7856). An alternative solution
is to multiplex using a 32-to-1 multiplexer (ADG732) into a
single-channel ADC (AD7671). The control loop is driven by an
ADSP-21065L, a 32-bit SHARC DSP with an SPI-compatible
SPORT interface. With its 14-bit monotonic behavior and 0 V to
200 V output range coupled with its fast serial interface, the
AD5535 is ideally suited for controlling a cluster of MEMS-
based mirrors.
Figure 15. AD5535 in a MEMS-Based Optical Switch
AD5535 BOARD LAYOUT TO ENSURE
COMPLIANCE WITH IPC-221 SPECIFICATION
The diagram in Figure 16 is a typical 2-layer printed circuit
board layout for the AD5535 complying with the specifications
outlined in IPC221. The four corner balls labeled as original no-
connects must remain, because no connections and no signals
should be connected to these balls. Balls labeled as additional
no-connects should be connected to AGND.
The routing shown in Figure 16 shows the feasibility of
connecting to the high voltage balls while complying with the
spacing requirements of IPC-221. Figure 17 shows the physical
distances that are available.
A1 BALL PAD CORNER
1
2
3
4
5
9
11 12 13 14
10
1
6
7
8
2
5
A
B
C
D
0
µ
m
1.414mm
DETAIL A
R
S
A
P
1
D
0
A
0
C
µ
E
m
S
=
4
0
5
5
P
E
F
µ
A
m
m
C
E
2
ORIGINAL
5
=
0
4
NO-CONNECTS
µ
G
0
m
µ
R
250µm RAD
A
H
J
ADDITIONAL
NO-CONNECTS
D
SPACE = 433µm
100µm
100µm
K
L
2mm
SPACE = 433µm
M
N
P
SPACE = 433µm
250µm RAD
1
1
1
Figure 16. Layout Guidelines to Comply with IPC-221
Rev. PrE | Page 13 of 16
AD5535
Preliminary Technical Data
shield and increase the signal-to-noise performance of the
converters by reducing the amount of high frequency digital
coupling. Avoid running digital lines under the device, because
they couple noise onto the die. The ground plane should be
allowed to run under the IC to avoid noise coupling.
POWER SUPPLY SEQUENCING AND DECOUPLING
RECOMMENDATIONS
The diagram in Figure 17 shows the recommended decoupling,
and power supply protection for the AD5535. On the AD5535 it
is recommended that all grounds be tied together as close to the
device as possible. All supplies should be brought back
separately and a provision be made on the board via a link
option to drive the AVCC and V+ from the same supply if
required to reduce the number of supplies. All power supplies
should be adequately decoupled with 10 uF tantalum and 0.1 uF
ceramic capacitors. Note that the capacitors on the VPP supply
must be rated at greater than 210 V. To overcome issues
associated with power supply sequencing when using high
voltage supplies, the use of protection diodes as indicated in
Figure 17 is recommended.
As large a trace as possible should be used for the supply lines to
the device to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals like clocks should be shielded with digital ground to
avoid radiating noise to other sections of the board, and clock
signals should never be run near analog inputs of devices. Avoid
crossovers of digital and analog signals. Traces for analog inputs
should be kept as wide and as short as possible and should be
shielded with analog ground where possible. Traces on opposite
sides of a 2-layer printed circuit board should run at right
angles to each other to reduce the effects of feedthrough
through the board.
V
= –5V
V
= +5V
V
= +210V
–
+
PP
10µF
10µF
SCHOTTKY DIODE
MFTR: ITT
A microstrip technique is by far the best, but not always possible
with a double-sided board. In this technique the component
side of the board is dedicated to ground planes, and signals are
placed on the solder side. Multilayer printed circuit boards with
dedicated ground, power, and tracking layers offer the optimum
solution in terms of obtaining analog performance but at
increased manufacturing costs.
HIGH VOLTAGE DIODE
MFTR: GS
0.1µF
0.1µF
0.1µF
10µF
SD103C
RS1G
PGND
AGND
V
V
+
V
–
PP
AV
AV = +5V
CC
CC
DACGND
DGND
10µF
0.1µF
Good decoupling is vitally important when using high resolu-
tion converters. All analog supplies should be decoupled with
10 µF tantalum in parallel with 0.1 µF ceramic capacitors to
analog ground. To achieve the best from the decoupling
components, these have to be placed as close to the device as
possible ideally right up against the IC or IC socket. The main
aim of a bypassing element is to maximize the charge stored in
the bypass loop while simultaneously minimizing the
inductance of this loop. Inductance in the loop acts as an
impedance to high frequency transients and results in power
supply spiking. By keeping the decoupling as close to the device
as possible, the loop area is kept as small as possible, thereby
reducing the possibility of power-supply spikes. Digital supplies
of high resolution converters should be decoupled with 10 µF
tantalum and 0.1 µF ceramic to the digital ground plane. VDD
and VSS supplies of amplifiers should be decoupled again with
10 µF and 0.1 µF to AGND.
AD5535
DV
DV = +5V
CC
CC
10µF
0.1µF
Figure 17. Recommended Power Supply Sequencing and Decoupling
GUIDELINES FOR PRINTED CIRCUIT BOARD
LAYOUT
Printed circuit boards should be designed such that the analog
and digital sections are separated and confined to designated
analog and digital sections of the board. This facilitates the use
of ground planes that can be separated easily. A minimum etch
technique is generally found to be the best for ground planes,
because this optimizes shielding of sensitive signal lines. Digital
and analog grounds planes should be joined only in one place,
at the AGND and DGND pins of the high resolution converter.
Data and address busses on the board should be buffered or
latched to isolate the high frequency bus of the processor from
the bus of the high-resolution converters. These act as a faraday
All logic chips should be decoupled with 0.1µF to digital
ground to decouple high frequency effects associated with
digital circuitry.
Rev. PrE | Page 14 of 16
Preliminary Technical Data
OUTLINE DIMENSIONS
AD5535
A1 CORNER
INDEX AREA
15.00
BSC SQ
14 13 12 11 10
2
7 4 1
9 8 6
5 3
A
B
C
D
E
F
G
H
J
TOP VIEW
K
L
M
N
P
1.00 BSC
BOTTOM VIEW
DETAIL A
1.70 MAX
*
DETAIL A
1.25 MAX
0.85 MIN
*
0.41
0.36
0.31
*
COMPLIANT WITH JEDEC STANDARDS
MO-192-AAE-1 EXCEPT FOR DIMENSIONS
INDICATED BY A "*" SYMBOL. NOMINAL BALL
SIZE IS REDUCED FROM 0.60mm TO 0.46mm.
0.12 NOM
COPLANARITY
ꢀ
SEATING
PLANE
*
0.46 NOM
BALL DIAMETER
Figure 18. 124-Lead CSB-BGA Package [CSP-BGA]
(BC-124)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Function
Output Voltage Span
Temperature Range
Package Description
Package Option
BC-124
ADꢀꢀ3ꢀABC 32 DACs
± to 2±± V maximum
124-Lead CSP-BGA
−1±°C to +8ꢀ°C
Rev. PrE | Page 1ꢀ of 16
AD5535
NOTES
Preliminary Technical Data
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05068–0–10/04(PrE)
Rev. PrE | Page 16 of 16
相关型号：
AD5535BKBC
32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V
ADI
AD5535BKBCZ
32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V
ADI
©2020 ICPDF网 联系我们和版权申明