AD5539S [ADI]
Ultrahigh Frequency Operational Amplifier; 超高频运算放大器
| 型号： | AD5539S |
| 厂家： | 
ADI |
| 描述： | Ultrahigh Frequency Operational Amplifier |
| 文件： | 总16页 (文件大小：475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultrahigh Frequency
Operational Amplifier
a
AD5539
FEATURES
CO NNECTIO N D IAGRAM
P lastic D IP (N) P ackage
or Cer dip (Q ) P ackage
Im proved Replacem ent for Signetics SE/ NE5539
AC PERFORMANCE
Gain Bandw idth Product: 1.4 GHz typ
Unity Gain Bandw idth: 220 MHz typ
High Slew Rate: 600 V/ s typ
Full Pow er Response: 82 MHz typ
Open-Loop Gain: 47 dB m in, 52 dB typ
DC PERFORMANCE
All Guaranteed DC Specifications Are 100% Tested
For Each Device Over Its Full Tem perature
Range – For All Grades and Packages
VOS : 5 m V m ax Over Full Tem perature Range
(AD5539S)
IB: 20 A m ax (AD5539J )
CMRR: 70 dB m in, 85 dB typ
PSRR: 100 V/ V typ
MIL-STD-883B Parts Available
P RO D UCT H IGH LIGH TS
1. All guaranteed dc specifications are 100% tested.
2. T he AD5539 drives 50 Ω and 75 Ω loads directly.
3. Input voltage noise is less than 4 nV√Hz.
4. Low cost RF and video speed performance.
5. ±2 volt output range into a 150 Ω load.
6. Low cost.
P RO D UCT D ESCRIP TIO N
T he AD5539 is an ultrahigh frequency operational amplifier de-
signed specifically for use in video circuits and RF amplifiers.
Requiring no external compensation for gains greater than 5, it
may be operated at lower gains with the addition of external
compensation.
As a superior replacement for the Signetics NE/SE5539, each
AD5539 is 100% dc tested to meet all of its guaranteed dc
specifications over the full temperature range of the device.
7. Chips available.
T he high slew rate and wide bandwidth of the AD5539 provide
low cost solutions to many otherwise complex and expensive
high frequency circuit design problems.
T he AD5539 is available specified to operate over either the
commercial (AD5539JN/JQ) or military (AD5539SQ) tempera-
ture range. T he commercial grade is available either in 14-pin
plastic or cerdip packages. T he military version is supplied in
the cerdip package. Chip versions are also available.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD5539–SPECIFICATIONS(@ +25؇C and V = ؎8 V dc, unless otherwise noted)
S
AD 5539J
Typ
AD 5539S
Typ
P aram eter
Min
Max
Min
Max
Units
INPUT OFFSET VOLT AGE
Initial Offset1
TMIN to T MAX
2
5
6
2
3
5
mV
mV
INPUT OFFSET CURRENT
Initial Offset2
TMIN to TMAX
0.1
2
5
0.1
1
3
µA
µA
INPUT BIAS CURRENT
Initial2
VCM = 0
Either Input
TMIN to T MAX
6
20
40
6
13
25
µA
µA
FREQUENCY RESPONSE
RL = 150 Ω3
Small Signal Bandwidth
ACL = 24
Gain Bandwidth Product
ACL = 26 dB
220
220
MHz
MHz
1400
1400
Full Power Response
ACL = 24
ACL = 7
ACL = 20
Settling T ime (1%)
Slew Rate
68
82
65
12
600
4
68
82
65
12
600
4
MHz
MHz
MHz
ns
V/µs
ns
Large Signal Propagation Delay
T otal Harmonic Distortion
RL = ∞
0.010
0.016
0.010
0.016
%
%
RL = 100 Ω3
VOUT = 2 V p–p
ACL = 7, f = 1 kHz
INPUT IMPEDANCE
100
2
100
2
kΩ
OUT PUT IMPEDANCE (f <10 MHz)
Ω
INPUT VOLT AGE RANGE
Differential5
(Max Nondestructive)
Common-Mode Voltage
(Max Nondestructive)
Common-Mode Rejection Ratio
∆VCM = 1.7 V
250
2.5
250
2.5
mV
V
RS = 100 Ω
TMIN to T MAX
70
60
85
70
60
85
dB
dB
INPUT VOLT AGE NOISE
Wideband RMS Noise (RT I)
BW = 5 MHz; RS = 50 Ω
Spot Noise
5
4
5
4
FV
nV√Hz
F = 1 kHz; RS = 50 Ω
OPEN-LOOP GAIN
VO = +2.3 V, –1.7 V
RL = 150 Ω3
RL = 2 kΩ
TMIN to T MAX –RL = 2 kΩ
47
47
43
52
58
58
63
47
48
46
52
58
57
60
dB
dB
dB
–2–
REV. B
AD5539
AD 5539J
Typ
AD 5539S
Typ
P aram eter
Min
Max
Min
Max
Units
OUT PUT CHARACT ERIST ICS
Positive Output Swing
RL = 150 Ω3
+2.3
+2.3
+2.8
+3.3
+2.3
+2.5
+2.8
+3.3
V
V
RL = 2 kΩ
TMIN to T MAX with
RL = 2 kΩ
+2.3
+2.3
V
Negative Output Swing
RL = 150 Ω3
RL = 2 kΩ
–2.2
–2.9
–1.7
–1.7
–2.2
–2.9
–1.7
–2.0
V
V
TMIN to T MAX with
RL = 2 kΩ
–1.5
–1.5
V
POWER SUPPLY (No Load, No Resistor to –VS)
Rated Performance
±8
±8
V
V
Operating Range
Quiescent Current
؎4.5
؎10
؎4.5
؎10
Initial ICC
T MIN to TMAX
Initial ICC
T MIN to T MAX
+
14
11
18
20
15
17
14
11
17
18
14
15
mA
mA
mA
mA
–
PSRR
Initial
100
1000
2000
100
1000
2000
µV/V
µV/V
TMIN to TMAX
T EMPERAT URE RANGE
Operating,
Rated Performance
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
PACKAGE OPT IONS
AD5539JN, AD5539JQ
AD5539SQ
Plastic (N-14)
Cerdip (Q-14)
AD5539JN
AD5539JQ
AD5539SQ, AD5539SQ/883B
J and S Grade Chips Available
NOT ES
1Input Offset Voltage specifications are guaranteed after 5 minutes of operation at T A = +25°C.
2Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25°C.
3RX = 470 Ω to –VS.
4Externally compensated.
5Defined as voltage between inputs, such that neither exceeds +2.5 V, –5.0 V from ground.
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
REV. B
–3–
AD5539
ABSO LUTE MAXIMUM RATINGS*
O FFSET NULL CO NFlGURATIO N
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 550 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5 V, –5.0 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 0.25 V
Storage T emperature Range (Q) . . . . . . . . . –65°C to +150°C
Storage T emperature Range (N) . . . . . . . . . –65°C to +125°C
Operating T emperature Range
AD5539JN . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD5539JQ . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD5539SQ . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead T emperature Range (Soldering 60 Seconds) . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
METALIZATIO N P H O TO GRAP H
D imensions shown in inches and (mm).
Contact factory for latest dimensions.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5539 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
Typical Characteristics AD5539
—
Figure 3. Maxim um Com m on-
Mode Voltage vs. Supply Voltage
Figure 1. Output Voltage Swing
vs. Supply Voltage
Figure 2. Output Voltage Swing
vs. Load Resistance
Figure 6. Low Frequency Input
Noise vs. Frequency
Figure 5. Input Voltage vs. Output
Voltage for Various Tem peratures
Figure 4. Positive Supply Current
vs. Supply Voltage
Figure 9. Harm onic Distortion
vs. Frequency – High Gain
Figure 8. Harm onic Distortion
vs. Frequency – Low Gain
Figure 7. Com m on-Mode
Rejection Ratio vs. Frequency
REV. B
–5–
AD5539
Figure 10. Full Power Response
Figure 11. Deviation from Ideal Gain
vs. Closed-Loop Voltage Gain
Figure 12. AD5539 Circuit
some special precautions are in order. All real-world applica-
tions circuits must be built using proper RF techniques: the use
of short interconnect leads, adequate shielding, groundplanes,
and very low profile IC sockets. In addition, very careful bypass-
ing of power supply leads is a must.
FUNCTIO NAL D ESCRIP TIO N
T he AD5539 is a two-stage, very high frequency amplifier.
Darlington input transistors Q1, Q4–Q2, Q3 form the first
stage—a differential gain amplifier with a voltage gain of ap-
proximately 50. T he second stage, Q5, is a single-ended ampli-
fier whose input is derived from one phase of the differential
amplifier output; the other phase of the differential output is
then summed with the output of Q5. T he all NPN design of the
AD5539 is configured such that the emitter of Q5 is returned,
via a small resistor to ground; this eliminates the need for sepa-
rate level shifting circuitry.
Low-impedance transmission line is frequently used to carry sig-
nals at RF frequencies: 50 Ω line for telecommunications pur-
poses and 75 Ω for video applications. T he AD5539 offers a
relatively low output impedance; therefore, some consideration
must be given to impedance matching. A common matching
technique involves simply placing a resistor in series with the
amplifier output that is equal to the characteristic impedance of
the transmission line. T his provides a good match (although at a
loss of 6 dB), adequate for many applications.
T he output stage, consisting of transistors Q9 and Q10, is a
Darlington voltage follower with a resistive pull-down. T he bias
section, consisting of transistors Q6, Q7 and Q8, provides a
stable emitter current for the input section, compensating for
temperature and power supply variations.
All of the circuits here were built and tested in a 50 Ω system.
Care should be taken in adapting these circuits for each particu-
lar use. Any system which has been properly matched and ter-
minated in its characteristic impedance should have the same
small signal frequency response as those shown in this
data sheet.
SO ME GENERAL P RINCIP LES O F H IGH FREQ UENCY
CIRCUIT D ESIGN
In designing practical circuits with the AD5539, the user must
remember that whenever very high frequencies are involved,
–6–
REV. B
AD5539
AP P LYING TH E AD 5539
when operating at a noise gain of 7. Under these conditions, ex-
cess phase shift causes nearly 10 dB of peaking at 150 MHz.
T he AD5539 is stable for closed-loop gains of 4 or more as an
inverter and at (noise) gains of 5 or greater as a voltage follower.
T his means that whenever the AD5539 is operated at noise
gains below 5, external frequency compensation must be used to
insure stable operation.
Figure 15 illustrates the use of both lead and lag compensation
to permit stable low-gain operation. T he AD5539 is shown con-
nected as an inverting amplifier with the required external com-
ponents added to provide stability and improve high frequency
response. T he stray capacitance between the amplifier summing
junction and ground, CX, represents whatever capacitance is as-
sociated with the particular type of op amp package used plus
the stray wiring capacitance at the summing junction.
T he following sections outline specific compensation circuits
which permit stable operation of the AD5539 down to follower
(noise) gains of 3 (inverting gains of 2) with corresponding
–3 dB bandwidths up to 390 MHz. External compensation is
achieved by modifying the frequency response to the AD5539’s
external feedback network (i.e., by adding lead-lag compensa-
tion) so that the amplifier operates at a noise gain of 5 (or more)
at frequencies over 44 MHz, independent of signal gain.
Evaluating the lead capacitance first (ignoring RLAG and CLAG
for now): the feedback network, consisting of R2 and CLEAD, has
a pole frequency equal to:
1
FA
=
(1)
(2)
2 π C
+ CX R1|| R2
(
) (
)
LEAD
and a zero frequency equal to:
1
FB =
2 π R1 × C
(
)
LEAD
Usually, frequency FA is made equal to FB; that is, (R1CX) =
(R2 CLEAD), in a manner similar to the compensation used for
an attenuator or scope probe. However, if the pole frequency,
FA, will lie above the unity gain crossover frequency (440 MHz),
then the optimum location of FB will be near the crossover
Figure 13. Sm all Signal Open-Loop Gain and
Phase vs. Frequency
GENERAL P RINCIP LES O F LEAD AND LAG
CO MP ENSATIO N
T he AD5539 has its first pole or breakpoint in its open-loop fre-
quency response at about 10 MHz (see Figure 13). At frequen-
cies beyond 100 MHz, phase shift increases such that the output
lags the input by 180°—well before the unity gain crossover fre-
quency. T herefore, severe peaking (and possible oscillation) will
result if the AD5539 is operated at noise gains below 5, unless
external compensation is employed. Figure 14 shows the un-
compensated closed-loop frequency response of the AD5539
Figure 15. Inverting Am plifier Model Showing Both Lead
and Lag Com pensation
Figure 16. A Model of the Feedback Network of the
Inverting Am plifier
Figure 14. AD5539 Uncom pensated Response, Closed-
Loop Gain = 7
REV. B
–7–
AD5539
frequency. Both of these circuit techniques add a large amount
of leading phase shift at the crossover frequency, greatly aiding
stability.
T he lag network (RLAG, CLAG) increases the feedback attenua-
tion, i.e., the amplifier operates at a higher noise gain, above
some frequency, typically one-tenth of the crossover frequency.
As an example, to achieve a noise gain of 5 at frequencies above
44 MHz, for the circuit of Figure 15, would require a network
of:
R1
RLAG
=
(3)
4R1 / R2 – 1
(
)
and . . .
1
CLAG
=
2 π RLAG 44 × 106
(4)
(
)
Figure 18. Response of the (Figure 17) Inverter Circuit
without a Lag Com pensation Network
It is worth noting that an RLAG resistor may be used alone, to in-
crease the noise gain above 5 at all frequencies. However, this
approach has the disadvantage of also increasing the dc offset
and low frequency noise errors by an amount equal to the in-
crease in gain, in this case, by a factor of 5.
A lag network (Figure 15) can be added to improve the response
of this circuit even further as shown in Figures 19 and 20. In al-
most all cases, it is imperative to make capacitor CLEAD adjust-
able; in some cases, CLAG must also be variable. Otherwise,
component and circuit capacitance variations will dominate cir-
cuit performance.
SO ME P RACTICAL CIRCUITS
T he preceding general principles may now be applied to some
actual circuits.
A Gener al P ur pose Inver ter Cir cuit
Figure 17 is a general purpose inverter circuit operating at a
gain of –2.
For this circuit, the total capacitance at the inverting input is ap-
proximately 3 pF; therefore, CLEAD from Equations 1 and 2
needs to be approximately 1.5 pF. As shown in Figure 17, a
small trimmer is used to optimize the frequency response of this
circuit. Without a lag compensation network, the noise gain of
the circuit is 3.0 and, as shown in Figure 18, the output ampli-
tude remains within ±0.5 dB to 170 MHz and the –3 dB band-
width is 200 MHz.
Figure 19. Response of the (Figure 17) Inverter Circuit
with an RLAG Com pensation Network Em ployed
Figure 17. A General Purpose Inverter Circuit
Figure 20. Response of the (Figure 17) Inverter Circuit
with an RLAG and a CLAG Com pensation Network
Em ployed
–8–
REV. B
AD5539
Figures 21 and 22 show the small and large signal pulse re-
sponses of the general purpose inverter circuit of Figure 17, with
CLEAD = 1.5 pF, RLAG = 330 Ω and CLAG = 3.5 pF.
Figure 21. Sm all Signal Pulse Response of the (Figure 17)
Inverter Circuit; Vertical Scale: 50 m V/div; Horizontal
Scale: 5 ns/div
Figure 23. A Gain of 2 Inverter Circuit with the CLEAD
Capacitor Connected to Pin 12
Figure 22. Large Signal Response of the (Figure 17)
Inverter Circuit; Vertical Scale: 200 m V/div, Horizontal
Scale: 5 ns/div
A CLEAD capacitor may be used to limit the circuit bandwidth
and to achieve a single pole response free of overshoot
Figure 24. Response of the Circuit of Figure 23 with
CLEAD = 10 pF
1
–3 dB frequency =
A Gener al P ur pose Voltage Follower Cir cuit
2 π R2 CLEAD
Noninverting (voltage follower) circuits pose an additional com-
plication, in that when a lag network is used, the source imped-
ance will affect the noise gain. In addition, the slightly greater
bandwidth of the noninverting configuration makes any excess
phase shift due to the output stage more of a problem.
If this option is selected, it is recommended that a CLEAD be
connected between Pin 12 and the summing junction, as shown
in Figure 23. Pin 12 provides a separately buffered version of
the output signal. Connecting the lead capacitor here avoids the
excess output-stage phase shift and subsequent oscillation prob-
lems (at approx. 350 MHz) which would otherwise occur when
using the circuit of Figure 17 with a CLEAD of more than about
2 pF.
For example, a gain of 3 noninverting circuit with CLEAD con-
nected normally (across the feedback resistor – Figure 25) will
require a source resistance of 200 Ω or greater to prevent UHF
oscillation; the extra source resistance provides some damping
as well as increasing the noise gain. T he frequency response plot
of Figure 26 shows that the highest –3 dB frequency of all the
applications circuits can be achieved using this connection, un-
fortunately, at the expense of a noise gain of 14.2.
Figure 24 shows the response of the circuit of Figure 23 for each
connection of CLEAD. Lag components may also be added to this
circuit to further tailor its response, but, in this case, the results
will be slightly less satisfactory than connecting CLEAD directly
to the output, as was done in Figure 17.
REV. B
–9–
AD5539
Figure 28. Response of the Gain of 3 Follower with CLEAD
CLAG and RLAG
,
T hese same principles may be applied when capacitor CLEAD is
connected to Pin 12 (Figure 29). Figure 30 shows the band-
width of the gain of 3 amplifier for various values of RLAG. It can
be seen from these response plots that a high noise gain is still
needed to achieve a reasonably flat response (the smaller the
Figure 25. A Gain of 3 Follower with Both Lead and Lag
Com pensation
Figure 26. Response of the Gain of 3 Follower Circuit
Adding a lag capacitor (Figure 27) will greatly reduce the
midband and low frequency noise gain of the circuit while sacri-
ficing only a small amount of bandwidth as shown in Figure 28.
Figure 29. A Gain of 3 Follower Circuit with CLEAD
Com pensation Connected to Pin 12
Figure 30. Response of the Gain of 3 Follower Circuit with
CLEAD Connected to Pin 12
Figure 27. A Gain of 3 Follower Circuit with Both CLEAD
and RLAG Com pensation
–10–
REV. B
AD5539
value of RLAG, the higher the noise gain). For example, with a
220 Ω RLAG and a 50 Ω source resistance, the noise gain will be
12.8, because the source resistance affects the noise gain.
Figures 31 and 32 show the small and large signal responses of
the circuit of Figure 29.
Figure 33. A 20 dB Gain Video Am plifier for 75 Ω System s
Figure 31. The Sm all-Signal Pulse Response of the Gain
of 3 Follower Circuit with RLAG and CLEAD Com pensation to
Pin 12; Vertical Scale: 50 m V/div; Horizontal Scale:
5 ns/div
Figure 34. Response of the 20 dB Video Am plifier
Figure 32. The Large-Signal Pulse Response of the Gain
of 3 Follower Circuit with RLAG and CLEAD Com pensation to
Pin 12; Vertical Scale: 200 m V/div; Horizontal Scale:
5 ns/div
In color video applications, the quality of differential gain and
differential phase response is very important. Figures 35 and 36
show a circuit and test setup to measure the AD5539’s response
to a modulated ramp signal (0-90 IRE p-p ramp, 40 IRE p-p
modulation, 4.4 MHz).
A Video Am plifier Cir cuit with 20 dB Gain (Ter m inated)
High gain applications (14 dB and up) require only a small lead
capacitance to obtain flat response. T he 26 dB (20 dB termi-
nated) video amplifier circuit of Figure 33 has the response
shown in Figure 34 using only approximately 0.5-1 pF lead ca-
pacitance. Again, a small CLEAD can be connected, either to the
output or to Pin 12 with very little difference in response.
Figures 37 and 38 show the differential gain and phase response.
REV. B
–11–
AD5539
Figure 38. Differential Phase vs. Ram p Am plitude
Figure 35. Differential Gain and Phase Measurem ent
Circuit
MEASURING AD 5539 SETTLING TIME
Measuring the very rapid settling times associated with AD5539
can be a real problem for the designer; proper component layout
must be used and appropriate test equipment selected. In addi-
tion, both cable dispersion (a function of cable losses) and the
quality of termination (SWR) directly affect the measurement.
T he circuit of Figure 39 was used to make a “brute force”
AD5539 settling time measurement. T he fixture containing the
circuit was connected directly—using a male BNC connector
(but no cable)—onto the front of a 50 Ω input oscilloscope
preamp. A digital mainframe was then used to capture, average,
and expand the error signal. Most of the small-scale waveform
aberrations shown on the figure were caused by the oscilloscope
itself, especially the glitch at 15 ns. T he pulse source used for
this measurement was an EH-SPG2000 pulse generator set for a
1 ns rise-time; it was coupled directly to the circuit using 18" of
microwave 50 Ω hard line.
Figure 36. Differential Gain and Phase Test Setup
Figure 37. Differential Gain vs. Ram p Am plitude
Figure 39. AD5539 Settling Tim e Test Circuit
–12–
REV. B
AD5539
AP P LICATIO NS SUMMARY CH ART
GAIN
FLATNESS
(TRIMMED )
3 dB
BAND WID TH
R21
RLAG
CLAG
CLEAD
GAIN
2
2
R1
Gain = –1 to –5
Circuit of Fig. 17
R2
1
3pF
R1
2 k
≤
≤
≤
≤
≥
≥
≥
≈
≈
≈
≈
–2
±0.2 dB
±1 dB
200 MHz
180 MHz
390 MHz
340 MHz
2 π 44 × 106 RLAG
G
G
R1
R2
(
)
4
– 1
– 1
– 1
– 1
Gain = –1 to –5
Circuit of Fig. 23
R2
1
3pF
R1
2 k
2 k
2 k
–2
+3
+3
2 π 44 × 106 RLAG
G
G
R1
R2
(
)
4
Gain = +2 to +53
Circuit of Fig. 27
R2
G –1
3 pF
G –1
1
R1
±1 dB
2 π 44 × 106 RLAG
R1
R2
(
)
10
10
Gain = +2 to +54
Circuit of Fig. 29
R2
G –1
3 pF
G –1
R1
R1
R2
NA
±0.5 dB
R2
Gain < –5
1.5 k
1.5 k
NA
NA
NA
T rimmer5
T rimmer5
–20
±0.2 dB
±0.2 dB
80 MHz
80 MHz
G
R2
G –1
Gain > +5
NOT ES
NA
+20
G = Gain NA = Not Applicable
1Values given for specific results summarized here—applications can be adapted for values different than those specified.
2It is recommended that C LEAD and CLAG be trimmers covering a range that includes the computed value above.
3RSOURCE ≥ 200 Ω.
4RSOURCE ≥ 50 Ω.
5Use Voltronics CPA2 0.1–2.5 pF T eflon T rimmer Capacitor (or equivalent).
T he photos of Figures 40 and 41 demonstrate how the AD5539
easily settles to 1% (1 mV) in less than 12 ns; settling to 0.1%
(100 µV) requires less than 25 ns.
Figure 41. Error Signal from AD5539 Settling Tim e Test
Circuit – Rising Edge. Vertical Scale: 5 ns/div.; Horizontal
Scale: 500 µV/div
Figure 40. Error Signal from AD5539 Settling Tim e Test
Circuit – Falling Edge. Vertical Scale: 5 ns/div.; Horizontal
Scale: 500 µV/div
REV. B
–13–
AD5539
Figure 42 shows the oscilloscope response of the generator
alone, set up to simulate the ideal test circuit error signal
(Figure 43).
Figure 42. The Oscilloscope Response Alone Directly
Driven by the Test Generator. Vertical Scale: 5 ns/div.;
Horizontal Scale: 500 µV/div
Figure 43. A Sim ulated Ideal Test Circuit Error Signal
A 50 MH z VO LTAGE-CO NTRO LLED AMP LIFIER
Figure 44 is a circuit for a 50 MHz voltage-controlled amplifier
(VCA) suitable for use in high quality video-speed applications.
T his circuit uses the AD5539 as an output amplifier for the
AD539, a high bandwidth multiplier. T he outputs from the two
signal channels of the AD539 are applied to the op amp in a
subtracting configuration. T his connection has two main advan-
tages: first, it results in better rejection of the control voltage,
particularly when over-driven (VX < 0 or VX > 3.3 V). Secondly,
it provides a choice of either noninverting or inverting responses,
using either input VY1 or VY2, respectively. In this circuit, the
output of the op amp will equal:
Hence, the gain is unity at VX = +2 V. Since VX can overrange
to +3.3 V, the maximum gain in this configuration is about
4.3 dB. (Note: If Pin 9 of the AD539 is grounded, rather than
connected to the output of the 5539N, the maximum gain be-
comes 10 dB.)
T he bandwidth of this circuit is over 50 MHz at full gain, and is
not substantially affected at lower gains. Of course, when VX is
zero (or slightly negative, to override the residual input offset)
there is still a small amount of capacitive feedthrough at high
frequencies; therefore, extreme care is needed in laying out the
PC board to minimize this effect. Also, for small values of VX,
the combination of this feedthrough with the multiplier output
can cause a dip in the response where they are out of phase.
Figure 45 shows the ac response from the noninverting input,
with the response from the inverting input, VY2, essentially iden-
tical. T est conditions: VY1 = 0.5 V rms for values of VX from
+10 mV to +3.16 V; this is with a 75 Ω load on the output. T he
feedthrough at VX = –10 mV is also shown.
VX
VY1 – VY 2
(
)
for VX > 0
VOUT
=
2V
Figure 45. AC Response of the VCA at Different Gains
VY = 0.5 V RMS
Figure 44. A Wide Bandwidth Voltage-Controlled Am plifier
–14–
REV. B
AD5539
T he transient response of the signal channel at VX = +2 V,
Y = VOUT = + or –1 V is shown in Figure 46; with the VCA
V
driving a 75 Ω load. T he rise and fall times are both approxi-
mately 7 ns.
A few final circuit details: in general, the control amplifier com-
pensation capacitor for Pin 2, CC, must have a minimum value
of 3000 pF (3 nF) to provide both circuit stability and maximum
control bandwidth. However, if the maximum control bandwidth
is not needed, then it is advisable to use a larger value of CC,
with typical values between 0.01 and 0.1 µF. Like many aspects
of design, the value of CC will be a tradeoff: higher values of CC
will lower the high frequency distortion, reduce the high fre-
quency crosstalk and improve the signal channel phase response.
Conversely, lower values of CC will provide a higher control
channel bandwidth at the expense of degraded linearity in the
output response when amplitude modulating a carrier signal.
Figure 46. Transient Response of the Voltage-Controlled
Am plifier VX = +2 Volts, VY = ±1 Volt
mic node, the settling time of the control channel with a pulse
input will vary with different control input step levels.
T he control channel bandwidth will vary in inverse proportion to
the value of CC, providing a typical bandwidth of 2 MHz with a
CC of 0.01 µF and a VX voltage of +1.7 volts.
Diode D1 clamps the logarithmic control node at Pin 2 of the
AD539, (preventing this point from going too negative); this
diode helps decrease the circuit recovery time when the control
input goes below ground potential.
Both the bandwidth and pulse response of the control channel
can be further increased by using a feedforward capacitor, Cff,
with a value between 5 and 20 percent of CC. Cff should be care-
fully adjusted to give the best pulse response for a particular step
input applied to the control channel. Note that since Cff is con-
nected between a linear control input (Pin 1) and a logarith-
TH E AD 539/5539 CO MBINATIO N AS A FAST, LO W
FEED TH RO UGH , VID EO SWITCH
Figure 47 shows how the AD539/5539 combination can be used
to create a fast video speed switch suitable for many high fre-
Figure 47. An Analog Multiplier Video Switch
REV. B
–15–
AD5539
quency applications including color key switching. It features
both inverting and noninverting inputs and can provide an out-
put of ±1 V into a reverse-terminated 75 Ω load (or ±2 V into
150 Ω). An optional output offset adjustment is provided. T he
input range of the video switch is the same as the output range:
±1 V at either input generates ±1 V (noninverting) or ϯ1 V
(inverting) across the 75 Ω load. T he circuit provides a gain of
about 1, when “ON,” or zero when “OFF.”
T he differential-gain and differential-phase characteristics of
this switch are compatible with video applications. T he incre-
mental gain changes less than 0.05 dB over a signal window of 0
to +1 V, with a phase variation of less than 0.5 degree at the
subcarrier frequency of 3.58 MHz. T he noise level of this cir-
cuit measured at the 75 Ω load is typically 200 µV in a 0 MHz
to 5 MHz bandwidth or approximately 100 nV per root hertz.
T he noise spectral density is essentially flat to 40 MHz.
T he differential configuration uses both channels of the AD539
not only to provide alternative input phases, but also to elimi-
nate the switching pedestal due to step changes in the output
current as the AD539 is gated on or off.
T he waveforms shown in Figures 48 and 49 were taken across a
75 Ω termination; in both photos, the signal of 0 to +1 V (in
this case, an offset sine wave at 1 MHz) was applied to the
noninverting input. In Figure 48, the envelope response shows
the output being fully switched in about 50 ns. Note that the
output is ON when the control input is zero (or more negative)
and OFF for a control input of +1 V or more. T here is very
little control-signal breakthrough.
Figure 49 shows the response to a pulse of 0 to +1 V on the
signal channel. With the control input held at zero, the rise
time is under 10 ns. T he response from the inverting input
is similar.
Figure 49. The Signal Response of the Video Switcher
Figure 48. The Control Response of the Video Switcher
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
14-P in Cer dip P ackage
(Q -14)
14-P in P lastic D IP P ackage
(N-14)
–16–
REV. B
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