AD5541_技术文档

5 V, Serial-Input

Voltage-Output, 16-Bit DACs

a

AD5541/AD5542

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

Full 16-Bit Performance

5 V Single Supply Operation

Low Power

V

DD

AD5541

Short Settling Time

V

16-BIT DAC

Unbuffered Voltage Output Capable of Driving 60 k⍀

Loads Directly

REF

OUT

SPI™/QSPI™/MICROWIRE™-Compatible Interface

Standards

AGND

16-BIT DATA LATCH

CS

Power-On Reset Clears DAC Output to 0 V (Unipolar

Mode)

Schmitt Trigger Inputs for Direct Optocoupler Interface

DIN

CONTROL

LOGIC

SCLK

SERIAL INPUT REGISTER

DGND

APPLICATIONS

Digital Gain and Offset Adjustment

Automatic Test Equipment

Data Acquisition Systems

Industrial Process Control

V

DD

R

FB

AD5542

RFB

INV

R

INV

REFF

16-BIT DAC

V

OUT

REFS

AGNDF

AGNDS

GENERAL DESCRIPTION

CS

16-BIT DATA LATCH

The AD5541 and AD5542 are single, 16-bit, serial input,

voltage output DACs that operate from a single 5 V ± 10%

supply.

LDAC

CONTROL

LOGIC

SCLK

SERIAL INPUT REGISTER

DGND

DIN

The AD5541 and AD5542 utilize a versatile 3-wire interface that

is compatible with SPI, QSPI, MICROWIRE, and DSP inter-

face standards.

These DACs provide 16-bit performance without any adjust-

ments. The DAC output is unbuffered, which reduces power

consumption and offset errors contributed to by an output buffer.

PRODUCT HIGHLIGHTS

1. Single Supply Operation.

The AD5541 and AD5542 are fully speciﬁed and guaranteed

for a single 5 V ± 10% supply.

The AD5542 can be operated in bipolar mode generating a

±V_REFoutput swing. The AD5542 also includes Kelvin sense

connections for the reference and analog ground pins to reduce

layout sensitivity.

2. Low Power Consumption.

These parts consume typically 1.5 mW with a 5 V supply.

3. 3-Wire Serial Interface.

The AD5541 and AD5542 are available in an SO package.

4. Unbuffered output capable of driving 60 kΩ loads.

This reduces power consumption as there is no internal buffer

to drive.

5. Power-On Reset circuitry.

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(V_DD= 5 V ؎ 10%, V_REF= 2.5 V, AGND = DGND = 0 V. All speciﬁcations

T_A= T_MINto T_MAX,unless otherwise noted.)

AD5541/AD5542–SPECIFICATIONS

Parameter

Min Typ

Max

Unit

Test Condition

STATIC PERFORMANCE

Resolution

16

Bits

Relative Accuracy, INL

±0.5

±1.0

±2.0

±4.0

±1.0

±1.5

±5

LSB

L, C Grades

B, J Grades

A Grade

Guaranteed Monotonic

J Grade

Differential Nonlinearity

Gain Error

–1.5

T_A= 25°C

±7

LSB

Gain Error Temperature Coefﬁcient

Zero Code Error

±0.1

0.3

ppm/°C

LSB

±1

±2

T_A= 25°C

Zero Code Temperature Coefﬁcient

AD5542

±0.05

ppm/°C

Bipolar Resistor Matching

1.000

Ω/Ω

R_FB/R_INV, Typically R_FB= R_INV= 28 kΩ

±0.0015 ±0.0076

%

Ratio Error

Bipolar Zero Offset Error

±1

±5

±7

LSB

ppm/°C

T_A= 25°C

Bipolar Zero Temperature Coefﬁcient

±0.2

OUTPUT CHARACTERISTICS

Output Voltage Range

0

V_REF– 1 LSB

V

µs

V/µs

nV-s

kΩ

Unipolar Operation

–V_REF

AD5542 Bipolar Operation

to 1/2 LSB of FS, C_L= 10 pF

C_L= 10 pF, Measured from 0% to 63%

1 LSB Change Around the Major Carry

All 1s Loaded to DAC, V_REF= 2.5 V

Tolerance Typically 20%

Output Voltage Settling Time

Slew Rate

Digital-to-Analog Glitch Impulse

Digital Feedthrough

DAC Output Impedance

Power Supply Rejection Ratio

1

25

10

6.25

±1.0

LSB

∆V_DD± 10%

DAC REFERENCE INPUT

Reference Input Range

2.0

9

7.5

V_DD

V

kΩ

Reference Input Resistance²

Unipolar Operation

AD5542, Bipolar Operation

LOGIC INPUTS

Input Current

±1

0.8

µA

V

_INL, Input Low Voltage

V_INH, Input High Voltage

2.4

V

pF

V

Input Capacitance³

10

Hysteresis Voltage³

0.4

REFERENCE

Reference –3 dB Bandwidth

Reference Feedthrough

Signal-to-Noise Ratio

Reference Input Capacitance

1.3

1

92

75

120

MHz

mV p-p

dB

pF

All 1s Loaded

All 0s Loaded, V_REF= 1 V p-p at 100 kHz

Code 0000 Hex

Code FFFF Hex

POWER REQUIREMENTS

V_DD

I_DD

4.50

5.50

1.1

6.05

V

mA

mW

0.3

1.5

Power Dissipation

NOTES

¹Temperature ranges are as follows: A, B, C Versions: –40°C to +85°C. J, L Versions: 0°C to 70°C.

²Reference input resistance is code-dependent, minimum at 8555 hex.

³Guaranteed by design, not subject to production test.

Speciﬁcations subject to change without notice.

REV. A

–2–

AD5541/AD5542

(V_DD= 5 V ؎ 5%, V_REF= 2.5 V, AGND = DGND = 0 V. All speciﬁcations T_A= T_MINto T_MAX,unless

TIMING CHARACTERISTICS^{1, 2}otherwise noted.)

Limit at T_MIN, T_MAX

All Versions

Parameter

Unit

Description

f_SCLK

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

25

40

20

15

35

20

15

0

MHz max

ns min

SCLK Cycle Frequency

SCLK Cycle Time

SCLK High Time

SCLK Low Time

CS Low to SCLK High Setup

CS High to SCLK High Setup

SCLK High to CS Low Hold Time

SCLK High to CS High Hold Time

Data Setup Time

Data Hold Time

LDAC Pulsewidth

CS High to LDAC Low Setup

CS High Time Between Active Periods

t₉

t₁₀

t₁₁

t₁₂

30

NOTES

¹Guaranteed by design. Not production tested.

²Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to

90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

Speciﬁcations subject to change without notice.

t₁

SCLK

t₂

t₃

t₆

t₅

t₇

t₄

CS

t₁₂

t₈

t₉

DB15

DB0

DIN

t₁₁

t₁₀

LDAC*

*AD5542 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.

Figure 1. Timing Diagram

REV. A

–3–

AD5541/AD5542

ABSOLUTE MAXIMUM RATINGS*

(T_A= 25°C unless otherwise noted)

Maximum Junction Temperature, (T_Jmax) . . . . . . . . . 150°C

Package Power Dissipation . . . . . . . . . . . . . (T_Jmax – T_A)/θ_JA

Thermal Impedance θ_JA

SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . 149.5°C/W

SOIC (R-14) . . . . . . . . . . . . . . . . . . . . . . . . . . 104.5°C/W

Lead Temperature, Soldering

V_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

Digital Input Voltage to DGND . . . . . –0.3 V to V_DD+ 0.3 V

V

_OUTto AGND . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

AGND, AGNDF, AGNDS to DGND . . . . . –0.3 V to +0.3 V

Input Current to Any Pin Except Supplies . . . . . . . . ±10 mA

Operating Temperature Range

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C

Commercial (J, L Versions) . . . . . . . . . . . . . . . 0°C to 70°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this speciﬁcation is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model

INL

DNL

Temperature Range

Package Description

Package Option

AD5541CR

AD5541LR

AD5541BR

AD5541JR

AD5541AR

±1 LSB

±2 LSB

±4 LSB

±1 LSB

±1.5 LSB

±1 LSB

–40°C to +85°C

0°C to 70°C

–40°C to +85°C

0°C to 70°C

8-Lead Small Outline IC

SO-8

–40°C to +85°C

AD5542CR

AD5542LR

AD5542BR

AD5542JR

AD5542AR

±1 LSB

±2 LSB

±4 LSB

±1 LSB

±1.5 LSB

±1 LSB

–40°C to +85°C

0°C to 70°C

–40°C to +85°C

0°C to 70°C

14-Lead Small Outline IC

R-14

–40°C to +85°C

Die Size = 80 × 139 = 11,120 sq mil; Number of Transistors = 1,230.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD5541/AD5542 features proprietary ESD protection circuitry, permanent damage may occur

on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions

are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A

–4–

AD5541/AD5542

AD5541 PIN FUNCTION DESCRIPTIONS

Description

Mnemonic

Pin No.

V_OUT

AGND

REF

1

2

3

Analog Output Voltage from the DAC.

Ground Reference Point for Analog Circuitry.

This is the voltage reference input for the DAC. Connect to external 2.5 V reference.

Reference can range from 2 V to V_DD

.

CS

4

5

This is a logic input signal. The chip select signal is used to frame the serial data input.

SCLK

Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle

must be between 40% and 60%.

DIN

6

Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on

the rising edge of SCLK.

DGND

V_DD

7

8

Digital Ground. Ground reference for digital circuitry.

Analog Supply Voltage, 5 V ± 10%.

AD5541 PIN CONFIGURATION

SOIC

AD5542 PIN CONFIGURATION

SOIC

1

2

3

4

8

7

6

5

V

1

2

3

4

5

6

7

14

13

V

DD

RFB

DD

OUT

DGND

DIN

AGND

REF

CS

AD5541

TOP VIEW

(Not to Scale)

INV

V

OUT

12 DGND

AGNDF

AD5542

TOP VIEW

(Not to Scale)

SCLK

11 LDAC

AGNDS

REFS

REFF

CS

10

9

DIN

NC

8

SCLK

NC = NO CONNECT

AD5542 PIN FUNCTION DESCRIPTIONS

Description

Mnemonic

Pin No.

RFB

1

2

3

4

5

Feedback Resistor. In bipolar mode connect this pin to external op amp output.

Analog Output Voltage from the DAC.

V_OUT

AGNDF

AGNDS

REFS

Ground Reference Point for Analog Circuitry (Force).

Ground Reference Point for Analog Circuitry (Sense).

This is the voltage reference input (sense) for the DAC. Connect to external 2.5 V reference.

Reference can range from 2 V to V_DD

This is the voltage reference input (force) for the DAC. Connect to external 2.5 V reference.

Reference can range from 2 V to V_DD

.

REFF

6

.

CS

7

8

This is a logic input signal. The chip select signal is used to frame the serial data input.

SCLK

Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle

must be between 40% and 60%.

NC

9

No Connect.

DIN

10

Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on

the rising edge of SCLK.

LDAC

11

LDAC Input. When this input is taken low, the DAC register is simultaneously updated with

the contents of the input register.

DGND

INV

12

13

Digital Ground. Ground reference for digital circuitry.

Connected to the Internal Scaling Resistors of the DAC. Connect INV pin to external op amps

inverting input in bipolar mode.

V_DD

14

Analog Supply Voltage, 5 V ± 10%.

REV. A

–5–

AD5541/AD5542

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL)

is a measure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer function.

A typical INL versus code plot can be seen in Figure 2.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally speciﬁed as the area of the glitch in nV-s

and is measured when the digital input code is changed by 1 LSB

at the major carry transition. A plot of the glitch impulse is shown

in Figure 15.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A speciﬁed differential nonlinearity of ±1 LSB maximum

ensures monotonicity. Figure 3 illustrates a typical DNL versus

code plot.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the

analog output of the DAC from the digital inputs of the DAC,

but is measured when the DAC output is not updated. CS is

held high, while the CLK and DIN signals are toggled. It is

speciﬁed in nV-s and is measured with a full-scale code change

on the data bus, i.e., from all 0s to all 1s and vice versa. A typi-

cal plot of digital feedthrough is shown in Figure 14.

Gain Error

Gain error is the difference between the actual and ideal analog

output range, expressed as a percent of the full-scale range.

It is the deviation in slope of the DAC transfer characteristic

from ideal.

Power Supply Rejection Ratio

This speciﬁcation indicates how the output of the DAC is affected

by changes in the power supply voltage. Power-supply rejection

ratio is quoted in terms of % change in output per % change in

V_DDfor full-scale output of the DAC. V_DDis varied by ±10%.

Gain Error Temperature Coefficient

This is a measure of the change in gain error with changes in

temperature. It is expressed in ppm/°C.

Reference Feedthrough

Zero Code Error

This is a measure of the feedthrough from the V_REFinput to the

DAC output when the DAC is loaded with all 0s. A 100 kHz,

1 V p-p is applied to V_REF. Reference feedthrough is expressed

in mV p-p.

Zero code error is a measure of the output error when zero code

is loaded to the DAC register.

Zero Code Temperature Coefﬁcient

This is a measure of the change in zero code error with a change

in temperature. It is expressed in mV/°C.

REV. A

–6–

Typical Performance Characteristics–AD5541/AD5542

0.50

0.25

V

= 5V

V

= 5V

DD

= 2.5V

REF

0.25

0

–0.25

–0.50

–0.75

0

8192 16384 24576 32768 40960 49152 57344 65536

CODE

8192 16384 24576 32768 40960 49152 57344 65536

CODE

Figure 5. Differential Nonlinearity vs. Code

Figure 2. Integral Nonlinearity vs. Code

0.75

0.25

0

V

= 5V

DD

V

= 5V

DD

= 2.5V

REF

= 2.5V

REF

0.50

0.25

0

–0.25

–0.50

–0.75

–1.00

–0.25

–0.50

–60 –40

–20

0

20

40

60

80

100 120 140

–60 –40

–20

0

20

40

60

80

100 120 140

TEMPERATURE –

؇

C

TEMPERATURE –

؇

C

Figure 6. Differential Nonlinearity vs. Temperature

Figure 3. Integral Nonlinearity vs. Temperature

0.75

0.50

V

T

= 5V

= 25؇C

V

T

= 2.5V

= 25؇C

DD

REF

A

0.50

0.25

DNL

0.25

0

–0.25

INL

–0.25

–0.50

–0.75

INL

0

1

2

3

4

5

6

2

3

4

5

6

7

REFERENCE VOLTAGE – V

SUPPLY VOLTAGE – V

Figure 7. Linearity Error vs. Reference Voltage

Figure 4. Linearity Error vs. Supply Voltage

REV. A

–7–

AD5541/AD5542

0.75

0.50

0.25

0

V

= 5V

DD

V

= 5V

DD

= 2.5V

REF

= 2.5V

REF

–0.25

–0.50

–0.75

–60 –40 –20

0

20

40

60

80

100 120 140

–60 –40 –20

0

20

40

60

80

100 120 140

TEMPERATURE –

؇

C

TEMPERATURE –

؇

C

Figure 8. Gain Error vs. Temperature

Figure 11. Zero-Code Error vs. Temperature

250

450

V

= 5V

DD

LOGIC

T

= 25؇C

A

= 5V

= 2.5V

400

350

REF

REFERENCE

VOLTAGE

SUPPLY

VOLTAGE

200

300

250

200

150

V

= 5V

V

= 2.5V

DD

REF

150

–40

–20

0

20

40

60

80

100

120

0

1

2

3

4

5

6

VOLTAGE – V

TEMPERATURE –

؇

C

Figure 9. Supply Current vs. Temperature

Figure 12. Supply Current vs Reference Voltage or Supply

Voltage

400

350

300

250

200

150

300

5555H

V

= 5V

DD

V

= 5V

DD

8555H

= 2.5V

REF

= 2.5V

REF

T

= 25؇C

250

200

150

A

T

= 25؇C

A

0555H

BIPOLAR MODE

UNIPOLAR MODE

100

50

0

1

2

3

4

5

0

8192 16384 24576 32768 40960 49152 57344 65536

CODE

DIGITAL INPUT VOLTAGE – V

Figure 10. Supply Current vs. Digital Input Voltage

Figure 13. Reference Current vs. Code

REV. A

–8–

AD5541/AD5542

V

T

= 2.5V

= 5V

= 25؇C

REF

2µs/DIV

100

90

DD

100

90

CLOCK (5V/DIV)

A

CS (5V/DIV)

10pF

50pF

100pF

200pF

= 2.5V

V

(50mV/DIV)

OUT

V

T

REF

= 5V

10

DD

= 25؇C

A

10

0%

V

(0.5V/DIV)

OUT

2␮s/DIV

Figure 16. Large Signal Settling Time

Figure 14. Digital Feedthrough

V

= 2.5V

= 5V

= 25؇C

REF

V

= 2.5V

= 5V

= 25؇C

REF

100

DD

100

90

DD

V

(1V/DIV)

OUT

T

90

A

T

A

CS (5V/DIV)

V

(50mV/DIV)

OUT

GAIN = –216

1LSB = 8.2mV

V

(0.1V/DIV)

OUT

10

0%

0.5␮s/DIV

2µs/DIV

Figure 17. Small Signal Settling Time

Figure 15. Digital-to-Analog Glitch Impulse

GENERAL DESCRIPTION

With this type of DAC conﬁguration, the output impedance

is independent of code, while the input impedance seen by

the reference is heavily code dependent. The output voltage

is dependent on the reference voltage as shown in the follow-

ing equation.

The AD5541/AD5542 are single, 16-bit, serial input, voltage

output DACs. They operate from a single supply ranging from

2.7 V to 5 V and consume typically 300 mA with a supply of

5 V. Data is written to these devices in a 16-bit word format, via

a 3- or 4-wire serial interface. To ensure a known power-up state,

these parts were designed with a power-on reset function. In uni-

polar mode, the output is reset to 0 V, while in bipolar mode, the

AD5542 output is set to –V_REF. Kelvin sense connections for

the reference and analog ground are included on the AD5542.

V_REF× D

V_OUT

=

2^N

where D is the decimal data word loaded to the DAC register

and N is the resolution of the DAC. For a reference of 2.5 V,

the equation simpliﬁes to the following.

Digital-to-Analog Section

The DAC architecture consists of two matched DAC sections.

A simpliﬁed circuit diagram is shown in Figure 18. The DAC

architecture of the AD5541/AD5542 is segmented. The four

MSBs of the 16-bit data word are decoded to drive 15 switches,

E1 to E15. Each of these switches connects one of 15 matched

resistors to either AGND or V_REF. The remaining 12 bits of the

data word drive switches S0 to S11 of a 12-bit voltage mode

R-2R ladder network.

2.5 × D

V_OUT

=

65,536

giving a V_OUTof 1.25 V with midscale loaded, and 2.5 V with

full-scale loaded to the DAC.

The LSB size is V_REF/65,536.

Serial Interface

The AD5541 and AD5542 are controlled by a versatile 3-wire

serial interface, which operates at clock rates up to 25 MHz and

is compatible with SPI, QSPI, MICROWIRE, and DSP interface

standards. The timing diagram can be seen in Figure 1. Input

data is framed by the chip select input, CS. After a high-to-low

transition on CS, data is shifted synchronously and latched into

the input register on the rising edge of the serial clock, SCLK.

Data is loaded MSB ﬁrst in 16-bit words. After 16 data bits

have been loaded into the serial input register, a low-to-high

transition on CS transfers the contents of the shift register to the

DAC. Data can only be loaded to the part while CS is low.

R

V

OUT

2R

S0

2R

S1

2R

S11

2R

E1

2R

E2

2R

E15

V

REF

12-BIT R-2R LADDER

FOUR MSB's DECODED INTO

15 EQUAL SEGMENTS

Figure 18. DAC Architecture

REV. A

–9–

AD5541/AD5542

+2.5V

The AD5542 has an LDAC function that allows the DAC latch

to be updated asynchronously by bringing LDAC low after CS

goes high. LDAC should be maintained high while data is written

to the shift register. Alternatively, LDAC may be tied permanently

low to update the DAC synchronously. With LDAC tied perma-

nently low, the rising edge of CS will load the data to the DAC.

10␮F

+5V

0.1␮F

RFB

+5V

–5V

SERIAL

V

REFF REFS

DD

INTERFACE

R

FB

INV

OUT

CS

R

DIN

INV

Unipolar Output Operation

BIPOLAR

OUTPUT

SCLK

LDAC

AD5541/AD5542

These DACs are capable of driving unbuffered loads of 60 kΩ.

Unbuffered operation results in low-supply current, typically

300 µA, and a low-offset error. The AD5541 provides a unipolar

output swing ranging from 0 V to V_REF. The AD5542 can be

conﬁgured to output both unipolar and bipolar voltages. Figure

19 shows a typical unipolar output voltage circuit. The code

table for this mode of operation is shown in Table I.

EXTERNAL

OP AMP

DGND AGNDF AGNDS

Figure 20. Bipolar Output (AD5542 Only)

Table II. Bipolar Code Table

DAC Latch Contents

MSB LSB

+5V

+2.5V

Analog Output

10␮F

1111 1111 1111 1111

1000 0000 0000 0001

1000 0000 0000 0000

0111 1111 1111 1111

0000 0000 0000 0000

+V_REF× (32,767/32,768)

+V_REF× (1/32,768)

0 V

–V_REF× (1/32,768)

–V_REF× (32,768/32,768) = –V_REF

0.1␮F

SERIAL

INTERFACE

V

REF(REFF*)

REFS*

DD

CS

AD820/

OP196

AD5541/AD5542

DIN

UNIPOLAR

OUTPUT

OUT

SCLK

LDAC*

Assuming a perfect reference, the worst-case bipolar output

voltage may be calculated from the following equation.

EXTERNAL

OP AMP

DGND

AGND

Bipolar Mode Worst-Case Output

* AD5542 ONLY

V_OUT–UNI+V_OS2 + RD – V_REF1 + RD

(

[

)(

)

(

)

]

Figure 19. Unipolar Output

V_OUT–BIP

where

=

1 + 2 + RD /A

(

)

Table I. Unipolar Code Table

DAC Latch Contents

MSB LSB

V_OS= External Op Amp Input Offset Voltage

RD = R_FBand R_INResistor Matching Error

Analog Output

1111 1111 1111 1111

1000 0000 0000 0000

0000 0000 0000 0001

0000 0000 0000 0000

V_REF× (65,535/65,536)

V_REF× (32,768/65,536) = 1/2 V_REF

V_REF× (1/65,536)

0 V

A

= Op Amp Open-Loop Gain

Output Ampliﬁer Selection

For bipolar mode, a precision ampliﬁer should be used, supplied

from a dual power supply. This will provide the ±V_REFoutput.

In a single-supply application, selection of a suitable op amp

may be more difﬁcult as the output swing of the ampliﬁer does

not usually include the negative rail, in this case AGND. This

can result in some degradation of the speciﬁed performance

unless the application does not use codes near zero.

Assuming a perfect reference, the worst case output voltage may

be calculated from the following equation.

Unipolar Mode Worst-Case Output

D

2¹⁶

V_OUT–UNI

=

× (V_REF+V_GE) +V_ZSE+ INL

The selected op amp needs to have very low-offset voltage, (the

DAC LSB is 38 µV with a 2.5 V reference), to eliminate the

need for output offset trims. Input bias current should also be

very low as the bias current multiplied by the DAC output

impedance (approximately 6K) will add to the zero code error.

Rail-to-rail input and output performance is required. For fast

settling, the slew rate of the op amp should not impede the

settling time of the DAC. Output impedance of the DAC is

constant and code-independent, but in order to minimize gain

errors, the input impedance of the output ampliﬁer should be

as high as possible. The ampliﬁer should also have a 3 dB band-

width of 1 MHz or greater. The ampliﬁer adds another time

constant to the system, hence increasing the settling time of the

output. A higher 3 dB ampliﬁer bandwidth results in a shorter

effective settling time of the combined DAC and ampliﬁer.

where

V_OUT–UNI= Unipolar Mode Worst-Case Output

D

= Code Loaded to DAC

= Reference Voltage Applied to Part

= Gain Error in Volts

= Zero Scale Error in Volts

= Integral Nonlinearity in Volts

V_REF

V_GE

V_ZSE

INL

Bipolar Output Operation

With the aid of an external op amp, the AD5542 may be conﬁg-

ured to provide a bipolar voltage output. A typical circuit of

such operation is shown in Figure 20. The matched bipolar off-

set resistors R_FBand R_INVare connected to an external op amp to

achieve this bipolar output swing, typically R_FB= R_INV= 28 kΩ.

Table II shows the transfer function for this output operating

mode. Also provided on the AD5542 are a set of Kelvin connec-

tions to the analog ground inputs.

Force Sense Ampliﬁer Selection

These ampliﬁers will be single-supply, low-noise ampliﬁers. A

low-output impedance at high frequencies is preferred as they

need to be able to handle dynamic currents of up to ±20 mA.

REV. A

–10–

AD5541/AD5542

Reference and Ground

AD5541/AD5542 to 68HC11 Interface

As the input impedance is code-dependent, the reference pin

should be driven from a low-impedance source. The AD5541/

AD5542 operates with a voltage reference ranging from 2 V to

V_DD. References below 2 V will result in reduced accuracy.

The DAC’s full-scale output voltage is determined by the

reference. Tables I and II outline the analog output voltage

or particular digital codes. For optimum performance, Kelvin

sense connections are provided on the AD5542.

Figure 22 shows a serial interface between the AD5541/AD5542

and the 68HC11 microcontroller. SCK of the 68HC11 drives

the SCLK of the DAC, while the MOSI output drives the

serial data lines SDIN. CS signal is driven from one of the

port lines. The 68HC11 is configured for master mode; MSTR

= 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI

output is valid on the rising edge of SCK.

If the application doesn’t require separate force and sense lines,

they should be tied together close to the package to minimize

voltage drops between the package leads and the internal die.

LDAC**

PC6

PC7

68HC11/

68L11*

CS

AD5541/

AD5542*

DIN

MOSI

SCK

SCLK

Power-On Reset

These parts have a power-on reset function to ensure the output

is at a known state upon power-up. On power-up, the DAC

register contains all zeros, until data is loaded from the serial

register. However, the serial register is not cleared on power-up,

so its contents are undeﬁned. When loading data initially to the

DAC, 16 bits or more should be loaded to prevent erroneous

data appearing on the output. If more than 16 bits are loaded,

the last 16 are kept, and if less than 16 are loaded, bits will remain

from the previous word. If the AD5541/AD5542 needs to be

interfaced with data shorter than 16 bits, the data should be

padded with zeros at the LSBs.

*ADDITIONAL PINS OMITTED FOR CLARITY.

**AD5542 ONLY

Figure 22. AD5541/AD5542 to 68HC11/68L11 Interface

AD5541/AD5542 to MICROWIRE Interface

Figure 23 shows an interface between the AD5541/AD5542 and

any MICROWIRE-compatible device. Serial data is shifted out

on the falling edge of the serial clock and into the AD5541/

AD5542 on the rising edge of the serial clock. No glue logic is

required as the DAC clocks data into the input shift register on

the rising edge.

Power Supply and Reference Bypassing

CS

For accurate high-resolution performance, it is recommended that

the reference and supply pins be bypassed with a 10 µF tantalum

capacitor in parallel with a 0.1 µF ceramic capacitor.

MICROWIRE*

SO

DIN

AD5541/

AD5542*

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

MICROPROCESSOR INTERFACING

Figure 23. AD5541/AD5542 to MICROWIRE Interface

Microprocessor interfacing to the AD5541/AD5542 is via a

serial bus that uses standard protocol compatible with DSP

processors and microcontrollers. The communications channel

requires a 3-wire interface consisting of a clock signal, a data

signal and a synchronization signal. The AD5541/AD5542

requires a 16-bit data word with data valid on the rising edge of

SCLK. The DAC update may be done automatically when all

the data is clocked in or it may be done under control of LDAC

(AD5542 only).

AD5541/AD5542 to 80C51/80L51 Interface

A serial interface between the AD5541/AD5542 and the 80C51/

80L51 microcontroller is shown in Figure 24. TxD of the

microcontroller drives the SCLK of the AD5541/AD5542, while

RxD drives the serial data line of the DAC. P3.3 is a bit program-

mable pin on the serial port which is used to drive CS.

The 80C51/80L51 provides the LSB ﬁrst, while the AD5541/

AD5542 expects the MSB of the 16-bit word ﬁrst. Care should

be taken to ensure the transmit routine takes this into account.

AD5541/AD5542–ADSP-2101/ADSP-2103 Interface

Figure 21 shows a serial interface between the AD5541/AD5542

and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103

should be set to operate in the SPORT transmit alternate framing

mode. The ADSP-2101/ADSP-2103 is programmed through the

SPORT control register and should be configured as follows:

Internal Clock Operation, Active Low Framing, 16-Bit Word

Length. Transmission is initiated by writing a word to the Tx regis-

ter after the SPORT has been enabled. As the data is clocked out

on each rising edge of the serial clock, an inverter is required

between the DSP and the DAC, because the AD5541/AD5542

clocks data in on the falling edge of the SCLK.

When data is to be transmitted to the DAC, P3.3 is taken low.

Data on RxD is valid on the falling edge of TxD, so the clock must

be inverted as the DAC clocks data into the input shift regis-

ter on the rising edge of the serial clock. The 80C51/80L51

transmits its data in 8-bit bytes with only eight falling clock

edges occurring in the transmit cycle. As the DAC requires a

16-bit word, P3.3 must be left low after the ﬁrst eight bits are

transferred, and brought high after the second byte is trans-

ferred. LDAC on the AD5542 may also be controlled by

the 80C51/80L51 serial port output by using another bit

programmable pin, P3.4.

LDAC**

FO

P3.4

P3.3

LDAC**

CS

ADSP-2101/

ADSP-2103*

AD5541/

AD5542*

TFS

DT

CS

80C51/

80L51*

AD5541/

AD5542*

DIN

RxD

TxD

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

**AD5542 ONLY

*ADDITIONAL PINS OMITTED FOR CLARITY.

**AD5542 ONLY

Figure 21. AD5541/AD5542 to ADSP-2101/ADSP-2103

Interface

Figure 24. AD5541/AD5542 to 80C51/80L51 Interface

REV. A

–11–

AD5541/AD5542

APPLICATIONS

Decoding Multiple AD5541/AD5542s

Optocoupler interface

The CS pin of the AD5541/AD5542 can be used to select one

of a number of DACs. All devices receive the same serial clock

and serial data, but only one device will receive the CS signal at

any one time. The DAC addressed will be determined by the

decoder. There will be some digital feedthrough from the digital

input lines. Using a burst clock will minimize the effects of digi-

tal feedthrough on the analog signal channels. Figure 26 shows a

typical circuit.

The digital inputs of the AD5541/AD5542 are Schmitt-

triggered, so they can accept slow transitions on the digital input

lines. This makes these parts ideal for industrial applications

where it may be necessary that the DAC is isolated from the

controller via optocouplers. Figure 25 illustrates such an interface.

5V

REGULATOR

0.1␮F

10␮F

POWER

AD5541/AD5542

SCLK

CS

V

OUT

V

DD

DIN

V

DD

SCLK

10k⍀

V

DD

SCLK

AD5541/AD5542

ENABLE

EN

CS

V

DD

CODED

ADDRESS

V

DECODER

DGND

OUT

AD5541/AD5542

V

DIN

10k⍀

SCLK

CS

OUT

AD5541/AD5542

V

DD

CS

V

OUT

DIN

10k⍀

SCLK

DIN

GND

AD5541/AD5542

CS

V

OUT

DIN

Figure 25. AD5541/AD5542 in an Optocoupler Interface

SCLK

Figure 26. Addressing Multiple AD5541/AD5542s

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead SO

(SO-8)

14-Lead SO

(R-14)

0.3444 (8.75)

0.3367 (8.55)

0.1968 (5.00)

0.1890 (4.80)

8

7

8

1

5

4

14

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

0.2440 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (3.80)

1

PIN 1

0.0688 (1.75)

0.0532 (1.35)

0.050 (1.27)

BSC

0.0196 (0.50)

0.0099 (0.25)

0.0196 (0.50)

0.0099 (0.25)

0.0500 (1.27)

BSC

؋

45؇

؋

45؇

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0040 (0.10)

SEATING

PLANE

8؇

0؇

8؇

0؇

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

SEATING

PLANE

0.0500 (1.27)

0.0160 (0.41)

0.0099 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

0.0192 (0.49)

0.0138 (0.35)

0.0098 (0.25)

0.0075 (0.19)

REV. A

–12–


型号：	AD5541
厂家：	ADI
描述：	5 V, Serial-Input Voltage-Output, 16-Bit DACs 5 V ，串行输入电压输出， 16位DAC
文件：	总12页 (文件大小：189K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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