AD5542_15_技术文档

2.7 V to 5.5 V, Serial-Input,

Voltage-Output, 16-Bit DACs

Data Sheet

AD5541/AD5542

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

V

DD

Full 16-bit performance

8

3 V and 5 V single-supply operation

Low 0.625 mW power dissipation

1 µs settling time

AD5541

3

1

2

V

16-BIT DAC

REF

OUT

AGND

Unbuffered voltage output capable of driving 60 kΩ

loads directly

SPI-/QSPI-/MICROWIRE-compatible interface standards

Power-on reset clears DAC output to 0 V (unipolar mode)

5 kV HBM ESD classification

4

6

16-BIT DAC LATCH

CS

DIN

CONTROL

LOGIC

5

SCLK

SERIAL INPUT REGISITER

7

Low glitch: 1.1 nV-sec

DGND

Figure 1. AD5541

V

APPLICATIONS

DD

14

R

Digital gain and offset adjustment

Automatic test equipment

Data acquisition systems

FB

AD5542

1

RFB

R

INV

13 INV

6

REFF

Industrial process control

2

3

V

OUT

16-BIT DAC

5

7

REFS

CS

GENERAL DESCRIPTION

AGNDF

AGNDS

The AD5541/AD5542 are single, 16-bit, serial input, voltage

output digital-to-analog converters (DACs) that operate from

a single 2.7 V to 5.5 V supply. The DAC output range extends

16-BIT DAC LATCH

4

LDAC 11

CONTROL

LOGIC

SCLK

DIN

8

10

SERIAL INPUT REGISITER

from 0 V to V_REF

.

12

The DAC output range extends from 0 V to V_REFand is guaranteed

monotonic, providing 1 LSB INL accuracy at 16 bits without

adjustment over the full specified temperature range of −40°C to

+85°C. Offering unbuffered outputs, the AD5541/AD5542

achieve a 1 µs settling time with low power consumption and low

offset errors. Providing a low noise performance of 11.8 nV/√Hz

and low glitch, the AD5541/AD5542 is suitable for deployment

across multiple end systems.

DGND

Figure 2. AD5542

Table 1.

Part No.

AD5541A/AD5542A

Description

Single, 16-bit unbuffered nanoDAC™,

1 LSB INL, LFCSP

AD5024/AD5044/AD5064 Quad 12-/14-/16-bit nanoDAC,

1 LSB INL, TSSOP

AD5062

AD5063

Single, 16-bit nanoDAC, 1 LSB INL,

SOT-23

Single, 16-bit nanoDAC, 1 LSB INL,

SOT-23

The AD5542 can be operated in bipolar mode, which generates

a

V

_REFoutput swing. The AD5542 also includes Kelvin sense

connections for the reference and analog ground pins to reduce

layout sensitivity.

PRODUCT HIGHLIGHTS

The AD5541/AD5542 utilize a versatile 3-wire interface that is

compatible with SPI, QSPI™, MICROWIRE™ and DSP interface

standards. The AD5541/AD5542 are available in 8-lead and

14-lead SOIC packages.

1. Single-Supply Operation. The AD5541 and AD5542 are fully

specified and guaranteed for a single 2.7 V to 5.5 V supply.

2. Low Power Consumption. These parts consume typically

0.625 mW with a 5 V supply and 0.375 mV at 3 V.

3. 3-Wire Serial Interface.

4. Unbuffered Output Capable of Driving 60 kΩ Loads. This

reduces power consumption because there is no internal

buffer to drive.

5. Power-On Reset Circuitry.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD5541/AD5542

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Bipolar Output Operation......................................................... 12

Output Amplifier Selection....................................................... 12

Force Sense Amplifier Selection............................................... 12

Reference and Ground............................................................... 12

Power-On Reset.......................................................................... 13

Power Supply and Reference Bypassing .................................. 13

Microprocessor Interfacing........................................................... 14

AD5541/AD5542 to ADSP-21xx Interface............................. 14

AD5541/AD5542 to 68HC11/68L11 Interface....................... 14

AD5541/AD5542 to MICROWIRE Interface ........................ 14

AD5541/AD5542 to 80C51/80L51 Interface.......................... 14

Applications Information .............................................................. 15

Optocoupler Interface................................................................ 15

Decoding Multiple AD5541/AD5542s.................................... 15

Outline Dimensions....................................................................... 16

Ordering Guide .......................................................................... 17

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagrams............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Terminology .................................................................................... 10

Theory of Operation ...................................................................... 11

Digital-to-Analog Section ......................................................... 11

Serial Interface ............................................................................ 11

Unipolar Output Operation...................................................... 11

REVISION HISTORY

3/12—Rev. E to Rev. F

Change to Figure 19 ......................................................................... 9

Changes to Ordering Guide .......................................................... 17

Changes to Product Highlights .......................................................1

Changes to Table 1.............................................................................3

Changes to Table 3.............................................................................5

Changes to Figure 16, Figure 17, and Figure 19....................... 8, 9

Changes to Theory of Operations Section.................................. 11

Changes to Microprocessor Interfacing Section ........................ 14

Changes to Outline Dimensions .................................................. 16

Changes to Ordering Guide.......................................................... 17

3/11—Rev. D to Rev. E

Changed +105°C to +85°C, General Description Section .......... 1

2/11—Rev. C to Rev. D

Changes to Features Section, General Description Section,

Product Highlights Section ............................................................. 1

Added Table 1; Renumbered Sequentially .................................... 1

Added Output Noise Spectral Density Parameter and Output

Noise Parameter, Table 2.................................................................. 3

Changes to Ordering Guide .......................................................... 17

8/08—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Timing Characteristics Section...................................4

Changes to Table 3.............................................................................5

Updated Outline Dimensions....................................................... 16

Changes to Ordering Guide.......................................................... 17

4/10—Rev. B to Rev. C

Changes to General Description Section ...................................... 1

10/99—Rev. 0 to Rev. A

Changes to Features List .................................................................. 1

Rev. F | Page 2 of 20

Data Sheet

AD5541/AD5542

SPECIFICATIONS

V_DD= 2.7 V to 5.5 V, 2.5 V ≤ V_REF≤ V_DD, AGND = DGND = 0 V. All specifications T_A= T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter¹

Min

Typ

Max

Unit

Test Conditions

STATIC PERFORMANCE

Resolution

16

Bits

Relative Accuracy (INL)

0.5

1.0

2.0

4.0

1.0

1.5

2

LSB

L, C grades

B, J grades

A grade

Guaranteed monotonic

J grade

Differential Nonlinearity (DNL)

Gain Error

+0.5

T_A= 25°C

3

LSB

Gain Error Temperature Coefficient

Unipolar Zero Code Error

0.1

0.3

ppm/°C

LSB

0.7

1.5

T_A= 25°C

Unipolar Zero Code Temperature Coefficient

AD5542

0.05

ppm/°C

Bipolar Resistor Matching

1.000

0.0015

Ω/Ω

%

R_FB/R_INV, typically R_FB= R_INV= 28 kΩ

Ratio error

0.0076

Bipolar Zero Offset Error

1

5

6

LSB

T_A= 25°C

Bipolar Zero Temperature Coefficient

Bipolar Zero Code Offset Error

0.2

1

ppm/°C

LSB

5

6

5

6

T_A= 25°C

LSB

Bipolar Gain Error

+1

0.1

Bipolar Gain Temperature Coefficient

OUTPUT CHARACTERISTICS

ppm/°C

Output Voltage Range

0

V_REF− 1 LSB

V

μs

V/μs

nV-sec

kΩ

nV/√Hz

µV p-p

LSB

Unipolar operation

−V_REF

AD5542 bipolar operation

To 1/2 LSB of FS, C_L= 10 pF

C_L= 10 pF, measured from 0% to 63%

1 LSB change around the major carry

All 1s loaded to DAC, V_REF= 2.5 V

Tolerance typically 20%

DAC code = 0x8400, frequency = 1 kHz

0.1 Hz to 10 Hz

ΔV_DD10%

Output Voltage Settling Time

Slew Rate

Digital-to-Analog Glitch Impulse

Digital Feedthrough

DAC Output Impedance

Output Noise Spectral Density

Output Noise

Power Supply Rejection Ratio

DAC REFERENCE INPUT

Reference Input Range

Reference Input Resistance²

1

17

1.1

0.2

6.25

11.8

0.134

1.0

V_DD

2.0

9

7.5

V

kΩ

Unipolar operation

AD5542, bipolar operation

LOGIC INPUTS

Input Current

1

0.8

μA

V

pF

V

Input Low Voltage, V_INL

Input High Voltage, V_INH

Input Capacitance³

Hysteresis Voltage³

REFERENCE ³

2.4

10

0.15

Reference −3 dB Bandwidth

Reference Feedthrough

Signal-to-Noise Ratio

Reference Input Capacitance

2.2

1

92

26

MHz

mV p-p

dB

pF

All 1s loaded

All 0s loaded, V_REF= 1 V p-p at 100 kHz

Code 0x0000

Code 0xFFFF

Rev. F | Page 3 of 20

AD5541/AD5542

Data Sheet

Parameter¹

Min

Typ

Max

Unit

Test Conditions

POWER REQUIREMENTS

Digital inputs at rails

V_DD

2.7

5.5

V

I_DD

125

0.625

150

0.825

μA

mW

Power Dissipation

¹Temperature ranges are as follows: A, B, C versions: −40°C to +85°C; J, L versions: 0°C to 70°C.

²Reference input resistance is code-dependent, minimum at 0x8555.

³Guaranteed by design, not subject to production test.

TIMING CHARACTERISTICS

V_DD= 2.7 V to 5.5 V 10%, V_REF= 2.5 V, V_INH= 3 V and 90% of V_DD, V_INL= 0 V and 10% of V_DD, AGND = DGND = 0 V; −40°C < T_A<

+85°C, unless otherwise noted.

Table 3.

Parameter^{1, 2}

Limit

25

40

20

10

15

30

20

15

4

Unit

Description

f_SCLK

t₁

t₂

t₃

t₄

MHz max

ns min

SCLK cycle frequency

SCLK cycle time

SCLK high time

SCLK low time

CS low to SCLK high setup

CS high to SCLK high setup

SCLK high to CS low hold time

SCLK high to CS high hold time

Data setup time

Data hold time (V_INH= 90% of V_DD, V_INL= 10% of V_DD

Data hold time (V_INH= 3V, V_INL= 0 V)

LDAC pulse width

t₅

t₆

t₇

t₈

t₉

t₁₀

t₁₁

t₁₂

)

7.5

30

CS high to LDAC low setup

CS high time between active periods

¹Guaranteed by design and characterization. Not production tested

²All input signals are specified with t_R= t_F= 1 ns/V and timed from a voltage level of (V_INL+ V_INH)/2.

t₁

SCLK

t₂

t₃

t₆

t₅

t₇

t₄

CS

t₁₂

t₈

t₅

DIN

DB15

t₁₁

t₁₀

LDAC*

*AD5542 ONLY. CAN BE TIED PERMANENTLY LOW IF REQUIRED.

Figure 3. Timing Diagram

Rev. F | Page 4 of 20

Data Sheet

AD5541/AD5542

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 4.

Parameter

Rating

V_DDto AGND

Digital Input Voltage to DGND

V_OUTto AGND

−0.3 V to +6 V

−0.3 V to V_DD+ 0.3 V

−0.3 V to +0.3 V

10 mA

AGND, AGNDF, AGNDS to DGND

Input Current to Any Pin Except Supplies

Operating Temperature Range

Industrial (A, B, C Versions)

Commercial (J, L Versions)

Storage Temperature Range

Maximum Junction Temperature (T_Jmax)

Package Power Dissipation

Thermal Impedance, θ_JA

SOIC (R-8)

ESD CAUTION

−40°C to +85°C

0°C to 70°C

−65°C to +150°C

150°C

(T_Jmax – T_A)/θ_JA

149.5°C/W

104.5°C/W

SOIC (R-14)

Lead Temperature, Soldering

Peak Temperature¹

ESD²

260°C

5 kV

¹As per JEDEC Standard 20.

²HBM Classification^.

Rev. F | Page 5 of 20

AD5541/AD5542

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

1

2

3

4

8

7

6

5

V

DD

OUT

AD5541

AGND

REF

CS

DGND

DIN

TOP VIEW

(Not to Scale)

SCLK

Figure 4. AD5541 Pin Configuration

Table 5. AD5541 Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

4

5

6

7

8

V_OUT

AGND

REF

Analog Output Voltage from the DAC.

Ground Reference Point for Analog Circuitry.

Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V_DD

Logic Input Signal. The chip select signal is used to frame the serial data input.

.

CS

SCLK

DIN

DGND

V_DD

Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%.

Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.

Digital Ground. Ground reference for digital circuitry.

Analog Supply Voltage, 5 V 10%.

RFB

1

2

3

4

5

6

7

14 V

DD

V

13 INV

OUT

AGNDF

12 DGND

11 LDAC

10 DIN

AD5542

TOP VIEW

(Not to Scale)

AGNDS

REFS

REFF

CS

9

8

NC

SCLK

NC = NO CONNECT

Figure 5. AD5542 Pin Configuration

Table 6. AD5542 Pin Function Descriptions

Pin No. Mnemonic Description

1

2

RFB

V_OUT

Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.

Analog Output Voltage from the DAC.

3

4

5

6

AGNDF

AGNDS

REFS

REFF

CS

Ground Reference Point for Analog Circuitry (Force).

Ground Reference Point for Analog Circuitry (Sense).

Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V_DD

Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V_DD

.

7

Logic Input Signal. The chip select signal is used to frame the serial data input.

8

9

SCLK

NC

Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%.

No Connect.

10

11

DIN

LDAC

Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.

LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the

input register.

12

13

DGND

INV

Digital Ground. Ground reference for digital circuitry.

Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to external op amps inverting input in

bipolar mode.

14

V_DD

Analog Supply Voltage, 5 V 10%.

Rev. F | Page 6 of 20

Data Sheet

AD5541/AD5542

TYPICAL PERFORMANCE CHARACTERISTICS

0.50

V

= 5V

V

= 5V

DD

= 2.5V

REF

0.25

0

0.25

0

–0.25

–0.50

–0.25

–0.50

–0.75

0

8192 16384 24576 32768 40960 49152 57344 65536

0

8192 16384 24576 32768 40960 49152 57344 65536

CODE

Figure 6. Integral Nonlinearity vs. Code

Figure 9. Differential Nonlinearity vs. Code

0.25

0.75

V

= 5V

V

= 5V

DD

V

= 2.5V

V

= 2.5V

REF

0

–0.25

–0.50

–0.75

0.50

0.25

0

–0.25

–1.00

–0.50

–60 –40 –20

0

20

40

60

80

100 120 140

–60 –40 –20

0

20

40

60

80

100 120 140

TEMPERATURE (°C)

Figure 7. Integral Nonlinearity vs. Temperature

Figure 10. Differential Nonlinearity vs. Temperature

0.50

0.75

V

T

= 5V

V

= 2.5V

DD

= 25°C

REF

= 25°C

T

A

0.25

0

0.50

0.25

0

DNL

–0.25

–0.50

INL

–0.25

INL

–0.75

–0.50

2

3

4

5

6

7

0

1

2

3

4

5

6

SUPPLY VOLTAGE (V)

REFERENCE VOLTAGE (V)

Figure 8. Linearity Error vs. Supply Voltage

Figure 11. Linearity Error vs. Reference Voltage

Rev. F | Page 7 of 20

AD5541/AD5542

Data Sheet

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

0.15

0.10

0.05

0

V

= 5V

V

= 5V

DD

= 2.5V

REF

T

= 25°C

T = 25°C

A

–0.05

–0.10

–0.15

–0.9

–40

25

85

–40

25

85

TEMPERATURE (°C)

Figure 12. Gain Error vs. Temperature

Figure 15. Zero-Code Error vs. Temperature

2.0

1.5

1.0

0.5

0

132

130

128

126

124

122

120

118

116

T

= 25°C

V

= 5V

A

DD

= 2.5V

REF

T

= 25°C

A

REFERENCE VOLTAGE

V

= 5V

DD

SUPPLY VOLTAGE

= 2.5V

V

REF

0

1

2

3

VOLTAGE (V)

4

5

6

–40

25

85

TEMPERATURE (°C)

Figure 16. Supply Current vs. Reference Voltage or Supply Voltage

Figure 13. Supply Current vs. Temperature

200

V

= 5V

DD

= 2.5V

REF

180

160

140

120

100

80

T

= 25°C

A

150

100

50

60

40

20

0

10,000 20,000 30,000 40,000 50,000 60,000 70,000

CODE (Decimal)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21

DIGITAL INPUT VOLTAGE (V)

Figure 17. Reference Current vs. Code

Figure 14. Supply Current vs. Digital Input Voltage

Rev. F | Page 8 of 20

Data Sheet

AD5541/AD5542

V

= 2.5V

REF

= 5V

V

= 2.5V

REF

= 5V

2µs/DIV

DD

= 25°C

DD

= 25°C

T

A

T

A

CS (5V/DIV)

100

DIN (5V/DIV)

10pF

50pF

100pF

200pF

V

(50mV/DIV)

OUT

10

V

(0.5V/DIV)

OUT

2µs/DIV

Figure 18. Digital Feedthrough

Figure 20. Large Signal Settling Time

1.236

1.234

1.232

1.230

1.228

1.226

1.224

5

CS

0

V

= 2.5V

REF

= 5V

DD

–5

T

•

= 25°C

A

•

100

90

•

• • • •

V

(1V/DIV)

OUT

–10

–15

–20

–25

–30

V

OUT

V

(50mV/DIV)

OUT

GAIN = –216

1LSB = 8.2mV

10

•

• • • •

0%

–0.5

0

0.5

1.0

1.5

2.0

0.5µs/DIV

TIME (µs)

Figure 19. Digital-to-Analog Glitch Impulse

Figure 21. Small Signal Settling Time

Rev. F | Page 9 of 20

AD5541/AD5542

TERMINOLOGY

Data Sheet

Digital-to-Analog Glitch Impulse

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or INL is a measure of the

maximum deviation, in LSBs, from a straight line passing

through the endpoints of the DAC transfer function. A typical

INL vs. code plot can be seen in Figure 6.

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-sec

and is measured when the digital input code is changed by

1 LSB at the major carry transition. A plot of the digital-to-

analog glitch impulse is shown in Figure 19.

Differential Nonlinearity (DNL)

DNL is the difference between the measured change and the

ideal 1 LSB change between any two adjacent codes. A specified

differential nonlinearity of 1 LSB maximum ensures mono-

tonicity. Figure 9 illustrates a typical DNL vs. code plot.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the

DAC, but it is measured when the DAC output is not updated.

Gain Error

CS

is held high while the CLK and DIN signals are toggled. It

Gain error is the difference between the actual and ideal analog

output range, expressed as a percent of the full-scale range.

It is the deviation in slope of the DAC transfer characteristic

from ideal.

is specified in nV-sec and is measured with a full-scale code

change on the data bus, that is, from all 0s to all 1s and vice

versa. A typical plot of digital feedthrough is shown in

Figure 18.

Gain Error Temperature Coefficient

Power Supply Rejection Ratio (PSRR)

Gain error temperature coefficient is a measure of the change

in gain error with changes in temperature. It is expressed in

ppm/°C.

PSRR indicates how the output of the DAC is affected by changes

in the power supply voltage. Power-supply rejection ratio is

quoted in terms of percent change in output per percent change

in V_DDfor full-scale output of the DAC. V_DDis varied by 10%.

Zero Code Error

Zero code error is a measure of the output error when zero code

is loaded to the DAC register.

Reference Feedthrough

Reference feedthrough is a measure of the feedthrough from the

_REFinput to the DAC output when the DAC is loaded with all

Zero Code Temperature Coefficient

V

This is a measure of the change in zero code error with a change

in temperature. It is expressed in mV/°C.

0s. A 100 kHz, 1 V p-p is applied to V_REF. Reference feedthrough

is expressed in mV p-p.

Rev. F | Page 10 of 20

Data Sheet

AD5541/AD5542

THEORY OF OPERATION

The AD5541/AD5542 are single, 16-bit, serial input, voltage

output DACs. They operate from a single supply ranging from

2.7 V to 5.5 V and consume typically 125 µA with a supply of

5 V. Data is written to these devices in a 16-bit word format,

via a 3- or 4-wire serial interface. To ensure a known power-up

state, these parts are designed with a power-on reset function.

In unipolar mode, the output is reset to 0 V; in bipolar mode,

the AD5542 output is set to −V_REF. Kelvin sense connections for

the reference and analog ground are included on the AD5542.

SERIAL INTERFACE

The AD5541/AD5542 are controlled by a versatile 3- or 4-wire

serial interface that operates at clock rates up to 25 MHz and is

compatible with SPI, QSPI, MICROWIRE, and DSP interface

standards. The timing diagram is shown in Figure 3. Input data

CS

is framed by the chip select input, . After a high-to-low

CS

transition on , data is shifted synchronously and latched into

the input register on the rising edge of the serial clock, SCLK.

Data is loaded MSB first in 16-bit words. After 16 data bits have

been loaded into the serial input register, a low-to-high transition

DIGITAL-TO-ANALOG SECTION

CS

on

can be loaded to the part only while

LDAC

transfers the contents of the shift register to the DAC. Data

The DAC architecture consists of two matched DAC sections.

A simplified circuit diagram is shown in Figure 22. The DAC

architecture of the AD5541/AD5542 is segmented. The four

MSBs of the 16-bit data-word are decoded to drive 15 switches,

E1 to E15. Each switch connects one of 15 matched resistors to

either AGND or V_REF. The remaining 12 bits of the data-word

drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder

network.

CS

is low.

function that allows the DAC latch

LDAC CS

The AD5542 has an

to be updated asynchronously by bringing

LDAC

low after

should be maintained high while data is written

LDAC

goes high.

to the shift register. Alternatively,

nently low to update the DAC synchronously. With

can be tied perma-

LDAC

tied

CS

permanently low, the rising edge of loads the data to the DAC.

R

V

OUT

UNIPOLAR OUTPUT OPERATION

2R

S0

2R . . . . .

S1 . . . . .

2R

E1

2R . . . . .

E2 . . . . .

2R

E15

These DACs are capable of driving unbuffered loads of 60 kΩ.

Unbuffered operation results in low supply current, typically

300 μA, and a low offset error. The AD5541 provides a unipolar

output swing ranging from 0 V to V_REF. The AD5542 can be

configured to output both unipolar and bipolar voltages. Figure 23

shows a typical unipolar output voltage circuit. The code table

for this mode of operation is shown in Table 7.

S11

V

REF

FOUR MSBs DECODED

INTO 15 EQUAL SEGMENTS

12-BIT R-2R LADDER

Figure 22. DAC Architecture

5V

2.5V

With this type of DAC configuration, the output impedance

is independent of code, while the input impedance seen by

the reference is heavily code dependent. The output voltage is

dependent on the reference voltage, as shown in the following

equation:

10µF

0.1µF

SERIAL

INTERFACE

V

REF(REFF*) REFS*

DD

AD820/

OP196

CS

V_REF× D

UNIPOLAR

OUTPUT

DIN

AD5541/AD5542

OUT

V_OUT

where:

=

2^N

SCLK

LDAC*

EXTERNAL

OP AMP

DGND

AGND

D is the decimal data-word loaded to the DAC register.

N is the resolution of the DAC.

*AD5542 ONLY.

Figure 23. Unipolar Output

For a reference of 2.5 V, the equation simplifies to the following:

Table 7. Unipolar Code Table

DAC Latch Contents

2.5 × D

V_OUT

=

65,536

MSB

LSB

Analog Output

V_REF× (65,535/65,536)

V_REF× (32,768/65,536) = ½ V_REF

V_REF× (1/65,536)

0 V

1111 1111 1111 1111

1000 0000 0000 0000

0000 0000 0000 0001

0000 0000 0000 0000

This gives a V_OUTof 1.25 V with midscale loaded and 2.5 V with

full-scale loaded to the DAC.

The LSB size is V_REF/65,536.

Rev. F | Page 11 of 20

AD5541/AD5542

Data Sheet

Assuming a perfect reference, the unipolar worst-case output

voltage can be calculated from the following equation:

Assuming a perfect reference, the worst-case bipolar output

voltage can be calculated from the following equation:

D

[

(

)

(

)

(

)

]

V_{OUT − UNI}+ V_OS2 + RD −V_REF1 + RD

V_OUT-UNI

=

×

(

V_REF+ V_GE+ V_ZSE+ INL

)

V_OUT-BIP

=

2¹⁶

1 +

(

2 + RD

)

A

where:

_OUT−UNIis unipolar mode worst-case output.

D is code loaded to DAC.

_REFis reference voltage applied to the part.

_GEis gain error in volts.

where:

V

_OUT-BIPis the bipolar mode worst-case output.

_OUT−UNIis the unipolar mode worst-case output.

_OSis the external op amp input offset voltage.

RD is the R_FBand R_INVresistor matching error.

A is the op amp open-loop gain.

V

_ZSEis zero scale error in volts.

INL is integral nonlinearity in volts.

OUTPUT AMPLIFIER SELECTION

BIPOLAR OUTPUT OPERATION

For bipolar mode, a precision amplifier should be used and

supplied from a dual power supply. This provides the V_REF

output. In a single-supply application, selection of a suitable op

amp may be more difficult as the output swing of the amplifier

does not usually include the negative rail, in this case, AGND.

This can result in some degradation of the specified performance

unless the application does not use codes near zero.

With the aid of an external op amp, the AD5542 can be confi-

gured to provide a bipolar voltage output. A typical circuit of

such operation is shown in Figure 24. The matched bipolar

offset resistors, R_FBand R_INV, are connected to an external op

amp to achieve this bipolar output swing, typically R_FB= R_INV

28 kΩ. Table 8 shows the transfer function for this output

operating mode. Also provided on the AD5542 are a set of

Kelvin connections to the analog ground inputs.

=

The selected op amp needs to have a very low-offset voltage (the

DAC LSB is 38 μV with a 2.5 V reference) to eliminate the need

for output offset trims. Input bias current should also be very

low because the bias current, multiplied by the DAC output

impedance (approximately 6 kΩ), adds to the zero code error.

Rail-to-rail input and output performance is required. For fast

settling, the slew rate of the op amp should not impede the

settling time of the DAC. Output impedance of the DAC is

constant and code-independent, but to minimize gain errors,

the input impedance of the output amplifier should be as high

as possible. The amplifier should also have a 3 dB bandwidth of

1 MHz or greater. The amplifier adds another time constant to

the system, hence increasing the settling time of the output. A

higher 3 dB amplifier bandwidth results in a shorter effective

settling time of the combined DAC and amplifier.

+5V +2.5V

10µF

0.1µF

+5V

RFB

SERIAL

INTERFACE

V

REFF REFS

R

DD

R

FB

CS

INV

DIN

INV

UNIPOLAR

OUTPUT

OUT

SCLK

LDAC

AD5541/AD5542

–5V

EXTERNAL

OP AMP

DGND AGNDF AGNDS

Figure 24. Bipolar Output (AD5542 Only)

Table 8. Bipolar Code Table

DAC Latch Contents

MSB

LSB

Analog Output

FORCE SENSE AMPLIFIER SELECTION

1111 1111 1111 1111

1000 0000 0000 0001

1000 0000 0000 0000

0111 1111 1111 1111

0000 0000 0000 0000

+V_REF× (32,767/32,768)

+V_REF× (1/32,768)

0 V

−V_REF× (1/32,768)

−V_REF× (32,768/32,768) = −V_REF

Use single-supply, low-noise amplifiers. A low-output impedance

at high frequencies is preferred because the amplifiers need to

be able to handle dynamic currents of up to 20 mA.

REFERENCE AND GROUND

Because the input impedance is code-dependent, the reference

pin should be driven from a low impedance source. The AD5541/

AD5542 operate with a voltage reference ranging from 2 V to

V

_DD. References below 2 V result in reduced accuracy. The full-

scale output voltage of the DAC is determined by the reference.

Table 7 and Table 8 outline the analog output voltage or partic-

ular digital codes. For optimum performance, Kelvin sense

connections are provided on the AD5542.

If the application does not require separate force and sense

lines, tie the lines close to the package to minimize voltage

drops between the package leads and the internal die.

Rev. F | Page 12 of 20

Data Sheet

AD5541/AD5542

POWER-ON RESET

POWER SUPPLY AND REFERENCE BYPASSING

The AD5541/AD5542 have a power-on reset function to ensure

that the output is at a known state on power-up. On power-up,

the DAC register contains all 0s until the data is loaded from

the serial register. However, the serial register is not cleared on

power-up, so its contents are undefined. When loading data

initially to the DAC, 16 bits or more should be loaded to prevent

erroneous data appearing on the output. If more than 16 bits are

loaded, the last 16 are kept, and if less than 16 bits are loaded,

bits remain from the previous word. If the AD5541/AD5542

need to be interfaced with data shorter than 16 bits, the data

should be padded with 0s at the LSBs.

For accurate high-resolution performance, it is recommended

that the reference and supply pins be bypassed with a 10 μF

tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.

Rev. F | Page 13 of 20

AD5541/AD5542

Data Sheet

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5541/AD5542 is via a

serial bus that uses standard protocol that is compatible with

DSP processors and microcontrollers. The communications

channel requires a 3- or 4-wire interface consisting of a clock

signal, a data signal and a synchronization signal. The

AD5541/AD5542 require a 16-bit data-word with data valid on

the rising edge of SCLK. The DAC update can be done

automatically when all the data is clocked in or it can be done

AD5541/AD5542 TO MICROWIRE INTERFACE

Figure 27 shows an interface between the AD5541/AD5542

and any MICROWIRE-compatible device. Serial data is shifted

out on the falling edge of the serial clock and into the AD5541/

AD5542 on the rising edge of the serial clock. No glue logic is

required because the DAC clocks data into the input shift

register on the rising edge.

LDAC

under control of the

(AD5542 only).

CS

SO

CS

AD5541/

AD5542*

MICROWIRE*

DIN

AD5541/AD5542 TO ADSP-21XX INTERFACE

SCLK

Figure 25 shows a serial interface between the AD5541/AD5542

and the ADSP-21xx. The ADSP-21xx should be set to operate in

the SPORT transmit alternate framing mode. The ADSP-21xx are

programmed through the SPORT control register and should be

configured as follows: internal clock operation, active low

framing, 16-bit word length. Transmission is initiated by

writing a word to the Tx register after the SPORT has been

enabled. As the data is clocked out on each rising edge of the

serial clock, an inverter is required between the DSP and the

DAC, because the AD5541/AD5542 clock data in on the falling

edge of the SCLK.

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 27. AD5541/AD5542 to MICROWIRE Interface

AD5541/AD5542 TO 80C51/80L51 INTERFACE

A serial interface between the AD5541/AD5542 and the 80C51/

80L51 microcontroller is shown in Figure 28. TxD of the micro-

controller drives the SCLK of the AD5541/AD5542, and RxD

drives the serial data line of the DAC. P3.3 is a bit programmable

CS

pin on the serial port that is used to drive

.

The 80C51/80L51 provide the LSB first, whereas the AD5541/

AD5542 expects the MSB of the 16-bit word first. Care should

be taken to ensure the transmit routine takes this into account.

FO

TFS

LDAC**

CS

AD5541/

AD5542*

ADSP-21xx

When data is to be transmitted to the DAC, P3.3 is taken low.

Data on RxD is valid on the falling edge of TxD, so the clock

must be inverted as the DAC clocks data into the input shift

register on the rising edge of the serial clock. The 80C51/80L51

transmit data in 8-bit bytes with only eight falling clock edges

occurring in the transmit cycle. As the DAC requires a 16-bit

word, P3.3 must be left low after the first eight bits are transferred,

DT

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

**AD5542 ONLY.

Figure 25. AD5541/AD5542 to ADSP-21xx Interface

AD5541/AD5542 TO 68HC11/68L11 INTERFACE

LDAC

and brought high after the second byte is transferred.

on

Figure 26 shows a serial interface between the AD5541/AD5542

and the 68HC11/68L11 microcontroller. SCK of the 68HC11/

68L11 drives the SCLK of the DAC, and the MOSI output drives

the AD5542 can also be controlled by the 80C51/ 80L51 serial

port output by using another bit programmable pin, P3.4.

CS

the serial data line serial DIN. The

signal is driven from one

P3.4

P3.3

RxD

TxD

LDAC**

of the port lines. The 68HC11/68L11 is configured for master

mode: MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing

on the MOSI output is valid on the rising edge of SCK.

80C51/

80L51*

CS

AD5541/

AD5542*

DIN

SCLK

PC6

PC7

LDAC**

*ADDITIONAL PINS OMITTED FOR CLARITY.

**AD5542 ONLY.

68HC11/

68L11*

CS

AD5541/

AD5542*

Figure 28. AD5541/AD5542 to 80C51/80L51 Interface

MOSI

SCK

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

**AD5542 ONLY.

Figure 26. AD5541/AD5542 to 68HC11/68L11 Interface

Rev. F | Page 14 of 20

Data Sheet

AD5541/AD5542

APPLICATIONS INFORMATION

OPTOCOUPLER INTERFACE

DECODING MULTIPLE AD5541/AD5542s

The digital inputs of the AD5541/AD5542 are Schmitt-triggered so

that they can accept slow transitions on the digital input lines.

This makes these parts ideal for industrial applications where it

may be necessary to isolate the DAC from the controller via

optocouplers. Figure 29 illustrates such an interface.

CS

pin of the AD5541/AD5542 can be used to select one of

The

a number of DACs. All devices receive the same serial clock and

CS

serial data, but only one device receives the

signal at any one

time. The DAC addressed is determined by the decoder. There is

some digital feedthrough from the digital input lines. Using a

burst clock minimizes the effects of digital feedthrough on the

analog signal channels. Figure 30 shows a typical circuit.

5V

REGULATOR

0.1µF

POWER

10µF

AD5541/AD5542

SCLK

CS

V

DD

OUT

DIN

V

DD

10kΩ

SCLK

V

DD

SCLK

ENABLE

AD5541/AD5542

EN

CS

V

CODED

ADDRESS

AD5541/AD5542

V

DECODER

DGND

OUT

DIN

10kΩ

SCLK

CS

V

OUT

AD5541/AD5542

V

CS

V

OUT

DIN

10kΩ

SCLK

DIN

GND

AD5541/AD5542

CS

V

OUT

Figure 29. AD5541/AD5542 in an Optocoupler Interface

DIN

SCLK

Figure 30. Addressing Multiple AD5541/AD5542s

Rev. F | Page 15 of 20

AD5541/AD5542

Data Sheet

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

8

1

5

4

6.20 (0.2441)

5.80 (0.2284)

4.00 (0.1574)

3.80 (0.1497)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

BSC

45°

1.75 (0.0688)

1.35 (0.0532)

0.25 (0.0098)

0.10 (0.0040)

8°

0°

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

1.27 (0.0500)

0.40 (0.0157)

0.25 (0.0098)

0.17 (0.0067)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 31. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

8.75 (0.3445)

8.55 (0.3366)

8

7

14

1

6.20 (0.2441)

5.80 (0.2283)

4.00 (0.1575)

3.80 (0.1496)

1.27 (0.0500)

0.50 (0.0197)

0.25 (0.0098)

45°

BSC

1.75 (0.0689)

1.35 (0.0531)

0.25 (0.0098)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

1.27 (0.0500)

0.40 (0.0157)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 32. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-14)

Dimensions shown in millimeters and (inches)

Rev. F | Page 16 of 20

Data Sheet

AD5541/AD5542

ORDERING GUIDE

Model¹

INL

1 LSB

DNL

1 LSB

Temperature Range

−40°C to +85°C

0°C to 70°C

−40°C to +85°C

0°C to 70°C

Package Description

8-Lead SOIC_N

14-Lead SOIC_N

Evaluation Board

Package Option

R-8

AD5541CR

AD5541CRZ

AD5541CRZ-REEL7

AD5541LR

AD5541LR-REEL7

AD5541LRZ

AD5541LRZ-REEL7

AD5541BR

AD5541BRZ

AD5541BRZ-REEL

AD5541JR

AD5541JR-REEL7

AD5541JRZ

AD5541JRZ-REEL7

AD5541AR

AD5541AR-REEL7

AD5541ARZ

AD5541ARZ-REEL7

AD5542CR

AD5542CR-REEL7

AD5542CRZ

AD5542CRZ-REEL7

AD5542LR

AD5542LRZ

AD5542BR

AD5542BRZ

1 LSB

2 LSB

4 LSB

1 LSB

2 LSB

4 LSB

1 LSB

1.5 LSB

1 LSB

1.5 LSB

1 LSB

0°C to 70°C

−40°C to +85°C

0°C to 70°C

R-8

R-14

0°C to 70°C

−40°C to +85°C

0°C to 70°C

AD5542BRZ-REEL7

AD5542JR

AD5542JR-REEL7

AD5542JRZ

AD5542JRZ-REEL7

AD5542AR

AD5542AR-REEL7

AD5542ARZ

0°C to 70°C

−40°C to +85°C

AD5542ARZ-REEL7

EVAL-AD5541/42EBZ

¹Z = RoHS Compliant Part.

Rev. F | Page 17 of 20

AD5541/AD5542

NOTES

Data Sheet

Rev. F | Page 18 of 20

Data Sheet

NOTES

AD5541/AD5542

Rev. F | Page 19 of 20

AD5541/AD5542

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D07557-0-3/12(F)

Rev. F | Page 20 of 20


型号：	AD5542_15
厂家：	ADI
描述：	2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-Bit DACs
文件：	总20页 (文件大小：382K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5542_15 [ADI]

相关型号：

AD5543

AD5543BR

AD5543BRM

AD5543BRM-REEL7

AD5543BRMZ

AD5543BRMZ-REEL7

AD5543BRZ

AD5543CRMZ

AD5543CRMZ-REEL7

AD5543CRZ

AD5543CRZ-REEL7

AD5543_12