AD5545 [ADI]
Dual, Current-Output, Serial-Input, 16-/14-Bit DAC; 双通道,电流输出,串行输入, 16位/ 14位DAC型号: | AD5545 |
厂家: | ADI |
描述: | Dual, Current-Output, Serial-Input, 16-/14-Bit DAC |
文件: | 总16页 (文件大小:922K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Dual, Current-Output,
Serial-Input, 16-/14-Bit DAC
AD5545/AD5555
FUNCTIONAꢀ BꢀOCK DIAGRAM
FEATURES
V
A
V
B
REF
REF
16-bit resolution AD5545
14-bit resolution AD5555
1 ꢀSB DNꢀ monotonic
2 ꢀSB INꢀ AD5545
2 mA full-scale current 20ꢁ, with VREF = 10 V
0.5 µs settling time
2Q multiplying reference-input 4 MHz BW
Zero or midscale power-up preset
Zero or midscale dynamic reset
3-wire interface
16 OR 14
V
DD
R
I
A
FB
D0..DX
INPUT
DAC A
SDI
A
DAC A
DAC B
OUT
REGISTER
REGISTER
R
R
R
R
A
A
GND
R
I
B
FB
CS
INPUT
DAC B
B
OUT
EN
REGISTER
REGISTER
CLK
A
B
GND
DAC A
B
POWER-
ON
ADDR
AD5545/
AD5555
DECODE
RESET
02918-0-001
Compact TSSOP-16 package
DGND
RS MSB
LDAC
Figure 1.
APPꢀICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
Industrial control PꢀCs
Programmable attentuator
PRODUCT OVERVIEW
The AD5545/AD5555 are 16-bit/14-bit, current-output, digital-
to-analog converters designed to operate from a single 5 V
supply with bipolar output up to 15 V capability.
An external reference is needed to establish the full-scale out-
put-current. An internal feedback resistor (RFB) enhances the
resistance and temperature tracking when combined with an
external op amp to complete the I-to-V conversion.
A serial data interface offers high speed, 3-wire microcontroller
compatible inputs using serial data in (SDI), clock (CLK), and
chip select ( ). Additional
function allows simultane-
CS
LDAC
ous update operation. The internal reset logic allows power-on
preset and dynamic reset at either zero or midscale, depending
on the state of the MSB pin.
The AD5545/AD5555 are packaged in the compact TSSOP-16
package and can be operated from –40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD5545/AD5555
TABLE OF CONTENTS
AD5545/AD5555—Electrical Characteristics .............................. 3
Applications..................................................................................... 13
Stability ........................................................................................ 13
Positive Voltage Output ............................................................. 13
Bipolar Output............................................................................ 13
Programmable Current Source ................................................ 13
DAC with Programmable Input Reference Range................ 14
Outline Dimensions....................................................................... 16
ESD Caution................................................................................ 16
Ordering Guide .......................................................................... 16
Absolute Maximum Ratings............................................................ 5
Pin Configuration And Functional Descriptions......................... 6
Typical Performance Characteristics ............................................. 9
Circuit Operation ........................................................................... 11
D/A Converter Section.............................................................. 11
Serial Data Interface................................................................... 11
Power-Up Sequence ................................................................... 12
Layout and Power Supply Bypassing ....................................... 12
Grounding ................................................................................... 12
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD5545/AD5555
AD5545/AD5555—ELECTRICAL CHARACTERISTICS
Table 1. VDD = 5 V 1ꢀ0, IOUT = Virtual GND, GND = ꢀ V, VREF = 1ꢀ V, TA = Full Operating Tempearture Range,
unless otherwise noted.
Parameter
Symbol
Conditions
5 V ꢀ10 Units
STATIC PERFORMANCE1
Resolution
Resolution
N
N
AD5545, 1 LSB = VREF/216 = 153 µV when VREF = 10 V
AD5555, 1 LSB = VREF/214 = 610 µV when VREF = 10 V
AD5545
AD5555
16
14
2
1
1
10
20
1/ 4
Bits
Bits
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
Output Leakage Current
Full-Scale Gain Error
Full-Scale Temperature Coefficient2
REFERENCE INPUT
VREF Range
INL
INL
DNL
IOUT
IOUT
GFSE
TCVFS
LSB max
LSB max
LSB max
nA max
nA max
mV typ/max
ppm/°C typ
Monotonic
Data = 0x0000, TA = 25°C
Data = 0x0000, TA = TA Max
Data = Full Scale
1
VREF
RREF
CREF
–12/+12
5
5
V min/V max
kΩ typ3
pF typ
Input Resistance
Input Capacitance2
ANALOG OUTPUT
Output Current
Output Capacitance2
IOUT
COUT
Data = Full Scale
Code Dependent
2
200
mA typ
pF typ
LOGIC INPUTS AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
INTERFACE TIMING2, 4
Clock Input Frequency
Clock Width High
Clock Width Low
CS to Clock Setup
Clock to CS Hold
Data Setup
VIL
VIH
IIL
0.8
2.4
10
V max
V min
µA max
pF max
CIL
10
fCLK
tCH
tCL
50
10
10
0
MHz
ns min
ns min
ns min
ns min
ns min
ns min
ns min
tCSS
tCSH
tDS
tDH
tLDS
10
5
10
5
Data Hold
LDAC Setup
Hold
tLDH
10
10
ns min
ns min
LDAC Width
tLDAC
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
VDD Range
IDD
PDISS
4.5/5.5
10
0.055
0.006
V min/V max
µA max
mW max
ꢀ/ꢀ max
Logic Inputs = 0 V
Logic Inputs = 0 V
∆VDD = 5ꢀ
Power Supply Sensitivity
PSS
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 RFB terminal
is tied to the amplifier output. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and not subject to production testing.
3 All ac characteristic tests are performed in a closed-loop system using an O42 I-to-V converter amplifier.
4 All input control signals are specified with tR = tF = 2.5 ns (10ꢀ to 90ꢀ of 3 V) and timed from a voltage level of 1.5 V.
Rev. 0 | Page 3 of 16
AD5545/AD5555
Parameter
Symbol
Conditions
5 V ꢀ10 Units
AC CHARACTERISTICS
Output Voltage Setting Time
To ±±0.1 ꢀull Sꢁaleꢂ ꢃata ꢄ ꢅeꢆo Sꢁale to
ꢀull Sꢁale to ꢅeꢆo Sꢁale
VREꢀ ꢄ 5 V p-pꢂ ꢃata ꢄ ꢀull Sꢁale
VREꢀ ꢄ ± Vꢂ ꢃata ꢄ ꢅeꢆo Sꢁale to Midsꢁale to ꢅeꢆo
Sꢁale
tS
±05
4
µs typ
Refeꢆenꢁe Multiplying BW
ꢃAC Glitꢁh Impulse
BW
Q
MHz typ
nV-s typ
7
ꢀeedthꢆough Eꢆꢆoꢆ
ꢃata ꢄ ꢅeꢆo Sꢁaleꢂ VREꢀ ꢄ .±± mV ꢆmsꢂ
f ꢄ . kHzꢂ Same Channel
VOUT/VREꢀ
–65
dB
ꢃigital ꢀeedthꢆough
Total Haꢆmoniꢁ ꢃistoꢆtion
Analog Cꢆosstalk
CS ꢄ Logiꢁ High and fCLK ꢄ . MHz
Q
7
nV-s typ
dB typ
THꢃ
VREꢀ ꢄ 5 V p-pꢂ ꢃata ꢄ ꢀull Sꢁaleꢂ f ꢄ . kHz to .± kHz
VREꢀB ꢄ ± Vꢂ Measuꢆe VOUTB with VREꢀA ꢄ 5 V p-p Sine
Waveꢂ ꢃata ꢄ ꢀull Sꢁaleꢂ f ꢄ . kHz to .± kHz
–85
CTA
eN
–95
.2
dB typ
Output Spot Noise Voltage
f ꢄ . kHzꢂ BW ꢄ . Hz
nV/√Hz
Rev0 ± | Page 4 of .6
AD5545/AD5555
ABSOLUTE MAXIMUM RATINGS
Table 2. AD5545/AD5555 Absolute Maximum Ratings
Parameter
Rating
VDD to GND
VREF to GND
Logic Inputs to GND
V(IOUT) to GND
Input Current to Any Pin except Supplies
Package Power Dissipation
–0.3 V, +8 V
–18 V, +18 V
–0.3 V, +8 V
–0.3 V, VDD + 0.3 V
50 mA
(TJ max – TA)/ θ
JA
Thermal Resistance θJA
16-Lead TSSOP
150°C/W
150°C
Maximum Junction Temperature (TJ max)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
–40°C to +85°C
–65°C to +150°C
RU-16 (Vapor Phase, 60 sec)
RU-16 (Infrared, 15 sec)
215°C
220°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 5 of 16
AD5545/AD5555
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
R
A
A
A
A
B
B
B
B
16 CLK
15 LDAC
14 MSB
1
2
3
4
5
6
7
8
FB
V
REF
OUT
I
AD5545/
A
A
V
DD
13
12
11
10
9
GND
GND
AD5555
DGND
CS
TOP VIEW
(Not to Scale)
I
OUT
V
RS
REF
R
SDI
FB
02918-0-002
Figure 2. 16-Lead TSSOP
Table 3. Pin Function Descriptions—16-Lead TSSOP
Pin No.
Mnemonic
Function
1
2
RFBA
Establish voltage output for DAC A by connecting to external amplifier output.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage.
Pin can be tied to VDD pin.
VREF
A
3
4
5
6
7
IOUT
AGND
AGND
IOUT
A
A
B
B
B
DAC A Current Output.
DAC A Analog Ground.
DAC B Analog Ground.
DAC B Current Output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage.
Pin can be tied to VDD pin.
VREF
8
9
10
RFBB
SDI
RS
Establish voltage output for DAC B by connecting to external amplifier output.
Serial Data Input. Input data loads directly into the shift register.
RESET Pin, Active Low Input. Input registers and DAC registers are set to all 0s or
midscale. Register Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and
0x2000 for AD5555 when MSB = 1.
11
CS
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial
LDAC
register data to the input register when CS/LDAC returns high. This does not affect
operation.
12
13
14
DGND
VDD
MSB
Digital Ground Pin.
Positive Power Supply Input. Specified range of operation 5 V 10ꢀ or 3 V 10ꢀ.
MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-
on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can
also be tied permanently to ground or VDD.
15
16
LDAC
CLK
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to
DAC registers. Asynchronous active low input. See Table 4 and Table 5 for operation.
Clock Input. Positive edge clocks data into shift register.
Rev. 0 | Page 6 of 16
AD5545/AD5555
SDI
A1
A0
D15
D14
D13
D12
D11
D10
D1
D0
INPUT REG LD
CLK
tDS
tDH
tCH
tCL
CS
tCSS
tCSH
LDAC
tLDH
tLDS
tLDAC
02918-0-003
Figure 3. AD5545 18-Bit Data Word Timing Diagram
SDI
A1
A0
D13
D12
D11
D10
D09
D08
D1
D0
INPUT REG LD
CLK
tDS
tDH
tCH
tCL
CS
tCSS
tCSH
LDAC
tLDH
tLDS
tLDAC
02918-0-004
Figure 4. AD5555 16-Bit Data Word Timing Diagram
Table 4. AD5545 Control Logic Truth Table
CS
CLK
LDAC
RS
MSB
Serial Shift Register Function
Input Register Function
DAC Register
H
L
L
X
L
H
H
H
H
H
H
X
X
X
No Effect
No Effect
Shift Register Data
Advanced One Bit
Latched
Latched
Latched
Latched
Latched
Latched
↑+
L
H
L
H
H
H
H
X
X
No Effect
No Effect
Latched
Selected DAC Updated
with Current SR Current
Latched
Latched
↑+
H
H
H
H
H
X
X
X
X
X
L
H
H
H
H
L
X
X
X
0
No Effect
No Effect
No Effect
No Effect
No Effect
Latched
Latched
Latched
Transparent
Latched
Latched
↑+
H
H
Latched Data = 0x0000
Latched Data = 0x8000
Latched Data = 0x0000
Latched Data = 0x8000
L
H
NOTES
1. SR = Shift Register, ↑+ = Positive Logic Transition, and X = Don’t Care.
2. At power-on, both the input register and the DAC register are loaded with all 0s.
Rev. 0 | Page 7 of 16
AD5545/AD5555
Table 5. AD5555 Control Logic Truth Table
CS
CLK
LDAC
RS
MSB
Serial Shift Register Function
Input Register Function
DAC Register
H
L
L
X
L
H
H
H
H
H
H
X
X
X
No Effect
No Effect
Shift Register Data
Advanced One Bit
Latched
Latched
Latched
Latched
Latched
Latched
↑+
L
H
L
H
H
H
H
X
X
No Effect
No Effect
Latched
Selected DAC Updated
with Current SR Current
Latched
Latched
↑+
H
H
H
H
H
X
X
X
X
X
L
H
H
H
H
L
X
X
X
0
No Effect
No Effect
No Effect
No Effect
No Effect
Latched
Latched
Latched
Transparent
Latched
Latched
↑+
H
H
Latched Data = 0x0000
Latched Data = 0x2000
Latched Data = 0x0000
Latched Data = 0x2000
L
H
NOTES
1. SR = Shift Register, ↑+ = Positive Logic Transition, and X = Don’t Care.
2. At power-on, both the input register and the DAC register are loaded with all 0s.
Table 6. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
LSB
B0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
line’s positive edge
Bit Position
Data Word
B17
A1
B16
A0
B15
D15
B14
D14
B13
D13
B12
D12
B11
D11
B10
D10
B9
B8
B7
B6
B5
B4
B3
B2
B1
Note that only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the
CS
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D15–D0) to the
decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5545 shift register are ignored; only
LDAC
the last 18 bits clocked in are used. If double-buffered data is not needed, the
pin can be tied logic low to disable the DAC registers.
Table 7. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
LSB
B0
D0
Bit Position
Data Word
B15
A1
B14
A0
B13
D13
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
Note that only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the
line’s positive edge
CS
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D13–D0) to the
decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5555 shift register are ignored; only
LDAC
the last 16 bits clocked in are used. If double-buffered data is not needed, the
pin can be tied logic low to disable the DAC registers.
Table 8. Address Decode
Aꢀ A1 DAC Decoded
0
0
1
1
0
1
0
1
None
DAC A
DAC B
DAC A and DAC B
Rev. 0 | Page 8 of 16
AD5545/AD5555
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0.6
0.4
1.0
0.8
0.6
0.4
0.2
0
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
0
0248 4096
6144
8192 10240 12288 14336 16384
CODE (Decimal)
CODE (Decimal)
02918-0-009
02918-0-012
Figure 5. AD5545 Integral Nonlinearity Error
Figure 8. AD5555 Differential Nonlinearity Error
1.0
0.8
1.5
V
= 2.5V
REF
T
= 25°C
A
1.0
0.5
0
0.6
0.4
0.2
INL
0
DNL
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
GE
8192 16384 24576 32768 40960 49152 57344 65536
2
4
6
8
10
CODE (Decimal)
SUPPLY VOLTAGE V (V)
DD
02918-0-010
02918-0-013
Figure 6. AD5545 Differential Nonlinearity Error
Figure 9. Linearity Errors vs. VDD
1.0
0.8
5
4
3
2
V
= 5V
DD
T
= 25°C
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
1
0
2048 4096
6144
8192 10240 12288 14336 16384
0
0.5
1.0 1.5
2.0
2.5 3.0
3.5
4.0
4.5 5.0
LOGIC INPUT VOLTAGE V (V)
CODE (Decimal)
IH
02918-0-014
02918-0-011
Figure 10. Supply Current vs. Logic Input Voltage
Figure 7. AD5555 Integral Nonlinearity Error
Rev. 0 | Page 9 of 16
AD5545/AD5555
3.0
2.5
2.0
CS
0x5555
0x8000
1.5
1.0
0.5
0xFFFF
0x0000
V
OUT
0
10k
100k
1M
CLOCK FREQUENCY (Hz)
10M
100M
02918-0-018
02918-0-015
Figure 14. Settling Time
Figure 11. Supply Current vs. Clock Frequency
90
V
V
= 5V ± 10%
DD
REF
80
70
= 10V
CS (5V/DIV)
60
50
V
V
= 5V
DD
= 10V
REF
CODES 0x8000 ↔ 0x7FFF
40
30
20
10
V
(50mV/DIV)
OUT
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5 5.0
10
100
1k
10k
100k
1M
TIME (µs)
FREQUENCY (Hz)
02918-0-019
02918-0-016
Figure 15. Midscale Transition and Digital Feedthrough
Figure 12. Power Supply Rejection Ration vs. Frequency
REF LEVEL
0.000dB
/DIV
MARKER 4 41 677.200Hz
MAG (A/R) –2.939db
12.000dB
0xFFFF
0x8000
0x4000
0x2000
0x1000
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
0x0002
0x0001
–12dB
–24dB
–36dB
–48dB
–60dB
–72dB
–84dB
–96dB
–108dB
0x0000
10
100
1k
10k
100k
1M
10M
START 10.000Hz
STOP 50 000 000.000Hz
02918-0-017
Figure 13. Reference Multiplying Bandwidth
Rev. 0 | Page 10 of 16
AD5545/AD5555
CIRCUIT OPERATION
5V
V
IN
The AD5545/AD5555 contain a 16-/14-bit, current-output,
digital-to-analog converter, a serial-input register, and a DAC
register. Both parts require a minimum of a 3-wire serial data
V
2.500V
OUT
ADR03
GND
LDAC
interface with additional
update.
for dual channel simultaneous
V
DD
R
R
R
R
I
A
FB
V
A
REF
2R
2R
2R
R
5kΩ
D/A CONVERTER SECTION
+3V
S2
S1
A
The DAC architecture uses a current-steering R-2R ladder
design. Figure 16 shows the typical equivalent DAC. The DAC
contains a matching feedback resistor for use with an external
I-to-V converter amplifier. The RFB pin is connected to the
output of the external amplifier. The IOUT terminal is connected
to the inverting input of the external amplifier. These DACs are
designed to operate with both negative or positive reference
voltages. The VDD power pin is used only by the logic to drive
the DAC switches ON and OFF. Note that a matching switch is
used in series with the internal 5 kΩ feedback resistor. If users
attempt to measure the RFB value, power must be applied to VDD
to achieve continuity. The VREF input voltage and the digital data
(D) loaded into the corresponding DAC register, according to
Equation 1 and Equation 2, determine the DAC output voltage.
OUT
V
CC
V
OUT
AD8628
V
EE
AD5545/AD5555
LOAD
–3V
A
A
GND
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY:
SWITCHES S1 AND S2 ARE CLOSED, V MUST BE POWERED
02918-0-006
DD
Figure 17. Recommended System Connections
SERIAꢀ DATA INTERFACE
The AD5545/AD5555 use a minimum 3-wire ( , SDI, CLK)
CS
serial data interface for single channel update operation. With
LDAC
Table 4 as an example (AD5545), users can tie
low and
high, then pull low for an 18-bit duration. New serial data
RS
CS
is then clocked into the serial-input register in an 18-bit data-
word format with the MSB bit loaded first. Table 5 defines the
truth table for the AD5555. Data is placed on the SDI pin and
clocked into the register on the positive clock edge of CLK. For
the AD5545, only the last 18-bits clocked into the serial register
VOUT = –VREF × D/65,536
VOUT = –VREF × D/16,384
(1)
(2)
Note that the output full-scale polarity is the opposite of the
REF polarity for dc reference voltages.
will be interrogated when the
pin is strobed high, transfer-
CS
V
ring the serial register data to the DAC register and updating
the output. If the applied microcontroller outputs serial data in
different lengths than the AD5545, such as 8-bit bytes, three
right justified data bytes can be written to the AD5545. The
AD5545 will ignore the six MSB and recognize the 18 LSB as
valid data. After loading the serial register, the rising edge of
V
DD
R
R
R
V
R
REF
FB
2R
2R
2R
R
5kΩ
S2
S1
I
OUT
transfers the serial register data to the DAC register and
CS
GND
updates the output; during the
strobe, the CLK should not
CS
be toggled.
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY:
If users want to program each channel separately but update
SWITCHES S1 AND S2 ARE CLOSED, V MUST BE POWERED
DD
LDAC
them simultaneously, they need to program
and high
RS
02918-0-005
initially, then pull low for an 18-bit duration and program
CS
Figure 16. Equivalent R-2R DAC Circuit
DAC A with the proper address and data bits. is then pulled
CS
high to latch data to the DAC A register.At this time, the output is
These DACs are also designed to accommodate ac reference
input signals. The AD5545/AD5555 will accommodate input
reference voltages in the range of –12 V to +12 V. The reference
voltage inputs exhibit a constant nominal input-resistance value
of 5 kΩ, 30ꢀ. The DAC output (IOUT) is code dependent,
producing various output resistances and capacitances. When
choosing an external amplifier, the user should take into
account the variation in impedance generated by the
AD5545/AD5555 on the amplifiers inverting input node. The
feedback resistance in parallel with the DAC ladder resistance
dominates output voltage noise.
not updated. To load DAC B data, pull
low for an 18-bit dura-
CS
tion and program DAC B with the proper address and data, then
pull
high to latch data to the DAC B register. Finally, pull
CS
LDAC
low and then high to update both the DAC A and DAC B
outputs simultaneously.
Rev. 0 | Page 11 of 16
AD5545/AD5555
Table 8 shows that each DAC A and DAC B can be individually
loaded with a new data value. In addition, a common new data
value can be loaded into both DACs simultaneously by setting Bit
A1 = A0 = high. This command enables the parallel combination
of both DACs, with IOUTA and IOUTB tied together, to act as one
DAC with significant improved noise performance.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The input leads should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µF to 0.1 µF disc or chip
ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or electro-
lytic capacitors should also be applied at VDD to minimize any
transient disturbance and to filter any low frequency ripple
(see Figure 19). Users should not apply switching regulators for
VDD due to the power supply rejection ratio degradation over
frequency.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to digital ground (DGND) and VDD as shown in
Figure 18.
V
DD
DIGITAL
INPUTS
5kΩ
DGND
AD5545/
AD5555
02918-0-007
V
V
DD
DD
Figure 18. Equivalent ESD Protection Circuits
+
C2
C1
10µF 0.1µF
A
X
GND
POWER-UP SEQUENCE
It is recommended to power-up VDD and ground prior to any
reference voltages. The ideal power-up sequence is AGNDX,
DGND, VDD, VREFX, and digital inputs. A noncompliance power-
up sequence can elevate reference current, but the device will
resume normal operation once VDD is powered.
DGND
02918-0-008
Figure 19. Power Supply Bypassing and Grounding Connection
GROUNDING
The DGND and AGNDX pins of the AD5545/AD5555 refer to the
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 19).
Rev. 0 | Page 12 of 16
AD5545/AD5555
circuit, the second amplifier, U4, provides a gain of +2, which
increases the output span magnitude to 5 V. Biasing the external
amplifier with a 2.5 V offset from the reference voltage results in a
full 4-quadrant multiplying circuit. The transfer equation of this
circuit shows that both negative and positive output voltages are
created because the input data (D) is incremented from code zero
APPLICATIONS
STABILITY
V
DD
U1
C1
V
R
FB
DD
(VOUT = –2.5 V) to midscale (VOUT = 0 V) to full scale (VOUT
+2.5 V).
=
V
V
I
OUT
REF
REF
V
O
AD8628
GND
VOUT
VOUT
=
=
(
(
D/32,768 –1
)
×VREF
×VREF
(
AD5545
AD5555
)
(3)
(4)
AD5545/AD5555
U2
02918-0-020
D/16,384 –1
)
(
)
Figure 20. Operational Compensation Capacitor for Gain Peaking Prevention
For the AD5545, the external resistance tolerance becomes the
dominant error that users should be aware of.
In the I-to-V configuration, the IOUT of the DAC and the invert-
ing node of the op amp must be connected as close as possible,
and proper PCB layout techniques must be employed. Since
every code change corresponds to a step function, gain peaking
may occur if the op amp has limited GBP, and if there is exces-
sive parasitic capacitance at the inverting node.
R1
R2
10kΩ±0.01% 10kΩ±0.01%
C2
U4
+5V
+5V
U1
5kΩ±0.01%
V
V+
1/2
O
An optional compensation capacitor, C1, can be added for sta-
bility as shown in Figure 20. C1 should be found empirically, but
20 pF is generally more than adequate for the compensation.
R3
ADR03
AD8620
C1
V
R
FB
V–
DD
5V
V
V
I
OUT
V
REF
IN
OUT
–5V
–2.5 < V < +2.5
1/2
GND
GND
AD8620
O
POSITIVE VOLTAGE OUTPUT
U3
To achieve the positive voltage output, an applied negative
reference to the input of the DAC is preferred over the output
inversion through an inverting amplifier because of the resis-
tors’ tolerance errors. To generate a negative reference, the
reference can be level shifted by an op amp such that the VOUT
and GND pins of the reference become the virtual ground and
–2.5 V, respectively (see Figure 21).
AD5545/AD5555
U2
02918-0-022
Figure 22. Four-Quadrant Multiplying Application Circuit
PROGRAMMABLE CURRENT SOURCE
Figure 23 shows a versatile V-to-I conversion circuit using
improved Howland Current Pump. In addition to the precision
current conversion it provides, this circuit enables a bidirec-
tional current flow and high voltage compliance. This circuit
can be used in a 4 mA to 20 mA current transmitter with up to
a 500 Ω of load. In Figure 23, it shows that if the resistor net-
work is matched, the load current is
+5V
ADR03
V
V
OUT IN
U4
+5V
V+
U1
V
GND
U3
C1
R
DD
FB
1/2
I
V
OUT
REF
AD8620
V
O
–2.5V
1/2
V–
GND
AD8628
(
R2 + R3)
–5V
R1
R3
0 < V < +2.5
AD5545/AD5555
IL =
× VREF × D
(5)
U2
O
02918-0-021
R3, in theory, can be made small to achieve the current needed
within the U3 output current driving capability. This circuit is
versatile such that the AD8510 can deliver 20 mA in both
directions, and the voltage compliance approaches 15 V, which
is mainly limited by the supply voltages of U3. However, users
must pay attention to the compensation. Without C1, it can be
shown that the output impedance becomes
Figure 21. Positive Voltage Output Configuration
BIPOLAR OUTPUT
The AD5545/AD5555 is inherently a 2-quadrant multiplying
D/A converter. It can easily set up for unipolar output opera-
tion. The full-scale output polarity is the inverse of the reference
input voltage.
′
R1 R3
(
)
R1+ R2
′
– R1 (R2 + R3
)
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing. This
is easily accomplished by using an additional external amplifier,
U4, configured as a summing amplifier (see Figure 22). In this
ZO
=
(6)
′
′
R1(
R2 + R3
)
Rev. 0 | Page 13 of 16
AD5545/AD5555
If the resistors are perfectly matched, ZO is infinite, which is
desirable, and the resistors behave as an ideal current source.
On the other hand, if they are not matched, ZO can be either
positive or negative. The latter can cause oscillation. As a result,
C1 is needed to prevent the oscillation. For critical applications,
C1 could be found empirically but typically falls in the range of
a few pF.
R
WB and RWA are digital potentiometer 128-step programmable
resistances and are given by
DC
128
RWB
≈
≈
RAB
(8)
(9)
128 − DC
RWA
RWB
RAB
128
DC
≈
(10)
V
DD
RWA 128 − DC
U1
V
where DC = Digital Potentiometer Digital Code in Decimal
R
FB
DD
(0 ≤ DC ≤ 127).
I
V
V
REF
R1'
R2'
OUT
REF
150kΩ 15kΩ
GND
AD8628
By putting Equations 7 through 10 together, the following
results:
C1
10pF
AD5545/AD5555
U2
V
DD
R3'
DC
128 − DC
50Ω
U3
1+
V+
AD8510
VREF AB =VREF
×
(11)
DA
2N
DC
V–
1−
×
R3
128 − DC
50Ω
V
SS
V
L
Table 9 shows a few examples of VREFAB of the 14-bit AD5555.
R1
R2
150kΩ
15kΩ
Table 9. VREFABvs. DB and DC of the AD5555
I
LOAD
L
DC
DA
VREFAB
0
X
VREF
32
32
64
64
96
96
0
1.33 VREF
1.6 VREF
2 VREF
4 VREF
4 VREF
02918-0-023
8192
0
8192
0
Figure 23. Programmable Current Source with Bidirectional
Current Control and High Voltage Compliance Capabilities
DAC WITH PROGRAMMABLE INPUT
REFERENCE RANGE
8192
–8 VREF
Since high voltage references can be costly, users may consider
using one of the DACs, a digital potentiometer, and a low
voltage reference to form a single-channel DAC with a
programmable input reference range. This approach optimizes
the programmable range as well as facilitates future system
upgrades with just software changes. Figure 24 shows this
implementation. VREFABis in the feedback network, therefore,
The output of DAC B is, therefore,
DB
VOB = −VREF AB
(12)
2N
where DB is the DAC B digital code in decimal.
The accuracy of VREFAB will be affected by the matching of the
input and feedback resistors and, therefore, a digital potenti-
ometer is used for U4 because of its inherent resistance
matching. The AD7376 is a 30 V or 15 V, 128-step digital
potentiometer. If 15 V or 7.5 V is adequate for the application,
a 256-step AD5260 digital potentiometer can be used instead.
RWB
RWA
DA RWB
VREF AB =VREF × 1+
– –VREF_AB
×
×
(7)
2N
RWA
where:
VREFAB = Reference Voltage of VREFA and VREF
REF = External Reference Voltage
B
V
DA = DAC A Digital Code in Decimal
N = Number of Bits of DAC
Rev. 0 | Page 14 of 16
AD5545/AD5555
+5V
C1
+15V
R
A
V
FB
DD
I
A
OUT
V+
U4
A
B
V
A
REF
U1A
A
OP4177
V–
AD7376
A
W
GND
C2
+15V
2
2.2p
–15V
U2A
U3
V
IN
3
5
6
OP4177
TEMP TRIM
AD5555
V
V
REF_AB
REF
V
OUT
GND
4
U2C
ADR03
C3
R
B
FB
POT
I
B
OUT
V
B
O
V
B
REF
OP4177
U1B
A
B
GND
U2B
02918-0-024
Figure 24. DAC with Programmable Input Reference Range
Rev. 0 | Page 15 of 16
AD5545/AD5555
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.65
BSC
SEATING
PLANE
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)—Dimensions shown in millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Outline
AD5545/AD5555 Products
AD5545BRU*
AD5545BRU–REEL7
AD5555CRU
INL LSB
±±
±±
±1
±1
DNL LSB
±1
±1
±1
±1
RES (Bits)
Qty
96
1000
96
16
16
14
14
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
RU–16
RU–16
RU–16
RU–16
AD5555CRU–REEL7
1000
*The AD5545/AD5555 contain 3131 transistors. The die size measures 71 mil. × 96 mil., 6816 sq. mil.
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis-
tered trademarks are the property of their respective companies.
C02918-0-7/03(0)
Rev. 0 | Page 16 of 16
相关型号:
AD5546BRU-REEL7
Current Output, Parallel Input, 16-/14-Bit Multiplying DACs with 4-Quadrant Resistors
ADI
©2020 ICPDF网 联系我们和版权申明