AD5672RBRUZ [ADI]
Octal, 12-/16-Bit nanoDAC with ppm/°C Reference, SPI Interface;
| 型号： | AD5672RBRUZ |
| 厂家： | 
ADI |
| 描述： | Octal, 12-/16-Bit nanoDAC with ppm/°C Reference, SPI Interface 光电二极管 转换器 |
| 文件： | 总34页 (文件大小：865K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Octal, 12-/16-Bit nanoDAC+ with
2 ppm/°C Reference, SPI Interface
Data Sheet
AD5672R/AD5676R
FEATURES
GENERAL DESCRIPTION
High performance
The AD5672R/AD5676R are low power, octal, 12-/16-bit buffered
voltage output digital-to-analog converters (DACs). They include
a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a
gain select pin giving a full-scale output of 2.5 V (gain = 1) or
5 V (gain = 2). The devices operate from a single 2.7 V to 5.5 V
supply and are guaranteed monotonic by design. The AD5672R/
AD5676R are available in a 20-lead TSSOP and in a 20-lead LFCSP
and incorporate a power-on reset circuit and a RSTSEL pin that
ensures that the DAC outputs power up to zero scale or midscale
and remain there until a valid write. The AD5672R/AD5676R
contain a power-down mode, reducing the current consumption to
1 µA typical while in power-down mode.
High relative accuracy (INL): 3 LSB maximum at 16 bits
Total unadjusted error (TUE): 0.14% of FSR maximum
Offset error: 1.5 mV maximum
Gain error: 0.06% of FSR maximum
Low drift 2.5 V reference: 2 ppm/°C typical
Wide operating ranges
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply range
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/gain bit)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Robust 2 kV HBM and 1.5 kV FICDM ESD rating
20-lead, RoHS-compliant TSSOP and LFCSP
Table 1. Octal nanoDAC+® Devices
Interface
Reference
16-Bit
12-Bit
SPI
Internal
AD5676R
AD5676
AD5675R
AD5672R
Not applicable
AD5671R
APPLICATIONS
Optical transceivers
External
Internal
I2C
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5672R (12-bit): 1 LSB maximum.
AD5676R (16-bit): 3 LSB maximum.
2. Low Drift, 2.5 V On-Chip Reference.
Data acquisition systems
FUNCTIONAL BLOCK DIAGRAM
V
V
V
REFOUT
LOGIC
DD
AD5672R/AD5676R
2.5V
REF
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
DAC
STRING
DAC 0
INPUT
V
V
V
V
V
V
V
V
0
1
2
3
4
5
6
7
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
REGISTER
REGISTER
DAC
REGISTER
STRING
DAC 1
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 2
INPUT
REGISTER
SCLK
DAC
REGISTER
STRING
DAC 3
INPUT
REGISTER
SYNC
SDI
DAC
REGISTER
STRING
DAC 4
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 5
INPUT
REGISTER
SDO
DAC
REGISTER
STRING
DAC 6
INPUT
REGISTER
LDAC
DAC
REGISTER
STRING
DAC 7
INPUT
REGISTER
RESET
GAIN POWER-DOWN
POWER-ON
RESET
×1/×2
LOGIC
RSTSEL
GAIN
GND
Figure 1.
Rev. B
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Technical Support
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AD5672R/AD5676R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Write and Update Commands.................................................. 26
Daisy-Chain Operation ............................................................. 26
Readback Operation .................................................................. 27
Power-Down Operation............................................................ 27
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD5672R Specifications.............................................................. 3
AD5676R Specifications.............................................................. 5
AC Characteristics........................................................................ 7
Timing Characteristics ................................................................ 8
Daisy-Chain and Readback Timing Characteristics ............... 9
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin ConfigurationS and Function Descriptions......................... 12
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 22
Theory of Operation ...................................................................... 24
Digital-to-Analog Converter .................................................... 24
Transfer Function ....................................................................... 24
DAC Architecture....................................................................... 24
Serial Interface ............................................................................ 25
Standalone Operation................................................................ 26
REVISION HISTORY
LDAC
Load DAC (Hardware
Pin)........................................... 28
LDAC
Mask Register ................................................................. 28
RESET
Hardware Reset (
) .......................................................... 29
Reset Select Pin (RSTSEL) ........................................................ 29
Amplifier Gain Selection on LFCSP........................................ 29
Internal Reference Setup ........................................................... 29
Solder Heat Reflow..................................................................... 29
Long-Term Temperature Drift ................................................. 29
Thermal Hysteresis .................................................................... 30
Applications Information .............................................................. 31
Power Supply Recommendations............................................. 31
Microprocessor Interfacing....................................................... 31
AD5672R/AD5676R to ADSP-BF531 Interface..................... 31
AD5672R/AD5676R to SPORT Interface............................... 31
Layout Guidelines....................................................................... 31
Galvanically Isolated Interface ................................................. 32
Outline Dimensions....................................................................... 33
Ordering Guide .......................................................................... 34
11/15—Rev. A to Rev. B
Added Amplifier Gain Selection on LFCSP Section ................. 29
Updated Outline Dimensions....................................................... 33
Changes to Ordering Guide.......................................................... 34
Added 20-Lead LFCSP.......................................................Universal
Change to Features ........................................................................... 1
Changed TA = −40°C to +125°C to TMIN to TMAX.......................... 7
Changes to Table 7 .......................................................................... 11
Added Thermal Resistance Section and Table 8; Renumbered
Sequentially ..................................................................................... 11
Added Figure 7; Renumbered Sequentially ................................ 12
Changes to Table 9.......................................................................... 12
Changes to Transfer Function Section, Internal Reference
Section, and Output Amplifiers Section...................................... 24
Changes to Table 10 ....................................................................... 25
Changes to Write to and Update DAC Channel n (Independent
2/15—Rev. 0 to Rev. A
Added AD5672R Specifications Section ........................................3
Changes to Table 2.............................................................................3
Added AD5676R Specifications Section and Table 3;
Renumbered Sequentially ................................................................5
RESET
Change to
Pulse Activation Parameter, Table 5 ...............8
Change to Terminology Section................................................... 22
Changes to Transfer Function Section and Output Amplifiers
Section.............................................................................................. 24
of
) Section ............................................................................ 26
LDAC
RESET
Changes to Hardware Reset (
) Section............................ 29
Changes to Readback Operation Section.................................... 27
LDAC
Changes to Ordering Guide.......................................................... 33
Changes to
Mask Register Section and Table 15............ 28
10/14—Revision 0: Initial Version
Changes to Reset Select Pin (RSTSEL) Section, Internal
Reference Setup Section, Table 17, and Table 18........................ 29
Rev. B | Page 2 of 34
Data Sheet
AD5672R/AD5676R
SPECIFICATIONS
AD5672R SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications TA = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE1
Min
Typ
Max
Unit
Test Conditions/Comments
Resolution
Relative Accuracy (INL)
12
Bits
LSB
LSB
LSB
LSB
mV
mV
mV
0.12
1
1
0.1
0.1
1.6
2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1 or gain = 2
Gain = 1
Gain = 2
0.12
0.01
0.01
Differential Nonlinearity (DNL)
Zero Code Error
Offset Error
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
0.03
0.006
1
1.5
0.14
Full-Scale Error
Gain Error
TUE
% of FSR Gain = 1
% of FSR Gain = 2
% of FSR Gain = 1
% of FSR Gain = 2
% of FSR Gain = 1
% of FSR Gain = 2
µV/°C
0.07
0.12
0.06
0.18
0.14
Offset Error Drift2
DC Power Supply Rejection Ratio (PSRR)2
DC Crosstalk2
0.25
2
3
mV/V
µV
µV/mA
µV
DAC code = midscale, VDD = 5 V 10%
Due to single channel, full-scale output change
Due to load current change
2
Due to powering down (per channel)
OUTPUT CHARACTERISTICS2
Output Voltage Range
0
0
2.5
5
V
V
Gain = 1
Gain = 2
Output Current Drive
Capacitive Load Stability
15
mA
nF
2
RL = ∞
10
nF
kΩ
µV/mA
RL = 1 kΩ
Resistive Load3
Load Regulation
1
183
177
VDD = 5 V 10%, DAC code = midscale,
−30 mA ≤ IOUT ≤ +30 mA
VDD = 3 V 10%, DAC code = midscale,
−20 mA ≤ IOUT ≤ +20 mA
µV/mA
Short-Circuit Current4
Load Impedance at Rails5
Power-Up Time
40
25
2.5
mA
Ω
µs
Exiting power-down mode, VDD = 5 V
REFERENCE OUTPUT
Output Voltage6
Reference Temperature Coefficient7, 8
Output Impedance2
Output Voltage Noise2
Output Voltage Noise Density2
2.4975
2.5025
5
V
2
0.04
13
ppm/°C
Ω
µV p-p
nV/√Hz
See the Terminology section
0.1 Hz to 10 Hz
240
At ambient temperature, f = 10 kHz, CL = 10 nF,
gain = 1 or 2
At ambient temperature
At ambient temperature
VDD ≥ 3 V
At ambient temperature
After 1000 hours at 125°C
First cycle
Load Regulation Sourcing2
Load Regulation Sinking2
Output Current Load Capability2
Line Regulation2
Long-Term Stability/Drift2
Thermal Hysteresis2
29
74
20
43
12
125
25
µV/mA
µV/mA
mA
µV/V
ppm
ppm
ppm
Additional cycles
Rev. B | Page 3 of 34
AD5672R/AD5676R
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS2
Input Current
Input Voltage
Low, VINL
1
µA
Per pin
0.3 × VLOGIC
V
High, VINH
0.7 × VLOGIC
V
Pin Capacitance
LOGIC OUTPUTS (SDO)2
Output Voltage
Low, VOL
3
4
pF
0.4
V
V
pF
ISINK = 200 μA
ISOURCE = 200 μA
High, VOH
VLOGIC − 0.4
Floating State Output Capacitance
POWER REQUIREMENTS
VLOGIC
1.8
5.5
1
V
ILOGIC
µA
µA
µA
µA
V
Power-on, −40°C to +105°C
Power-on, −40°C to +125°C
Power-down, −40°C to +105°C
Power-down, −40°C to +125°C
Gain = 1
1.3
0.5
1.3
5.5
5.5
VDD
2.7
VREF + 1.5
V
Gain = 2
IDD
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off, −40°C to +85°C
Internal reference on, −40°C to +85°C
Internal reference off
Normal Mode9
1.1
1.8
1.1
1.8
1
1
1
1
1
1.26
2.0
1.3
2.1
1.7
1.7
2.5
2.5
5.5
5.5
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
Internal reference on
All Power-Down Modes10
Tristate to 1 kΩ, −40°C to +85°C
Power down to 1 kΩ, −40°C to +85°C
Tristate, −40°C to +105°C
Power down to 1 kΩ, −40°C to +105°C
Tristate to 1 kΩ, −40°C to +125°C
Power down to 1 kΩ, −40°C to +125°C
1
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 =
V
DD with gain = 2. Linearity calculated using a reduced code range of 12 to 4080.
2 Guaranteed by design and characterization; not production tested.
3 Together, Channel 0, Channel 1, Channel 2, and Channel 3 can source/sink 40 mA. Similarly, together, Channel 4, Channel 5, Channel 6, and Channel 7 can source/sink
40 mA up to a junction temperature of 125°C.
4 VDD = 5 V. The devices include current limiting intended to protect the devices during temporary overload conditions. Junction temperature can be exceeded during
current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
6 Initial accuracy presolder reflow is 750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +125°C.
8 Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
9 Interface inactive. All DACs active. DAC outputs unloaded.
10 All DACs powered down.
Rev. B | Page 4 of 34
Data Sheet
AD5672R/AD5676R
AD5676R SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications TA = −40°C to +125°C, unless otherwise noted.
Table 3.
A Grade
Typ
B Grade
Typ
Parameter
STATIC PERFORMANCE1
Min
Max
Min
Max
Unit
Test Conditions/Comments
Resolution
16
16
Bits
Relative Accuracy (INL)
1.8
1.7
8
8
1.8
1.7
3
3
LSB
LSB
Gain = 1
Gain = 2
Differential Nonlinearity (DNL)
0.7
1
0.7
1
LSB
Gain = 1
0.5
1
0.5
1
LSB
Gain = 2
Zero Code Error
Offset Error
0.8
3
0.8
1.6
2
1.5
mV
mV
mV
Gain = 1 or gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
0.03
0.006
1
6
4
0.28
0.14
0.24
0.12
0.3
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
0.03
0.006
1
Full-Scale Error
Gain Error
0.14
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
mV/V
0.07
0.12
0.06
0.18
0.14
TUE
0.25
Offset Error Drift2
DC Power Supply Rejection
0.25
0.25
DAC code = midscale, VDD
5 V 10%
Due to single channel, full-scale
output change
=
Ratio (PSRR)2
DC Crosstalk2
2
2
µV
3
2
3
2
µV/mA
µV
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS2
Output Voltage Range
0
0
2.5
5
0
0
2.5
5
V
V
Gain = 1
Gain = 2
Output Current Drive
Capacitive Load Stability
15
15
mA
nF
2
2
RL = ∞
10
10
nF
kΩ
µV/mA
RL = 1 kΩ
Resistive Load3
Load Regulation
1
1
183
177
183
177
VDD = 5 V 10%, DAC code =
midscale, −30 mA ≤ IOUT ≤ +30 mA
VDD = 3 V 10%, DAC code =
µV/mA
midscale, −20 mA ≤ IOUT ≤ +20 mA
Short-Circuit Current4
Load Impedance at Rails5
Power-Up Time
40
25
2.5
40
25
2.5
mA
Ω
µs
Exiting power-down mode, VDD = 5 V
REFERENCE OUTPUT
Output Voltage6
2.4975
2.5025 2.4975
20
2.5025
5
V
Reference Temperature
5
2
ppm/°C
See the Terminology section
0.1 Hz to 10 Hz
Coefficient7, 8
Output Impedance2
0.04
13
240
0.04
13
240
Ω
Output Voltage Noise2
Output Voltage Noise Density2
µV p-p
nV/√Hz
At ambient temperature, f = 10 kHz,
CL = 10 nF, gain = 1 or 2
At ambient temperature
At ambient temperature
VDD ≥ 3 V
Load Regulation Sourcing2
Load Regulation Sinking2
29
74
20
29
74
20
µV/mA
µV/mA
mA
Output Current Load
Capability2
Line Regulation2
43
12
125
25
43
12
125
25
µV/V
ppm
ppm
ppm
At ambient temperature
After 1000 hours at 125°C
First cycle
Long-Term Stability/Drift2
Thermal Hysteresis2
Additional cycles
Rev. B | Page 5 of 34
AD5672R/AD5676R
Data Sheet
A Grade
Typ
B Grade
Typ
Parameter
LOGIC INPUTS2
Input Current
Input Voltage
Low, VINL
Min
Max
Min
Max
Unit
Test Conditions/Comments
1
1
µA
Per pin
0.3 ×
VLOGIC
0.3 ×
VLOGIC
V
High, VINH
0.7 ×
VLOGIC
0.7 ×
VLOGIC
V
Pin Capacitance
LOGIC OUTPUTS (SDO)2
Output Voltage
Low, VOL
3
4
3
4
pF
0.4
0.4
V
V
ISINK = 200 μA
ISOURCE = 200 μA
High, VOH
VLOGIC
0.4
−
VLOGIC
0.4
−
Floating State Output
Capacitance
pF
POWER REQUIREMENTS
VLOGIC
ILOGIC
1.8
5.5
1
1.8
5.5
1
V
µA
µA
µA
µA
V
Power-on, −40°C to +105°C
Power-on, −40°C to +125°C
Power-down, −40°C to +105°C
Power-down, −40°C to +125°C
Gain = 1
1.3
0.5
1.3
5.5
5.5
1.3
0.5
1.3
5.5
5.5
VDD
2.7
VREF + 1.5
2.7
VREF + 1.5
V
Gain = 2
IDD
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off, −40°C to +85°C
Internal reference on, −40°C to +85°C
Internal reference off
Normal Mode9
1.1
1.8
1.1
1.8
1
1
1
1
1.26
2.0
1.3
2.1
1.7
1.7
2.5
2.5
1.1
1.8
1.1
1.8
1
1
1
1
1.26
2.0
1.3
2.1
1.7
1.7
2.5
2.5
mA
mA
mA
mA
µA
µA
µA
µA
Internal reference on
All Power-Down Modes10
Tristate to 1 kΩ, −40°C to +85°C
Power down to 1 kΩ, −40°C to +85°C
Tristate, −40°C to +105°C
Power down to 1 kΩ, −40°C to
+105°C
1
1
5.5
5.5
1
1
5.5
5.5
µA
µA
Tristate to 1 kΩ, −40°C to +125°C
Power down to 1 kΩ, −40°C to +125°C
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 =
V
DD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.
2 Guaranteed by design and characterization; not production tested.
3 Together, Channel 0, Channel 1, Channel 2, and Channel 3 can source/sink 40 mA. Similarly, together, Channel 4, Channel 5, Channel 6, and Channel 7 can source/sink
40 mA up to a junction temperature of 125°C.
4 VDD = 5 V. The devices include current limiting intended to protect the devices during temporary overload conditions. Junction temperature can be exceeded during
current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
6 Initial accuracy presolder reflow is 750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +125°C.
8 Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
9 Interface inactive. All DACs active. DAC outputs unloaded.
10 All DACs powered down.
Rev. B | Page 6 of 34
Data Sheet
AD5672R/AD5676R
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX unless otherwise
noted. The operating temperature range is −40°C to +125°C; TA = 25°C. Guaranteed by design and characterization, not production tested.
Table 4.
Parameter
OUTPUT VOLTAGE SETTLING TIME1
Min Typ
Max
Unit
Test Conditions/Comments
AD5672R
AD5676R
5
5
8
8
µs
µs
¼ to ¾ scale settling to 2 LSB
¼ to ¾ scale settling to 2 LSB
SLEW RATE
DIGITAL-TO-ANALOG GLITCH IMPULSE1
DIGITAL FEEDTHROUGH1
CROSSTALK1
Digital
0.8
1.4
0.13
V/µs
nV-sec
nV-sec
1 LSB change around major carry (internal reference, gain = 1)
0.1
−0.25
nV-sec
nV-sec
nV-sec
nV-sec
dB
Analog
−1.3
−2.0
−80
300
6
Internal reference, gain = 2
Internal reference, gain = 2
DAC-to-DAC
TOTAL HARMONIC DISTORTION2
OUTPUT NOISE SPECTRAL DENSITY1
OUTPUT NOISE1
At TA, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
nV/√Hz DAC code = midscale, 10 kHz, gain = 2
µV p-p
dB
0.1 Hz to 10 Hz, gain = 1
SIGNAL-TO-NOISE RATIO (SNR)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
90
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
83
dB
SIGNAL-TO-NOISE-AND-DISTORTION
RATIO (SINAD)
80
dB
1 See the Terminology section. Measured using internal reference and gain = 1, unless otherwise noted.
2 Digitally generated sine wave at 1 kHz.
Rev. B | Page 7 of 34
AD5672R/AD5676R
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, and VREFIN = 2.5 V. All specifications −40°C to +125°C, unless otherwise noted. Maximum
SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Table 5.
1.8 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter Min
Max
Min
20
1.7
4.3
10.1
0.8
−0.8
1.25
6.75
9.7
Max
Unit Description
t1
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
t2
4
t3
4.5
t4
15.1
0.8
t5
t6
0.1
Data Hold Time
t7
0.95
9.65
4.75
4.85
41.25
26.35
4.8
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single, Combined, or All Channel Update)
SYNC Falling Edge to SCLK Fall Ignore
LDAC Pulse Width Low
t8
t9
t10
t11
t12
t13
t14
5.45
25
SCLK Falling Edge to LDAC Rising Edge
SCLK Falling Edge to LDAC Falling Edge
RESET Minimum Pulse Width Low
RESET Pulse Activation Time
Power-Up Time1
20.3
6.2
132
5.15
80
5.18
1 Time to exit power-down to normal mode of AD5672R/AD5676R operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
t9
t1
SCLK
t2
t8
t7
t3
t4
SYNC
SDI
t6
t5
DB23
DB0
t12
t10
1
LDAC
t11
2
LDAC
t13
RESET
t14
V
OUT
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. B | Page 8 of 34
Data Sheet
AD5672R/AD5676R
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and
Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V. All specifications −40°C to +125°C, unless otherwise noted. Maximum
SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not
production tested.
Table 6.
1.8 V ≤ VLOGIC < 2.7 V
Min Max
2.7 V ≤ VLOGIC ≤ 5.5 V
Min Max
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
t1
t2
t3
t4
t5
t6
t7
t8
t10
t11
120
33
2.8
83.3
25.3
3.25
50
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge
Data Setup Time
75
1.2
0.3
16.2
55.1
21.5
24.4
0.5
0.4
13
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SDO Data Valid from SCLK Rising Edge
SCLK Falling Edge to SYNC Rising Edge
45
22.7
20.3
t12
85.5
54
ns
SYNC Rising Edge to SCLK Rising Edge
Circuit Diagram and Daisy-Chain and Readback Timing Diagrams
200µA
I
OL
TO OUTPUT
PIN
V
(MIN)
OH
C
L
20pF
200µA
I
OH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
SCLK
24
48
t11
t8
t12
t4
SYNC
SDI
t6
t5
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
t10
DB23
DB0
SDO
UNDEFINED
Figure 4. Daisy-Chain Timing Diagram
Rev. B | Page 9 of 34
AD5672R/AD5676R
Data Sheet
t1
SCLK
24
24
1
1
t3
t7
t4
t2
t8
SYNC
t6
t5
DB23
DB0
DB23
DB0
SDI
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
t10
DB23
DB0
DB23
DB0
SDO
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 5. Readback Timing Diagram
Rev. B | Page 10 of 34
Data Sheet
AD5672R/AD5676R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
The design of the thermal board requires close attention. Thermal
resistance is highly impacted by the printed circuit board (PCB)
being used, layout, and environmental conditions.
Table 7.
Parameter
Rating
VDD to GND
VLOGIC to GND
VOUTx to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak Temperature,
Pb-Free (J-STD-020)
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +125°C
−65°C to +150°C
125°C
Table 8. Thermal Resistance
Package Type
θJA
θJB
θJC
ΨJT
ΨJB
Unit
20-Lead TSSOP
(RU-20)1
98.65 44.39 17.58 1.77 43.9 °C/W
20-Lead LFCSP
(CP-20-8)2
82
16.67 32.5
0.43 22
°C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD51
260°C
2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD51.
ESD Ratings
Human Body Model (HBM)
2 kV
Field-Induced Charged Device Model
(FICDM)
1.5 kV
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 11 of 34
AD5672R/AD5676R
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
20
19
18
17
16
15
14
13
12
11
V
1
V
2
OUT
OUT
2
V
0
V
V
3
OUT
OUT
REFOUT
3
V
DD
AD5672R/
AD5676R
TOP VIEW
(Not to Scale)
4
V
RESET
SDO
V
REFOUT
V
LOGIC
15
14
13
12
11
1
2
3
4
5
DD
5
RESET
SDO
V
SYNC
SCLK
SDI
LOGIC
AD5672R/
AD5676R
SYNC
SCLK
SDI
6
LDAC
RSTSEL
GND
LDAC
GND
7
8
GAIN
9
V
7
6
V
V
4
5
OUT
OUT
OUT
OUT
10
V
TOP VIEW
(Not to Scale)
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. THE EXPOSED PAD MUST BE TIED TO GND.
Figure 6. TSSOP Pin Configuration
Figure 7. LFCSP Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1
2
3
19
20
1
VOUT
VOUT
VDD
1
0
Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
Power Supply Input. These devices operate from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 µF
capacitor in parallel with a 0.1 µF capacitor to GND.
4
5
2
3
VLOGIC
SYNC
Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, data transfers in on the falling edges of the next 24 clocks.
6
7
8
4
5
SCLK
SDI
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data transfers at rates of up to 50 MHz.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the
falling edge of the serial clock input.
GAIN
Span Set Pin. When this pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. If this pin is
tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF
.
9
6
7
8
9
10
11
VOUT
VOUT
VOUT
VOUT
NIC
7
6
5
4
Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
No Internal Connection.
Ground Reference Point for All Circuitry on the Device.
Power-On Reset Pin. Tie this pin to GND to power up all eight DACs to zero scale. Tie this pin to VLOGIC to
power up all eight DACs to midscale.
10
11
12
13
14
GND
RSTSEL
15
12
LDAC
Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or
all DAC registers to be updated if the input registers have new data, which allows all DAC outputs to update
simultaneously. This pin can also be tied permanently low.
16
17
13
14
SDO
Serial Data Output. This pin can be used to daisy-chain a number of devices together, or it can be used for
readback. The serial data transfers on the rising edge of SCLK and is valid on the falling edge.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are
ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or
midscale, depending on the state of the RSTSEL pin.
RESET
18
19
20
N/A1
15
17
18
0
VREFOUT
Reference Output Voltage. When using the internal reference, this is the reference output pin.
Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
VOUT
VOUT
3
2
EPAD
1 N/A means not applicable.
Rev. B | Page 12 of 34
Data Sheet
AD5672R/AD5676R
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.0
0.8
1.5
0.6
1.0
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
0
10000
20000
30000
40000
50000
60000
70000
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
CODE
Figure 8. AD5676R INL Error vs. Code
Figure 11. AD5672R DNL Error vs. Code
2.0
1.5
0.04
0.03
0.02
0.01
0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.01
–0.02
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
10000
20000
30000
40000
50000
60000
70000
CODE
Figure 9. AD5672R INL Error vs. Code
Figure 12. AD5676R TUE vs. Code
1.0
0.8
0.04
0.03
0.02
0.01
0
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.01
–0.02
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
10000
20000
30000
40000
50000
60000
70000
CODE
Figure 10. AD5676R DNL Error vs. Code
Figure 13. AD5672R TUE vs. Code
AD5672R/AD5676R
Data Sheet
10
10
8
8
6
6
4
4
2
2
0
0
–2
–4
–2
–4
–6
–8
–10
V
T
= 5V
V
T
= 5V
–6
–8
DD
= 25°C
DD
= 25°C
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
–10
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
120
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. AD5676R INL Error vs. Temperature
Figure 17. AD5672R DNL Error vs. Temperature
10
8
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
6
4
2
0
V
= 5V
= 25°C
DD
–2
–4
–6
–8
–10
T
A
INTERNAL REFERENCE = 2.5V
V
= 5V
= 25°C
DD
T
A
INTERNAL REFERENCE = 2.5V
–40
–20
0
20
40
60
80
100
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 18. AD5676R TUE vs. Temperature
Figure 15. AD5672R INL Error vs. Supply Voltage
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
10
8
6
4
2
0
V
= 5V
= 25°C
DD
–2
–4
–6
–8
–10
T
A
INTERNAL REFERENCE = 2.5V
V
T
= 5V
DD
= 25°C
A
INTERNAL REFERENCE = 2.5V
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. AD5672R TUE vs. Temperature
Figure 16. AD5676R DNL Error vs. Temperature
Rev. B | Page 14 of 34
Data Sheet
AD5672R/AD5676R
10
0.10
0.08
0.06
0.04
0.02
0
8
6
4
2
0
–2
–4
–0.02
–0.04
–0.06
–0.08
–0.10
V
= 5V
= 25°C
V
= 5V
–6
–8
DD
DD
T
T = 25°C
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
–10
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 20. AD5676R INL Error vs. Supply Voltage
Figure 23. AD5676R TUE vs. Supply Voltage
10
8
0.10
0.08
0.06
0.04
0.02
0
6
4
2
0
–2
–4
–6
–8
–10
–0.02
–0.04
–0.06
–0.08
–0.10
V
= 5V
= 25°C
V
= 5V
DD
DD
T
T = 25°C
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 21. AD5676R DNL Error vs. Supply Voltage
Figure 24. AD5672R TUE vs. Supply Voltage
10
8
0.10
0.08
0.06
0.04
0.02
0
6
4
2
FULL-SCALE ERROR
GAIN ERROR
0
–2
–4
–6
–8
–10
–0.02
–0.04
–0.06
–0.08
–0.10
V
T
= 5V
= 25°C
DD
V
T
= 5V
DD
A
= 25°C
INTERNAL REFERENCE = 2.5V
A
INTERNAL REFERENCE = 2.5V
2.7
3.2
3.7
4.2
4.7
5.2
–40
–20
0
20
40
60
80
100
120
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 22. AD5672R DNL Error vs. Supply Voltage
Figure 25. AD5676R Gain Error and Full-Scale Error vs. Temperature
Rev. B | Page 15 of 34
AD5672R/AD5676R
Data Sheet
0.10
0.08
0.06
0.04
0.02
0
1.8
1.5
1.2
0.9
0.6
0.3
0
V
T
= 5V
= 25°C
DD
A
INTERNAL REFERENCE = 2.5V
ZERO CODE ERROR
OFFSET ERROR
GAIN ERROR
–0.02
–0.04
–0.06
FULL-SCALE ERROR
V
= 5V
DD
–0.3
–0.6
–0.08
–0.10
T = 25°C
A
INTERNAL REFERENCE = 2.5V
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 29. AD5676R Zero Code Error and Offset Error vs. Temperature
Figure 26. AD5672R Gain Error and Full-Scale Error vs. Temperature
1.8
0.10
0.08
0.06
0.04
0.02
V
T
= 5V
= 25°C
DD
1.5
1.2
0.9
0.6
0.3
0
A
INTERNAL REFERENCE = 2.5V
ZERO CODE ERROR
GAIN ERROR
OFFSET ERROR
0
–0.02
FULL-SCALE ERROR
–0.04
–0.06
V
= 5V
–0.3
–0.6
DD
–0.08
–0.10
T = 25°C
A
INTERNAL REFERENCE = 2.5V
–40
–20
0
20
40
60
80
100
120
2.7
3.2
3.7
4.2
4.7
5.2
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 30. AD5672R Zero Code Error and Offset Error vs. Temperature
Figure 27. AD5676R Gain Error and Full-Scale Error vs. Supply Voltage
1.5
0.10
0.08
0.06
0.04
0.02
1.0
ZERO CODE ERROR
0.5
OFFSET ERROR
0
0
–0.02
–0.04
–0.06
–0.08
–0.10
GAIN ERROR
–0.5
FULL-SCALE ERROR
–1.0
–1.5
V
= 5V
DD
V
= 5V
= 25°C
DD
T
= 25°C
A
T
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 31. AD5676R Zero Code Error and Offset Error vs. Supply Voltage
Figure 28. AD5672R Gain Error and Full-Scale Error vs. Supply Voltage
Rev. B | Page 16 of 34
Data Sheet
AD5672R/AD5676R
1.5
1.0
0.5
0
6
5
0xFFFF
0xC000
0x8000
ZERO CODE ERROR
OFFSET ERROR
4
3
2
0x4000
0x0000
1
–0.5
0
–1.0
–1.5
V
= 5V
= 25°C
DD
–1
–2
T
A
INTERNAL REFERENCE = 2.5V
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
LOAD CURRENT (A)
Figure 35. Source and Sink Capability at 5 V
Figure 32. AD5672R Zero Code Error and Offset Error vs. Supply Voltage
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
70
V
= 5V
= 25°C
DD
T
A
60
50
40
30
20
10
0
INTERNAL REFERENCE = 2.5V
0xFFFF
0xC000
0x8000
0x4000
0x0000
–0.5
–1.0
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
LOAD CURRENT (A)
I
FULL SCALE (µA)
DD
Figure 36. Source and Sink Capability at 3 V
Figure 33. Supply Current (IDD) Histogram with Internal Reference
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1.4
SINKING, V = –2.7V
DD
U1284
U1285
U1286
SINKING, V = –3.0V
DD
1.0
0.6
SINKING, V = –5.0V
DD
SOURCING, V = –5.0V
DD
SOURCING, V = –3.0V
DD
SOURCING, V = –2.7V
DD
0.2
–0.2
–0.6
–1.0
–1.4
0
10000
20000
30000
40000
50000
60000
70000
0
0.005
0.010
0.015
0.020
0.025
0.030
CODE
LOAD CURRENT (A)
Figure 37. Supply Current (IDD) vs. Code
Figure 34. Headroom/Footroom (ΔVOUT) vs. Load Current
Rev. B | Page 17 of 34
AD5672R/AD5676R
Data Sheet
2.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
FULL-SCALE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 5
DAC 7
DAC 8
ZERO CODE
EXTERNAL REFERENCE, FULL-SCALE
V
= 5.5V
DD
GAIN = +1
INTERNAL REFERENCE = 2.5V
1/4 TO 3/4 SCALE
–40
–20
0
20
40
60
80
100
120
80
100
120
140
160
180
200
TEMPERATURE (°C)
TIME (µs)
Figure 38. Supply Current (IDD) vs. Temperature
Figure 41. Full-Scale Settling Time
6
5
0.006
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.005
0.004
0.003
0.002
0.001
0
V
V
(V)
DD
0 (V)
1 (V)
2 (V)
3 (V)
4 (V)
5 (V)
6 (V)
7 (V)
OUT
4
FULL-SCALE
V
OUT
V
V
OUT
3
OUT
V
OUT
ZERO CODE
V
OUT
2
V
V
OUT
OUT
EXTERNAL REFERENCE, FULL-SCALE
1
0
–1
–0.001
10
0
2
4
6
8
2.7
3.2
3.7
4.2
4.7
5.2
TIME (ms)
SUPPLY VOLTAGE (V)
Figure 39. Supply Current (IDD) vs. Supply Voltage
Figure 42. Power-On Reset to 0 V and Midscale
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
3.0
2.5
2.0
1.5
1.0
0.5
0
MIDSCALE, GAIN = 2
FULL-SCALE
ZERO CODE
MIDSCALE, GAIN = 1
EXTERNAL REFERENCE, FULL-SCALE
V
T
= 5V
= 25°C
DD
A
INTERNAL REFERENCE = 2.5V
2.7
3.2
3.7
4.2
4.7
5.2
–5
0
5 10
SUPPLY VOLTAGE (V)
TIME (µs)
Figure 40. Supply Current (IDD) vs. Zero Code and Full-Scale
Figure 43. Exiting Power-Down to Midscale
Rev. B | Page 18 of 34
Data Sheet
AD5672R/AD5676R
0.004
0.003
0.002
0.001
0
1
–0.001
–0.002
–0.003
–0.004
V
= 5V
DD
GAIN = 1
= 25°C
T
D
REFERENCE = 2.5V
CODE = 7FFF TO 8000
ENERGY = 1.209376nV-s
2
CH1 50.0mV
M1.00s
A
CH1
401mV
15
16
17
18
19
20
21
22
TIME (µs)
Figure 44. Digital-to-Analog Glitch Impulse
Figure 47. 0.1 Hz to 10 Hz Output Noise
0.003
0.002
0.001
0
1200
1000
800
600
400
200
0
V
= 5V
= 25°C
DD
T
A
GAIN = 1
INTERNAL REFERENCE = 2.5V
–0.001
–0.002
–0.003
–0.004
–0.005
–0.006
FULL SCALE
MID SCALE
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
ZERO SCALE
0
2
4
6
8
10
12
14
16
18
20
10
100
1k
10k
100k
1M
TIME (µs)
FREQUENCY (Hz)
Figure 45. Analog Crosstalk
Figure 48. Noise Spectral Density (NSD)
0.012
0.010
0.008
0.006
0.004
0.002
0
0
–20
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
V
= 5V
= 25°C
DD
T
A
INTERNAL REFERENCE = 2.5V
–40
–60
–80
–100
–120
–140
–160
–180
–0.002
–0.004
–0.006
–0.008
–0.010
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
TIME (µs)
FREQUENCY (kHz)
Figure 46. DAC-to-DAC Crosstalk
Figure 49. Total Harmonic Distortion (THD) at 1 kHz
Rev. B | Page 19 of 34
AD5672R/AD5676R
Data Sheet
2.0
1.9
1.8
1600
1400
1200
1000
800
600
400
200
0
V
A
= 5V
DD
T
= 25°C
C
C
C
C
C
= 0nF
= 0.1nF
= 1nF
= 4.7nF
= 10nF
L
L
L
L
L
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
10
100
1k
10k
100k
1M
0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20
TIME (ms)
FREQUENCY (Hz)
Figure 50. Settling Time vs. Capacitive Load
Figure 53. Internal Reference NSD vs. Frequency
2.0
2.5020
2.5015
2.5010
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
DEVICE1
DEVICE2
DEVICE3
DEVICE4
DEVICE5
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
DAC 8
–40
–20
0
20
40
60
80
100
120
80
100
120
140
160
180
200
TIME (µs)
TEMPERATURE (°C)
Figure 51. Settling Time, 5.5 V
Figure 54. Internal Reference Voltage (VREF) vs. Temperature (A Grade)
3
2
1
0
0.3
0.2
0.1
0
RESET
MIDSCALE,GAIN=1
ZERO SCALE, GAIN = 1
–20
0
20
40
60
TIME (µs)
Figure 52. Hardware Reset
Rev. B | Page 20 of 34
Data Sheet
AD5672R/AD5676R
2.5020
2.5015
2.5010
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
2.50050
2.50045
2.50040
2.50035
2.50030
2.50025
2.50020
2.50015
2.50010
T
= 25°C
A
DEVICE1
DEVICE2
DEVICE3
DEVICE4
DEVICE5
DEVICE1
DEVICE2
DEVICE3
2.5
3.0
3.5
4.0
V
4.5
5.0
5.5
–40
–20
0
20
40
60
80
100
120
(V)
TEMPERATURE (°C)
DD
Figure 55. Internal Reference Voltage (VREF) vs. Temperature (B Grade)
Figure 57. Internal Reference Voltage (VREF) vs. Supply Voltage (VDD
)
2.5035
V
T
= 5V
= 25°C
DD
2.5030
2.5025
2.5020
2.5015
2.5010
2.5005
2.5000
2.4995
A
–0.035 –0.025
–0.015 –0.005
0.005
0.015
0.025
0.035
LOAD CURRENT (A)
Figure 56. Internal Reference Voltage (VREF) vs. Load Current and Supply
Voltage (VDD
)
Rev. B | Page 21 of 34
AD5672R/AD5676R
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Output Voltage Settling Time
The output voltage settling time is the amount of time it takes
for the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change and is measured from the rising edge
SYNC
of
.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. These DACs are guaranteed monotonic
by design.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000).
Zero Code Error
Zero code error is a measurement of the output error when zero
code (0x0000) is loaded to the DAC register. The ideal output is
0 V. The zero code error is always positive because the output of
the DAC cannot go below 0 V due to a combination of the offset
errors in the DAC and the output amplifier. Zero code error is
expressed in mV.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Full-Scale Error
Reference Feedthrough
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. The ideal
output is VDD − 1 LSB. Full-scale error is expressed in percent of
full-scale range (% of FSR).
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Noise Spectral Density
Gain Error
Noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nV/√Hz). It is measured by loading the DAC
to midscale and measuring noise at the output. It is measured in
nV/√Hz.
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % of FSR.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale. It
is expressed in μV.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured with Code 256
loaded in the DAC register. It can be negative or positive.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has on
another DAC kept at midscale. It is expressed in μV/mA.
DC Power Supply Rejection Ratio (PSRR)
The dc power supply rejection ratio indicates how the output of
the DAC is affected by changes in the supply voltage. PSRR is
the ratio of the change in VOUT to a change in VDD for full-scale
output of the DAC. It is measured in mV/V. VREF is held at 2 V,
and VDD is varied by 10%.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-sec.
Rev. B | Page 22 of 34
Data Sheet
AD5672R/AD5676R
Analog Crosstalk
Total Harmonic Distortion (THD)
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by first loading one of the input registers with a full-
scale code change (all 0s to all 1s and vice versa). Then, execute
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
LDAC
a software
and monitor the output of the DAC whose
Voltage Reference Temperature Coefficient (TC)
digital code was not changed. The area of the glitch is expressed
in nV-sec.
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given tempera-
ture range expressed in ppm/°C, as follows:
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by
loading the attack channel with a full-scale code change (all 0s
to all 1s and vice versa), using the write to and update commands
while monitoring the output of the victim channel that is at
midscale. The energy of the glitch is expressed in nV-sec.
VREF (MAX ) −VREF (MIN )
TC =
×106
VREF (NOM ) ×Temp Range
where:
REF (MAX) is the maximum reference output measured over the
total temperature range.
REF (MIN) is the minimum reference output measured over the
total temperature range.
REF (NOM) is the nominal reference output voltage, 2.5 V.
V
Multiplying Bandwidth
The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input.
V
V
Temp Range is the specified temperature range of −40°C to
+125°C.
Rev. B | Page 23 of 34
AD5672R/AD5676R
Data Sheet
THEORY OF OPERATION
V
REF
DIGITAL-TO-ANALOG CONVERTER
R
The AD5672R/AD5676R are octal, 12-/16-bit, serial input,
voltage output DACs with an internal reference. The devices
operate from supply voltages of 2.7 V to 5.5 V. Data is written to
the AD5672R/AD5676R in a 24-bit word format via a 3-wire
serial interface. The AD5672R/AD5676R incorporate a power-
on reset circuit to ensure that the DAC output powers up to a
known output state. The devices also have a software power-
down mode that reduces the typical current consumption to 1 µA.
R
R
TO OUTPUT
AMPLIFIER
TRANSFER FUNCTION
The internal reference is on by default.
R
R
The gain of the output amplifier can be set to ×1 or ×2 using the
gain select pin (GAIN) on the TSSOP or the gain bit on the LFCSP.
When the GAIN pin is tied to GND, all eight DAC outputs have
a span from 0 V to VREF. When the GAIN pin is tied to VLOGIC
,
Figure 59. Resistor String Structure
all eight DACs output a span of 0 V to 2 × VREF. When using the
LFCSP, the gain bit in the internal reference and gain setup
register is used to set the gain of the output amplifier. The gain
bit is 0 by default. When the gain bit is 0, the output span of all
eight DACs is 0 V to VREF. When the gain bit is 1, the output span
of all eight DACs is 0 V to 2 × VREF. The gain bit is ignored on
the TSSOP.
Internal Reference
The AD5672R/AD5676R on-chip reference is enabled at power-
up, but can be disabled via a write to the control register. See the
Internal Reference Setup section for details.
The AD5672R/AD5676R have a 2.5 V, 2 ppm/°C reference, giving
a full-scale output of 2.5 V or 5 V, depending on the state of the
GAIN pin or gain bit. The internal reference associated with the
device is available at the VREFOUT pin. This buffered reference is
capable of driving external loads of up to 15 mA.
DAC ARCHITECTURE
The AD5672R/AD5676R implement a segmented string DAC
architecture with an internal output buffer. Figure 58 shows the
internal block diagram.
Output Amplifiers
V
REF
The output buffer amplifier generates rail-to-rail voltages on its
output. The actual range depends on the value of VREF, the gain
setting, the offset error, and the gain error.
2.5V
REF
REF (+)
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
X
OUT
The output amplifiers can drive a load of 1 kΩ in parallel with
10 nF to GND. The slew rate is 0.8 V/µs with a typical ¼ to ¾
scale settling time of 5 µs.
REF (–)
GAIN
(GAIN = 1 OR 2)
GND
Figure 58. Single DAC Channel Architecture Block Diagram
Figure 59 shows the resistor string structure. The code loaded to
the DAC register determines the node on the string where the
voltage is tapped off and fed into the output amplifier. The voltage
is tapped off by closing one of the switches and connecting the
string to the amplifier. Because each resistance in the string has
same value, R, the string DAC is guaranteed monotonic.
Rev. B | Page 24 of 34
Data Sheet
AD5672R/AD5676R
SERIAL INTERFACE
Table 10. Command Definitions
Command
SYNC
The AD5672R/AD5676R use a 3-wire serial interface (
,
SCLK, and SDI that is compatible with SPI, QSPI™, and
MICROWIRE interface standards, as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence. The
AD5672R/AD5676R contain an SDO pin to allow the user to
daisy-chain multiple devices together (see the Daisy-Chain
Operation section) or for readback.
C3 C2 C1 C0 Description
0
0
0
0
0
0
0
1
No operation
Write to Input Register n where n = 1 to 8,
depending on the DAC selected from the
address bits in Table 11 (dependent
on LDAC)
0
0
1
0
Update DAC Register n with contents of
Input Register n
Input Shift Register
0
0
0
0
0
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
Write to and update DAC Channel n
Power down/power up the DAC
Hardware LDAC mask register
The input shift register of the AD5672R/AD5676R is 24 bits
wide. Data is loaded MSB first (DB23), and the first four bits are
the command bits, C3 to C0 (see Table 10), followed by the 4-
bit DAC address bits, A3 to A0 (see Table 11), and finally, the
bit data-word.
Software reset (power-on reset)
Internal reference and gain setup register
Set up the DCEN register (daisy-chain
enable)
Set up the readback register (readback
enable)
Update all channels of the input register
simultaneously with the input data
The data-word comprises 12-bit or 16-bit input code, followed by
zero or four don’t care bits for the AD5676R and AD5672R,
respectively (see Figure 60 and Figure 61). These data bits are
transferred to the input register on the 24 falling edges of SCLK
1
1
1
0
0
0
0
1
1
1
0
1
SYNC
and are updated on the rising edge of
.
Update all channels of the DAC register
and input register simultaneously with
the input data
Commands execute on individual DAC channels, combined DAC
channels, or on all DACs, depending on the address bits selected.
1
1
0
0
Reserved
…
1
…
1
…
1
…
1
Reserved
Table 11. Address Commands
Channel Address[3:0]
A3
0
A2
0
A1
0
A0
0
Selected Channel1
DAC 0
0
0
0
1
DAC 1
0
0
1
0
DAC 2
0
0
1
1
DAC 3
0
1
0
0
DAC 4
0
1
0
1
DAC 5
0
1
1
0
DAC 6
0
1
1
1
DAC 7
1 Any combination of DAC channels can be selected using the address bits.
DB23 (MSB)
DB0 (LSB)
C3
C2
C1
C0
A3
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 60. AD5672R Input Shift Register Content
DB23 (MSB)
C3 C2
DB0 (LSB)
D1 D0
C1
C0
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 61. AD5676R Input Shift Register Content
Rev. B | Page 25 of 34
AD5672R/AD5676R
Data Sheet
STANDALONE OPERATION
AD5672R/
AD5676R
68HC11*
SYNC
Bring the
line low to begin the write sequence. Data from
MOSI
SDI
the SDI line is clocked into the 24-bit input shift register on the
falling edge of SCLK. After the last of 24 data bits is clocked in,
SCK
PC7
PC6
SCLK
SYNC
LDAC
SYNC
that is, an
bring
high. The programmed function is then executed,
LDAC
-dependent change in DAC register contents
SDO
SDI
MISO
SYNC
and/or a change in the mode of operation. If
is taken
high at a clock before the 24th clock, it is considered a valid
SYNC
frame, and invalid data is loaded to the DAC. Bring
for a minimum of 20 ns (single channel, see t8 in Figure 2)
SYNC
high
AD5672R/
AD5676R
before the next write sequence so that a falling edge of
SCLK
SYNC
can initiate the next write sequence. Idle
at rails between
SYNC
LDAC
SYNC
write sequences for even lower power operation. The
is kept low for 24 falling edges of SCLK, and the DAC is
SYNC
line
SDO
SDI
updated on the rising edge of
.
When data is transferred into the input register of the addressed
LDAC
DAC, all DAC registers and outputs update by taking
SYNC
low
AD5672R/
AD5676R
while the
line is high.
SCLK
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on
SYNC
LDAC
)
LDAC
SDO
Command 0001 allows the user to write the dedicated input
LDAC
register of each DAC individually. When
is low, the input
Figure 62. Daisy-Chaining the AD5672R/AD5676R
LDAC
register is transparent, if not controlled by the
register.
mask
The SCLK pin is continuously applied to the input shift register
SYNC
when
is low. If more than 24 clock pulses are applied, the
Update DAC Register n with Contents of Input Register n
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting this line to the
SDI input on the next DAC in the chain, a daisy-chain interface is
constructed. Each DAC in the system requires 24 clock pulses.
Therefore, the total number of clock cycles must equal 24 × N,
Command 0010 loads the DAC registers and outputs with the
contents of the input registers selected and updates the DAC
outputs directly.
Write to and Update DAC Channel n (Independent of
)
LDAC
Command 0011 allows the user to write to the DAC registers
and updates the DAC outputs directly. Bit D7 to Bit D0
determine which DACs have data from the input register
transferred to the DAC register. Setting a bit to 1 transfers data
from the input register to the appropriate DAC register.
SYNC
where N is the total number of devices updated. If
is
taken high at a clock that is not a multiple of 24, it is considered
a valid frame, and invalid data may be loaded to the DAC.
SYNC
When the serial transfer to all devices is complete,
goes
high, which latches the input data in each device in the daisy
chain and prevents any further data from being clocked into the
input shift register. The serial clock can be continuous or a gated
DAISY-CHAIN OPERATION
For systems that contain several DACs, the SDO pin can daisy-
chain several devices together and is enabled through a software
executable daisy-chain enable (DCEN) command. Command
1000 is reserved for this DCEN function (see Table 10). The
daisy-chain mode is enabled by setting Bit DB0 in the DCEN
register. The default setting is standalone mode, where DB0 = 0.
Table 12 shows how the state of the bit corresponds to the mode
of operation of the device.
SYNC
clock. If
is held low for the correct number of clock
cycles, a continuous SCLK source is used. In gated clock mode,
use a burst clock containing the exact number of clock cycles,
SYNC
and take
high after the final clock to latch the data.
Table 12. Daisy-Chain Enable (DCEN) Register
DB0
Description
0
1
Standalone mode (default)
DCEN mode
Rev. B | Page 26 of 34
Data Sheet
AD5672R/AD5676R
READBACK OPERATION
Table 13. Modes of Operation
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisy-
chain mode disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
disabled again. Command 1001 is reserved for the readback
function. This command, in association with the address bits
A3 to A0, selects the DAC input register to read (see Table 10
and Table 11). Note that, during readback, only one input
register can be selected. The remaining data bits in the write
sequence are don’t care bits. During the next SPI write, the data
appearing on the SDO output contains the data from the
previously addressed register.
PD1
PD0
0
0
0
1
1
1
Tristate
When both Bit PD1 and Bit PD0 in the input shift register are set to
0, the device works normally with a typical power consumption of
1 mA at 5 V. However, for the two power-down modes, the
supply current typically falls to 1 µA. In addition to this fall, the
output stage switches internally from the amplifier output to a
resistor network of known values. This has the advantage that the
output impedance of the devices is known while the devices are
in power-down mode. There are two different power-down
options. The output is either connected internally to GND
through a 1 kΩ resistor or it is left open-circuited (tristate).
Figure 63 shows the output stage.
For example, to read back the DAC register for Channel 0,
implement the following sequence:
1. Write 0x900000 to the AD5672R/AD5676R input register.
This configures the device for read mode with the DAC
register of Channel 0 selected. Note that all data bits, DB15
to DB0, are don’t care bits.
AMPLIFIER
V
DAC
OUT
2. Follow this with a second write, a no operation (NOP)
condition, 0x000000. During this write, the data from the
register is clocked out on the SDO line. DB23 to DB20
contain undefined data, and the last 16 bits contain the
DB19 to DB4 DAC register contents.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
SYNC
When
is high, the SDO pin is driven by a weak latch that
Figure 63. Output Stage During Power-Down
holds the last data bit. The SDO pin can be overdriven by the
SDO pin of another device, thus allowing multiple devices to be
read using the same SPI interface.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry shut down when power-down mode is
activated. However, the contents of the DAC register are unaffected
when in power-down. The DAC register updates while the device
is in power-down mode. The time required to exit power-down is
typically 2.5 µs for VDD = 5 V.
POWER-DOWN OPERATION
The AD5672R/AD5676R contain two separate power-down
modes. Command 0100 is designated for the power-down
function (see Table 10). These power-down modes are software
programmable by setting 16 bits, Bit DB15 to Bit DB0, in the
input shift register. There are two bits associated with each DAC
channel. Table 13 shows how the state of the two bits corresponds
to the mode of operation of the device.
To reduce the current consumption further, power off the on-chip
reference. See the Internal Reference Setup section.
Any or all DACs (DAC A to DAC D) power down to the
selected mode by setting the corresponding bits. See Table 14
for the contents of the input shift register during the power-
down/power-up operation.
Table 14. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation
DAC 7
DAC 6
DAC 5
DAC 4
DAC 3
DAC 2
DAC 1
DAC 0
[DB23:DB20]
DB19
[DB18:DB16]
XXX1
[DB15: B14] [DB13: B12] [DB11: B10] [DB9:DB8]
[DB7:DB6]
[PD1:PD0]
[DB5:DB4]
[PD1:PD0]
[DB3:DB2]
[PD1:PD0]
[DB1:DB0]
[PD1:PD0]
0100
0
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
1 X means don’t care
Rev. B | Page 27 of 34
AD5672R/AD5676R
Data Sheet
LDAC
Deferred DAC Updating (
is Pulsed Low)
is held high while data is clocked into the input register
using Command 0001. All DAC outputs are asynchronously
LDAC SYNC
LOAD DAC (HARDWARE LDAC PIN)
LDAC
The AD5672R/AD5676R DACs have double buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The user can write to any combination of the input
registers. Updates to the DAC register are controlled by
updated by taking
low after
is taken high. The
LDAC
update now occurs on the falling edge of
.
LDAC
the
Instantaneous DAC Updating (
LDAC
pin.
LDAC MASK REGISTER
LDAC
Held Low)
is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
LDAC
Command 0101 is reserved for this software
function.
Address bits are ignored. Writing to the DAC, using
LDAC
Command 0101, loads the 8-bit
register (DB7 to DB0).
LDAC
SYNC
the DAC register are updated on the rising edge of
and
The default for each channel is 0; that is, the
pin works
the output begins to change (see Table 16).
normally. Setting the bits to 1 forces this DAC channel to ignore
LDAC
AMPLIFIER
transitions on the
pin, regardless of the state of the
12-/16-BIT
DAC
LDAC
hardware
pin. This flexibility is useful in applications
V
V
X
OUT
REF
where the user wishes to select which channels respond to
LDAC
the
pin.
DAC
REGISTER
LDAC
LDAC
The
register gives the user extra flexibility and control
LDAC
LDAC
pin (see Table 15). Setting the
over the hardware
bits (DB0 to DB7) to 0 for a DAC channel means that this
LDAC
INPUT
REGISTER
channel update is controlled by the hardware
pin.
SCL
SDA
INTERFACE
LOGIC
Figure 64. Simplified Diagram of Input Loading Circuitry for a Single DAC
LDAC
Table 15.
Overwrite Definition
Load LDAC Register
LDAC Bits (DB7 to DB0)
00000000
LDAC Pin
1 or 0
X1
LDAC Operation
Determined by the LDAC pin.
11111111
DAC channels update and override the LDAC pin. DAC channels see LDAC as 1.
1 X means don’t care.
1
LDAC
Table 16. Write Commands and
Pin Truth Table
Hardware LDAC Pin State
Command Description
Input Register Contents
Data update
Data update
DAC Register Contents
0001
Write to Input Register n
VLOGIC
GND2
VLOGIC
GND
No change (no update)
Data update
(dependent on LDAC)
0010
Update DAC Register n
with contents of Input
Register n
No change
Updated with input register contents
Updated with input register contents
No change
0011
Write to and update DAC VLOGIC
Channel n
Data update
Data update
Data update
Data update
GND
1
LDAC
A high to low hardware
pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that
LDAC
are not masked (blocked) by the mask register.
is permanently tied low, the LDAC mask bits are ignored.
2
LDAC
When
Rev. B | Page 28 of 34
Data Sheet
AD5672R/AD5676R
HARDWARE RESET (RESET)
SOLDER HEAT REFLOW
As with all IC reference voltage circuits, the reference value
experiences a shift induced by the soldering process. Analog
Devices, Inc. performs a reliability test called precondition to
mimic the effect of soldering a device to a board. The output
voltage specification quoted previously includes the effect of
this reliability test.
RESET
The
be cleared to either zero scale or midscale. The clear code value
RESET
pin is an active low reset that allows the outputs to
is user selectable via the
select pin. It is necessary to
pin low for a minimum time (see Table 5) to
RESET
RESET
keep the
complete the operation. When the
high, the output remains at the cleared value until a new value is
RESET
signal is returned
Figure 65 shows the effect of solder heat reflow (SHR) as
measured through the reliability test (precondition).
programmed. While the
pin is low, the outputs cannot
be updated with a new value. A software executable reset function
is also available, which resets the DAC to the power-on reset code.
Command 0110 is designated for this software reset function (see
Table 10). Any events on the
on reset are ignored.
35
POSTSOLDER
HEAT REFLOW
30
LDAC RESET
or
pins during power-
PRESOLDER
HEAT REFLOW
25
20
15
10
5
RESET SELECT PIN (RSTSEL)
The AD5672R/AD5676R contain a power-on reset circuit that
controls the output voltage during power-up. By connecting the
RSTSEL pin low, the output powers up to zero scale. Note that
this is outside the linear region of the DAC; by connecting the
RSTSEL pin high, VOUTx power up to midscale. The output
remains powered up at this level until a valid write sequence is
made to the DAC. The RSTSEL pin is only available on the
TSSOP. When the AD5672R/AD5676R LFCSP is used, the
outputs power up to 0 V
0
2.497
2.498
2.499
2.500
(V)
2.501
2.502
V
REF
Figure 65. Solder Heat Reflow Reference Voltage Shift
AMPLIFIER GAIN SELECTION ON LFCSP
LONG-TERM TEMPERATURE DRIFT
The output amplifier gain setting for the LFCSP is determined
by the state of the DB2 bit in the internal reference and gain
setup register (see Table 17 and Table 18).
Figure 66 shows the change in VREF value after 1000 hours in the
life test at 150°C.
70
0
HOURS
168 HOURS
500 HOURS
1000 HOURS
INTERNAL REFERENCE SETUP
60
50
40
30
20
10
0
The on-chip reference is on at power-up by default. To reduce
the supply current, turn off this reference by setting the software
programmable bit, DB0, in the control register. Table 17 shows
how the state of the bit corresponds to the mode of operation.
Command 0111 is reserved for setting up the internal reference
and the gain setting on the LFCSP (see Table 10).
Table 17. Internal Reference and Gain Setup Register
Bit
Description
DB2
Amplifier gain setting
2.498
2.499
2.500
(V)
2.501
2.502
DB2 = 0: amplifier gain = 1 (default)
DB2 = 1: amplifier gain = 2
Reference enable
V
REF
Figure 66. Reference Drift Through to 1000 Hours
DB0
DB0 = 0: internal reference enabled (default)
DB0 = 1: internal reference disabled
Table 18. 24-Bit Input Shift Register Contents for Internal Reference and Gain Setup Command
DB23 (MSB)
DB22
DB21
DB20
DB19 to DB3
DB2
DB1
DB0 (LSB)
Reference enable
0
1
1
1
Don’t care
Gain
Reserved. Set to 0
Rev. B | Page 29 of 34
Data Sheet
AD5672R/AD5676R
3
2
1
0
THERMAL HYSTERESIS
FIRST TEMPERATURE SWEEP
SUBSEQUENT TEMPERATURE SWEEPS
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient to
cold, to hot, and then back to ambient.
Figure 67 shows thermal hysteresis data. It is measured by
sweeping the temperature from ambient to −40°C, then to
+125°C, and returning to ambient. The VREF delta, shown in
blue in Figure 67, is then measured between the two ambient
measurements. The same temperature sweep and measurements
were immediately repeated and the results are shown in red in
Figure 67.
–130 –110 –90 –70 –50 –30 –10
10
30
50
70
DISTORTION (ppm)
Figure 67. Thermal Hysteresis
Rev. B | Page 30 of 34
Data Sheet
AD5672R/AD5676R
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS
The following supplies typically power the AD5672R/AD5676R:
AD5672R/AD5676R TO SPORT INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 70 shows how a SPORT interface is used to control the
AD5672R/AD5676R.
VDD = 3.3 V and VLOGIC = 1.8 V.
The ADP7118 can be used to power the VDD pin. The ADP160
can be used to power the VLOGIC pin. Figure 68 shows this setup.
The ADP7118 can operate from input voltages up to 20 V. The
ADP160 can operate from input voltages up to 5.5 V.
AD5672R/
AD5676R
ADSP-BF531
5V
INPUT
ADP7118
LDO
3.3V: V
DD
SPORT_TFS
SPORT_TSCK
SPORT_DTO
SYNC
SCLK
SDI
ADP160
LDO
1.8V: V
LOGIC
GPIO0
GPIO1
LDAC
Figure 68. Low Noise Power Solution for the AD5672R/AD5676R
RESET
MICROPROCESSOR INTERFACING
Figure 70. SPORT Interface
Microprocessor interfacing to the AD5672R/AD5676R is
performed via a serial bus that uses a standard protocol
compatible with DSP processors and microcontrollers. The
communications channel requires a 3-wire or 4-wire interface
consisting of a clock signal, a data signal, and a synchronization
signal. The devices require a 24-bit data-word with data valid
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. Design the printed circuit board (PCB) on
which the AD5672R/AD5676R are mounted so that the devices
lie on the analog plane.
SYNC
on the rising edge of
.
The AD5672R/AD5676R must have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply, located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are tantalum bead type. The 0.1 µF capacitors
must have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types,
which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
AD5672R/AD5676R TO ADSP-BF531 INTERFACE
The SPI interface of the AD5672R/AD5676R can easily
connected to industry-standard DSPs and microcontrollers.
Figure 69 shows the AD5672R/AD5676R connected to the
Analog Devices Blackfin® DSP. The Blackfin has an integrated
SPI port that can connect directly to the SPI pins of the
AD5672R/AD5676R.
AD5672R/
AD5676R
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
ADSP-BF531
SPISELx
SCK
SYNC
SCLK
SDI
The GND plane on the device can be increased (as shown in
Figure 71) to provide a natural heat sinking effect.
MOSI
PF9
PF8
LDAC
AD5672R/
AD5676R
RESET
Figure 69. ADSP-BF531 Interface
GND
PLANE
BOARD
Figure 71. Pad Connection to the Board
Rev. B | Page 31 of 34
AD5672R/AD5676R
Data Sheet
GALVANICALLY ISOLATED INTERFACE
ADuM14001
CONTROLLER
V
V
V
V
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. iCoupler®
products from Analog Devices provide voltage isolation in excess
of 2.5 kV. The serial loading structure of the AD5672R/AD5676R
makes the devices ideal for isolated interfaces because the number
of interface lines is kept to a minimum. Figure 72 shows a
4-channel isolated interface to the AD5672R/AD5676R using
an ADuM1400. For further information, visit
TO
SERIAL
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
SCLK
CLOCK IN
TO
SDI
SERIAL
DATA OUT
DECODE
DECODE
DECODE
TO
SYNC
SYNC
LOAD DAC
OUT
TO
LDAC
www.analog.com/icoupler.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 72. Isolated Interface
Rev. B | Page 32 of 34
Data Sheet
AD5672R/AD5676R
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 73. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
16
15
20
0.50
BSC
1
EXPOSED
PAD
2.75
2.60 SQ
2.35
11
5
6
BOTTOM VIEW
10
0.50
0.40
0.30
0.25 MIN
TOP VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 74. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 × 4 mm Body, Very Very Thin Quad
(CP-20-8)
Dimensions shown in millimeters
Rev. B | Page 33 of 34
AD5672R/AD5676R
Data Sheet
ORDERING GUIDE
Typical
Resolution
(Bits)
12
Temperature
Range
Accuracy
(LSB INL)
Reference Temperature
Coefficient (ppm/°C)
Package
Description
Package
Option
Model1
AD5672RBRUZ
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
1
1
1
1
8
8
8
8
3
3
3
3
2
2
2
2
5
5
5
5
2
2
2
2
20-Lead TSSOP
20-Lead TSSOP
20-Lead LFCSP_WQ
20-Lead LFCSP_WQ
20-Lead TSSOP
RU-20
RU-20
CP-20-8
CP-20-8
RU-20
AD5672RBRUZ-REEL7 12
AD5672RBCPZ-REEL7 12
AD5672RBCPZ-RL
AD5676RARUZ
12
16
AD5676RARUZ REEL7 16
AD5676RACPZ-REEL7 16
20-Lead TSSOP
RU-20
20-Lead LFCSP_WQ
20-Lead LFCSP_WQ
20-Lead TSSOP
CP-20-8
CP-20-8
RU-20
RU-20
CP-20-8
CP-20-8
AD5676RACPZ-RL
AD5676RBRUZ
16
16
AD5676RBRUZ-REEL7 16
AD5676RBCPZ-REEL7 16
20-Lead TSSOP
20-Lead LFCSP_WQ
20-Lead LFCSP_WQ
Evaluation Board
AD5676RBCPZ-RL
EVAL-AD5676RSDZ
16
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11954-0-11/15(B)
Rev. B | Page 34 of 34
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