AD5684BRUZ [ADI]
Quad, 12-Bit nanoDAC+ with SPI Interface;
| 型号： | AD5684BRUZ |
| 厂家： | 
ADI |
| 描述： | Quad, 12-Bit nanoDAC+ with SPI Interface 光电二极管 转换器 |
| 文件： | 总27页 (文件大小：753K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, 16-/12-Bit nanoDAC+
with SPI Interface
Data Sheet
AD5686/AD5684
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
GND
V
REF
DD
High relative accuracy (INL): 2 LSB maximum @ 16 bits
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): 0.1% of FSR maximum
Offset error: 1.5 mV maximum
Gain error: 0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
AD5686/AD5684
V
LOGIC
STRING
DAC A
INPUT
REGISTER
DAC
V
V
V
V
A
B
C
D
OUT
OUT
OUT
OUT
REGISTER
SCLK
SYNC
SDIN
SDO
BUFFER
BUFFER
BUFFER
BUFFER
STRING
DAC B
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
INPUT
REGISTER
DAC
REGISTER
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
STRING
DAC D
INPUT
REGISTER
DAC
REGISTER
POWER-ON
RESET
GAIN
×1/×2
POWER-
DOWN
LOGIC
Low power: 1.8 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
LDAC RESET
RSTSEL
GAIN
Figure 1.
APPLICATIONS
Digital gain and offset adjustment
Programmable attenuators
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5686/AD5684, members of the nanoDAC+™ family, are
low power, quad, 16-/12-bit buffered voltage output DACs.
The devices include a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from
a single 2.7 V to 5.5 V supply, are guaranteed monotonic by
design, and exhibit less than 0.1% FSR gain error and 1.5 mV
offset error performance. The devices are available in a 3 mm
× 3 mm LFCSP and a TSSOP package.
Table 1. Quad nanoDAC+ Devices
Interface Reference 16-Bit
14-Bit
12-Bit
SPI
SPI
I2C
I2C
Internal
External
Internal
External
AD5686R
AD5686
AD5696R
AD5696
AD5685R AD5684R
AD5684
AD5695R AD5694R
AD5694
PRODUCT HIGHLIGHTS
The AD5686/AD5684 also incorporate a power-on reset circuit
and a RSTSEL pin that ensures that the DAC outputs power up
to zero scale or midscale and remain at that level until a valid
write takes place. Each part contains a per-channel power-down
feature that reduces the current consumption of the device to
4 µA at 3 V while in power-down mode.
1. High Relative Accuracy (INL).
AD5686 (16-bit): 2 LSB maximum
AD5684 (12-bit): 1 LSB maximum
2. Excellent DC Performance.
Total unadjusted error: 0.1% of FSR maximum
Offset error: 1.5 mV maximum
The AD5686/AD5684 employ a versatile SPI interface that
operates at clock rates up to 50 MHz, and all devices contain
a VLOGIC pin intended for 1.8 V/3 V/5 V logic.
Gain error: 0.1% of FSR maximum
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. C
Document Feedback
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5686/AD5684
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface ............................................................................ 19
Standalone Operation................................................................ 20
Write and Update Commands.................................................. 20
Daisy-Chain Operation ............................................................. 20
Readback Operation .................................................................. 21
Power-Down Operation ............................................................ 21
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Daisy-Chain and Readback Timing Characteristics................ 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 18
Digital-to-Analog Converter .................................................... 18
Transfer Function ....................................................................... 18
DAC Architecture....................................................................... 18
LDAC
Load DAC (Hardware
Pin)........................................... 22
Mask Register ................................................................. 22
Hardware Reset ( ) .......................................................... 23
LDAC
RESET
Reset Select Pin (RSTSEL) ........................................................ 23
Applications Information .............................................................. 24
Microprocessor Interfacing....................................................... 24
AD5686/AD5684 to ADSP-BF531 Interface .......................... 24
AD5686/AD5684 to SPORT Interface .................................... 24
Layout Guidelines....................................................................... 24
Galvanically Isolated Interface ................................................. 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 27
REVISION HISTORY
6/2017—Rev. B to Rev. C
3/2015—Rev. A to Rev. B
Changes to Features Section 1 ........................................................ 1
Changes to Table 2............................................................................ 3
Changes to Table 3............................................................................ 5
Changes to Table 4............................................................................ 6
Changes to Table 5 and Figure 4..................................................... 7
Changes to Figure 5.......................................................................... 8
Changes to Table 6............................................................................ 9
Changes to Table 4 and Figure 2......................................................6
Inserted Note 2 to Ordering Guide.............................................. 27
6/2013—Rev. 0 to Rev. A
Changes to Pin GAIN and Pin RSTSEL Descriptions; Table 7.. 10
7/2012—Revision 0: Initial Version
RESET
Change to VLOGIC Pin Description and
Pin Description,
Table 7 ................................................................................................ 9
Changes to Figure 12 and Figure 13............................................. 11
Changes to Figure 14 to Figure 19................................................ 12
Changes to Figure 20, Figure 22, and Figure 25 ......................... 13
Changes to Figure 32...................................................................... 15
Changes to Table 8.......................................................................... 19
Changes to Readback Operation Section.................................... 21
RESET
Changes to Hardware Reset (
) Section............................ 23
Changes to Ordering Guide .......................................................... 27
Rev. C | Page 2 of 27
Data Sheet
AD5686/AD5684
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2.
A Grade1
Typ
B Grade1
Typ
Parameter
Min
Max
Min
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE2
AD5686
Resolution
Relative Accuracy
16
16
Bits
LSB
LSB
LSB
2
2
8
8
1
1
1
2
3
1
Gain = 2
Gain = 1
Differential Nonlinearity
AD5684
Guaranteed monotonic by design
Resolution
12
12
Bits
LSB
LSB
mV
mV
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
0.12
2
1
0.12
1
1
1.5
1.5
0.1
Guaranteed monotonic by design
All 0s loaded to DAC register
0.4
+0.1
+0.01
4
0.4
+0.1
+0.01
4
0.2
Full-Scale Error
% of
FSR
All 1s loaded to DAC register
Gain Error
0.02
0.01
0.2
0.02
0.01
0.1
0.1
0.2
% of
FSR
% of
FSR
% of
FSR
Total Unadjusted Error
0.25
0.25
Gain = 2
Gain = 1
Offset Error Drift3
Gain Temperature
Coefficient3
1
1
1
1
µV/°C
ppm
Of FSR/°C
DC Power Supply Rejection
Ratio3
DC Crosstalk3
0.15
2
0.15
2
mV/V
µV
DAC code = midscale; VDD = 5 V 10%
Due to single channel, full-scale
output change
3
2
3
2
µV/mA Due to load current change
µV
Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
0
VREF
2 × VREF
0
0
VREF
2 × VREF
V
Gain = 1
V
Gain = 2, see Figure 23
RL = ∞
RL = 1 kΩ
Capacitive Load Stability
2
2
nF
nF
kΩ
10
10
Resistive Load4
Load Regulation
1
1
80
80
80
80
µV/mA 5 V 10%, DAC code = midscale;
−30 mA ≤ IOUT ≤ +30 mA
µV/mA 3 V 10%, DAC code = midscale;
−20 mA ≤ IOUT ≤ +20 mA
Short-Circuit Current5
Load Impedance at Rails6
Power-Up Time
40
25
2.5
40
25
2.5
mA
Ω
µs
See Figure 23
Coming out of power-down mode;
VDD = 5 V
REFERENCE INPUT
Reference Current
90
180
90
180
µA
µA
V
V
kΩ
kΩ
VREF = VDD = VLOGIC = 5.5 V, gain = 1
VREF = VDD = VLOGIC = 5.5 V, gain = 2
Gain = 1
Gain = 2
Gain = 2
Gain = 1
Reference Input Range
1
1
VDD
VDD/2
1
1
VDD
VDD/2
Reference Input Impedance
16
32
16
32
Rev. C | Page 3 of 27
AD5686/AD5684
Data Sheet
A Grade1
Typ
B Grade1
Typ
Parameter
LOGIC INPUTS3
Min
Max
Min
Max
Unit
Test Conditions/Comments
Input Current
Input Low Voltage (VINL
2
2
µA
V
Per pin
)
0.3 × VLOGIC
0.3 × VLOGIC
Input High Voltage (VINH
)
0.7 × VLOGIC
0.7 × VLOGIC
V
Pin Capacitance
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
Floating State Output
Capacitance
2
4
2
4
pF
0.4
0.4
V
V
pF
ISINK = 200 μA
ISOURCE = 200 μA
VLOGIC − 0.4
VLOGIC − 0.4
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
1.62
5.5
3
5.5
5.5
1.62
5.5
3
5.5
5.5
V
µA
V
2.7
VREF + 1.5
2.7
VREF + 1.5
Gain = 1
Gain = 2
V
IDD
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Normal Mode7
All Power-Down Modes8
0.59
1
0.7
4
6
0.59
1
0.7
4
6
mA
µA
µA
−40°C to +85°C
−40°C to +105°C
1 Temperature range, A and B grade: −40°C to +105°C.
2 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5686) or 12 to 4080 (AD5684).
3 Guaranteed by design and characterization; not production tested.
4 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to
30 mA up to a junction temperature of 110°C.
5 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 23).
7 Interface inactive. All DACs active. DAC outputs unloaded.
8 All DACs powered down.
Rev. C | Page 4 of 27
Data Sheet
AD5686/AD5684
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless
otherwise noted.1
Table 3.
Parameter2
Min
Typ
Max
Unit
Test Conditions/Comments3
Output Voltage Settling Time
AD5686
AD5684
5
5
8
7
µs
µs
¼ to ¾ scale settling to 2 LSB
¼ to ¾ scale settling to 2 LSB
Slew Rate
0.8
0.5
0.13
500
0.1
0.2
0.3
−80
100
V/µs
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Multiplying Bandwidth
Digital Crosstalk
nV-sec
nV-sec
kHz
nV-sec
nV-sec
nV-sec
dB
1 LSB change around major carry
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion4
Output Noise Spectral Density
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz; gain = 2, internal reference
enabled
nV/√Hz
Output Noise
SNR
SFDR
6
µV p-p
dB
dB
0.1 Hz to 10 Hz
90
83
80
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
SINAD
dB
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C, typical @ 25°C.
4 Digitally generated sine wave @ 1 kHz.
Rev. C | Page 5 of 27
AD5686/AD5684
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
DD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
V
Table 4.
1.62 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter1
Symbol
Min
20
10
10
15
5
Max
Min
20
10
10
10
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
t1
t2
t3
t4
t5
Data Hold Time
t6
t7
5
5
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SYNC Rising Edge to SYNC Rising Edge (DAC Register Update/s)
SYNC Falling Edge to SCLK Fall Ignore
LDAC Pulse Width Low
10
20
870
16
15
20
30
840
30
30
4.5
10
20
830
10
15
20
30
800
30
30
4.5
t8
t9
t10
t11
t12
t13
t14
t15
t16
SYNC Rising Edge to LDAC Rising Edge
SYNC Rising Edge to LDAC Falling Edge
LDAC Falling Edge to SYNC Rising Edge
Minimum Pulse Width Low
Pulse Activation Time
Power-Up Time2
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
2
SYNC
Time to exit power-down to normal mode of AD5686/AD5684 operation,
rising edge to 90% of DAC midscale value, with output unloaded.
t10
t1
SCLK
SYNC
t2
t8
t7
t3
t14
t4
t9
t6
t5
SDIN
DB23
DB0
t11
t13
1
LDAC
t12
2
LDAC
t15
RESET
t16
V
OUT
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. C | Page 6 of 27
Data Sheet
AD5686/AD5684
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 5.
1.62 V ≤ VLOGIC < 2.7 V
Max
2.7 V ≤ VLOGIC ≤ 5.5 V
Max
Parameter1
Symbol
Min
66
33
33
33
5
5
15
60
Min
40
20
20
20
5
5
10
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SDO Data Valid from SCLK Rising Edge
SYNC Rising Edge to SCLK Falling Edge
SYNC Rising Edge to SDO Disable
45
30
15
60
10
60
1 Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
200µA
I
OL
TO OUTPUT
PIN
V
(MIN)
OH
C
L
20pF
200µA
I
OH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
t1
SCLK
24
48
t7
t2
t8
t3
t10
t4
SYNC
SDIN
t6
t5
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
t9
DB23
DB0
SDO
UNDEFINED
Figure 4. Daisy-Chain Timing Diagram
Rev. C | Page 7 of 27
AD5686/AD5684
Data Sheet
t1
SCLK
24
24
1
1
t3
t8
t7
t4
t2
t10
t8
SYNC
t6
t5
DB23
DB0
DB23
DB0
SDIN
SDO
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
t9
t11
DB23
DB0
HI-Z
SELECTED REGISTER DATA
CLOCKED OUT
Figure 5. Readback Timing Diagram
Rev. C | Page 8 of 27
Data Sheet
AD5686/AD5684
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 6.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
VLOGIC to GND
−0.3 V to +7 V
VOUT to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +105°C
−65°C to +150°C
125°C
ESD CAUTION
16-Lead TSSOP, θJA Thermal
112.6°C/W
Impedance, 0 Airflow (4-Layer Board)
16-Lead LFCSP, θJA Thermal
Impedance, 0 Airflow (4-Layer Board)
Reflow Soldering Peak
70°C/W
260°C
Temperature, Pb Free (J-STD-020)
Rev. C | Page 9 of 27
AD5686/AD5684
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5686/AD5684
V
V
A 1
12 SDIN
11 SYNC
10 SCLK
OUT
GND 2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
RSTSEL
RESET
SDIN
REF
V
3
DD
V
V
B
A
OUT
9
V
LOGIC
C 4
AD5686/
AD5684
OUT
OUT
GND
SYNC
SCLK
TOP VIEW
(Not to Scale)
V
DD
V
V
C
D
V
LOGIC
OUT
OUT
TOP VIEW
(Not to Scale)
GAIN
LDAC
SDO
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
Figure 6. 16-Lead LFCSP Pin Configuration
Figure 7. 16-Lead TSSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic Description
1
2
3
3
4
5
VOUT
GND
VDD
A
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4
5
6
6
7
8
VOUT
VOUT
SDO
C
D
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Serial Data Output. Can be used to daisy-chain a number of AD5686/AD5684 devices together or
can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid on
the falling edge of the clock.
7
8
9
LDAC
GAIN
LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows
any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs
to be simultaneously updated. This pin can also be tied permanently low.
10
Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to VREF. When
this pin is tied to VLOGIC, all four DAC outputs have a span from 0 V to 2 × VREF
.
9
10
11
12
VLOGIC
SCLK
Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
11
12
13
13
14
15
SYNC
SDIN
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, data is transferred in on the falling edges of the next 24 clocks.
Serial Data Input. These devices have a 24-bit input shift register. Data is clocked into the register on
the falling edge of the serial clock input.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC
pulses are ignored. When RESET is activated, the input register and the DAC register are updated with
zero scale or midscale, depending on the state of the RSTSEL pin. If the pin is forced low at power-up,
the POR circuit does not initialize correctly until the pin is released.
RESET
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to
VLOGIC powers up all four DACs to midscale.
Reference Input Voltage.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
14
16
RSTSEL
VREF
15
16
17
1
2
N/A
VOUT
B
EPAD
Rev. C | Page 10 of 27
Data Sheet
AD5686/AD5684
TYPICAL PERFORMANCE CHARACTERISTICS
10
1.0
0.8
8
6
0.6
0.4
4
0.2
2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
V
T
= 5V
= 25°C
V
T
= 5V
= 25°C
DD
DD
–8
A
A
REFERENCE = 2.5V
REFERENCE = 2.5V
–10
0
625
1250
1875
CODE
2500
3125
3750 4096
0
10000
20000
30000
CODE
40000
50000
60000
Figure 11. AD5684 DNL
Figure 8. AD5686 INL
10
8
10
8
6
6
4
4
2
2
INL
0
0
DNL
–2
–4
–6
–8
–10
–2
–4
–6
–8
–10
V
= 5V
= 25°C
DD
V
= 5V
DD
T
A
REFERENCE = 2.5V
REFERENCE = 2.5V
–40 10
60
110
0
625
1250
1875
CODE
2500
3125
3750 4096
TEMPERATURE (°C)
Figure 12. INL Error and DNL Error vs. Temperature
Figure 9. AD5684 INL
10
8
1.0
0.8
6
0.6
4
0.4
2
0.2
INL
0
0
DNL
–2
–4
–6
–8
–10
–0.2
–0.4
–0.6
–0.8
–1.0
V
T
= 5V
= 25°C
DD
A
V
= 5V
= 25°C
DD
T
A
REFERENCE = 2.5V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
10000 20000
30000
CODE
40000
50000
60000
V
(V)
REF
Figure 13. INL Error and DNL Error vs. VREF
Figure 10. AD5686 DNL
Rev. C | Page 11 of 27
AD5686/AD5684
Data Sheet
0.10
0.08
0.06
0.04
0.02
0
10
8
6
4
2
GAIN ERROR
INL
0
DNL
FULL-SCALE ERROR
–2
–4
–6
–0.02
–0.04
–0.06
–0.08
–0.10
T
= 25°C
–8
T
= 25°C
A
A
REFERENCE = 2.5V
REFERENCE = 2.5V
–10
2.7
3.2
3.7
4.2
4.7
5.2
2.7 3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 14. INL Error and DNL Error vs. Supply Voltage
Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage
0.10
0.08
0.06
0.04
0.02
0
1.5
1.0
0.5
ZERO-CODE ERROR
FULL-SCALE ERROR
GAIN ERROR
0
OFFSET ERROR
–0.02
–0.04
–0.06
–0.08
–0.10
–0.5
–1.0
–1.5
T = 25°C
A
REFERENCE = 2.5V
V
= 5V
DD
REFERENCE = 2.5V
–40 –20
0
20
40
60
80
100
120
2.7 3.2
3.7
4.2
4.7
5.2
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 15. Gain Error and Full-Scale Error vs. Temperature
Figure 18. Zero-Code Error and Offset Error vs. Supply Voltage
0.10
V
= 5V
DD
V
= 5V
DD
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
REFERENCE = 2.5V
REFERENCE = 2.5V
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
ZERO-CODE ERROR
OFFSET ERROR
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Zero-Code Error and Offset Error vs. Temperature
Figure 19. TUE vs. Temperature
Rev. C | Page 12 of 27
Data Sheet
AD5686/AD5684
1.0
0.8
0.10
0.08
0.06
0.04
0.02
0
0.6
0.4
SINKING 2.7V
0.2
SINKING 5V
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.02
–0.04
–0.06
SOURCING 5V
SOURCING 2.7V
15
V
= 5V
= 25°C
DD
–0.08
–0.10
T
A
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7
SUPPLY VOLTAGE (V)
0
5
10
20
25
30
4.2
4.7
5.2
LOAD CURRENT (mA)
Figure 23. Headroom/Footroom vs. Load Current
Figure 20. TUE vs. Supply Voltage, Gain = 1
7
6
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.10
V
= 5V
= 25°C
DD
T
A
GAIN = 2
REFERENCE = 2.5V
0xFFFF
5
4
0xC000
0x8000
0x4000
0x0000
3
2
1
0
V
= 5V
= 25°C
DD
–1
T
A
REFERENCE = 2.5V
–2
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0
10000 20000
30000
CODE
40000
50000
60000 65535
LOAD CURRENT (A)
Figure 24. Source and Sink Capability at 5 V
Figure 21. TUE vs. Code
5
V
T
= 5V
= 25°C
V
= 3V
= 25°C
DD
DD
25
T
A
A
EXTERNAL
REFERENCE = 2.5V
GAIN = 1
EXTERNAL
REFERENCE = 2.5V
4
3
0xFFFF
0xC000
20
15
10
5
2
0x8000
0x4000
1
0x0000
0
–1
0
–2
–0.06
540
560
580
600
620
640
–0.04
–0.02
0
0.02
0.04
0.06
I
(µA)
LOAD CURRENT (A)
DD
Figure 25. Source and Sink Capability at 3 V
Figure 22. IDD Histogram
Rev. C | Page 13 of 27
AD5686/AD5684
Data Sheet
3
2
1
0
CH A
CH B
CH C
CH D
SYNC
1.4
1.2
1.0
0.8
GAIN = 2
GAIN = 1
FULL-SCALE
0.6
0.4
0.2
0
V
= 5V
= 25°C
REFERENCE = 2.5V
DD
T
A
–5
0
5 10
–40
10
60
110
TIME (µs)
TEMPERATURE (°C)
Figure 29. Exiting Power-Down to Midscale
Figure 26. Supply Current vs. Temperature
2.5008
2.5003
2.4998
2.4993
2.4988
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
DAC A
DAC B
DAC C
DAC D
CHANNEL B
T
= 25°C
A
V
= 5.25V
V
T
= 5V
= 25°C
REFERENCE = 2.5V
¼ TO ¾ SCALE
DD
DD
REFERENCE = 2.5V
CODE = 7FFF TO 8000
ENERGY = 0.227206nV-sec
A
0
2
4
6
8
10
12
10
20
40
80
160
320
TIME (µs)
TIME (µs)
Figure 30. Digital-to-Analog Glitch Impulse
Figure 27. Settling Time, 5 V
0.003
0.002
0.001
0
0.06
6
CH A
CH B
CH C
CH D
CH B
CH C
CH D
0.05
0.04
0.03
0.02
0.01
0
5
V
DD
4
3
2
1
–0.001
–0.002
0
T
= 25°C
REFERENCE = 2.5V
A
–0.01
–1
15
0
5
10
15
20
25
–10
–5
0
5
10
TIME (µs)
TIME (µs)
Figure 31. Analog Crosstalk, Channel A
Figure 28. Power-On Reset to 0 V
Rev. C | Page 14 of 27
Data Sheet
AD5686/AD5684
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
0nF
V
= 5V
= 25°C
DD
0.1nF
10nF
0.22nF
4.7nF
T
A
T
REFERENCE = 2.5V
1
V
= 5V
= 25°C
DD
T
A
EXTERNAL REFERENCE = 2.5V
1.590 1.595 1.600 1.605 1.610 1.615 1.620 1.625 1.630
TIME (ms)
CH1 10µV M1.0s
A
CH1
802mV
Figure 34. Settling Time vs. Capacitive Load
Figure 32. 0.1 Hz to 10 Hz Output Noise Plot
0
20
0
V
= 5V
= 25°C
DD
T
A
REFERENCE = 2.5V
–10
–20
–40
–20
–30
–40
–50
–60
–60
–80
–100
–120
–140
–160
–180
V
= 5V
DD
T
= 25°C
A
REFERENCE = 2.5V, ±0.1V p-p
10k 100k
FREQUENCY (Hz)
1M
10M
0
2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
FREQUENCY (Hz)
Figure 35. Multiplying Bandwidth, Reference = 2.5 V, 0.1 V p-p,
10 kHz to 10 MHz
Figure 33. Total Harmonic Distortion @ 1 kHz
Rev. C | Page 15 of 27
AD5686/AD5684
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 8.
Output Voltage Settling Time
The output voltage setting time is the amount of time it takes
for the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change and is measured from the rising edge
SYNC
of
.
Differential Nonlinearity (DNL)
Digital-to-Analog Glitch Impulse
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. These DACs are guaranteed monotonic
by design. A typical DNL vs. code plot can be seen in Figure 10.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 30).
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5686/AD5684 because the output of the DAC cannot go
below 0 V due to a combination of the offset errors in the DAC
and the output amplifier. Zero-code error is expressed in mV. A
plot of zero-code error vs. temperature can be seen in Figure 16.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Noise Spectral Density
Full-Scale Error
Noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nV/√Hz). It is measured by loading the DAC
to midscale and measuring noise at the output. It is measured in
nV/√Hz.
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in
percent of full-scale range (% of FSR). A plot of full-scale error
vs. temperature can be seen in Figure 15.
DC Crosstalk
Gain Error
DC crosstalk is the dc change in the output level of one DAC
in response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC
kept at midscale. It is expressed in μV.
Gain error is a measurement of the span error of the DAC. It is
the deviation in slope of the DAC transfer characteristic from
the ideal expressed as % of FSR.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
DC crosstalk due to load current change is a measurement of
the impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-sec.
Offset Error
Offset error is a measurement of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV in the linear region of
the transfer function. It can be negative or positive.
DC Power Supply Rejection Ratio (PSRR)
DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
V
OUT to a change in VDD for full-scale output of the DAC. It is
measured in mV/V. VREF is held at 2.5 V, and VDD is varied by
10%.
Rev. C | Page 16 of 27
Data Sheet
AD5686/AD5684
Analog Crosstalk
Multiplying Bandwidth
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa). Then execute a
software LDAC and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-sec.
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to
the output of one DAC in response to a digital code change
and subsequent analog output change of another DAC. It is
measured by loading the attack channel with a full-scale code
change (all 0s to all 1s and vice versa) using the write to and
update commands while monitoring the output of another
channel that is at midscale. The energy of the glitch is
expressed in nV-sec.
Rev. C | Page 17 of 27
AD5686/AD5684
Data Sheet
THEORY OF OPERATION
The resistor string structure is shown in Figure 37. It is a string
of resistors, each of Value R. The code loaded to the DAC register
determines the node on the string where the voltage is to be
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because the DAC is a string of resistors,
it is guaranteed monotonic.
DIGITAL-TO-ANALOG CONVERTER
The AD5686/AD5684 are quad, 16-/12-bit, serial input, voltage
output DACs. The parts operate from supply voltages of 2.7 V to
5.5 V. Data is written to the AD5686/AD5684 in a 24-bit word
format via a 3-wire serial interface. The AD5686/AD5684
incorporate a power-on reset circuit to ensure that the DAC
output powers up to a known output state. The devices also
have a software power-down mode that reduces the typical
current consumption to typically 4 µA.
V
REF
R
TRANSFER FUNCTION
R
R
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
TO OUTPUT
AMPLIFIER
D
VOUT =VREF ×Gain
N
2
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register as follows:
R
R
0 to 4095 for the 12-bit device.
0 to 65,535 for the 16-bit device.
N is the DAC resolution.
VREF is the value of the external reference.
Gain is the gain of the output amplifier and is set to 1 by default.
The gain can be set to ×1 or ×2 using the gain select pin. When
this pin is tied to GND, all four DAC outputs have a span of 0 V
to VREF. When this pin is tied to VDD, all four DAC outputs have
Figure 37. Resistor String Structure
Output Amplifiers
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the GAIN pin, offset error,
and gain error. The GAIN pin selects the gain of the output.
a span of 0 V to 2 × VREF
.
DAC ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 36 shows a block diagram of the DAC
architecture.
•
If this pin is tied to GND, all four outputs have a gain of 1,
and the output range is 0 V to VREF
If this pin is tied to VDD, all four outputs have a gain of 2,
and the output range is 0 V to 2 × VREF
.
V
•
REF
.
These amplifiers are capable of driving a load of 1 kΩ in parallel
with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale
settling time of 5 µs.
REF (+)
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
X
OUT
REF (–)
GAIN
(GAIN = 1 OR 2)
GND
Figure 36. Single DAC Channel Architecture Block Diagram
Rev. C | Page 18 of 27
Data Sheet
AD5686/AD5684
Table 8. Command Bit Definitions
SERIAL INTERFACE
Command Bits
SYNC
The AD5686/AD5684 have a 3-wire serial interface (
SCLK, and SDIN) that is compatible with SPI, QSPI™, and
MICROWIRE® interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence. The
AD5686/AD5684 contain an SDO pin to allow the user to daisy-
chain multiple devices together (see the Daisy-Chain Operation
section) or for readback.
,
C3
0
0
C2 C1 C0 Description
0
0
0
0
0
1
0
1
0
No operation
LDAC
)
Write to Input Register n (dependent on
0
Update DAC Register n with contents of Input
Register n
0
0
0
0
0
1
1
1
…
1
0
1
1
1
1
0
0
0
…
1
1
0
0
1
1
0
0
1
…
1
1
0
1
0
1
0
1
0
…
1
Write to and update DAC Channel n
Power down/power up DAC
LDAC
Hardware
mask register
Input Shift Register
Software reset (power-on reset)
Reserved
Set up DCEN register (daisy-chain enable)
Set up readback register (readback enable)
Reserved
The input shift register of the AD5686/AD5684 is 24 bits wide.
Data is loaded MSB first (DB23). The first four bits are the
command bits, C3 to C0 (see Table 8), followed by the 4-bit
DAC address bits, DAC A, DAC B, DAC C, andDAC D (see
Table 9), and finally the bit data-word.
Reserved
No operation, daisy-chain mode
For the AD5686, the data-word comprises 16-bit input code(see
Figure 38). For the AD5684, the data-word comprises 12-bit input
code, followed by zero or four don’t care bits (see Figure 39).
These data bits are transferred to the input register on the 24
falling edges of SCLK and are updated on the rising edge
SYNC
Table 9. Address Bits and Selected DACs
Address Bits
DAC D DAC C DAC B DAC A Selected DAC Channel1
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
1
1
0
0
0
1
1
DAC A
DAC B
DAC C
DAC D
DAC A and DAC B
All DACs
of
.
Commands can be executed on individual DAC channels,
combined DAC channels, or on all DACs, depending on the
address bits selected (see Table 9).
1 Any combination of DAC channels can be selected using the address bits.
DB23 (MSB)
DB0 (LSB)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
DAC DAC DAC DAC
C3 C2 C1 C0
D
C
B
A
COMMAND BITS
ADDRESS BITS
Figure 38. AD5686 Input Shift Register Contents
DB23 (MSB)
DB0 (LSB)
DAC DAC DAC DAC
C3 C2 C1 C0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
X
X
X
X
D
C
B
A
COMMAND BITS
ADDRESS BITS
Figure 39. AD5684 Input Shift Register Contents
Rev. C | Page 19 of 27
AD5686/AD5684
Data Sheet
STANDALONE OPERATION
AD5686/
AD5684
68HC11*
MOSI
SYNC
The write sequence begins by bringing the
from the SDIN line is clocked into the 24-bit input shift register
on the falling edge of SCLK. After the last of 24 data bits is
line low. Data
SDIN
SCK
PC7
PC6
SCLK
SYNC
LDAC
SYNC
clocked in,
function is then executed, that is, an
in DAC register contents and/or a change in the mode of
should be brought high. The programmed
LDAC
-dependent change
SDO
MISO
th
SYNC
operation. If
clock, it is considered a valid frame and invalid data may be
SYNC
is taken high at a clock before the 24
SDIN
loaded to the DAC.
of 20 ns (single channel, see t8 in Figure 2) before the next write
SYNC
must be brought high for a minimum
AD5686/
AD5684
SCLK
sequence so that a falling edge of
can initiate the next
should be idle at rails between write
sequences for even lower power operation of the part.
SYNC
SYNC
LDAC
SYNC
write sequence.
SDO
The
line is kept low for 24 falling edges of SCLK, and the
SYNC
DAC is updated on the rising edge of
.
After data is transferred into the input register of the addressed
DAC, all DAC registers and outputs can be updated by
SDIN
AD5686/
AD5684
LDAC
SYNC
taking
low while the
line is high.
SCLK
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on
SYNC
LDAC
)
LDAC
SDO
Command 0001 allows the user to write to each DAC’s
LDAC
dedicated input register individually. When
the input register is transparent (if not controlled by the
LDAC
is low,
*ADDITIONAL PINS OMITTED FOR CLARITY.
mask register).
Figure 40. Daisy-Chaining the AD5686/AD5684
Update DAC Register n with Contents of Input Register n
The SCLK pin is continuously applied to the input shift register
Command 0010 loads the DAC registers/outputs with the
contents of the selected input registers and updates the DAC
outputs directly.
SYNC
when
is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting the SDO line to
the SDIN input on the next DAC in the chain, a daisy-chain
interface is constructed. Each DAC in the system requires 24
clock pulses. Therefore, the total number of clock cycles must
equal 24 × N, where N is the total number of devices that are
is taken high at a clock that is not a multiple
of 24, it is considered a valid frame and invalid data may be
loaded to the DAC. When the serial transfer to all devices is
Write to and Update DAC Channel n (Independent
of
)
LDAC
Command 0011 allows the user to write to the DAC registers
and update the DAC outputs directly.
DAISY-CHAIN OPERATION
SYNC
updated. If
For systems that contain several DACs, the SDO pin can be
used to daisy-chain several devices together. This function
is enabled through a software executable daisy-chain enable
(DCEN) command. Command 1000 is reserved for this DCEN
function (see Table 8). The daisy-chain mode is enabled by
setting Bit DB0 in the DCEN register. The default setting is
standalone mode, where DB0 = 0. Table 10 shows how the state
of the bit corresponds to the mode of operation of the device.
SYNC
complete,
is taken high. This latches the input data in
each device in the daisy chain and prevents any further data
from being clocked into the input shift register. The serial clock
can be continuous or a gated clock. A continuous SCLK source
can be held low for the correct
number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used,
SYNC
can be used only if
Table 10. Daisy-Chain Enable (DCEN) Register
DB0
Description
SYNC
and
must be taken high after the final clock to latch the data.
0
1
Standalone mode (default)
DCEN mode
Rev. C | Page 20 of 27
Data Sheet
AD5686/AD5684
Table 11. Modes of Operation
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
READBACK OPERATION
PDx1
PDx0
Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisy-
chain mode disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
disabled again. Command 1001 is reserved for the readback
function. This command, in association with selecting one
of the address bits, DAC A to DAC D, selects the register to
read. Note that only one DAC register can be selected during
readback. The remaining three address bits must be set to
Logic 0. The remaining data bits in the write sequence are
don’t care bits. If more than one or no bits are selected, DAC
Channel A is read back by default. During the next SPI write,
the data appearing on the SDO output contains the data from
the previously addressed register.
0
0
0
1
1
1
0
1
100 kΩ to GND
Three-State
Any or all DACs (DAC A to DAC D) can be powered down
to the selected mode by setting the corresponding bits. See
Table 12 for the contents of the input shift register during the
power-down/power-up operation.
When both Bit PDx1 and Bit PDx0 (where x is the channel
selected) in the input shift register are set to 0, the parts work
normally with their normal power consumption of 0.59 mA at
5 V. However, for the three power-down modes, the supply
current falls to 4 μA at 5 V. Not only does the supply current
fall, but the output stage is also internally switched from the
output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. There are three
different power-down options (see Table 11). The output is
connected internally to GND through either a 1 kΩ or a 100 kΩ
resistor, or it is left open-circuited (three-state). The output stage
is illustrated in Figure 41.
For example, to read back the DAC register for Channel A, the
following sequence should be implemented:
1. Write 0x900000 to the AD5686/AD5684 input register.
This configures the part for read mode with the DAC
register of Channel A selected. Note that all data bits,
DB15 to DB0, are don’t care bits.
2. Follow this with a second write, a NOP condition,
0x000000 (0xF00000 in daisy-chain mode). During this
write, the data from the register is clocked out on the SDO
line. DB23 to DB20 contain undefined data, and the last
16 bits contain the DB19 to DB4 DAC register contents.
AMPLIFIER
V
X
DAC
OUT
POWER-DOWN OPERATION
The AD5686/AD5684 provide three separate power-down
modes (see Table 11). Command 0100 is designated for the power-
down function (see Table 8). These power-down modes are
software programmable by setting eight bits, Bit DB7 to Bit DB0,
in the input shift register. Two bits are associated with each DAC
channel. Table 11 shows how the state of the two bits corresponds
to the mode of operation of the device.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 41. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC registers
are unaffected when in power-down. The DAC registers can be
updated while the device is in power-down mode. The time
required to exit power-down is typically 4.5 µs for VDD = 5 V.
Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation1
DB15
to
DB8
DB0
(LSB)
DB23 DB22
DB21
DB20
DB19 to DB16
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
1
0
0
X
X
PDD1
PDD0
PDC1
PDC0
PDB1
PDB0 PDA1
PDA0
Command bits (C3 to C0)
Address bits
(don’t care)
Power-Down
Select DAC D
Power-Down
Select DAC C
Power-Down
Select DAC B
Power-Down
Select DAC A
1 X = don’t care.
Rev. C | Page 21 of 27
AD5686/AD5684
Data Sheet
LOAD DAC (HARDWARE LDAC PIN)
LDAC MASK REGISTER
The AD5686/AD5684 DACs have double buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The user can write to any combination of the input
registers. Updates to the DAC register are controlled by
LDAC
function.
Command 0101 is reserved for the software
Address bits are ignored. Writing to the DAC using Command
LDAC
0101 loads the 4-bit
for each channel is 0; that is, the
Setting the bits to 1 forces this DAC channel to ignore transitions
LDAC LDAC
register (DB3 to DB0). The default
LDAC
pin works normally.
LDAC
the
pin.
on the
pin. This flexibility is useful in applications where the user
LDAC
pin, regardless of the state of the hardware
OUTPUT
AMPLIFIER
V
16-/12-BIT
DAC
REF
V
X
OUT
wishes to select which channels respond to the
pin.
register gives the user extra flexibility and control
LDAC LDAC
LDAC
The
over the hardware
bits (DB3 to DB0) to 0 for a DAC channel means that this
LDAC
DAC
REGISTER
pin (see Table 13). Setting the
LDAC
channel’s update is controlled by the hardware
LDAC
pin.
INPUT
REGISTER
Table 13.
Load
Overwrite Definition
Register
LDAC
SCLK
SYNC
SDIN
INTERFACE
LOGIC
Bits
(DB3 to DB0)
LDAC
SDO
Pin
Operation
LDAC
LDAC
1 or 0
X1
Figure 42. Simplified Diagram of Input Loading Circuitry for a Single DAC
0
1
Determined by the LDAC pin.
DAC channels are updated and
override the LDAC pin. DAC
channels see LDAC as 1.
LDAC
Instantaneous DAC Updating (
Held Low)
is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
LDAC
1 X = don’t care.
SYNC
the DAC register are updated on the rising edge of
the output begins to change (see Table 14).
and
LDAC
Deferred DAC Updating (
Is Pulsed Low)
is held high while data is clocked into the input register
using Command 0001. All DAC outputs are asynchronously
LDAC SYNC
LDAC
updated by taking
low after
has been taken
LDAC
high. The update now occurs on the falling edge of
.
1
LDAC
Table 14. Write Commands and
Pin Truth Table
Hardware LDAC
Pin State
Input Register
Contents
Command
Description
DAC Register Contents
No change (no update)
Data update
0001
VLOGIC
GND2
VLOGIC
Data update
Data update
No change
Write to Input Register n (dependent on LDAC)
0010
0011
Update DAC Register n with contents of Input
Register n
Updated with input register contents
GND
VLOGIC
GND
No change
Data update
Data update
Updated with input register contents
Data update
Write to and update DAC Channel n
Data update
1
LDAC
A high to low hardware
pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked
mask register.
2 When LDAC is permanently tied low, the LDAC mask bits are ignored.
LDAC
(blocked) by the
Rev. C | Page 22 of 27
Data Sheet
AD5686/AD5684
HARDWARE RESET (
)
RESET SELECT PIN (RSTSEL)
RESET
The AD5686/AD5684 contain a power-on reset circuit that
controls the output voltage during power-up. By connecting
the RSTSEL pin low, the output powers up to zero scale. Note
that this is outside the linear region of the DAC. By connecting
the RSTSEL pin high, VOUT powers up to midscale. The output
remains powered up at this level until a valid write sequence
is made to the DAC.
RESET
is an active low reset that allows the outputs to be
cleared to either zero scale or midscale. The clear code value is
RESET
user selectable via the
select pin. It is necessary to
low for a minimum of 30 ns to complete the
RESET
RESET
keep
operation (see Figure 2). When the
signal is returned
high, the output remains at the cleared value until a new value
is programmed. The outputs cannot be updated with a new
RESET
value while the
pin is low. There is also a software
executable reset function that resets the DAC to the power-
on reset code. Command 0110 is designated for this software
LDAC
reset function (see Table 8). Any events on
during a
RESET
power-on reset are ignored. If the
pin is pulled low at
power-up, the device does not initialize correctly until the pin is
released.
Rev. C | Page 23 of 27
AD5686/AD5684
Data Sheet
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
LAYOUT GUIDELINES
Microprocessor interfacing to the AD5686/AD5684 is via a
serial bus that uses a standard protocol that is compatible with
DSP processors and microcontrollers. The communications
channel requires a 3- or 4-wire interface consisting of a clock
signal, a data signal, and a synchronization signal. The devices
require a 24-bit data-word with data valid on the rising edge
In any circuit where accuracy is important, careful consider-
ation of the power supply and ground return layout helps to
ensure the rated performance. The PCB on which the AD5686/
AD5684 are mounted should be designed so that the AD5686/
AD5684 lie on the analog plane.
The AD5686/AD5684 should have ample supply bypassing
of 10 µF in parallel with 0.1 µF on each supply, located as close
to the package as possible, ideally right up against the device.
The 10 µF capacitors are the tantalum bead type. The 0.1 µF
capacitor should have low effective series resistance (ESR)
and low effective series inductance (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching.
SYNC
of
.
AD5686/AD5684 TO ADSP-BF531 INTERFACE
The SPI interface of the AD5686/AD5684 is designed to be
easily connected to industry-standard DSPs and micro-
controllers. Figure 43 shows the AD5686/AD5684 connected
to the Analog Devices, Inc., Blackfin® DSP. The Blackfin has an
integrated SPI port that can be connected directly to the SPI
pins of the AD5686/AD5684.
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
AD5686/
AD5684
The AD5686/AD5684 LFCSP models have an exposed pad
beneath the device. Connect this pad to the GND supply for the
part. For optimum performance, use special considerations to
design the motherboard and to mount the package. For
enhanced thermal, electrical, and board level performance,
solder the exposed pad on the bottom of the package to the
corresponding thermal land pad on the PCB. Design thermal
vias into the PCB land pad area to further improve heat
dissipation.
ADSP-BF531
SPISELx
SCK
SYNC
SCLK
SDIN
MOSI
PF9
PF8
LDAC
RESET
Figure 43. ADSP-BF531 Interface
AD5686/AD5684 TO SPORT INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial
port. Figure 44 shows how one SPORT interface can be used
to control theAD5686/AD5684.
The GND plane on the device can be increased (as shown in
Figure 45) to provide a natural heat sinking effect.
AD5686/
AD5684
AD5686/
AD5684
ADSP-BF527
SPORT_TFS
SPORT_TSCK
SPORT_DTO
SYNC
SCLK
SDIN
GND
PLANE
GPIO0
GPIO1
LDAC
RESET
BOARD
Figure 44. SPORT Interface
Figure 45. Pad Connection to Board
Rev. C | Page 24 of 27
Data Sheet
AD5686/AD5684
GALVANICALLY ISOLATED INTERFACE
ADuM14001
CONTROLLER
V
V
V
V
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
In many process control applications, it is necessary to
provide an isolation barrier between the controller and
the unit being controlled to protect and isolate the controlling
circuitry from any hazardous common-mode voltages that may
occur. iCoupler® products from Analog Devices provide voltage
isolation in excess of 2.5 kV. The serial loading structure of the
AD5686/AD5684 makes the part ideal for isolated interfaces
because the number of interface lines is kept to a minimum.
Figure 46 shows a 4-channel isolated interface to the AD5686/
AD5684 using an ADuM1400. For more information, visit
http://www.analog.com/icouplers.
TO
SERIAL
ENCODE
DECODE
DECODE
DECODE
DECODE
SCLK
CLOCK IN
TO
SDIN
SERIAL
DATA OUT
ENCODE
ENCODE
ENCODE
TO
SYNC
SYNC OUT
LOAD DAC
OUT
TO
LDAC
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 46. Isolated Interface
Rev. C | Page 25 of 27
AD5686/AD5684
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 48. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. C | Page 26 of 27
Data Sheet
AD5686/AD5684
ORDERING GUIDE
Package
Description
Package
Model1, 2
Resolution
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Accuracy
8 LSB INL
2 LSB INL
8 LSB INL
8 LSB INL
2 LSB INL
2 LSB INL
1 LSB INL
2 LSB INL
2 LSB INL
1 LSB INL
1 LSB INL
Option
CP-16-22
CP-16-22
RU-16
RU-16
RU-16
Branding
DJH
DJJ
AD5686ACPZ-RL7
AD5686BCPZ-RL7
AD5686ARUZ
AD5686ARUZ-RL7
AD5686BRUZ
AD5686BRUZ-RL7
AD5684BCPZ-RL7
AD5684ARUZ
AD5684ARUZ-RL7
AD5684BRUZ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
RU-16
CP-16-22
RU-16
RU-16
RU-16
RU-16
DJP
AD5684BRUZ-RL7
1 Z = RoHS Compliant Part.
2 The EVAL-AD5686RSDZ can be used to evaluate the AD5686/AD5684. The EVAL-AD5686RSDZ requires the EVAL-SDP-CB1Z support board for operation.
©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10797-0-6/17(C)
Rev. C | Page 27 of 27
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