AD5765CSUZ-REEL7 [ADI]
QUAD, SERIAL INPUT LOADING, 8us SETTLING TIME, 16-BIT DAC, PQFP32, ROHS COMPLIANT, MS-026ABA, TQFP-32;
| 型号： | AD5765CSUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | QUAD, SERIAL INPUT LOADING, 8us SETTLING TIME, 16-BIT DAC, PQFP32, ROHS COMPLIANT, MS-026ABA, TQFP-32 输入元件 转换器 |
| 文件： | 总29页 (文件大小：752K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete Quad, 16-Bit, High Accuracy,
Serial Input, ± ± ꢀ ꢁAC
ꢁata Sheet
Aꢁ±76±
FEATURES
GENERAꢀ DESCRIPTION
Complete quad, 16-bit digital-to-analog converter (DAC)
Programmable output range: 4.096 V, 4.201 V, or 4.311 V
1 ꢀSB maximum INꢀ error, 1 ꢀSB maximum DNꢀ error
ꢀow noise: 70 nV/√Hz
Settling time: 10 μs maximum
Integrated reference buffers
On-chip die temperature sensor
Output control during power-up/brownout
Programmable short-circuit protection
The AD5765 is a quad, 16-bit, serial input, bipolar voltage
output, digital-to-analog converter (DAC) that operates from
supply voltages of ±±475 ꢀ to ±54.5 ꢀ4 The nominal full-scale
output range is ±±4ꢁ06 ꢀ4 The AD5765 provides integrated
output amplifiers, reference buffers, and proprietary power-
up/power-down control circuitry4 The part also features a
digital I/O port, which is programmed via the serial interface4
The part incorporates digital offset and gain adjustment
registers per channel4
ꢀDAC
Simultaneous updating via
CꢀR
The AD5765 is a high performance converter that offers
guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB,
low noise, and 1ꢁ μs settling time4 During power-up (when the
supply voltages are changing), the outputs are clamped to ꢁ ꢀ
via a low impedance path4
Asynchronous
to zero code
Digital offset and gain adjustment
ꢀogic output control pins
DSP-/microcontroller-compatible serial interface
Temperature range: −40°C to +105°C
iCMOS® process technology1
The AD5765 uses a serial interface that operates at clock rates of
up to 3ꢁ MHz and is compatible with DSP and microcontroller
interface standards4 Double buffering allows the simultaneous
updating of all DACs4 The input coding is programmable to
either a twos complement or an offset binary format4 The
asynchronous clear function clears all DAC registers to either
bipolar zero or zero scale, depending on the coding used4 The
AD5765 is ideal for both closed-loop servo control and open-
loop control applications4 The AD5765 is available in a 3.-lead
TQFP and offers guaranteed specifications over the −±ꢁ°C to
+1ꢁ5°C industrial temperature range4 Figure 1 contains a
functional block diagram of the AD57654
APPꢀICATIONS
Industrial automation
Open-/closed-loop servo control
Process control
Data acquisition systems
Automatic test equipment
Automotive test and measurement
High accuracy instrumentation
Table 1. Related Devices
Part No.
Description
AD5764
Complete quad, 16-bit, high accuracy, serial input,
1ꢀ ꢁ DAC
AD5763
Complete dual, 16-bit, high accuracy, serial input,
5 ꢁ DAC
1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS is a technology
platform that enables the development of analog ICs capable of 3ꢀ ꢁ and operating at 15 ꢁ supplies, allowing dramatic reductions in power consumption and
package size and increased ac and dc performance.
Rev. C
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved.
AD5765* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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REFERENCE MATERIALS
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
EVALUATION KITS
DESIGN RESOURCES
• AD5765 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• AD5765 Evaluation Board
DOCUMENTATION
Application Notes
• AN-1238: High Accuracy, Bipolar Voltage Output Digital-
to-Analog Conversion Using the AD5765 DAC
Data Sheet
DISCUSSIONS
View all AD5765 EngineerZone Discussions.
• AD5765: Complete Quad, 16-Bit, High Accuracy, Serial
Input, ±5V DAC Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
SOFTWARE AND SYSTEMS REQUIREMENTS
• AD5765 Software Evaluation
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
REFERENCE DESIGNS
• CN0073
DOCUMENT FEEDBACK
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AD5765
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Data Register............................................................................... 20
Coarse Gain Register ................................................................. 20
Fine Gain Register...................................................................... 21
Offset Register ............................................................................ 21
Offset and Gain Adjustment Worked Example...................... 22
Design Features............................................................................... 23
Analog Output Control ............................................................. 23
Digital Offset and Gain Control............................................... 23
Programmable Short-Circuit Protection ................................ 23
Digital I/O Port........................................................................... 23
Die Temperature Sensor............................................................ 23
Local-Ground-Offset Adjustment ........................................... 23
Power-On Status......................................................................... 24
Applications Information.............................................................. 25
Typical Operating Circuit ......................................................... 25
Precision Voltage Reference Selection..................................... 25
Layout Guidelines........................................................................... 26
Galvanically Isolated Interface ................................................. 26
Microprocessor Interfacing....................................................... 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
AC Performance Characteristics................................................ 6
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
DAC Architecture....................................................................... 17
Reference Buffers........................................................................ 17
Serial Interface ............................................................................ 17
LDAC
Simultaneous Updating via
Transfer Function ....................................................................... 19
Asynchronous Clear ( )....................................................... 19
........................................... 18
CLR
Function Register ....................................................................... 20
REVISION HISTORY
10/11—Rev. B to Rev. C
Changed 50 MHz to 30 MHz....................................... Throughout
Changes to t1, t2, and t3 Parameters, Table 4.................................. 7
7/11—Rev. A to Rev. B
Changed 30 MHz to 50 MHz Throughout.................................... 1
Changes to t1, t2, and t3 Parameters, Table 4.................................. 7
Changes to Table 21........................................................................ 25
Changes to Ordering Guide .......................................................... 27
10/09—Rev. 0 to Rev. A
Deleted Endnote 1, Table 2.............................................................. 4
Deleted Endnote 1, Table 3.............................................................. 6
Deleted Endnote 1, Table 4.............................................................. 7
Changes to t6 Parameter, Table 4 .................................................... 7
1/09—Revision 0: Initial Version
Rev. C | Page 2 of 28
Data Sheet
AD5765
FUNCTIONAL BLOCK DIAGRAM
AV
AV
AV
AV
SS
RSTOUT
RSTIN
PGND
REFGND
REFAB
DD
SS
DD
VOLTAGE
MONITOR
AND
DV
CC
REFERENCE
BUFFERS
AD5765
CONTROL
DGND
ISCC
G1
G1
G1
16
16
16
16
16
INPUT
REG A
DAC
REG A
DAC A
DAC B
DAC C
DAC D
SDIN
SCLK
SYNC
SDO
VOUTA
AGNDA
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
G2
GAIN REG A
OFFSET REG A
INPUT
REG B
DAC
REG B
VOUTB
AGNDB
G2
GAIN REG B
OFFSET REG B
D0
D1
INPUT
REG C
DAC
REG C
VOUTC
AGNDC
G2
GAIN REG C
OFFSET REG C
BIN/2sCOMP
G1
INPUT
REG D
DAC
REG D
VOUTD
AGNDD
G2
GAIN REG D
CLR
OFFSET REG D
TEMP
SENSOR
REFERENCE
BUFFERS
LDAC
REFCD
TEMP
Figure 1.
Rev. C | Page 3 of 28
AD5765
Data Sheet
SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, AV SS = −4.75 V to −5.25 V, AGNDx = DGND = REFGND = PGND = 0 V, REFAB = REFCD = 2.048 V,
DVCC = 2.7 V to 5.25 V, RLOAD = 5 kΩ, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
B Grade1
C Grade1
Unit
Test Conditions/Comments
ACCURACY
Outputs unloaded
Resolution
16
2
1
2
3
16
1
1
2
3
Bits
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Bipolar Zero Error
LSB max
LSB max
mV max
mV max
ppm FSR/°C typ
Guaranteed monotonic
At 25°C
Bipolar Zero Temperature
Coefficient (TC)2
1
1
Zero-Scale Error
2
2
mV max
At 25°C
3.5
1
3.5
1
mV max
ppm FSR/°C typ
Zero-Scale Temperature
Coefficient (TC)2
Gain Error
0.03
0.04
1
0.03
0.04
1
% FSR max
% FSR max
ppm FSR/°C typ
LSB max
At 25°C, coarse gain register = 0
Coarse gain register = 0
Gain TC2
DC Crosstalk2
0.5
0.5
REFERENCE INPUT2
Reference Input Voltage
DC Input Impedance
Input Current
2.048
1
10
2.048
1
10
V nominal
MΩ min
µA max
1% for specified performance
Typically, 100 MΩ
Typically, 30 nA
Reference Range
1 to 2.1
1 to 2.1
V min to V max
OUTPUT CHARACTERISTICS2
Output Voltage Range3
4.31158
4.20103
4.096
4.42105
32
37
10
1
4.31158
4.20103
4.096
4.42105
32
37
10
1
V min/V max
V min/V max
V min/V max
V min/V max
ppm FSR/500 hours typ
ppm FSR/1000 hours typ
mA typ
Coarse gain register = 2
Coarse gain register = 1
Coarse gain register = 0
VREFIN = 2.1 V, coarse gain register = 2
Output Voltage Drift vs. Time
Short-Circuit Current
Load Current
RISCC = 6 kΩ; see Figure 23
For specified performance
mA max
Capacitive Load Stability
RLOAD = ∞
RLOAD = 10 kΩ
DC Output Impedance
DIGITAL INPUTS2
200
1000
0.3
200
1000
0.3
pF max
pF max
Ω max
DVCC = 2.7 V to 5.25 V, JEDEC
compliant
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
2
0.8
1
2
0.8
1
V min
V max
µA max
pF max
Per pin
Per pin
Pin Capacitance
10
10
Rev. C | Page 4 of 28
Data Sheet
AD5765
Parameter
DIGITAL OUTPUTS (D0, D1, SDO)2
B Grade1
C Grade1
Unit
Test Conditions/Comments
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
High Impedance Leakage Current
High Impedance Output
Capacitance
0.4
DVCC − 1
0.4
DVCC − 0.5
1
5
0.4
DVCC − 1
0.4
DVCC − 0.5
1
5
V max
V min
V max
V min
µA max
pF typ
DVCC = 5 V 5%, sinking 200 µA
DVCC = 5 V 5%, sourcing 200 µA
DVCC = 2.7 V to 3.6 V, sinking 200 µA
DVCC = 2.7 V to 3.6 V, sourcing 200 µA
SDO only
SDO only
DIE TEMPERATURE SENSOR
Output Voltage at 25°C
Output Voltage Scale Factor
Output Voltage Range
Output Load Current
Power-On Time
POWER REQUIREMENTS
AVDD/AVSS
1.44
3
1.175 to 1.9
200
10
1.44
3
1.175 to 1.9
200
10
V typ
mV/°C typ
V min to V max
µA max
ms typ
4.75 to 5.25
2.7 to 5.25
2.25
1.9
1.2
4.75 to 5.25
2.7 to 5.25
2.25
1.9
1.2
V min to V max
V min to V max
mA/channel max
mA/channel max
mA max
DVCC
AIDD
AISS
DICC
Outputs unloaded
Outputs unloaded
VIH = DVCC, VIL = DGND, 750 µA typ
Power Supply Sensitivity2
∆VOUT/∆ΑVDD
Power Dissipation
−110
76
−110
76
dB typ
mW typ
5 V operation output unloaded
1 Temperature range: −40°C to +105°C; typical at +25°C.
2 Guaranteed by design and characterization; not production tested.
3 Output amplifier headroom requirement is 0.5 V minimum.
Rev. C | Page 5 of 28
AD5765
Data Sheet
AC PERFORMANCE CHARACTERISTICS
AVDD = 4.75 V to 5.25 V, AV SS = −4.75 V to −5.25 V, AGNDx = DGND = REFGND = PGND = 0 V, REFAB = REFCD = 2.048 V,
DVCC = 2.7 V to 5.25 V, RLOAD = 5 kΩ, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
B Grade C Grade Unit
Test Conditions/Comments
Full-scale step to 1 LSB
512 LSB step settling
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
8
8
µs typ
10
2
10
2
µs max
µs typ
Slew Rate
5
5
V/µs typ
nV-sec typ
mV typ
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise, 0.1 Hz to 10 Hz
Output Noise, 0.1 Hz to 100 kHz
1/f Corner Frequency
Output Noise Spectral Density
Complete System Output Noise Spectral Density2
20
30
60
8
2
2
0.1
50
300
70
80
20
30
60
8
2
2
0.1
50
300
70
80
dB typ
nV-sec typ
nV-sec typ
nV-sec typ
LSB p-p typ
µV rms typ
Hz typ
Effect of input bus activity on DAC outputs
nV/√Hz typ
nV/√Hz typ
Measured at 10 kHz
Measured at 10 kHz
1 Guaranteed by design and characterization; not production tested.
2 Includes noise contributions from integrated reference buffers, 16-bit DAC, and output amplifier.
Rev. C | Page 6 of 28
Data Sheet
AD5765
TIMING CHARACTERISTICS
AVDD = 4.75 V to 5.25 V, AV SS = −4.75 V to −5.25 V, AGNDx = DGND = REFGND = PGND = 0 V, REFAB = REFCD = 2.048 V,
DVCC = 2.7 V to 5.25 V, RLOAD = 5 kΩ, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t1
t2
t3
t4
33
13
13
13
13
90
2
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs min
ns min
ns min
ns max
µs max
ns min
µs max
ns max
ns min
µs max
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC rising edge
Minimum SYNC high time
4
t5
t6
t7
t8
t9
Data setup time
Data hold time
5
1.7
480
10
500
10
10
2
SYNC rising edge to LDAC falling edge when all DACs are updated
SYNC rising edge to LDAC falling edge when a single DAC is updated
LDAC pulse width low
t10
t11
t12
t13
t14
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
5, 6
t15
25
13
2
SCLK rising edge to SDO valid
SYNC rising edge to SCLK falling edge
SYNC rising edge to DAC output response time (LDAC = 0)
LDAC falling edge to SYNC rising edge
t16
t17
t18
170
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 Standalone mode only.
5 Measured with the load circuit of Figure 5.
6 Daisy-chain mode only.
Rev. C | Page 7 of 28
AD5765
Data Sheet
t1
SCLK
SYNC
1
2
24
t3
t2
t6
t4
t5
t8
t7
DB23
SDIN
DB0
t10
t10
t9
LDAC
t18
t12
t11
VOUTx
LDAC = 0
t12
t17
VOUTx
CLR
t13
t14
VOUTx
Figure 2. Serial Interface Timing Diagram
t1
SCLK
24
48
t3
t2
t5
t6
t16
t4
SYNC
SDIN
t8
t7
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N – 1
INPUT WORD FOR DAC N
t15
DB23
DB0
SDO
t9
UNDEFINED
t10
LDAC
Figure 3. Daisy-Chain Timing Diagram
Rev. C | Page 8 of 28
Data Sheet
AD5765
SCLK
24
48
SYNC
SDIN
DB23
DB0
DB23
DB0
NOP CONDITION
INPUT WORD SPECIFIES
REGISTER TO BE READ
DB23
DB0
SDO
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Readback Timing Diagram
200µA
I
OL
V
V
(MIN) OR
(MAX)
TO OUTPUT
PIN
OH
OL
C
L
50pF
200µA
I
OH
Figure 5. Load Circuit for SDO Timing Diagram
Rev. C | Page 9 of 28
AD5765
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
Rating
AVDD to AGNDx, DGND
AVSS to AGNDx, DGND
DVCC to DGND
−0.3 V to +7 V
+0.3 V to −7 V
−0.3 V to +7 V
−DVCC to +0.25 V
THERMAL RESISTANCE
DVCC to AVDD
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Digital Inputs to DGND
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
−0.3 V to DVCC + 0.3 V
−0.3 V to AVDD + 0.3 V
AVSS to AVDD
Digital Outputs to DGND
REFx to AGNDx, PGND
VOUTx to AGNDx
Table 6. Thermal Resistance
Package Type
θJA
θJC
Unit
32-Lead TQFP
65
12
°C/W
AGNDx to DGND
−0.3 V to +0.3 V
Operating Temperature Range (TA)
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
ESD CAUTION
−40°C to +105°C
−65°C to +150°C
150°C
(TJ max – TA)/θJA
JEDEC industry standard
J-STD-020
Lead Temperature
Soldering
Rev. C | Page 10 of 28
Data Sheet
AD5765
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D0
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
PIN 1
AD5765
TOP VIEW
(Not to Scale)
D1
9
10 11 12
13 14 15
16
NC = NO CONNECT
Figure 6. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
2
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds
of up to 30 MHz.
3
4
51
SDIN
SDO
CLR
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. This is used to clock data from the serial register in daisy-chain or readback mode.
Negative Edge Triggered Input. Asserting this pin sets the DAC registers to 0x0000.
6
LDAC
Load DAC. Logic input. This is used to update the DAC registers and consequently the analog outputs. When tied
permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during
the write cycle, the DAC input register is updated but the output update is held off until the falling edge of LDAC.
In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must
not be left unconnected.
7, 8
D0, D1
D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are configurable and
readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DVCC. When
programmed as outputs, D0 and D1 are referenced by DVCC and DGND.
9
RSTOUT
RSTIN
Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it can
be used to control other system components.
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input
clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain
unchanged.
10
11
12
13, 31
14
15, 30
16
DGND
DVCC
AVDD
PGND
AVSS
Digital Ground Pin.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V.
Positive Analog Supply Pins. Voltage ranges from 4.75 V to 5.25 V.
Ground Reference Point for Analog Circuitry.
Negative Analog Supply Pins. Voltage ranges from –4.75 V to –5.25 V.
This pin is used in association with an optional external resistor to AGND to program the short-circuit current of
the output amplifiers. See the Design Features section for additional details.
ISCC
17
18
AGNDD
VOUTD
Ground Reference Pin for the DAC D Output Amplifier.
Analog Output Voltage of DAC D. This provides buffered output with a nominal full-scale output range of 4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
Rev. C | Page 11 of 28
AD5765
Data Sheet
Pin No. Mnemonic
Description
19
VOUTC
Analog Output Voltage of DAC C. This provides buffered output with a nominal full-scale output range of 4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
20
21
22
AGNDC
AGNDB
VOUTB
Ground Reference Pin for the DAC C Output Amplifier.
Ground Reference Pin for the DAC B Output Amplifier.
Analog Output Voltage of DAC B. This provides buffered output with a nominal full-scale output range of 4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
23
VOUTA
Analog Output Voltage of DAC A. This provides buffered output with a nominal full-scale output range of 4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
24
25
AGNDA
REFAB
Ground Reference Pin for the DAC A Output Amplifier.
External Reference Voltage Input for Channel A and Channel B. The reference input range is 1 V to 2.1 V; this
programs the full-scale output voltage. VREFIN = 2.048 V for specified performance.
26
REFCD
External Reference Voltage Input for Channel C and Channel D. The reference input range is 1 V to 2.1 V; this
programs the full-scale output voltage. VREFIN = 2.048 V for specified performance.
27
28
29
NC
REFGND
TEMP
No Connect.
Reference Ground Return for the Reference Generator and Buffers.
This pin provides an output voltage proportional to temperature. The output voltage is 1.4 V, typical, at 25°C die
temperature; variation with temperature is 5 mV/°C.
32
BIN/2sCOMP Determines the DAC Coding. This pin should be hardwired to either DVCC or DGND. When hardwired to DVCC, input
coding is offset binary. When hardwired to DGND, input coding is twos complement
(see Table 8).
1 Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.
Rev. C | Page 12 of 28
Data Sheet
AD5765
TYPICAL PERFORMANCE CHARACTERISTICS
0.30
0.25
0.20
0.15
0.10
0.05
0
1.0
T
= 25°C
0.8
0.6
A
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0.05
0.10
–0.15
–0.20
–0.25
–40
–20
0
20
40
60
80
100
0
10,000
20,000 30,000
CODE
40,000 50,000
60,000
TEMPERATURE (°C)
Figure 7. Integral Nonlinearity Error vs. Code
Figure 10. Differential Nonlinearity Error vs. Temperature
8.7
1.0
0.8
AI
DD
8.6
8.5
8.4
8.3
8.2
8.1
8.0
7.9
7.8
7.7
T
= 25°C
A
0.6
T
= 25°C
A
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
AI
SS
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
0
10,000
20,000 30,000
CODE
40,000 50,000
60,000
AV /AV (V)
DD SS
Figure 11. AIDD/AISS vs. AVDD/AVSS
Figure 8. Differential Nonlinearity Error vs. Code
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Integral Nonlinearity Error vs. Temperature
Figure 12. Zero-Scale Error vs. Temperature
Rev. C | Page 13 of 28
AD5765
Data Sheet
0.20
0.18
0.16
0.14
0.12
0.10
0.08
2.0
1.5
AV
AV = –5V
= +5V
DD
SS
= 25°C
T
A
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0.06
–40
–8
–6
–4
–2
0
2
4
6
8
10
–20
0
20
40
60
80
100
TEMPERATURE (°C)
SOURCE/SINK CURRENT (mA)
Figure 13. Bipolar Zero Error vs. Temperature
Figure 16. Source and Sink Capability of Output Amplifier with Positive
Full-Scale Loaded
–0.008
–0.009
–0.010
–0.011
–0.012
–0.013
–0.014
–0.015
4
AV
AV = –5V
= +5V
DD
3
2
SS
= 25°C
T
A
1
0
–1
–2
–3
–4
–0.016
–40
–10
–8
–6
–4
–2
0
2
4
6
8
10
–20
0
20
40
60
80
100
TEMPERATURE (°C)
SOURCE/SINK CURRENT (mA)
Figure 14. Gain Error vs. Temperature
Figure 17. Source and Sink Capability of Output Amplifier with Negative Full-
Scale Loaded
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
T
= 25°C
A
1
0
0
CH1 1.25V
M1.00µs
CH1
–175mV
1
2
3
4
5
LOGIC INPUT VOLTAGE (V)
Figure 15. DICC vs. Logic Input Voltage
Figure 18. Positive Full-Scale Step
Rev. C | Page 14 of 28
Data Sheet
AD5765
1
2
1
3
CH1 1.25V
M1.00µs
CH1
175mV
CH1 5.00V
CH3 50.0mV
CH2 5.00V
M25.0ms
CH1
4.1V
Figure 19. Negative Full-Scale Step
Figure 22. VOUT vs. AVDD/AVSS on Power-Up
40
10
9
8
7
6
5
4
3
2
1
0
T
= 25°C
A
0x7FFF TO 0x8000
0x8000 TO 0x7FFF
T
= 25°C
A
30
20
10
0
–10
–20
–30
–40
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
RI
SCC
(kΩ)
Figure 20. Major Code Transition Glitch Energy
Figure 23. Short-Circuit Current vs. RISCC
1.8
1.7
1.6
1.5
1.4
1.3
1.2
AV
AV = –5V
= +5V
DD
SS
4
CH4 50µV
M1.00µs
CH4
26µV
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 21. Peak-to-Peak Noise (100 kHz Bandwidth)
Figure 24. TEMP Output Voltage vs. Temperature
Rev. C | Page 15 of 28
AD5765
Data Sheet
TERMINOLOGY
Total unadjusted error (TUE) is a measure of the output error
considering all the various errors.
Zero-Scale Error Temperature Coefficient
Zero-scale error temperature coefficient is a measure of the
change in zero-scale error with a change in temperature. Zero-
scale error TC is expressed as (ppm FSR)/°C.
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 7.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic. A
typical DNL vs. code plot can be seen in Figure 8.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change in
gain error with changes in temperature. Gain error temperature
coefficient is expressed as (ppm of FSR)/°C.
Digital-to-Analog Glitch Impulse
Monotonicity
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by 1 LSB at
the major carry transition, 0x7FFF to 0x8000 (see Figure 20).
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5765 is
monotonic over its full operating temperature range.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (offset binary coding) or 0x0000 (twos complement
coding). A plot of bipolar zero error vs. temperature can be seen
in Figure 13.
Bipolar Zero Temperature Coefficient (TC)
Bipolar zero temperature coefficient is the measure of the
change in the bipolar zero error with a change in temperature. It
is expressed as (ppm FSR)/°C.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the DAC
but is measured when the DAC output is not updated. It is spec-
ified in nV-sec and is measured with a full-scale code change on
the data bus, that is, from all 0s to all 1s and vice versa.
Power Supply Sensitivity
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage.
Full-Scale Error
DC Crosstalk
Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC register. Ideally, the output voltage
should be 2 × VREF − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range.
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC while
monitoring another DAC and is expressed in LSBs.
Negative Full-Scale Error/Zero Scale Error
DAC-to-DAC Crosstalk
Negative full-scale error is the error in the DAC output voltage
when 0x0000 (offset binary coding) or 0x8000 (twos complement
coding) is loaded to the DAC register. Ideally, the output voltage
is −2 × VREF. A plot of zero-scale error vs. temperature can be
seen in Figure 12.
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s and vice versa) with
LDAC
low and monitoring the output of another DAC. The
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for the
output to settle to a specified level for a full-scale input change.
energy of the glitch is expressed in nV-sec.
Channel-to-Channel Isolation
Channel-to-channel isolation is the ratio of the amplitude of the
signal at the output of one DAC to a sine wave on the reference
input of another DAC. It is measured in decibels.
Slew Rate
The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltage-
output DAC is usually limited by the slew rate of the amplifier
used at its output. Slew rate is measured from 10% to 90% of the
output signal and is given in V/µs.
Digital Crosstalk
Digital crosstalk is a measure of the impulse injected into the
analog output of one DAC from the digital inputs of another
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range. A plot of
gain error vs. temperature can be seen in Figure 14.
Total Unadjusted Error (TUE)
Rev. C | Page 16 of 28
Data Sheet
AD5765
THEORY OF OPERATION
The AD5765 is a quad, 16-bit, serial input, bipolar voltage output
DAC that operates from supply voltages of 4.75 V to 5.25 V and
has a buffered output voltage of up to 4.311 V. Data is written to
the AD5765 in a 24-bit word format, via a 3-wire serial interface.
The device also offers an SDO pin, which is available for daisy-
chaining or readback.
SERIAL INTERFACE
The AD5765 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI™, MICROWIRE™, and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. The input register consists of a read/write
bit, three register select bits, three DAC address bits, and 16 data
bits as shown in Table 9. The timing diagram for this operation
is shown in Figure 2.
The AD5765 incorporates a power-on reset circuit, which
ensures that the DAC registers power up loaded with 0x0000.
The AD5765 features a digital I/O port that can be programmed
via the serial interface, on-chip reference buffers and per
channel digital gain, and offset registers.
DAC ARCHITECTURE
At power-up, the DAC registers are loaded with zero code
(0x0000), and the outputs are clamped to 0 V via a low impedance
path. The outputs can be updated with the zero code value at
The DAC architecture of the AD5765 consists of a 16-bit
current mode segmented R-2R DAC. The simplified circuit
diagram for the DAC section is shown in Figure 25.
LDAC CLR
this time by asserting either
or
. The corresponding
2sCOMP
The four MSBs of the 16-bit data-word are decoded to drive 15
switches, E1 to E15. Each of these switches connects one of the
15 matched resistors to either AGNDx or IOUT. The remaining
12 bits of the data-word drive switches S0 to S11 of the 12-bit
R-2R ladder network.
output voltage depends on the state of the BIN/
pin.
pin is tied to DGND, the data coding is
twos complement, and the outputs update to 0 V. If the
2sCOMP
2sCOMP
If the BIN/
BIN/
pin is tied to DVCC, the data coding is offset
binary, and the outputs update to negative full scale. To have the
R
R
R
CLR
V
outputs power up with zero code loaded to the outputs, the
pin should be held low during power-up.
REF
2R
2R
2R
2R
2R
2R
2R
Standalone Operation
R/8
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can be used
E15
E14
E1
S0
S11
S10
IOUT
SYNC
only if
In gated clock mode, a burst clock containing the exact number
SYNC
is held low for the correct number of clock cycles.
VOUTx
AGNDx
of clock cycles must be used, and
must be taken high
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
12-BIT, R-2R LADDER
after the final clock to latch the data. The first falling edge of
Figure 25. DAC Ladder Structure
SYNC
starts the write cycle. Exactly 24 falling clock edges must
SYNC
REFERENCE BUFFERS
be applied to SCLK before
SYNC
is brought high again. If
th
is brought high before the 24 falling SCLK edge, the data
The AD5765 operates with an external reference. The reference
inputs (REFAB and REFCD) have an input range up to 2.1 V.
This input voltage is then used to provide a buffered positive
and negative reference for the DAC cores. The positive
reference is given by
written is invalid. If more than 24 falling SCLK edges are applied
SYNC
before
input register addressed is updated on the rising edge of
SYNC
is brought high, the input data is also invalid. The
SYNC
must be
.
In order for another serial transfer to take place,
brought low again. After the end of the serial data transfer, data
is automatically transferred from the input shift register to the
addressed register.
+VREF = 2 VREF
The negative reference to the DAC cores is given by
−VREF = −2 VREF
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be
These positive and negative reference voltages (along with the
gain register values) define the output ranges of the DACs.
LDAC
updated by taking
low.
Rev. C | Page 17 of 28
AD5765
Data Sheet
1
AD57651
The remaining data bits in the write sequence are don’t care.
During the next SPI write, the data appearing on the SDO
output is the data from the previously addressed register. For a
read of a single register, the NOP command can be used in
clocking out the data from the selected register on SDO. The
readback diagram in Figure 4 shows the readback sequence. For
example, to read back the fine gain register of Channel A on the
AD5765, implement the following sequence:
68HC11
MOSI
SCK
PC7
SDIN
SCLK
SYNC
LDAC
PC6
MISO
SDO
SDIN
AD57651
1. Write 0xA0XXXX to the AD5765 input register. This
configures the AD5765 for read mode with the fine gain
register of Channel A selected. Note that all the data bits,
DB15 to DB0, are don’t cares.
SCLK
SYNC
LDAC
SDO
2. Follow this with a second write, an NOP condition,
0x00XXXX. During this write, the data from the fine gain
register is clocked out on the SDO line; that is, data clocked
out contains the data from the fine gain register in Bit DB5
to Bit DB0.
SDIN
AD57651
SCLK
SYNC
LDAC
SDO
SIMULTANEOUS UPDATING VIA LDAC
SYNC
LDAC
, and after
1
Depending on the status of both
and
ADDITIONAL PINS OMITTED FOR CLARITY.
data has been transferred into the input register of the DACs,
there are two ways in which the DAC registers and DAC
outputs can be updated: individually and simultaneously
Figure 26. Daisy-Chaining the AD5765
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
Individual DAC Updating
LDAC
In this mode,
input shift register. The addressed DAC output is updated on
SYNC
is held low while data is clocked into the
SYNC
number of serial interface lines. The first falling edge of
starts the write cycle. The SCLK is continuously applied to the
SYNC
the rising edge of
Simultaneous Updating of All DACs
LDAC
.
input shift register when
is low. If more than 24 clock
pulses are applied, the data ripples out of the shift register and
appears on the SDO line. This data is clocked out on the rising
edge of SCLK and is valid on the falling edge. By connecting the
SDO of the first device to the SDIN input of the next device in
the chain, a multidevice interface is constructed. Each device in
the system requires 24 clock pulses. Therefore, the total number
of clock cycles must equal 24 N, where N is the total number of
AD5765 devices in the chain. When the serial transfer to all
In this mode,
input shift register. All DAC outputs are updated by taking
LDAC SYNC
is held high while data is clocked into the
low any time after
has been taken high. The
LDAC
update now occurs on the falling edge of
.
OUTPUT
I/V AMPLIFIER
16-BIT
DAC
V
REFIN
VOUTx
SYNC
devices is complete,
is taken high. This latches the input
DAC
data in each device in the daisy chain and prevents additional
data from being clocked into the input shift register. The serial
clock can be a continuous or a gated clock.
LDAC
REGISTER
INPUT
REGISTER
SYNC
A continuous SCLK source can be used only if
is held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
SYNC
be used, and
latch the data.
must be taken high after the final clock to
Figure 27. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
Readback Operation
Before a readback operation is initiated, the SDO pin must be
enabled by writing to the function register and clearing the
SDO disable bit; this bit is cleared by default. Readback mode is
W
invoked by setting the R/ bit to 1 in the serial input register
W
write. With R/ = 1, Bit A2 to Bit A0, in association with Bit
REG2, Bit REG1, and Bit REG0, select the register to be read.
Rev. C | Page 18 of 28
Data Sheet
AD5765
TRANSFER FUNCTION
The output voltage expression for the AD5765 is given by
Table 8 shows the ideal input-code-to-output-voltage rela-
tionship for the AD5765 for both offset binary and twos
complement data coding.
D
VOUT = −2×VREFIN + 4×VREFIN
65,536
where:
D is the decimal equivalent of the code loaded to the DAC.
REFIN is the reference voltage applied at the REFAB and
Table 8. Ideal Output Voltage to Input Code Relationship
Digital Input
Offset Binary Data Coding
MSB
Analog Output
V
REFCD pins.
LSB VOUTx
ASYNCHRONOUS CLEAR (
)
CLR
1111 1111
1000 0000
1000 0000
0111 1111
0000 0000
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
2 VREF × (32,767/32,768)
2 VREF × (1/32,768)
0 V
is a negative edge triggered clear that allows the outputs to
CLR
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain
low for a minimum amount of time (see Figure 2) for the
−2 VREF × (1/32,768)
−2 VREF × (32,767/32,768)
CLR
operation to complete. When the
signal is returned high,
Twos Complement Data Coding
CLR
the output remains at the cleared value until a new value is
programmed. If, at power-on, is at 0 V, then all DAC
MSB
LSB VOUTx
CLR
0111 1111
0000 0000
0000 0000
1111 1111
1000 0000
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
2 VREF × (32,767/32,768)
2 VREF × (1/32,768)
0 V
outputs are updated with the clear value. A clear can also be
initiated through software by writing the command 0x04XXXX
to the AD5765.
−2 VREF × (1/32,768)
−2 VREF × (32,767/32,768)
Table 9. AD5765 Input Register Format
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15:DB0
R/W
0
REG2
REG1
REG0
A2
A1
A0
Data
Table 10. Input Register Bit Functions
Bit
Description
R/W
Indicates a read from or a write to the addressed register
REG2, REG1, REG0
Used in association with the address bits to determine if a read or write operation is to the data register, offset
register, gain register, or function register
REG2
REG1
REG0
Function
0
0
0
1
1
0
1
1
0
0
0
0
1
0
1
Function register
Data register
Coarse gain register
Fine gain register
Offset register
A2, A1, A0
Used to decode the DAC channels
A2
A1
0
A0
0
Channel Address
DAC A
0
0
0
1
DAC B
0
1
0
DAC C
0
1
1
DAC D
1
0
0
All DACs
D15:D0
Data bits
Rev. C | Page 19 of 28
AD5765
Data Sheet
FUNCTION REGISTER
The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine
the function addressed. The functions available via the function register are outlined in Table 11 and Table 12.
Table 11. Function Register Options
REG2 REG1 REG0 A2 A1 A0
DB15:DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
0
1
No operation, data = don’t care
Don’t care
Local ground
D1
D1
D0
D0
SDO
offset adjustment
direction
value
direction
value
disable
0
0
0
0
0
0
1
1
0
0
0
1
Clear, data = don’t care
Load, data = don’t care
Table 12. Explanation of Function Register Options
Option
Description
No operation instruction used in readback operations.
Set by the user to enable the local ground offset adjustment function. Cleared by the user to disable the local ground
NOP
Local Ground
Offset Adjustment offset adjustment function (default). See the Design Features section for additional details.
D0/D1 Direction
D0/D1 Value
Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). See the Design
Features section for additional details.
I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when
configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input.
When enabled as inputs, these bits are don’t cares during a write operation.
SDO Disable
Clear
Load
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode.
Addressing this function updates the DAC registers and, consequently, the analog outputs.
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select the DAC channel with which the data
transfer is to take place (see Table 10). The data bits are in the DB15 to DB0 positions, as shown in Table 13.
Table 13. Programming the AD5765 Data Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB0
0
1
0
DAC address
16-bit DAC data
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select the DAC channel with which the
data transfer is to take place (see Table 10). The coarse gain register is a 2-bit register and allows the user to select the output range of each
DAC, as shown in Table 14 and Table 15.
Table 14. Programming the AD5765 Coarse Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB2
DB1
DB0
0
1
1
DAC address
Don’t care
CG1
CG0
Table 15. Output Range Selection
Output Range
CG1
CG0
4.096 V (default)
4.20103 V
4.31158 V
0
0
1
0
1
0
Rev. C | Page 20 of 28
Data Sheet
AD5765
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select the DAC channel with which the data
transfer is to take place (see Table 10). The fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC channel
by −32 LSBs to +31 LSBs in 1 LSB increments as shown in Table 16 and Table 17. The adjustment is made to both the positive full-scale
and negative full-scale points simultaneously, each point being adjusted by ½ of one step. The fine gain register coding is twos complement.
Table 16. Programming AD5765 Fine Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
DAC address
Don’t care
FG5
FG4
FG3
FG2
FG1
FG0
Table 17. AD5765 Fine Gain Register Options
Gain Adjustment
FG5
FG4
1
FG3
FG2
FG1
1
FG0
1
+31 LSBs
0
1
1
+30 LSBs
0
1
1
1
1
0
…
…
0
…
0
…
0
...
0
…
0
…
0
No Adjustment (Default)
…
−31 LSBs
−32 LSBs
…
1
1
…
0
0
…
0
0
…
0
0
…
0
0
…
1
0
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to 101. The DAC address bits select the DAC channel with which the data
transfer is to take place (see Table 10). The AD5765 offset register is an 8-bit register and allows the user to adjust the offset of each channel
by −16 LSBs to +15.875 LSBs in increments of ⅛ LSB as shown in Table 18 and Table 19. The offset register coding is twos complement.
Table 18. Programming the AD5765 Offset Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
DAC address
Don’t care
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OF0
Table 19. AD5765 Offset Register Options
Offset Adjustment
+15.875 LSBs
+15.75 LSBs
…
No Adjustment (Default)
…
OF7
OF6
OF5
1
1
…
0
…
0
OF4
OF3
OF2
1
1
…
0
…
0
OF1
OF0
1
0
…
0
…
1
0
0
…
0
…
1
1
1
…
0
…
0
1
1
…
0
…
0
1
1
…
0
…
0
1
1
…
0
…
0
−15.875 LSBs
−16 LSBs
1
0
0
0
0
0
0
0
Rev. C | Page 21 of 28
AD5765
Data Sheet
2. Convert the binary number to a negative twos complement
number by inverting all bits and adding 1: 11011000.
OFFSET AND GAIN ADJUSTMENT WORKED
EXAMPLE
11011000 is the value that should be programmed to the
offset register.
Using the information provided in the Theory of Operation
section, the following worked example demonstrates how the
AD5765 functions can be used to eliminate both offset and gain
errors. Because the AD5765 is factory calibrated, offset and gain
errors should be negligible. However, errors can be introduced
by the system that the AD5765 is operating within; for example,
a voltage reference value that is not equal to 2.048 V introduces
a gain error. An output range of 4.096 V and twos complement
data coding are assumed.
Note that this twos complement conversion is not
necessary in the case of a positive offset adjustment. The
value to be programmed to the offset register is simply the
binary representation of the adjustment value.
Removing Gain Error
The AD5765 can eliminate a gain error at negative full-scale
output in the range of −2 mV to +1.94 mV with a step size of ½
of a 16-bit LSB.
Removing Offset Error
The AD5765 can eliminate an offset error in the range of −2 mV to
+1.98 mV with a step size of ⅛ of a 16-bit LSB.
1. Calculate the step size of the gain adjustment.
8.192
216 × 2
1. Calculate the step size of the offset adjustment.
Gain Adjust StepSize =
= 62.5 μV
8.192
216 × 8
Offset Adjust StepSize =
= 15.625 μV
2. Measure the gain error by programming 0x8000 to the data
register and measuring the resulting output voltage. The
gain error is the difference between this value and −4.096 V;
for this example, the gain error is −0.8 m V.
2. Measure the offset error by programming 0x0000 to the
data register and measuring the resulting output voltage;
for this example, the measured value is 614 µV.
3. Calculate the number of offset adjustment steps that this
value represents.
3. Calculate how many gain adjustment steps this value
represents.
Measured Gain Value 0.8 mV
Number of Steps =
=
= 13 Steps
Measured Offset Value
Offset Step Size
614 μV
Gain Step Size
62.5 μV
Number of Steps =
=
= 13 Steps
15.625 μV
The gain error measured is negative (in terms of magnitude);
therefore, a positive adjustment of 13 steps is required. The gain
register is six bits wide and the coding is twos complement.
The required gain register value can be determined as follows:
1. Convert the adjustment value to binary: 001101.
The offset error measured is positive; therefore, a negative
adjustment of 40 steps is required. The offset register is 8-bits
wide and the coding is twos complement.
The required offset register value can be calculated as follows:
1. Convert the adjustment value to binary: 00101000.
The value to be programmed to the gain register is simply
this binary number.
Rev. C | Page 22 of 28
Data Sheet
AD5765
DESIGN FEATURES
If the ISCC pin is left unconnected, the short-circuit current
ANALOG OUTPUT CONTROL
limit defaults to 5 mA. It should be noted that limiting the
short-circuit current to a small value can affect the slew rate of
the output when driving into a capacitive load; therefore, the
value of the short-circuit current programmed should take into
account the size of the capacitive load being driven.
In many industrial process control applications, it is vital that
the output voltage be controlled during power-up and during
brownout conditions. When the supply voltages are changing,
the output pins are clamped to 0 V via a low impedance path.
To prevent the output amp being shorted to 0 V during this
time, transmission gate G1 is also opened (see Figure 28). These
conditions are maintained until the power supplies stabilize and
a valid word is written to the DAC register. At this time, G2
opens and G1 closes.
DIGITAL I/O PORT
The AD5765 contains a 2-bit digital I/O port (D1 and D0).
These bits can be configured as inputs or outputs independently
and can be driven or have their values read back via the serial
interface. The I/O port signals are referenced to DVCC and DGND.
When configured as outputs, they can be used as control signals
to multiplexers or can be used to control calibration circuitry
elsewhere in the system. When configured as inputs, the logic
signals from limit switches, for example, can be applied to D0
and D1 and can be read back via the digital interface.
Both transmission gates are also externally controllable via the
RSTIN
RSTIN
input is
reset logic (
) control input. For instance, if
RSTIN
is
driven from a battery supervisor chip, the
driven low to open G1 and close G2 on power-down or during a
brownout. Conversely, the on-chip voltage detector output
RSTOUT
(
) is also available to the user to control other parts of
DIE TEMPERATURE SENSOR
the system. The basic transmission gate functionality is shown
in Figure 28.
The on-chip die temperature sensor provides a voltage output
that is linearly proportional to the centigrade temperature scale.
Its nominal output voltage is 1.44 V at +25°C die temperature,
varying at 3 mV/°C and resulting in a typical output range of
1.175 V to 1.9 V over the full temperature range. Its low output
impedance and linear output simplify interfacing to temperature
control circuitry and ADCs. The temperature sensor is provided
as more of a convenience than a precise feature; it is intended to
indicate a die temperature change for recalibration purposes.
RSTOUT
RSTIN
VOLTAGE
MONITOR
AND
CONTROL
G1
VOUTA
AGNDA
G2
LOCAL-GROUND-OFFSET ADJUSTMENT
Figure 28. Analog Output Control Circuitry
The AD5765 incorporates a local-ground-offset adjustment
feature that, when enabled in the function register, adjusts the
DAC outputs for voltage differences between the individual
DAC ground pins and the REFGND pin, ensuring that the DAC
output voltages are always referenced with respect to the local
DAC ground pin. For instance, if Pin AGNDA is at +5 mV with
respect to the REFGND pin and VOUTA is measured with
respect to AGNDA, a −5 mV error results, enabling the local-
ground-offset adjustment feature to adjust VO U TA by + 5 m V,
thereby eliminating the error.
DIGITAL OFFSET AND GAIN CONTROL
The AD5765 incorporates a digital offset adjustment function
with a 16 LSB adjustment range and 0.125 LSB resolution. The
gain register allows the user to adjust the AD5765 full-scale
output range. The full-scale output can be programmed to
achieve full-scale ranges of 4.096 V, 4.201 V, and 4.311 V. A
fine gain trim is also provided.
PROGRAMMABLE SHORT-CIRCUIT PROTECTION
The short-circuit current of the output amplifiers can be pro-
grammed by inserting an external resistor between the ISCC
pin and PGND. The programmable range for the current is
500 µA to 10 mA, corresponding to a resistor range of 120 kΩ
to 6 kΩ. The resistor value is calculated as follows:
60
R ≈
ISC
Rev. C | Page 23 of 28
AD5765
Data Sheet
LDAC
pins are connected to DVCC during power-up, the
POWER-ON STATUS
outputs power on clamped to AGNDx and remain so until a
valid write is made to the device. Table 20 outlines the possible
output power-on states.
The AD5765 has multiple power supply and digital input pins.
It is important to consider the sequence in which the pins are
powered up to ensure that the AD5765 powers on in the
required state. The outputs power on either clamped to
AGNDx, driving 0 V, or driving negative full-scale output
Table 20. Output Power-On States
2sCOMP CLR
BIN/
LDAC
VOUT at Power-On
2sCOMP CLR
(−4.096 V), depending on how the BIN/
LDAC
,
, and
DGND
DGND
DGND
DGND
DVCC
DVCC
DVCC
DVCC
DGND
DGND
DVCC
DGND
DVCC
DGND
DVCC
DGND
DVCC
DGND
DVCC
0 V
0 V
0 V
pins are configured during power-up.
CLR
The
pin, if connected to DGND, causes the DAC registers
to be loaded with 0x0000 and the outputs to be updated;
DVCC
Clamped to AGNDx
−4.096 V
−4.096 V
−4.096 V
Clamped to AGNDx
2sCOMP
DGND
DGND
DVCC
consequently, the outputs are loaded with 0 V if BIN/
is connected to DGND or with negative full-scale (−4.096 V) if
2sCOMP
BIN/
is connected to DVCC, corresponding respectively
DVCC
to the twos complement and binary voltages for the digital code
LDAC
pin. If both the
0x0000. During power-up, the state of the
pin has an
CLR
CLR
identical effect to that of the
and
Rev. C | Page 24 of 28
Data Sheet
AD5765
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
PRECISION VOLTAGE REFERENCE SELECTION
Figure 29 shows the typical operating circuit for the AD5765.
The only external components needed for this precision 16-bit
DAC are a reference voltage source, decoupling capacitors on
the supply pins and reference inputs, and an optional short-
circuit current setting resistor. Because the device incorporates
reference buffers, it eliminates the need for an external bipolar
reference and associated buffers. This leads to an overall savings
in both cost and board space.
To achieve the optimum performance from the AD5765 over its
full operating temperature range, a precision voltage reference
must be used. Thought should be given to the selection of a
precision voltage reference. The AD5765 has two reference
inputs, REFAB and REFCD. The voltages applied to the
reference inputs are used to provide a buffered positive and
negative reference for the DAC cores. Therefore, any error in
the voltage reference is reflected in the outputs of the device.
In Figure 29, AVDD is connected to +5 V and AVSS is connected
There are four possible sources of error to consider when
choosing a voltage reference for high accuracy applications:
initial accuracy, temperature coefficient of the output voltage,
long-term drift, and output voltage noise.
to −5 V. In Figure 29, AGNDx is connected to REFGND.
+5V
10µF
ADR420
100nF
2
6
VIN
VOUT
GND
4
Initial accuracy error on the output voltage of an external refer-
ence may lead to a full-scale error in the DAC. Therefore, to
minimize these errors, a reference with low initial accuracy
error specification is preferred. Choosing a reference with an
output trim adjustment, such as the ADR430, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal. The trim adjust-
ment can also be used at temperature to trim out any error.
+5V –5V
10µF
10µF
100nF
100nF
100nF
BIN/2sCOMP
32 31 30 29 28 27 26 25
+5V
1
24
23
22
21
20
19
18
17
SYNC
SCLK
SDIN
SDO
SYNC
SCLK
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
Long-term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
2
3
4
5
6
7
8
VOUTA
VOUTB
SDIN
SDO
CLR
LDAC
D0
AD5765
LDAC
D0
VOUTC
VOUTD
The temperature coefficient of a reference output voltage affects
INL, DNL, and TUE. A reference with a tight temperature
coefficient specification should be chosen to reduce the
dependence of the DAC output voltage on ambient conditions.
D1
D1
9
10 11 12 13 14 15 16
RSTOUT
RSTIN
In high accuracy applications (which have a relatively low noise
budget), reference output voltage noise needs to be considered.
Choosing a reference with as low an output noise voltage as
practical for the system resolution required is important.
Precision voltage references such as the ADR420 (XFET® design)
produce low output noise in the 0.1 Hz to 10 Hz region.
However, as the circuit bandwidth increases, filtering the output
of the reference may be required to minimize the output noise.
10µF
100nF
NC = NO CONNECT
10µF
+5V
+5V –5V
Figure 29. Typical Operating Circuit
Table 21. Some Precision References Recommended for Use with the AD5765
Part No. Initial Accuracy (mV Max) Long-Term Drift (ppm Typ) Temp Drift (ppm/°C Max) 0.1 Hz to 10 Hz Noise (µV p-p Typ)
ADR430
ADR420
1
1
40
50
3
3
3.5
1.75
Rev. C | Page 25 of 28
AD5765
Data Sheet
LAYOUT GUIDELINES
For any circuit in which accuracy is important, careful consid-
eration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5765 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the AD5765 is in a system in which
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
The AD5765 should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on each supply located as close to the
package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF capa-
citor should have low effective series resistance (ESR) and low
effective series inductance (ESI) such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
isolated interfaces because the number of interface lines is kept
to a minimum. Figure 30 shows a 4-channel isolated interface to
the AD5765 using an ADuM1400. For more information, go to
www.analog.com.
MICRO-
ADuM14001
CONTROLLER
V
V
V
V
OA
OB
OC
OD
V
V
V
V
IA
IB
IC
ID
SERIAL CLOCK
OUT
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
TO SCLK
TO SDIN
TO SYNC
TO LDAC
SERIAL DATA
OUT
SYNC OUT
CONTROL OUT
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 30. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5765 is via a serial bus
that uses a standard protocol that is compatible with micro-
controllers and DSP processors. The communications channel
is a 3-wire (minimum) interface consisting of a clock signal, a
data signal, and a synchronization signal. The AD5765 requires
a 24-bit data-word with data valid on the falling edge of SCLK.
The power supply lines of the AD5765 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals, such as clocks, should be shielded with digital ground
to avoid radiating noise to other parts of the board and should
never be run near the reference inputs. A ground line routed
between the SDIN and SCLK lines helps reduce crosstalk
between them (this is not required on a multilayer board, which
has a separate ground plane; however, it is helpful to separate
the lines). It is essential to minimize noise on the reference
inputs because such noise couples through to the DAC output.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough on the board. A
microstrip technique is recommended but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane, and signal
traces are placed on the solder side.
For all the interfaces, the DAC output update can be done
automatically when all the data is clocked in, or it can be done
LDAC
under the control of
. The contents of the DAC register
can be read using the readback function.
AD5765 to Blackfin DSP Interface
Figure 31 shows how the AD5765 can be interfaced to an Analog
Devices, Inc., Blackfin® DSP. The Blackfin has an integrated SPI
port that can be connected directly to the SPI pins of the AD5765
and programmable I/O pins that can be used to set the state of a
LDAC
digital input such as the
pin.
ADSP-BF531
AD57651
SYNC
SPISELx
SCK
GALVANICALLY ISOLATED INTERFACE
SCLK
SDIN
MOSI
PF10
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur.
Isocouplers provide voltage isolation in excess of 2.5 kV. The
serial loading structure of the AD5765 makes it ideal for
LDAC
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 31. AD5765 to Blackfin Interface
Rev. C | Page 26 of 28
Data Sheet
AD5765
OUTLINE DIMENSIONS
1.20
MAX
0.75
0.60
0.45
9.00 BSC SQ
25
32
1
24
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
8
17
3.5°
0.15
0.05
9
16
0°
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
0.80
0.45
0.37
0.30
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ABA
Figure 32. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5765BSUZ
AD5765BSUZ-REEL7
AD5765CSUZ
AD5765CSUZ-REEL7
EVAL-AD5765EBZ
INL
2 LSB
2 LSB
1 LSB
1 LSB
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
32-Lead TQFP
32-Lead TQFP
32-Lead TQFP
32-Lead TQFP
Package Option
SU-32-2
SU-32-2
SU-32-2
SU-32-2
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. C | Page 27 of 28
AD5765
NOTES
Data Sheet
©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07249-0-10/11(C)
Rev. C | Page 28 of 28
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