AD5790 [ADI]
System Ready, 18-Bit ±1 LSB INL; 系统就绪， 18位± 1 LSB INL
| 型号： | AD5790 |
| 厂家： | 
ADI |
| 描述： | System Ready, 18-Bit ±1 LSB INL |
| 文件： | 总28页 (文件大小：594K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
System Ready, 18-Bit 1 ꢀSB ꢁIꢀ,
Voltage Output DAC
Data Sheet
AD5780
FEATURES
FUNCTIONAꢀ BꢀOCK DIAGRAM
V
V
V
REFP
CC
DD
True 18-bit voltage output DAC, 1 ꢀSB INꢀ
8 nV/√Hz output noise spectral density
0.025 ꢀSB long-term linearity error stability
0.018 ppm/°C gain error temperature coefficient
2.5 μs output voltage settling time
R
R1
FB
6.8kΩ 6.8kΩ
AD5780
A1
R
IOV
CC
FB
INV
SDIN
SCLK
SYNC
SDO
INPUT
SHIFT
18
18
18-BIT
DAC
DAC
REG
V
OUT
REGISTER
AND
CONTROL
LOGIC
3.5 nV-sec midscale glitch impulse
Integrated precision reference buffers
Operating temperature range: −40°C to +125°C
4 mm × 5 mm ꢀFCSP package
Wide power supply range of up to 16.5 V
35 MHz Schmitt triggered digital interface
1.8 V-compatible digital interface
6kΩ
LDAC
CLR
POWER-ON RESET
AND CLEAR LOGIC
RESET
DGND
V
AGND
V
REFN
SS
Figure 1.
APPꢀICATIONS
Table 1. Related Devices
Medical instrumentation
Test and measurement
Industrial control
Scientific and aerospace instrumentation
Data acquisition systems
Digital gain and offset adjustment
Power supply control
Part No.
AD5790
AD5791
AD5781
Description
20-bit, 2 LSB accurate DAC
20-bit, 1 ppm accurate DAC
18-bit, 0.5 LSB accurate DAC
AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC
AD5760 16-bit, 0.5 LSB accurate DAC
GENERAꢀ DESCRIPTION
The AD57801 is a true 18-bit, unbuffered voltage output DAC
that operates from a bipolar supply of up to 33 V. The AD5780
accepts a positive reference input range of 5 V to VDD − 2.5 V
and a negative reference input range of VSS + 2.5 V to 0 V. Both
reference inputs are buffered on chip and external buffers are
not required. The AD5780 offers a relative accuracy specifica-
tion of 1 LSB maximum range, and operation is guaranteed
monotonic with a 1 LSB DNL maximum range specification.
PRODUCT HIGHꢀIGHTS
1. True 18-bit accuracy.
2. Wide power supply range of up to 1ꢀ.5 V.
3. −40°C to +125°C operating temperature range.
4. Low 8 nV/√Hz noise.
5. Low 0.018 ppm/°C gain error temperature coefficient.
COMPANION PRODUCTS
Output Amplifier Buffer: AD8ꢀ75, ADA4898-1, ADA4004-1
External Reference: ADR445
The part uses a versatile 3-wire serial interface that operates at
clock rates of up to 35 MHz and is compatible with standard
SPI, QSPI™, MICROWIRE™, and DSP interface standards. The
part incorporates a power-on reset circuit that ensures that the
DAC output powers up to 0 V in a known output impedance
state and remains in this state until a valid write to the device
takes place. The part provides an output clamp feature that
places the output in a defined load state.
DC-to-DC Design Tool: ADIsimPower™
Additional companion products on the AD5780 product page
1 Protected by U.S. Patent No. 7,884,747 and 8,089,380.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
AD5780
Data Sheet
TABꢀE OF COITEITS
Features .............................................................................................. 1
DAC Architecture....................................................................... 19
Serial Interface............................................................................ 19
Hardware Control Pins.............................................................. 20
On-Chip Registers...................................................................... 21
AD5780 Features ............................................................................ 24
Power-On to 0 V......................................................................... 24
Configuring the AD5780 .......................................................... 24
DAC Output State ...................................................................... 24
Output Amplifier Configuration.............................................. 24
Applications Information.............................................................. 2ꢀ
Typical Operating Circuit ......................................................... 2ꢀ
Evaluation Board........................................................................ 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Companion Products....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 19
REVISION HISTORY
3/12—Rev. B to Rev. C
Changes to Data Sheet Title and added Patent 8,089,380........... 1
2/12—Rev. A to Rev. B
Deleted Linearity Compensation Section ................................... 24
12/11—Rev. 0 to Rev. A
Edits to Table 2.................................................................................. 3
Changes to Figure 48...................................................................... 17
Changes to DAC Register Section................................................ 21
Changes to Table 10 and Table 11 ................................................ 22
11/11—Revision 0: Initial Version
Rev. C | Page 2 of 28
Data Sheet
AD5780
SPECꢁFꢁCATꢁOIS
VDD = 12.5 V to 1ꢀ.5 V, VSS = −1ꢀ.5 V to −12.5 V, VREFP = 10 V, VREFN = −10 V, VCC = 2.7 V to 5.5 V, IOVCC = 1.71 V to 5.5 V,
RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted.
Table 2.
A, B Versions1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE2
Resolution
Integral Nonlinearity Error (Relative
Accuracy)
18
−0.85
Bits
LSB
+0.85
B grade, VREFP = +10 V, VREFN = −10 V,
TA = 25°C
−1
−2
−0.25
−1
+1
+2
+0.75
+1
LSB
LSB
LSB
LSB
B grade, VREFx
A grade, VREFx
B grade, VREFx
A grade, VREFx
=
=
=
=
10 V, +10 V, and +5 V
10 V, +10 V, and +5 V
10 V, +10 V, and +5 V
10 V, +10 V, and +5 V
Differential Nonlinearity Error
Long-Term Linearity Error Stability3
Full-Scale Error
0.025
0.95
0.675
0.45
LSB
LSB
LSB
LSB
After 750 hours at TA = 135°C
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
−3
−5.5
−10
+3
+0.5
+10
VREFP = 5 V, VREFN = 0 V
Full-Scale Error Temperature Coefficient
Zero-Scale Error
0.026
0.325
0.175
0.225
0.025
ppm/°C
LSB
LSB
LSB
ppm/°C
VREFP = +10 V, VREFN = −10 V
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
VREFP = 5 V, VREFN = 0 V
VREFP = +10 V, VREFN = −10 V
−4.8
−10
−20.5
+4.8
+10
+20.5
Zero-Scale Error Temperature
Coefficient
Gain Error
−19
−35
−68
2.3
1.9
0.9
0.018
0.015
+19
+35
+68
ppm FSR
ppm FSR
ppm FSR
ppm/°C
%
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
VREFP = 5 V, VREFN = 0 V
Gain Error Temperature Coefficient
R1, RFB Matching
VREFP = +10 V, VREFN = −10 V
OUTPUT CHARACTERISTICS
Output Voltage Range
VREFN
VREFP
V
Output Voltage Settling Time
2.5
μs
10 V step to 0.02%, using the ADA4898-1
buffer in unity-gain mode
3.5
8
8
μs
500 code step to 1 LSB4
Output Noise Spectral Density
nV/√Hz
nV/√Hz
μV p-p
At 1 kHz, DAC code = midscale
At 10 kHz, DAC code = midscale
DAC code = midscale, 0.1 Hz to
10 Hz bandwidth
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
Output Voltage Noise
1.1
Midscale Glitch Impulse4
14
3.5
4
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kΩ
VREFP = 5 V, VREFN = 0 V
MSB Segment Glitch Impulse4
14
3.5
4
57
0.27
3.4
6
VREFP = +10 V, VREFN = −10 V, see Figure 43
VREFP = 10 V, VREFN = 0 V, see Figure 44
VREFP = 5 V, VREFN = 0 V, see Figure 45
On removal of output ground clamp
Output Enabled Glitch Impulse
Digital Feedthrough
DC Output Impedance (Normal Mode)
DC Output Impedance (Output
Clamped to Ground)
kΩ
Rev. C | Page 3 of 28
AD5780
Data Sheet
A, B Versions1
Typ
Parameter
Min
Max
Unit
Test Conditions/Comments
REFERENCE INPUTS
VREFP Input Range
VREFN Input Range
Input Bias Current
5
VDD − 2.5
0
+20
+4
V
V
nA
VSS + 2.5
−20
−4
−0.63
−0.63
1
TA = 0°C to 105°C
VREFP, VREFN
Input Capacitance
pF
LOGIC INPUTS
Input Current5
Input Low Voltage, VIL
−1
+1
μA
V
0.3 × IOVCC
IOVCC = 1.71 V to 5.5 V
IOVCC = 1.71 V to 5.5 V
Input High Voltage, VIH
0.7 × IOVCC
V
Pin Capacitance
5
3
pF
LOGIC OUTPUT (SDO)
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage Current
0.4
1
V
V
μA
pF
IOVCC = 1.71 V to 5.5 V, sinking 1 mA
IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
IOVCC − 0.5
High Impedance Output Capacitance
POWER REQUIREMENTS
All digital inputs at DGND or IOVCC
VDD
VSS
VCC
7.5
VDD − 33
2.7
VSS + 33
−2.5
5.5
V
V
V
IOVCC
1.71
5.5
V
IOVCC ≤ VCC
IDD
ISS
ICC
IOICC
10.3
−10
600
52
7.5
1.5
90
14
mA
mA
μA
μA
μV/V
μV/V
dB
dB
−14
900
140
SDO disabled
∆VDD 10%, VSS = −15 V
∆VSS 10%, VDD = 15 V
∆VDD 200 mV, 50 Hz/60 Hz, VSS = −15 V
∆VSS 200 mV, 50 Hz/60 Hz, VDD = 15 V
DC Power Supply Rejection Ratio
AC Power Supply Rejection Ratio
90
1 Temperature range: −40°C to +125°C, typical conditions: TA = 25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V.
2 Performance characterized with the AD8675ARZ output buffer.
3 Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified.
4 The AD5780 is configured in the unity-gain mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead
capacitance, and so forth).
5 Current flowing in an individual logic pin.
Rev. C | Page 4 of 28
Data Sheet
AD5780
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
ꢀimit1
Parameter
Unit
Test Conditions/Comments
IOVCC = 1.71 V to 3.3 V
IOVCC = 3.3 V to 5.5 V
2
t1
40
92
15
9
28
60
10
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns min
ns typ
ns min
SCLK cycle time
SCLK cycle time (readback and daisy-chain modes)
SCLK high time
t2
t3
t4
SCLK low time
5
5
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge hold time
Minimum SYNC high time
t5
2
2
t6
48
8
40
6
t7
SYNC rising edge to next SCLK falling edge ignore
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
t8
t9
9
7
7
12
13
20
14
130
130
50
140
0
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
10
16
11
130
130
50
140
0
LDAC falling edge to output response time
SYNC rising edge to output response time (LDAC tied low)
CLR pulse width low
CLR pulse activation time
SYNC falling edge to first SCLK rising edge
65
62
0
60
45
0
ns max SYNC rising edge to SDO tristate (CL = 50 pF)
ns max SCLK rising edge to SDO valid (CL = 50 pF)
ns min
ns typ
ns typ
SYNC rising edge to SCLK rising edge ignore
RESET pulse width low
35
150
35
150
RESET pulse activation time
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes.
Rev. C | Page 5 of 28
AD5780
Data Sheet
t1
t7
SCLK
1
2
24
t3
t2
t6
t4
t5
SYNC
SDIN
t9
t8
DB23
DB0
t12
t10
t11
LDAC
t13
V
V
OUT
OUT
t14
t15
CLR
t16
V
OUT
t21
RESET
t22
V
OUT
Figure 2. Write Mode Timing Diagram
t20
t1
t17
t7
SCLK
1
2
24
1
2
24
t3
t2
t6
t17
t5
t5
t4
SYNC
SDIN
t9
t8
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
t18
t19
DB23
DB0
SDO
REGISTER CONTENTS CLOCKED OUT
Figure 3. Readback Mode Timing Diagram
Rev. C | Page 6 of 28
Data Sheet
AD5780
t20
t1
t17
SCLK
26
1
2
24
25
48
t3
t2
t6
t5
t4
SYNC
SDIN
t9
t8
DB23
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N – 1
t19
INPUT WORD FOR DAC N
t18
DB0
DB23
DB0
SDO
INPUT WORD FOR DAC N
UNDEFINED
Figure 4. Daisy-Chain Mode Timing Diagram
Rev. C | Page 7 of 28
AD5780
Data Sheet
ABSOꢀUTE MAXꢁMUM RATꢁIGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
VDD to AGND
VSS to AGND
VDD to VSS
VCC to DGND
IOVCC to DGND
Rating
−0.3 V to +34 V
−34 V to +0.3 V
−0.3 V to +34 V
−0.3 V to +7 V
−0.3 V to VCC + 3 V or +7 V
(whichever is less)
This device is a high performance integrated circuit with an
ESD rating of 1.ꢀ kV, and it is ESD sensitive. Proper precautions
must be taken for handling and assembly.
Digital Inputs to DGND
−0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
ESD CAUTION
VOUT to AGND
VREFP to AGND
VREFN to AGND
DGND to AGND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
VSS − 0.3 V to +0.3 V
−0.3 V to +0.3 V
Operating Temperature Range, TA
Industrial
Storage Temperature Range
Maximum Junction Temperature,
TJ max
−40°C to +125°C
−65°C to +150°C
150°C
Power Dissipation
LFCSP Package
(TJ max − TA)/θJA
θJA Thermal Impedance
Lead Temperature
Soldering
31.0°C/W
JEDEC industry standard
J-STD-020
ESD (Human Body Model)
1.6 kV
Rev. C | Page 8 of 28
Data Sheet
AD5780
PꢁI COIFꢁGURATꢁOI AID FUICTꢁOI DESCRꢁPTꢁOIS
AGND
1
2
3
4
5
6
7
19
18
17
16
15
14
V
OUT
V
V
SS
REFP
V
V
SS
DD
AD5780
V
TOP VIEW
RESET
V
REFN
(Not to Scale)
DGND
SYNC
DD
CLR
13 SCLK
LDAC
NOTES
TO THIS PIN.
SS
1. DNC = DO NOT CONNECT. DO NOT CONNECT
2. NEGATIVE ANALOG SUPPLY CONNECTION (V ).
A VOLTAGE IN THE RANGE OF –16.5 V TO –2.5 V
CAN BE CONNECTED. V SHOULD BE DECOUPLED
SS
RICALLY
TO AGND. THE PADDLE CAN BE LEFT ELECT
UNCONNECTED PROVIDED THAT A SUPPLY
CONNECTION IS MADE AT THE VSS PINS. IT IS
RECOMMENDED THAT THE PADDLE BE THERMAL
LY
CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic
Description
1
2
3, 5
VOUT
VREFP
VDD
Analog Output Voltage.
Positive Reference Voltage Input. A voltage in the range of 5 V to VDD − 2.5 V can be connected to this pin.
Positive Analog Supply Connection. A voltage in the range of 7.5 V to 16.5 V can be connected to this pin. VDD must be
decoupled to AGND.
4
6
RESET
CLR
Active Low Reset. Asserting this pin returns the AD5780 to its power-on status.
Active Low Input. Asserting this pin sets the DAC register to a user defined value (see Table 12) and updates the DAC
output. The output value depends on the DAC register coding that is being used, either binary or twos complement.
7
LDAC
Active Low Load DAC Logic Input. This pin is used to update the DAC register and, consequently, the analog output.
SYNC LDAC
When tied permanently low, the output is updated on the rising edge of
. If
is held high during the write cycle,
LDAC LDAC
the input register is updated, but the output update is held off until the falling edge of
unconnected.
. Do not leave the
pin
8
9
VCC
IOVCC
Digital Supply. Voltage range is from 2.7 V to 5.5 V. VCC should be decoupled to DGND.
Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. Voltage range is from
1.71 V to 5.5 V.
10, 21,
22, 23
DNC
Do Not Connect. Do not connect to these pins.
11
12
SDO
SDIN
Serial Data Output.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the
serial clock input.
13
14
SCLK
SYNC
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at rates of up to 35 MHz.
SYNC
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. The DAC
SYNC
goes
is updated on the rising edge of
.
15
16
17, 18
DGND
VREFN
VSS
Ground Reference Pin for Digital Circuitry.
Negative Reference Voltage Input.
Negative Analog Supply Connection. A voltage in the range of −16.5 V to −2.5 V can be connected to this pin.
VSS must be decoupled to AGND.
19
20
AGND
RFB
Ground Reference Pin for Analog Circuitry.
Feedback Connection for External Amplifier. See the AD5780 Features section for further details.
Inverting Input Connection for External Amplifier. See the AD5780 Features section for further details.
Negative Analog Supply Connection (VSS). A voltage in the range of −16.5 V to −2.5 V can be connected to this pin. VSS
must be decoupled to AGND. The paddle can be left electrically unconnected provided that a supply connection is made
at the VSS pins. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal
performance.
24
INV
VSS
EPAD
Rev. C | Page 9 of 28
AD5780
Data Sheet
TYPꢁCAꢀ PERFORMAICE CHARACTERꢁSTꢁCS
0.4
0.3
0.4
AD8675 OUTPUT BUFFER
AD8675 OUTPUT BUFFER
T = 25°C
A
T
= 25°C
A
0.3
0.2
0.2
0.1
0
0.1
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
0
–0.1
–0.2
–0.3
–0.4
V
V
V
V
= +10V
= –10V
V
V
V
V
= +5V
= 0V
REFP
REFN
DD
SS
REFP
REFN
DD
SS
= +15V
= +15V
= –15V
= –15V
0
50000
100000
150000
200000
250000
300000
0
50000
100000
150000
200000
250000
300000
DAC CODE
DAC CODE
Figure 6. Integral Nonlinearity Error vs. DAC Code, 1ꢀ V Span
Figure 9. Integral Nonlinearity Error vs. DAC Code, 5 V Span, ×2 Gain Mode
0.5
0.6
AD8675 OUTPUT BUFFER
A
AD8675 OUTPUT BUFFER
= 25°C
T
= 25°C
T
A
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
V
V
V
V
= +10V
= –10V
V
V
V
V
= +10V
= 0V
REFP
REFN
DD
SS
REFP
REFN
DD
SS
= +15V
= +15V
= –15V
= –15V
0
50000
100000
150000
200000
250000
300000
0
50000
100000
150000
200000
250000
300000
DAC CODE
DAC CODE
Figure 7. Integral Nonlinearity Error vs. DAC Code, 1ꢀ V Span
Figure 1ꢀ. Differential Nonlinearity Error vs. DAC Code, 1ꢀ V Span
0.8
0.7
AD8675 OUTPUT BUFFER
= 25°C
AD8675 OUTPUT BUFFER
A
T
T
= 25°C
A
0.6
0.4
0.5
0.3
0.2
0.1
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.3
–0.5
–0.7
V
V
V
V
= +5V
= 0V
REFP
REFN
DD
SS
V
V
V
V
= +10V
= 0V
REFP
REFN
DD
SS
= +15V
= –15V
= +15V
= –15V
0
50000
100000
150000
200000
250000
300000
0
50000
100000
150000
200000
250000
300000
DAC CODE
DAC CODE
Figure 8. Integral Nonlinearity Error vs. DAC Code, 5 V Span
Figure 11. Differential Nonlinearity Error vs. DAC Code, 1ꢀ V Span
Rev. C | Page 10 of 28
Data Sheet
AD5780
0.5
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
±10V SPAN MAX DNL
+10V SPAN MAX DNL
+5V SPAN MAX DNL
±10V SPAN MIN DNL
+10V SPAN MIN DNL
+5V SPAN MIN DNL
0.4
0.3
0.2
0.1
V
V
= +15V
= –15V
DD
SS
0
AD8675 OUTPUT BUFFER
–0.1
–0.2
–0.3
V
V
V
V
= +5V
= 0V
REFP
REFN
DD
SS
AD8675 OUTPUT BUFFER
= 25°C
= +15V
= –15V
T
A
–0.05
–0.4
–40
–20
0
20
40
60
80
100
0
50000
100000
150000
200000
250000
300000
TEMPERATURE (°C)
DAC CODE
Figure 12. Differential Nonlinearity Error vs. DAC Code, 5 V Span
Figure 15. Differential Nonlinearity Error vs. Temperature
0.6
0.4
V
V
V
V
= +5V
= 0V
AD8675 OUTPUT BUFFER
= 25°C
REFP
REFN
DD
SS
T
A
= +15V
= –15V
0.5
0.4
0.3
0.2
0.1
0
0.3
0.2
INL MAX
0.1
T
= 25°C
A
V
= +10V
REFP
REFN
0
V
= –10V
AD8675 OUTPUTBUFFER
–0.1
–0.2
–0.3
–0.4
INL MIN
15.0
–0.1
–0.2
0
50000
100000
150000
200000
250000
300000
12.5
13.0
13.5
14.0
14.5
15.5
16.0
16.5
DAC CODE
V
/|V | (V)
DD SS
Figure 13. Differential Nonlinearity Error vs. DAC Code, 5 V Span,
×2 Gain Mode
Figure 16. Integral Nonlinearity Error vs. Supply Voltage, 1ꢀ V Span
±10V SPAN MAX INL
+10V SPAN MAX INL
+5V SPAN MAX INL
±10V SPAN MIN INL
+10V SPAN MIN INL
+5V SPAN MIN INL
0.7
0.5
0.4
INL MAX
0.2
0.3
T
= 25°C
A
0
–0.2
–0.4
–0.6
V
= 5V
REFP
REFN
V
= 0V
0.1
AD8675 OUTPUTBUFFER
–0.1
–0.3
–0.5
INL MIN
V
V
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
40 60 80 100
TEMPERATURE (°C)
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
–40
–20
0
20
V
DD SS
Figure 17. Integral Nonlinearity Error vs. Supply Voltage, 5 V Span
Figure 14. Integral Nonlinearity Error vs. Temperature
Rev. C | Page 11 of 28
AD5780
Data Sheet
0.35
0.30
0.25
4
3
T
V
V
= 25°C
A
= 5V
DNL MAX
REFP
REFN
= 0V
AD8675 OUTPUT BUFFER
2
0.20
0.15
0.10
0.05
0
T
V
V
= 25°C
A
= +10V
= –10V
REFP
REFN
1
AD8675 OUTPUT BUFFER
0
–1
–2
DNL MIN
–0.05
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
V
/|V | (V)
V
DD SS
DD SS
Figure 18. Differential Nonlinearity Error vs. Supply Voltage, 1ꢀ V Span
Figure 21. Zero-Scale Error vs. Supply Voltage, 5 V Span
0.35
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
T
V
V
= 25°C
A
DNL MAX
= +10V
= –10V
REFP
REFN
0.30
AD8675 OUTPUT BUFFER
0.25
0.20
0.15
0.10
0.05
0
T
V
V
= 25°C
A
= 5V
= 0V
REFP
REFN
AD8675 OUTPUT BUFFER
DNL MIN
–0.05
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
V
/|V | (V)
V
DD SS
DD SS
Figure 22. Midscale Error vs. Supply Voltage, 1ꢀ V Span
Figure 19. Differential Nonlinearity Error vs. Supply Voltage, 5 V Span
0.5
2.0
1.5
T
V
V
= 25°C
A
= +10V
0.4
0.3
REFP
REFN
= –10V
AD8675 OUTPUT BUFFER
1.0
0.2
0.5
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
–1.0
–1.5
–2.0
T
V
V
= 25°C
A
= 5V
REFP
REFN
= 0V
AD8675 OUTPUT BUFFER
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
V
/|V | (V)
V
DD SS
DD SS
Figure 2ꢀ. Zero-Scale Error vs. Supply Voltage, 1ꢀ V Span
Figure 23. Midscale Error vs. Supply Voltage, 5 V Span
Rev. C | Page 12 of 28
Data Sheet
AD5780
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.50
T
V
V
= 25°C
A
= +10V
= –10V
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
REFP
REFN
AD8675 OUTPUT BUFFER
T
= 25°C
A
V
V
= 5V
REFP
= 0V
REFN
AD8675 OUTPUT BUFFER
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
V
V
/|V | (V)
DD SS
DD SS
Figure 27. Gain Error vs. Supply Voltage, 5 V Span
Figure 24. Full-Scale Error vs. Supply Voltage, 1ꢀ V Span
1.5
1.0
0.3
0.2
T
V
V
= 25°C
A
INL MAX
= 5V
REFP
REFN
= 0V
AD8675 OUTPUT BUFFER
0.5
0.1
0
0
T
V
V
= 25°C
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
A
= +15V
= –15V
DD
SS
–0.1
–0.2
–0.3
–0.4
AD8675 OUTPUT BUFFER
INL MIN
8.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
9.0
9.5 10.0
V
V
| (V)
DD SS
REFP
REFN
Figure 25. Full-Scale Error vs. Supply Voltage, 5 V Span
Figure 28. Integral Nonlinearity Error vs. Reference Voltage
0.35
0.25
0.30
T
V
V
= 25°C
A
INL MAX
= +10V
= –10V
REFP
REFN
0.25
0.20
0.15
0.10
0.05
0
AD8675 OUTPUT BUFFER
0.15
T
V
V
= 25°C
A
= +15V
= –15V
DD
SS
0.05
AD8675 OUTPUT BUFFER
–0.05
–0.15
–0.25
INL MIN
7.5
–0.05
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
5.0
5.5
6.0
6.5
7.0
8.0
| (V)
8.5
9.0
9.5 10.0
V
/|V | (V)
V
/|V
REFP REFN
DD SS
Figure 26. Gain Error vs. Supply Voltage, 1ꢀ V Span
Figure 29. Differential Nonlinearity Error vs. Reference Voltage
Rev. C | Page 13 of 28
AD5780
Data Sheet
–1.0
–1.1
–1.2
–1.3
–1.4
–1.5
–1.6
–1.7
–1.8
–1.9
–2.0
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
T
V
V
= 25°C
= +15V
SS
T
V
V
= 25°C
= +15V
DD
A
A
DD
= –15V
= –15V
SS
AD8675 OUTPUT BUFFER
AD8675 OUTPUT BUFFER
–0.40
5.0
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
V
| (V)
V
| (V)
REFP
REFN
REFP
REFN
Figure 3ꢀ. Zero-Scale Error vs. Reference Voltage
Figure 33. Gain Error vs. Reference Voltage
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
1.8
±10V SPAN
T
V
V
= 25°C
A
+10V SPAN
+5V SPAN
= +15V
= –15V
DD
SS
1.6
1.4
1.2
1.0
0.8
0.6
AD8675 OUTPUT BUFFER
V
V
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
40 60 80 100
TEMPERATURE (°C)
–1.0
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
–40
–20
0
20
V
| (V)
REFP
REFN
Figure 34. Full-Scale Error vs. Temperature
Figure 31. Midscale Error vs. Reference Voltage
0.6
0.4
T
V
V
= 25°C
±10V SPAN
+10V SPAN
+5V SPAN
1.7
1.5
1.3
1.1
0.9
A
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
V
V
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
–40 –20 20
TEMPERATURE (°C)
0.7
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
0
40
60
80
100
V
| (V)
REFP
REFN
Figure 35. Midscale Error vs. Temperature
Figure 32. Full-Scale Error vs. Reference Voltage
Rev. C | Page 14 of 28
Data Sheet
AD5780
1.0
0.010
0.008
0.006
0.004
0.002
0
±10V SPAN
+10V SPAN
+5V SPAN
0.5
0
I
DD
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.002
–0.004
–0.006
–0.008
–0.010
I
SS
V
V
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
40 60 80 100
TEMPERATURE (°C)
–40
–20
0
20
–20
–15
–10
–5
0
5
10
15
20
V
/V (V)
DD SS
Figure 36. Zero-Scale Error vs. Temperature
Figure 39. Power Supply Currents vs. Power Supply Voltages
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
6
4
2
0
±10V SPAN
+10V SPAN
+5V SPAN
V
V
= +15V
= –15V
DD
SS
–2
–4
V
V
= +10V
= –10V
REFP
REFN
ADA4808-1 BUFFERED
LOAD = 10MΩ || 20pF
–6
–8
V
V
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
40 60 80 100
TEMPERATURE (°C)
–10
–1
0
1
2
3
4
5
–40
–20
0
20
TIME (µs)
Figure 37. Gain Error vs. Temperature
Figure 4ꢀ. Rising Full-Scale Voltage Step
6
4
900
800
700
600
500
400
300
200
100
0
IOV = 5V, LOGIC VOLTAGE
CC
INCREASING
V
V
V
V
= +15V
= –15V
DD
SS
T
= 25°C
A
= +10V
IOV = 5V, LOGIC VOLTAGE
REFP
REFN
CC
= –10V
DECREASING
ADA4808-1 BUFFERED
LOAD = 10MΩ || 20pF
IOV = 3V, LOGIC VOLTAGE
CC
2
INCREASING
IOV = 3V, LOGIC VOLTAGE
CC
0
DECREASING
–2
–4
–6
–8
–10
–1
0
1
2
3
4
5
0
1
2
3
4
5
6
TIME (µs)
LOGIC INPUT VOLTAGE (V)
Figure 41. Falling Full-Scale Voltage Step
Figure 38. IOICC vs. Logic Input Voltage
Rev. C | Page 15 of 28
AD5780
Data Sheet
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
VREFP = 5V
REFN = 0V
UNITY-GAIN MODE
ADA4898-1 OUTPUT BUFFER
RC LOW-PASS FILTER
NEGATIVE
POSITIVE
V
V
V
= +10V
= –10V
REFP
REFN
RC LOW-PASS FILTER
UNITY-GAIN MODE
ADA4898-1 OUTPUT BUFFER
0
–1
0
1
2
3
4
5
TIME (µs)
CODE
Figure 42. 5ꢀꢀ Code Step Settling Time
Figure 45. 6 MSB Segment Glitch Energy for 5 V VREF
25
V
55
45
NEGATIVE
POSITIVE
±10V SPAN
+10V SPAN
+5V SPAN
= +10V
= –10V
REFP
REFN
V
UNITY-GAIN MODE
ADA4898-1 OUTPUT BUFFER
RC LOW-PASS FILTER
20
15
10
5
POSITIVE
CODE CHANGE
NEGATIVE
CODE CHANGE
35
25
15
5
–5
–15
–25
0
–1
0
1
2
3
TIME (µs)
CODE
Figure 43. 6 MSB Segment Glitch Energy for 1ꢀ V VREF
Figure 46. Midscale Peak-to-Peak Glitch for 1ꢀ V
4.0
800
V
V
= 10V
= 0V
NEGATIVE
POSITIVE
T
= 25°C
= +15V
MIDSCALE CODE LOADED
OUTPUT UNBUFFERED
REFP
REFN
A
V
V
V
V
DD
UNITY-GAIN MODE
ADA4898-1
OUTPUT BUFFER
RC LOW-PASS FILTER
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
= –15V
600
400
SS
= +10V
= –10V
REFP
REFN
200
0
–200
–400
–600
0
1
2
3
4
5
6
7
8
9
10
TIME (Seconds)
CODE
Figure 44. 6 MSB Segment Glitch Energy for 1ꢀ V VREF
Figure 47. Voltage Output Noise, ꢀ.1 Hz to 1ꢀ Hz Bandwidth
Rev. C | Page 16 of 28
Data Sheet
AD5780
200
180
160
140
120
100
80
100
V
V
V
V
= +15V
= –15V
REFP
REFN
V
V
V
V
= +15V
DD
SS
DD
SS
= –15V
= +10V
= –10V
= +10V
REFP
REFN
= –10V
UNITY GAIN
ADA4898-1
10
60
40
20
0
1
–20
0.1
1
10
100
1k
10k
0
1
2
3
4
5
6
TIME (µs)
FREQUENCY (Hz)
Figure 49. Glitch Impulse on Removal of Output Clamp
Figure 48. Noise Spectral Density vs. Frequency
Rev. C | Page 17 of 28
AD5780
Data Sheet
TERMꢁIOꢀOGY
Relative Accuracy
Output Voltage Settling Time
Relative accuracy, or integral nonlinearity (INL), is a measure of
the maximum deviation, in LSB, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL error vs. code plot is shown in Figure ꢀ.
Output voltage settling time is the amount of time it takes for
the output voltage to settle to a specified level for a specified
change in voltage. For fast settling applications, a high speed
buffer amplifier is required to buffer the load from the 3.4 kΩ
output impedance of the AD5780, in which case, it is the
amplifier that determines the settling time.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic. A
typical DNL error vs. code plot is shown in Figure 10.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-sec and is
measured when the digital input code is changed by 1 LSB at
the major carry transition (see Figure 49).
Linearity Error Long-Term Stability
Linearity error long-term stability is a measure of the stability of
the linearity of the DAC over a long period of time. It is speci-
fied in LSB for a time period of 500 hours and 1000 hours at an
elevated ambient temperature.
Output Enabled Glitch Impulse
Output enabled glitch impulse is the impulse injected into the
analog output when the clamp to ground on the DAC output is
removed. It is specified as the area of the glitch in nV-sec (see
Figure 49).
Zero-Scale Error
Zero-scale error is a measure of the output error when zero-scale
code (0x00000) is loaded to the DAC register. Ideally, the output
voltage should be VREFN. Zero-scale error is expressed in LSBs.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s, and vice versa.
Zero-Scale Error Temperature Coefficient
Zero-scale error temperature coefficient is a measure of the
change in zero-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
Total Harmonic Distortion (THD)
Full-Scale Error
Total harmonic distortion is the ratio of the rms sum of the
harmonics of the DAC output to the fundamental value. Only
the second to fifth harmonics are included.
Full-scale error is a measure of the output error when full-scale
code (0x3FFFF) is loaded to the DAC register. Ideally, the
output voltage should be VREFP − 1 LSB. Full-scale error is
expressed in LSBs.
DC Power Supply Rejection Ratio
DC power supply rejection ratio is a measure of the rejection of
the output voltage to dc changes in the power supplies applied
to the DAC. It is measured for a given dc change in power
supply voltage and is expressed in μV/V.
Full-Scale Error Temperature Coefficient
Full-scale error temperature coefficient is a measure of the
change in full-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
AC Power Supply Rejection Ratio (AC PSRR)
Gain Error
AC power supply rejection ratio is a measure of the rejection of
the output voltage to ac changes in the power supplies applied
to the DAC. It is measured for a given amplitude and frequency
change in power supply voltage and is expressed in decibels.
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed in ppm of the full-scale range.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change
in gain error with a change in temperature. It is expressed in
ppm FSR/°C.
Midscale Error
Midscale error is a measure of the output error when midscale
code (0x20000) is loaded to the DAC register. Ideally, the output
voltage should be (VREFP – VREFN)/2 + VREFN. Midscale error is
expressed in LSBs.
Rev. C | Page 18 of 28
Data Sheet
AD5780
THEORY OF OPERATꢁOI
R
R
R
The AD5780 is a high accuracy, fast settling, single, 18-bit,
serial input, voltage output DAC. It operates from a VDD supply
voltage of 7.5 V to 1ꢀ.5 V and a VSS supply of −1ꢀ.5 V to −2.5 V.
Data is written to the AD5780 in a 24-bit word format via a 3-wire
serial interface. The AD5780 incorporates a power-on reset
circuit that ensures the DAC output powers up to 0 V with the
V
OUT
...
...
...
...
2R
S1
2R
S11
2R
2R
2R
E0
2R
2R
S0
E62
E61
V
REFP
V
REFN
VOUT pin clamped to AGND through a ~ꢀ kΩ internal resistor.
12-BIT R-2R LADDER
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
DAC ARCHITECTURE
Figure 5ꢀ. DAC Ladder Structure Serial Interface
The architecture of the AD5780 consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 50.
The six MSBs of the 18-bit data-word are decoded to drive
ꢀ3 switches, E0 to Eꢀ2. Each of these switches connects one
of ꢀ3 matched resistors to either the buffered VREFP or buffered
VREFN voltage. The remaining 12 bits of the data-word drive
the S0 to S11 switches of a 12-bit voltage mode R-2R ladder
network.
SERIAꢀ INTERFACE
The AD5780 has a 3-wire serial interface (
, SCLK, and
SYNC
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see Figure 2 for a
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 35 MHz. The
W
input register consists of a R/ bit, three address bits, and
20 data bits as shown in Table ꢀ. The timing diagram for this
operation is shown in Figure 2.
Table 6. Input Shift Register Format
MSB
ꢀSB
DB23
DB22
DB21
Register address
DB20
DB19 to DB0
R/W
Register data
Table 7. Decoding the Input Shift Register
R/W
X1
0
0
0
0
1
1
Register Address
Description
0
0
0
0
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No operation (NOP). Used in readback operations.
Write to the DAC register.
Write to the control register.
Write to the clearcode register.
Write to the software control register.
Read from the DAC register.
Read from the control register.
Read from the clearcode register.
1
1 X is don’t care.
Rev. C | Page 19 of 28
AD5780
Data Sheet
Standalone Operation
AD5780*
CONTROLLER
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can be used
DATA OUT
SERIAL CLOCK
CONTROL OUT
SDIN
SCLK
SYNC
SYNC
only if
In gated clock mode, a burst clock containing the exact number
SYNC
is held low for the correct number of clock cycles.
DATA IN
SDO
of clock cycles must be used, and
the final clock to latch the data. The first falling edge of
starts the write cycle. Exactly 24 falling clock edges must be
must be taken high after
SYNC
SDIN
AD5780*
SYNC
SYNC
applied to SCLK before
is brought high again. If
is
brought high before the 24th falling SCLK edge, the data written
is invalid. If more than 24 falling SCLK edges are applied before
SCLK
SYNC
SYNC
is brought high, the input data is also invalid.
The input shift register is updated on the rising edge of
SYNC
SYNC
must be brought
.
SDO
For another serial transfer to take place,
low again. After the end of the serial data transfer, data is
automatically transferred from the input shift register to the
addressed register. When the write cycle is complete, the output
SDIN
AD5780*
LDAC
SYNC
can be updated by taking
low while
is high.
SCLK
SYNC
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. Daisy-chain mode
can be useful in system diagnostics and in reducing the number
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
of serial interface lines. The first falling edge of
write cycle. SCLK is continuously applied to the input shift register
SYNC
starts the
Figure 51. Daisy-Chain Block Diagram
Readback
when
is low. If more than 24 clock pulses are applied, the
The contents of all the on-chip registers can be read back via
the SDO pin. Table 7 outlines how the registers are decoded.
After a register has been addressed for a read, the next 24 clock
cycles clock the data out on the SDO pin. The clocks must be
data ripples out of the shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and
is valid on the falling edge. By connecting the SDO of the first
device to the SDIN input of the next device in the chain, a
multidevice interface is constructed. Each device in the system
requires 24 clock pulses. Therefore, the total number of clock
cycles must equal 24 × N, where N is the total number of
AD5780 devices in the chain. When the serial transfer to all
SYNC
SYNC
applied while
is low. When
is returned high, the
SDO pin is placed in tristate. For a read of a single register, the
NOP function can be used to clock out the data. Alternatively,
if more than one register is to be read, the data of the first
register to be addressed can be clocked out at the same time
that the second register to be read is being addressed. The SDO
pin must be enabled to complete a readback operation. The
SDO pin is enabled by default.
SYNC
devices is complete,
is taken high. This latches the input
data in each device in the daisy chain and prevents any further
data from being clocked into the input shift register. The serial
clock can be a continuous or a gated clock.
SYNC
HARDWARE CONTROꢀ PINS
A continuous SCLK source can be used only if
is held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
LDAC
Load DAC Function (
)
After data has been transferred into the input register of the
DAC, there are two ways to update the DAC register and DAC
output. Depending on the status of both
SYNC
be used, and
latch the data.
must be taken high after the final clock to
SYNC
LDAC
and
, one
In any one daisy-chain sequence, do not mix writes to the DAC
register with writes to any of the other registers. All writes to the
daisy-chained parts must be either writes to the DAC registers
or writes to the control, clearcode, or software control register.
of two update modes is selected: synchronous DAC update or
asynchronous DAC update.
Synchronous DAC Update
LDAC
In this mode,
the input shift register. The DAC output is updated on the rising
SYNC
is held low while data is being clocked into
edge of
.
Rev. C | Page 20 of 28
Data Sheet
AD5780
is high) until a new value is loaded to the DAC register. The
CLR
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see Table 13).
Asynchronous DAC Update
output cannot be updated with a new value while the
pin is
LDAC
In this mode,
into the input shift register. The DAC output is asynchronously
LDAC SYNC
is held high while data is being clocked
updated by taking
The update now occurs on the falling edge of
RESET
low after
has been taken high.
ON-CHIP REGISTERS
DAC Register
LDAC
.
Reset Function (
The AD5780 can be reset to its power-on state by two means:
RESET
)
Table 9 outlines how data is written to and read from the DAC
register.
either by asserting the
in the software control register (see Table 13). If the
is not used, hardwire it to IOVCC
pin or by using the reset function
The following equation describes the ideal transfer function of
the DAC:
RESET
pin
.
VREFP −VREFN × D
)
CLR
Asynchronous Clear Function (
)
VOUT
=
+VREFN
218
CLR
The
pin is an active low clear that allows the output to be
where:
V
V
cleared to a user defined value. The 18-bit clearcode value is
programmed to the clearcode register (see Table 12). It is
REFN is the negative voltage applied at the VREFN input pin.
REFP is the positive voltage applied at the VREFP input pin.
D is the 18-bit code programmed to the DAC.
CLR
necessary to maintain
low for a minimum amount of time
CLR
to complete the operation (see Figure 2). When the
is returned high, the output remains at the clear value (if
signal
LDAC
Table 8. Hardware Control Pins Truth Table
ꢀDAC
CꢀR
RESET
Function
X1
X1
0
0
1
X1
X1
0
1
0
1
0
1
0
0
The AD5780 is in reset mode. The device cannot be programmed.
The AD5780 is returned to its power-on state. All registers are set to their default values.
The DAC register is loaded with the clearcode register value, and the output is set accordingly.
The output is set according to the DAC register value.
The DAC register is loaded with the clearcode register value, and the output is set accordingly.
The output is set according to the DAC register value.
The output remains at the clearcode register value.
The output remains set according to the DAC register value.
The output remains at the clearcode register value.
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The output remains at the clearcode register value.
The output is set according to the DAC register value.
1 X is don’t care.
Table 9. DAC Register
MSB
ꢀSB
DB23
R/W
DB22
DB21
DB20
DB19 to DB2
DB1
DB0
Register address
0
DAC register data
18 bits of data
R/W
0
1
X1
X1
1 X is don’t care.
Rev. C | Page 21 of 28
AD5780
Data Sheet
Control Register
is asserted. The output value depends on the DAC coding that is
being used, either binary or twos complement. The default
register value is 0.
The control register controls the mode of operation of the
AD5780.
Clearcode Register
The clearcode register sets the value to which the DAC output is
set when the
pin or CLR bit in the software control register
CLR
Table 10. Control Register
MSB
ꢀSB
DB23 DB22 DB21 DB20 DB19 to DB11 DB10
DB9 DB8 DB7 DB6 DB5
Control register data
SDODIS BIN/2sC DACTRI OPGND RBUF Reserved
DB4
DB3
DB2
DB1
DB0
W
Register address
R/
R/
W
0
1
0
Reserved
Reserved
0000
Table 11. Control Register Functions
Bit Name
Reserved
RBUF
Description
These bits are reserved and should be programmed to zero.
Output amplifier configuration control.
0: the internal amplifier, A1, is powered up and Resistors RFB and R1 are connected in series as shown in Figure 54. This allows
an external amplifier to be connected in a gain of two configuration. See the AD5780 Features section for further details.
1: (default) the internal amplifier, A1, is powered down and Resistors RFB and R1 are connected in parallel, as shown in Figure 53,
so that the resistance between the RFB and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the RFB and INV
pins to be used for input bias current compensation for an external unity-gain amplifier. See the AD5780 Features section for
further details.
OPGND
Output ground clamp control.
0: the DAC output clamp to ground is removed, and the DAC is placed in normal mode.
1: (default) the DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode.
Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated. Setting
the OPGND bit to 1 in the control register overrules any write to the DACTRI bit
DACTRI
BIN/2sC
SDODIS
DAC tristate control.
0: the DAC is in normal operating mode.
1: (default) the DAC is in tristate mode.
DAC register coding selection.
0: (default) the DAC register uses twos complement coding.
1: the DAC register uses offset binary coding.
SDO pin enable/disable control.
0: (default) the SDO pin is enabled.
1: the SDO pin is disabled (tristate).
Read/write select bit.
W
R/
0: AD5780 is addressed for a write operation.
1: AD5780 is addressed for a read operation.
Table 12. Clearcode Register
MSB
ꢀSB
DB23
R/W
DB22
DB21
DB20
DB19 to DB2
DB1
DB0
Register address
1
Clearcode register data
18 bits of data
R/W
0
1
X1
X1
1 X is don’t care.
Rev. C | Page 22 of 28
Data Sheet
AD5780
Software Control Register
This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low.
Table 13. Software Control Register
MSB
ꢀSB
DB23
R/W
0
DB22
DB21
DB20
DB19 to DB3
DB2
Software control register data
Reset
CLR1
DB1
DB0
LDAC2
Register address
0
1
0
Reserved
1
LDAC
CLR
The CLR function has no effect when the
The LDAC function has no effect when the
pin is low.
pin is low.
2
Table 14. Software Control Register Functions
Bit Name
Description
LDAC
Setting this bit to 1 updates the DAC register and consequently the DAC output.
CLR
Setting this bit to 1 sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output
value depends on the DAC register coding that is being used, either binary or twos complement.
Reset
Setting this bit to 1 returns the AD5780 to its power-on state.
Rev. C | Page 23 of 28
AD5780
Data Sheet
AD5780 FEATURES
Unity-Gain Configuration
Figure 52 shows an output amplifier configured for unity gain.
POWER-ON TO 0 V
The AD5780 contains a power-on reset circuit that, as well as
resetting all registers to their default values, controls the output
voltage during power-up. Upon power-on, the DAC is placed in
tristate (its reference inputs are disconnected), and its output is
clamped to AGND through a ~ꢀ kΩ resistor. The DAC remains
in this state until programmed otherwise via the control register.
This is a useful feature in applications where it is important to
know the state of the DAC output while it is in the process of
powering up.
In this configuration, the output spans from VREFN to VREFP
.
V
REFP
R
R1
R
FB
FB
A1
AD8675,
ADA4898-1,
ADA4004-1
6.8kΩ 6.8kΩ
INV
OUT
18-BIT
DAC
V
V
OUT
CONFIGURING THE AD5780
AD5780
After power-on, the AD5780 must be configured to put it into
normal operating mode before programming the output. To
do this, the control register must be programmed. The DAC
is removed from tristate by clearing the DACTRI bit, and the
output clamp is removed by clearing the OPGND bit. At this
point, the output goes to VREFN unless an alternative value is first
programmed to the DAC register.
V
REFN
Figure 52. Output Amplifier in Unity-Gain Configuration
A second unity-gain configuration for the output amplifier is
one that removes an offset from the input bias currents of the
amplifier. It does this by inserting a resistance in the feedback
path of the amplifier that is equal to the output resistance of the
DAC. The DAC output resistance is 3.4 kΩ. By connecting R1
and RFB in parallel, a resistance equal to the DAC resistance is
available on chip. Because the resistors are all on one piece of
silicon, they are temperature coefficient matched. To enable this
mode of operation, the RBUF bit of the control register must be
set to Logic 1. Figure 53 shows how the output amplifier is
connected to the AD5780. In this configuration, the output
amplifier is in unity gain and the output spans from VREFN to
DAC OUTPUT STATE
The DAC output can be placed in one of three states, controlled
by the DACTRI and OPGND bits of the control register, as
shown in Table 15.
Table 15. Output State Truth Table
DACTRI OPGND Output State
0
0
1
1
0
1
0
1
Normal operating mode.
Output is clamped via ~6 kΩ to AGND.
Output is in tristate.
V
REFP. This unity-gain configuration allows a capacitor to be
placed in the amplifier feedback path to improve dynamic
performance.
Output is clamped via ~6 kΩ to AGND.
V
REFP
OUTPUT AMPꢀIFIER CONFIGURATION
R
FB
There are a number of different ways that an output amplifier
can be connected to the AD5780, depending on the voltage
references applied and the desired output voltage span.
R1
6.8kΩ
R
FB
10pF
6.8kΩ
V
INV
OUT
18-BIT
DAC
V
OUT
AD8675,
ADA4898-1,
ADA4004-1
AD5780
V
= 0V
REFN
Figure 53. Output Amplifier in Unity Gain with Amplifier Input Bias Current
Compensation
Rev. C | Page 24 of 28
Data Sheet
AD5780
V
REFP
Gain of Two Configuration (×2 Gain Mode)
Figure 54 shows an output amplifier configured for a gain of
two. The gain is set by the internal matched ꢀ.8 kΩ resistors,
which are exactly twice the DAC resistance, having the effect
of removing an offset from the input bias current of the external
R
R1
R
FB
FB
A1
10pF
6.8kΩ 6.8kΩ
V
INV
OUT
OUT
18-BIT
DAC
amplifier. In this configuration, the output spans from 2 × VREFN
−
V
AD8675,
ADA4898-1,
ADA4004-1
VREFP to VREFP. This configuration is used to generate a bipolar
output span from a single-ended reference input, with VREFN
=
AD5780
0 V. For this mode of operation, the RBUF bit of the control
register must be cleared to Logic 0.
V
REFN
Figure 54. Output Amplifier in Gain-of-Two Configuration
Rev. C | Page 25 of 28
AD5780
Data Sheet
APPꢀꢁCATꢁOIS ꢁIFORMATꢁOI
TYPICAꢀ OPERATING CIRCUIT
4
0 - 5
0 9 6 4 9
Figure 55. Typical Operating Circuit
Rev. C | Page 26 of 28
Data Sheet
AD5780
Figure 55 shows a typical operating circuit for the AD5780
using an AD8ꢀ75 as an output buffer. Because the output
impedance of the AD5780 is 3.4 kΩ, an output buffer is
required for driving low resistive, high capacitive loads.
populated and tested AD5780 printed circuit board (PCB). The
evaluation board interfaces to the USB port of a PC. Software is
available with the evaluation board to allow the user to easily
program the AD5780. The software runs on any PC that has
Microsoft® Windows® XP (SP2), Vista (32-bit or ꢀ4-bit), or
Windows 7 installed. The AD5780 user guide, UG-25ꢀ, is
available, which gives full details on the operation of the
evaluation board.
EVAꢀUATION BOARD
An evaluation board is available for the AD5780 to aid
designers in evaluating the high performance of the part
with minimum effort. The AD5780 evaluation kit includes a
Rev. C | Page 27 of 28
AD5780
Data Sheet
OUTꢀꢁIE DꢁMEISꢁOIS
2.75
2.65
2.50
4.00 BSC
PIN 1
PIN 1
INDICATOR
INDICATOR
(Chamfer 0.225)
20
24
19
1
0.50
BSC
5.00 BSC
3.75
3.65
3.50
EXPOSED
PAD
13
7
12
8
0.50
0.40
0.30
TOP VIEW
BOTTOM VIEW
1.00
0.90
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.30
0.25
0.20
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 5 mm Body, Very Thin Quad
(CP-24-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
INꢀ
2 LSB
2 LSB
1 LSB
1 LSB
Package Description
Package Option
AD5780ACPZ
AD5780ACPZ-REEL7
AD5780BCPZ
AD5780BCPZ-REEL7
EVAL-AD5780SDZ
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Evaluation Board
CP-24-5
CP-24-5
CP-24-5
CP-24-5
1 Z = RoHS Compliant Part.
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09649-0-3/12(C)
Rev. C | Page 28 of 28
相关型号：
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IC 2-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP32, SIDE BRAZED, CERAMIC, DIP-32, Analog to Digital Converter
ADI
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