AD6436 [ADI]
IC SPECIALTY TELECOM CIRCUIT, PQFP128, PLASTIC, TQFP-128, Telecom IC:Other;
| 型号： | AD6436 |
| 厂家： | 
ADI |
| 描述： | IC SPECIALTY TELECOM CIRCUIT, PQFP128, PLASTIC, TQFP-128, Telecom IC:Other 电信 电信集成电路 |
| 文件： | 总12页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DMT Coprocessor for
ADSL Chipset
a
AD6436
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Com ponent in Analog Devices DMT ADSL Chipset—
AD20m sp910
TO DAC
Designed to ANSI/ ETSI T1.413 (Cat 1 FDM)
Suitable for CO or Residence (ATU-R and ATU-C)
Perform s All DMT Functions and Operations:
QAM Encoding and Decoding Operations
Tone Reordering and Scaling
INTERPOLATE
& FILTER
IFFT
512/64PT
TX SERIAL
RX SERIAL
16
QAM
DIGITAL FILTER
ENCODE/
DECODE
16
FFT
512/64PT
DECIMATE, FILTER
& EQUALIZE
FROM ADC
FFT for Receive (512/ 64 Point at RT/ CO)
Inverse FFT on Transm ission (512/ 64 Point)
Frequency and Tim e Dom ain Equalization (FDQ and
TDQ)
CONTROL LOGIC
DSP PORT
Digital Filters (Interpolation and Decim ation)
128-Lead TQFP
–40؇C to +85؇C
3.3 V Operation, 600 m W
GENERAL D ESCRIP TIO N
T he AD6436 is part of the Analog Devices ADSL chipset, the
AD20msp910. It accompanies the AD6435 (Interface and
Framer), AD6437 (single-chip analog front end) and ADSP-
2183 (control and DSP). Object code is also supplied. Offering
a flexible, standard based approach (designed to ANSI T 1.413,
Category 1 FDM) with low total bill of materials and high per-
formance, the chipset offers a straightforward approach to real-
izing an ADSL modem.
The AD6436 is a dedicated DMT accelerator, implementing
transmit (QAM encode, IFFT , filtering and interpolation filter-
ing) and receive (decimation, filtering and equalization, FFT
and QAM decode) operations.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
AD6436–SPECIFICATIONS
P aram eter
Value
Com m ents
TRANSMIT DAC PORT —DAT A WIDT H
16-Bit
T RANSMIT DAC PORT —RAT E
CO Mode
17.664 MHz, 8.832 MHz,
4.416 MHz
RT Mode
2.208 MHz, 1.104 MHz,
552 kHz
RECEIVE ADC PORT —DAT A WIDT H
RECEIVE ADC PORT —RAT ES
DOWNST REAM FFT /IFFT
UPST REAM FFT /IFFT
16-Bit
8.832 MHz or 2.208 MHz
512 Points
At Either CO or RT
256 T ones
64 Points
32 T ones
BIT S/CARRIER (MAX)
16
This is more than the fifteen required by ANSI T 1.413.
Both T ransmit and Receive
INT ERFACE T O AD6435/AD6438
Serial 35.328 MHz
POWER SUPPLIES
VDD
3.3 V ± 10%
PDISS
600 mW
T EMPERAT URE RANGE
–40°C to +85°C
Specifications are subject to change without notice.
Timing Specifications
P aram eter
D escription
Typ
Units
TX Tim ing
tT X-S
tT X-H
Setup T ime of T X [15:0] from Rising Edge of T X_CLK
Hold T ime of T X [15:0] from Rising Edge of T X_CLK
12
12
ns
ns
TX_CLK
VALID
tTX-S
DATA
tTX-H
TX[15:0]
Figure 1. TX Tim ing
P aram eter
D escription
Typ
Units
RX Tim ing
tRX-S
tRX-H
Setup T ime of RX [15:0] from Rising Edge of RX_CLK
Hold T ime of RX [15:0] from Rising Edge of RX_CLK
5
0
ns
ns
RX_CLK
VALID
tRX-S
DATA
tRX-H
RX[15:0]
Figure 2. RX Tim ing
–2–
REV. 0
AD6436
P aram eter
D escription
Typ
Units
TX Ser ial I/F Tim ing
tT FRM-S
tT FRM-H
tT DREQ-S
tT DREQ-H
tT BS-S
tT BS-H
tT D_S
tT D_H
Setup T ime of T X_FRM from Falling Edge of T X_RX_SCLK
Hold T ime of T X_FRM from Falling Edge of T X_RX_SCLK
Setup T ime of T X_DREQ from Rising Edge of T X_RX_SCLK
Hold T ime of T X_DREQ from Rising Edge of T X_RX_SCLK
Setup T ime of T X_BS from Rising Edge of T X_RX_SCLK
Hold T ime of T X_BS from Rising Edge of T X_RX_SCLK
Setup T ime of T X_SDAT A from Rising Edge of T X_RX_SCLK
Hold T ime of T X_SDAT A from Rising Edge of T X_RX_SCLK
5
15
5
15
10
0
ns
ns
ns
ns
ns
ns
ns
ns
5
0
TX_RX_SCLK
TX_FRM
tTFRM-S tTFRM-H
TX_DREQ
tTDREQ-S tTDREQ-H
TX_BS
tTBS-S tTBS-H
TX_SDATA
VALID
tTD-S
DATA
tTD-H
Figure 3. TX Serial I/F Tim ing
P aram eter
D escription
Typ
Units
RX Ser ial I/F Tim ing
tRFRM-S
tRFRM-H
tRDREQ-S
tRDREQ-H
tRBS-S
tRBS-H
tRD-S
tRD-H
Setup T ime of RX_FRM from Falling Edge of T X_RX_SCLK
Hold T ime of RX_FRM from Falling Edge of T X_RX_SCLK
Setup T ime of RX_DREQ from Rising Edge of T X_RX_SCLK
Hold T ime of RX_DREQ from Rising Edge of T X_RX_SCLK
Setup T ime of RX_BS from Falling Edge of T X_RX_SCLK
Hold T ime of RX_BS from Falling Edge of T X_RX_SCLK
Setup T ime of RX_SDAT A from Falling Edge of T X_RX_SCLK
Hold T ime of RX_SDAT A from Falling Edge of T X_RX_SCLK
5
15
5
0
5
15
5
15
ns
ns
ns
ns
ns
ns
ns
ns
TX_RX_SCLK
RX_FRM
tRFRM-S tRFRM-H
RX_DREQ
tRDREQ-S tRDREQ-H
RX_BS
tRBS-S tRBS-H
RX_SDATA
VALID
tRD-S
DATA
tRD-H
Figure 4. RX Serial I/F Tim ing
–3–
REV. 0
AD6436
P aram eter
Min
Max
Unit
Read O per ation
Timing Requirements:
tRDD
tAA
tRDH
NRD Low to Data Valid
A0–A13, NCS to Data Valid
Data Hold from NRD High
8
14
ns
ns
ns
0
Switching Characteristics:
tRP
NRD Pulsewidth
DSP_CLK High to NRD Low
A0–A13, NCS Setup before NRD Low
A0–A13, NCS Hold after NRD Deasserted
NRD High to NRD or NWR Low
12
3
2
5
12
ns
ns
ns
ns
ns
tCRD
tASR
tRDA
tRWR
16
NOTE:
DSP clock 28 MHz (35.7 ns)
DSP_CLK
A0–A13
NCS
NRD
tRDA
tASR
tCRD
tRP
tRWR
D
tRDD
tRDH
tAA
NWR
Figure 5. Read Operation
–4–
REV. 0
AD6436
P aram eter
Min
Max
Unit
Wr ite O per ation
Switching Characteristics:
tDW
tDH
tWP
tWDE
tASW
tDDR
tCWR
tAW
Data Setup before NWR High
Data Hold after NWR High
NWR Pulsewidth
NWR Low to Data Enabled
A0–A13, NCS Setup before NWR Low
Data Disable before NWR or NRD Low
DSP_CLK High to NWR Low
A0–A13, NCS, Setup before NWR Deasserted
A0–A13, NCS Hold after NWR Deasserted
NWR High to NRD or NWR Low
10
6
12
0
2
1
3
17
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16
tWRA
tWWR
12
NOTE:
DSP clock 28 MHz (35.7 ns)
DSP_CLK
A0–A13
NCS
tWRA
NWR
tWWR
tASW
tWP
tAW
tDH
tDDR
tCWR
D
tDW
tWDE
NRD
Figure 6. Write Operation
REV. 0
–5–
AD6436
ABSO LUTE MAXIMUM RATINGS*
ELECTRICAL SP ECIFICATIO NS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Operating T emperature Range (Ambient) . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (5 sec) T QFP . . . . . . . . . . . . . . . . +280°C
P aram eter
Typ Value
Com m ents*
VOH
VOL
VIH
VIL
IIH
VDD–0.4 V dc
0.4 V dc
2.0 V dc
1.0 V dc
±500 nA
±500 nA
At IOH = –0.5 mA
At IOL = +1.0 mA
VIN = VDD = 3.6 V
VIN = 0 V, VDD = 3.6 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
IIL
*VDD = 3.3 V dc ± 10%.
O RD ERING GUID E
Model
Tem perature Range
P ackage D escription
P ackage O ption
AD6436
–40°C to +85°C
128-Lead Plastic T hin Quad Flatpack
ST -128
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6436 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6–
REV. 0
AD6436
P IN D ESCRIP TIO N
T he AD6436 is a 128-lead T QFP. It contains 93 signal pins, 37 output pins, 40 input pins, 16 bidirectional pins and 28 supply pins.
P IN FUNCTIO N D ESCRIP TIO NS
P in No.
P in Nam e
Type
D escription
1–3, 34, 35,
63–71, 99
NC
Not Connected Pins.
4–6, 9–12,
A(13:0)
VDD
Input
14-Bit Address Bus for DSP Port.
14, 17–21, 128
7, 15, 23, 30,
41, 51, 62, 72,
78, 87, 95, 104,
114, 125
Supply
T hese pins supply 3.3 V power to the AD6436.
8, 16, 22, 29,
37, 42, 52, 61,
73, 79, 86, 94,
105, 115, 124
GND
Ground
Input
T hese pins supply ground for the AD6436.
13
DSP_CLK
T his comes from the DSP and is used to direct the register ports and
for accessing the RAMs.
24
RX_FRM
RX_SDAT A
RX_DREQ
RX_BS
Output
Output
Input
Frame Pulse for RX Serial Port.
Serial Data for RX Serial Port.
25
26
Data Request for RX Serial Port.
Byte Strobe for RX Serial Port.
27
Output
Output
Output
Input
28
T X_RX_SCLK
T X_FRM
T X_SDAT A
T X_BS
Serial Clock for T X and RX Serial Ports.
Frame Pulse for T X Serial Port.
Serial Data for T X Serial Port.
31
32
33
Input
Byte Strobe for T X Serial Port.
36
T X_DREQ
MCLK
Output
Input
Data Request for T X Serial Port.
Master Clock for AD6436 (35.328 MHz).
Mode Pin, 1 = RT Mode; 0 = CO Mode.
Output Clock Used to Qualify Valid Data for DAC.
16-Bit Output for T ransmit DAC.
T est Pin.
38
39
RT _NCO
T X_CLK
T X(15:0)
T EST
Input
40
Output
Output
Output
Output
Input
43–50, 53–60
74
75
RX_CLK
RX(15:0)
Output Clock Used to Qualify Valid Data for ADC.
16-Bit Input from receive ADC.
76, 77, 80–85,
88–93, 96, 97
98, 100, 101
T ST _CT L[2:0]
D(15:0)
Input
I/O
T est Control Pins. T hese pins are for ADI internal use only. T hey
should be tied low.
102, 103,
16-Bit Data Bus from DSP Port.
106–113, 116–121
122
123
126
127
NRESET
NWR
Input
Input
Input
Input
Reset Pin, Active Low.
Write Strobe from DSP Port, Active Low.
Read Strobe from DSP Port, Active Low.
Chipset from DSP Port, Active Low.
NRD
NCS
REV. 0
–7–
AD6436
P IN CO NFIGURATIO N
128-Lead TQFP
102
101
100
99
98
97
96
95
94
NC
NC
NC
A1
1
2
D15
PIN 1
IDENTIFIER
TST_CTL2
TST_CTL1
NC
3
4
TST_CTL0
5
A2
A3
6
RX0
RX1
VDD
VDD
7
GND
A4
8
GND
9
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
10
A5
RX2
RX3
RX4
RX5
RX6
RX7
VDD
GND
A6 11
12
A7
DSP_CLK 13
A8 14
VDD
15
GND
16
17
A9
AD6436
DME
A10 18
RX8
19
20
A11
A12
RX9
TOP VIEW
(Not to Scale)
RX10
RX11
RX12
RX13
GND
VDD
A13 21
GND
22
VDD
23
24
25
26
27
RX_FRM
RX_SDATA
RX_DREQ
RX_BS
RX14
RX15
RX_CLK
TEST
GND
TX_RX_SCLK 28
GND
29
VDD
30
VDD
TX_FRM 31
32
TX_SDATA
TX_BS 33
NC
NC
70 NC
69
68
34
NC
NC
NC 35
TX_DREQ 36
GND 37
67 NC
66
NC
65 NC
MCLK 38
NC = NO CONNECT
–8–
REV. 0
AD6436
INTRO D UCTIO N
T he AD 6436 is one of the IC s that make up the
second generation ADSL chipset. T he other portions within
the AD20msp910 chipset are the AD6435 (which connects to
the AD6436, and is responsible for error correction, interleaving
and elastic store/framing operations), the AD6437 analog front-
end IC, the AD816 driver/receiver and ADSP-2183, which is
used as the system control processor. An object code license for
all modem software is supplied with the AD20msp910 chipset.
PAYLOAD DATA IN
PAYLOAD DATA OUT
ELASTIC STORE
EOC
REMOVE
EOC INSERT
SYNC
FRAMER
CRC
FRAMER
AD6435 DTIR
CRC
DETECT
RAM
ARBITRATION
SCRAMBLER
UNSCRAMBLE
T he AD6436 performs the QAM encoding and decoding opera-
tions, the frequency domain equalization (FDQ), the FFT and
IFFT operations. It also implements a number of digital filter
operations including interpolation/decimation and time-domain
equalization (T DQ). It is designed to process up to 256 down-
stream tones (although in a typical system only those numbered
28–255 will be used) and 32 upstream ones (although in a typi-
cal implementation only Numbers 8–27 will be used). It is de-
signed to Category 1 of the ANSI/ET SI standard and relies on
frequency division multiplexing (FDM) to separate the up-
stream and downstream signals.
FEC
DECODE
FEC
ENCODE
INTERLEAVER
DE-INTERLEAVER
RAM
TONE
REORDER
TONE
SHUFFLE
CONSTELLATION
ENCODE
CONSTELLATION
DECODE
AD6436 DME
Although the AD6436 is designed as part of the AD20msp910
ADSL chipset, it is suitable for use in other multitone (DMT or
OFDM) communication systems.
INVERSE
FFT
FFT
DECIMATE
& TDQ
T his data sheet gives a user’s description of the AD6436. It
describes functionality and interfacing, but does not give any
details of the internal structure.
INTERPOLATE
When used as part of the AD20msp910 ADSL chipset, this
internal functionality is under the control of the firmware sup-
plied with the ADSP-2183, and the Messaging Protocol (MP)
implemented there. T his protocol supplies a hardware-neutral
method of controlling the operation of the ADSL chipset, which
will be compatible between different hardware implementations.
SERIAL DAC
(TO VCXO)
CONTROL
ADC
DAC
AD6437 AFIC
FILTER
FILTER
PGA
RECEIVER
DRIVER
POTS
SPLITTER
AD6436
HYBRID
TX_DREQ
TX_BS
TX(15:0)
TX_CLK
POTS
TO AD6437
TX_SDATA
TX_FRM
AD816
DRIVER/RECEIVER
LINE
RX(15:0)
RX_CLK
TX_RX_SCLK
TO AD6435
RX_DREQ
RX_BS
Figure 8. AD20m sp910 System Block Diagram
RX_SDATA
RX_FRM
FUNCTIO NAL D ESCRIP TIO N
MCLK
RT_NCO
NRESET
T he AD6436 consists of six major blocks: a QAM encoder/
decoder block, an FFT block, an IFFT block, a DFIC block, a
DSP port control block and a clock control block.
TO ADSP-2183
DAC I/F
ADC I/F
IFFT
FFT
TX SERIAL
PORT
QAM
Figure 7. Functional Pin Diagram
DFIC
BLOCK
RX SERIAL
PORT
ENCODE/
DECODE
DSP PORT
CONTROL
CLOCK
CONTROL
DSP
PORT
Figure 9. Block Diagram
REV. 0
–9–
AD6436
Q AM Encoder /D ecoder
TX SERIAL P O RT
T he QAM block handles the QAM encoding and decoding of
data. It corresponds to the “T one Ordering” and “Constellation
encoder and gain scaling” blocks in the T 1.413 reference model.
T he T X serial interface between the AD6436 and AD6435/
AD6438 uses five (5) signals:
T X_RX_SCLK: Serial clock provided by AD6436.
Data is received from the AD6435/AD6438 at 35.328 MHz as a
serial stream, and is fed to the encoder buffer. T his block is
responsible for the encoding, bin allocation and tone reordering
operations. Each subcarrier (from 0 to 255) can handle from 0
to 16 bits, with the density controlled by the bin allocation. T his
block also handles the pilot tone insertion (Bin 64 in CO mode
and Bin 16 in the RT ).
T X_DREQ:
T X_FRAME:
T X_BS:
Data request provided by AD6436.
Frame strobe provided by AD6436.
Byte strobe provided by AD6435/AD6438.
Serial data provided by AD6435/AD6438.
T X_SDAT A:
This is a byte protocol. The AD6436 raises TX_DREQ to request
data (ref T0). The AD6435/AD6438 samples the TX_DREQ on
its rising clock and when seen, outputs a one clock byte strobe
T X_BS (ref T 1) and simultaneously places Bit 0 of the byte
on the T X_SDAT A pin. T hen on the next seven rising clocks
the AD6435/AD6438 places Bits 1 through 7 on the TX_SDATA
pin. On the next rising clock, the T X_DREQ line is again
sampled (ref T 5), and if high, and another byte is ready to
transmit, outputs the byte strobe coincident with the first bit of
the next byte, then proceeds to output the reset of the byte in
successive clock cycles. If T X_DREQ were low, or another byte
was not available yet, the byte strobe would not be output, and
T X_DREQ would continue to be sampled on successive rising
clock edges while waiting for available data. T he AD6435/
AD6438 is free to place Bit 0 of a byte on the T X_SDAT A pin
even if the AD6436 will not be taking it, as long as the byte
strobe is not pulsed. Once the byte strobe is pulsed for Bit 0, the
T X_DREQ line is ignored until all eight bits are sent.
T he QAM decoder is very similar, recovering the data from the
subcarriers and reversing the tone ordering and bit allocation
operations. It also operates the same way in CO and RT mode.
T he receive serial interface between the QAM decoder and the
AD6435/AD6438 operates at 35.328 MHz.
IFFT Block
T he IFFT block performs a 512-point inverse FFT in CO mode
(transmitting the downstream data) and a 64-point inverse FFT
in RT mode (transmitting the upstream data). It also imple-
ments gain-scaling at this time.
While the data is read out of the IFFT block and into the DFIC,
the cyclic prefix is added to the transmit path. T he purpose of
the cyclic prefix is to make the symbol appear periodic in nature
to the receiver. T he IFFT produces 512 real data samples in
CO mode, to which 32 samples are added, and 64 real data
samples in RT mode, to which four are added.
T he AD6436, once T X_DREQ is raised, leaves T X_DREQ
high and samples T X_BS on successive rising edges of the
clock. Once T X_BS is seen high (ref T 2), the AD6436 knows
that Bit 0 can be sampled, followed by the remaining seven bits
on the next seven rising clocks edges (ref T 3). If desired, the
T X_DREQ can be dropped at this time. When Bit 6 is being
sampled (ref T4), the AD6436 must raise or lower the TX_DREQ
line depending on whether it knows it wants another byte imme-
diately following the current byte. This timing is needed to ensure
the AD6435/AD6438 will (or will not) see the TX_DREQ signal
as it outputs the last bit.
FFT Block
On the receive channel, the FFT block performs a 64-point
FFT in CO mode (receiving the upstream duplex data) and a
512-point FFT in RT mode (receiving the downstream simplex
data). In addition, carriers can be scaled up to provide full pre-
cision for the FDQ and QAM decode operations. After the
transform, the FFT performs the FDQ operation in the output
buffer. In addition to performing the FFT , this block also strips
off the cyclic prefixes and removes the pilot tones from the
symbol.
D igital Filter Block
T he T X_FRAME signal, which is not shown, is pulsed on the
rising edge of the AD6436 clock at the beginning of frame. T he
AD6435/AD6438 will not respond to the T X_DREQ line be-
fore the start of a frame, or after the number of data bytes pro-
grammed by the DSP has been transferred within a frame.
T his implements a variety of digital filtering operations, includ-
ing T ime Domain Equalization (T DQ) and the interpolation/
decimation tasks that connect the digital devices to the analog
stage (AD6437/AD6440).
NB D ata Width
RX SERIAL INTERFACE
T he RX serial interface between the AD6436 and AD6435/
AD6438 uses five (5) signals:
T he AD6436 uses 16-bit datapaths internally. As such, it may
be used with high resolution analog stages with up to 16-bit
resolution and take full advantage of them. T he AD6437/
AD6440—its companion part in the AD20msp910 chipset—
is only specified to 12-bit linearity.
T X_RX_SCLK: Serial clock provided by AD6436.
RX_FRAME:
RX_BS:
Frame strobe provided by AD6436.
Byte strobe provided by AD6436.
Serial data provided by AD6436.
Data request provided by AD6435/AD6438.
INTERFACE TIMING
RX_SDAT A:
RX_DREQ:
T he AD6436 contains a transmit serial port in which the
AD6435/AD6438 transmits a bit stream to the AD6436 and a
receive serial port in which AD6435/AD6438 receives a serial
bit stream from the AD6436. T he AD6436 also interfaces with
an ADC and a DAC, and has a DSP host port, which allows a
DSP to monitor the AD6436 and control the data through the
device.
This is a byte protocol. The AD6435/AD6438 raises RX_DREQ
to request data (ref T 0). T he AD6436 samples the RX_DREQ
on its rising clock and when seen, outputs a one clock byte
strobe RX_BS (ref T 1), and at the same time places Bit 0 of the
byte on the RX_SDAT A pin. T hen on the next seven rising
clocks the AD6435/AD6438 places Bits 1 through 7 on the
RX_SDAT A pin. As the last bit is output, the RX_DREQ line is
–10–
REV. 0
AD6436
again sampled (ref T 5), and if high, and another byte is ready to
transmit, outputs the byte strobe coincident with the first bit of
the next byte, then proceeds to output the remainder of the byte
in successive clock cycles. If RX_DREQ were low, or another
byte not yet available, the byte strobe would not be output, and
RX_DREQ would continue to be sampled on successive rising
clock edges while waiting for available data. T he AD6436 is free
to place Bit 0 of the next byte on the pin even if RX_DREQ is
low, as long the byte strobe is not pulsed. Once the byte strobe
is pulsed for Bit 0, the RX_DREQ line is ignored until all eight
bits are sent.
The AD6435/AD6438, once RX_DREQ is raised, leaves RX_DREQ
high and samples RX_BS on successive falling edges of the
clock. Once RX_BS is seen high (ref T 2), the AD6435/AD6438
samples Bit 0 and knows that the data bits can be sampled on
the next seven falling clocks edges (ref T 3). If desired, the
RX_DREQ can be dropped at this time. When Bit 7 is being
sampled (ref T 4), the AD6435/AD6438 must raise or lower the
RX_DREQ line depending on whether it knows it wants another
byte immediately following the current byte. T his timing is
needed to ensure the AD6436 will (or will not) see the RX_DREQ
signal on the rising edge after the last bit.
AD6436 VIEW
TX_RX_SCLK
TX_DREQ
TX_BS
TX_SDATA
B0
B1
B2
B5
B6
B7
T5
B0
T0
T1
T2
T3
T4
AD6435/AD6438 VIEW
TX_SCLK
TX_DREQ
TX_BS
TX_SDATA
B0
B1
B2
B5
B6
B7
B0
TX_RX_SCLK
TX_DREQ
TX_FRAME
TX_DS
DTIR
DME
TX_SDATA
Figure 10. AD6436–AD6435/AD6438 Interface—Transm it
AD6436 VIEW
TX_RX_SCLK
RX_DREQ
RX_BS
RX_SDATA
B0
T2
B1
T3
B2
B5
B6
B7
T5
B0
T0
T1
T4
AD6435/AD6438 VIEW
RX_SCLK
RX_DREQ
RX_BS
RX_SDATA
B0
B1
B2
B5
B6
B7
B0
TX_RX_SCLK
RX_DREQ
RX_FRAME
RX_DS
DTIR
DME
RX_SDATA
Figure 11. AD6436–AD6435/AD6438 Interface—Receive
–11–
REV. 0
AD6436
T he RX_FRAME signal, which is not shown, is pulsed on the
rising edge of the AD6436 clock at the beginning of frame. T he
AD6435/AD6438 will not raise the RX_DREQ line before the
start of a frame, or after the number of data bytes programmed
by the DSP has been received within a frame.
AD C INTERFACE
T he AD6436 can accept sixteen bits from an A/D converter.
T he sample rate for both RT and CO mode is 8.832 MH z
normally, but can optionally be 2.208 MH z. A signal called
RX_CLK is provided to qualify when the A/D converter needs
to provide valid data.
D AC INTERFACE
All 16 bits are valid, but if the ADC has fewer bits, it is the most
significant bits of the word should be connected to the ADC
(i.e., when connecting the AD6436 to the AD6437, Bits D0 to
D3 should be tied to ground). T hese bits will be used in future,
higher precision, analog stages.
T he AD6436 provides sixteen bits to an A/D converter. Sample
rates of 17.664 MHz, 8.832 MHz and 4.416 MHz can be sent
out in CO mode. In RT mode, rates of 2.208 MHz, 1.104 MHz
and 552 kHz can be sent out in RT mode. T he sample rate is
determined by the setting of the programmable down sampler in
the DFIC.
D SP P O RT
Accompanying the 16-bit data is a clock, T X_CLK, to qualify
when the data is valid.
T he DSP port consist of:
A 14-Bit Address Bus, A[13:0]
All 16 bits are valid, but if the DAC has fewer bits, it is the most
significant bits of the word that should be connected to the
DAC (i.e., when connecting the AD6436 to the AD6437, Bits
D0 and D1 should be left NC). T hese bits will be used in fu-
ture, higher precision, analog stages.
A 16-Bit Data Bus, D[15:0]
T hree Bus Control Pins, NRD, NWR, NCS.
T he DSP port allows a 2183 DSP to access the AD6436.
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
128-Lead P lastic Thin Q uad Flatpack
(ST-128)
0.063 (1.60)
TYP
0.630 (16.00) BSC
0.551 (14.00) BSC
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
128
1
103
102
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.787 0.866
(20.00) (22.00)
BSC
BSC
0.003 (0.08)
MAX
38
65
64
39
0.006 (0.15)
0.002 (0.05)
0.011 (0.27)
0.020 (0.50)
BSC
0.009 (0.22)
0.007 (0.17)
0.057 (1.45)
0.053 (1.40)
0.018 (1.35)
–12–
REV. 0
相关型号：
AD644JH
DUAL OP-AMP, 3500uV OFFSET-MAX, 2MHz BAND WIDTH, MBCY8, HERMETIC SEALED, METAL CAN, TO-99, 8 PIN
ROCHESTER
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