AD706KN [ADI]
Dual Picoampere Input Current Bipolar Op Amp; 双Picoampere输入电流双极运算放大器
| 型号： | AD706KN |
| 厂家： | 
ADI |
| 描述： | Dual Picoampere Input Current Bipolar Op Amp |
| 文件： | 总8页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Picoampere Input
Current Bipolar Op Amp
a
AD706
FEATURE
CO NNECTIO N D IAGRAM
HIGH DC PRECISION
P lastic Mini-D IP (N)
Cerdip (Q) and
P lastic SO IC (R) P ackages
50 V m ax Offset Voltage
0.6 V/ ؇C m ax Offset Drift
110 pA m ax Input Bias Current
LOW NOISE
0.5 V p-p Voltage Noise, 0.1 Hz to 10 Hz
AMPLIFIER 1
AMPLIFIER 2
AD706
OUTPUT
–IN
1
2
3
4
8
7
6
5
V؉
LOW POWER
750 A Supply Current
Available in 8-Lead Plastic Mini-DlP, Herm etic Cerdip
and Surface Mount (SOIC) Packages
Available in Tape and Reel in Accordance w ith
EIA-481A Standard
OUTPUT
–IN
؉IN
V–
؉IN
TOP VIEW
Single Version: AD705, Quad Version: AD704
PRIMARY APPLICATIONS
Low Frequency Active Filters
Precision Instrum entation
Precision Integrators
T he AD706 is offered in three varieties of an 8-lead package:
plastic mini-DIP, hermetic cerdip and surface mount (SOIC).
“J” grade chips are also available.
P RO D UCT D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD706 is a dual, low power, bipolar op amp that has the
low input bias current of a BiFET amplifier, but which offers a
significantly lower IB drift over temperature. It utilizes superbeta
bipolar input transistors to achieve picoampere input bias cur-
rent levels (similar to FET input amplifiers at room tempera-
ture), while its IB typically only increases by 5× at 125°C (unlike
a BiFET amp, for which IB doubles every 10°C for a 1000×
increase at 125°C). T he AD706 also achieves the microvolt
offset voltage and low noise characteristics of a precision bipolar
input amplifier.
1. T he AD706 is a dual low drift op amp that offers BiFET
level input bias currents, yet has the low IB drift of a bipolar
amplifier. It may be used in circuits using dual op amps such
as the LT 1024.
2. T he AD706 provides both low drift and high dc precision.
3. T he AD706 can be used in applications where a chopper
amplifier would normally be required but without the
chopper’s inherent noise.
100
Since it has only 1/20 the input bias current of an OP07, the
AD706 does not require the commonly used “balancing” resis-
tor. Furthermore, the current noise is 1/5 that of the OP07,
which makes this amplifier usable with much higher source
impedances. At 1/6 the supply current (per amplifier) of the
OP07, the AD706 is better suited for today’s higher density
boards.
10
TYPICAL JFET AMP
1
T he AD706 is an excellent choice for use in low frequency
active filters in 12- and 14-bit data acquisition systems, in preci-
sion instrumentation and as a high quality integrator. T he
AD706 is internally compensated for unity gain and is available
in five performance grades. T he AD706J and AD706K are rated
over the commercial temperature range of 0°C to +70°C. T he
AD706A and AD706B are rated over the industrial temperature
range of –40°C to +85°C.
0.1
AD706
0.01
–55
+25
+110
+125
TEMPERATURE – ؇C
Figure 1. Input Bias Current vs. Tem perature
REV. C
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
(@ T = +25؇C, V = 0 V and ؎15 V dc, unless otherwise noted)
A
CM
AD706–SPECIFICATIONS
AD 706J/A
Typ
AD 706K/B
Typ
P aram eter
Conditions
Min
Max
Min
Max
Units
INPUT OFFSET VOLT AGE
Initial Offset
Offset
vs. T emp, Average T C
vs. Supply (PSRR)
T MIN to T MAX
30
40
0.2
132
126
0.3
100
150
1.5
10
25
0.2
132
126
0.3
50
100
0.6
µV
µV
µV/°C
dB
dB
T MIN to T MAX
VS = ±2 V to ±18 V
VS = ±2.5 V to ±18 V
110
106
112
108
Long T erm Stability
µV/Month
INPUT BIAS CURRENT 1
VCM = 0 V
VCM = ±13.5 V
50
200
250
30
110
160
pA
pA
vs. T emp, Average T C
T MIN to T MAX
T MIN to T MAX
0.3
0.2
pA/°C
pA
pA
VCM = 0 V
VCM = ±13.5 V
300
400
200
300
INPUT OFFSET CURRENT
VCM = 0 V
VCM = ±13.5 V
30
150
250
30
100
200
pA
pA
vs. T emp, Average T C
T MIN to T MAX
T MIN to T MAX
0.6
80
80
0.4
80
80
pA/°C
pA
pA
VCM = 0 V
VCM = ±13.5 V
250
350
200
300
MAT CHING CHARACT ERIST ICS
Offset Voltage
150
250
300
500
75
µV
µV
pA
pA
dB
dB
dB
dB
T MIN to T MAX
T MIN to T MAX
T MIN to T MAX
150
150
250
Input Bias Current2
Common-Mode Rejection
Power Supply Rejection
106
106
106
104
110
108
110
106
T MIN to T MAX
@ f = 10 Hz
RL = 2 kΩ
Crosstalk
(Figure 19a)
150
150
dB
FREQUENCY RESPONSE
Unity Gain Crossover
Frequency
0.8
0.15
0.15
0.8
0.15
0.15
MHz
V/µs
V/µs
Slew Rate
G = –1
T MIN to T MAX
INPUT IMPEDANCE
Differential
Common Mode
40ʈ2
300ʈ2
40ʈ2
300ʈ2
MΩʈpF
GΩʈpF
INPUT VOLT AGE RANGE
Common-Mode Voltage
Common-Mode Rejection
Ratio
±13.5
±14
±13.5
±14
V
VCM = ±13.5 V
T MIN to T MAX
110
108
132
128
114
108
132
128
dB
dB
INPUT CURRENT NOISE
INPUT VOLT AGE NOISE
0.1 Hz to 10 Hz
f = 10 Hz
3
50
3
50
pA p-p
fA/√Hz
0.1 Hz to 10 Hz
f = 10 Hz
f = 1 kHz
0.5
17
15
0.5
17
15
1.0
22
µV p-p
nV/√Hz
nV/√Hz
22
OPEN-LOOP GAIN
VO = ±12 V
RLOAD = 10 kΩ
T MIN to T MAX
VO = ±10 V
200
150
2000
1500
400
300
2000
1500
V/mV
V/mV
RLOAD = 2 kΩ
T MIN to T MAX
200
150
1000
1000
300
200
1000
1000
V/mV
V/mV
OUT PUT CHARACT ERIST ICS
Voltage Swing
RLOAD = 10 kΩ
T MIN to T MAX
Short Circuit
±13
±13
±14
±14
±15
±13
±13
±14
±14
±15
V
V
mA
Current
Capacitive Load
Drive Capability
Gain = +1
10,000
10,000
pF
REV. C
–2–
AD706
AD 706J/A
Typ
AD 706K/B
Typ
P aram eter
Conditions
Min
Max
Min
Max
Units
POWER SUPPLY
Rated Performance
Operating Range
±15
±15
V
V
mA
mA
±2.0
±18
1.2
1.4
±2.0
±18
1.2
1.4
Quiescent Current, T otal
0.75
0.8
0.75
0.8
T MIN to T MAX
T RANSIST OR COUNT
NOT ES
# of T ransistors
90
90
lBias current specifications are guaranteed maximum at either input.
2Input bias current match is the difference between corresponding inputs (I B of –IN of Amplifier # 1 minus IB of –IN of Amplifier # 2).
∆VOS # 1
∆VOS # 2
CMRR match is the difference between
for amplifier # 1 and
for amplifier # l and
for amplifier # 2 expressed in dB.
for amplifier # 2 expressed in dB.
∆V
∆V
CM
CM
∆VOS # 1
∆VSUPPLY
∆VOS # 2
∆VSUPPLY
PSRR match is the difference between
All min and max specifications are guaranteed.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGSl
O RD ERING GUID E
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation
Tem perature
Range
P ackage
O ption*
(T otal: Both Amplifiers)2 . . . . . . . . . . . . . . . . . . . . 650 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage3 . . . . . . . . . . . . . . . . . . . . +0.7 Volts
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage T emperature Range (Q) . . . . . . . . . –65°C to +150°C
Storage T emperature Range (N, R) . . . . . . . –65°C to +125°C
Operating T emperature Range
Model
D escription
AD706AN
AD706JN
AD706KN
AD706JR
–40°C to +85°C Plastic DIP
N-8
N-8
N-8
R-8
0°C to +70°C
0°C to +70°C
0°C to +70°C
Plastic DIP
Plastic DIP
SOIC
AD706JR-REEL 0°C to +70°C
T ape and Reel
AD706AQ
AD706BQ
AD706AR
–40°C to +85°C Cerdip
–40°C to +85°C Cerdip
–40°C to +85°C SOIC
Q-8
Q-8
R-8
AD706J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD706A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead T emperature (Soldering 10 secs) . . . . . . . . . . . . +300°C
AD706AR-REEL –40°C to +85°C T ape and Reel
NOT ES
*N = Plastic DIP; Q = Cerdip, R = Small Outline Package.
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
METALIZATIO N P H O TO GRAP H
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
8-Lead Plastic Package: θJA = 100°C/Watt
1
OUTPUT A
8-Lead Cerdip Package: θJA = 110°C/Watt
+V
8-Lead Small Outline Package: θJA = 155°C/Watt
8
S
3T he input pins of this amplifier are protected by back-to-back diodes. If the
differential voltage exceeds ±0.7 volts, external series protection resistors should
be added to limit the input current to less than 25 mA.
2
–INPUT A
+INPUT A
OUTPUT B
7
3
6
5
–INPUT B
+INPUT B
–V
S
4
0.074 (1.88)
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD706 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
AD706–Typical Characteristics(@ +25؇C, V = ؎15 V, unless otherwise noted)
S
1000
800
600
400
200
0
1000
800
600
400
200
0
1000
800
600
400
200
0
SAMPLE
SIZE: 3000
SAMPLE SIZE: 2400
SAMPLE
SIZE: 5100
–80
–40
0
40
80
–160
–80
0
80
160
–120
–60
0
60
120
INPUT OFFSET VOLTAGE – V
INPUT BIAS CURRENT – pA
INPUT OFFSET CURRENT – pA
Figure 2. Typical Distribution of Input
Offset Voltage
Figure 3. Typical Distribution of
Input Bias Current
Figure 4. Typical Distribution of
Input Offset Current
؉V
35
30
25
20
15
10
5
100
S
–0.5
–1.0
–1.5
SOURCE RESISTANCE
MAY BE EITHER BALANCED
OR UNBALANCED
10
FOR INDUSTRIAL
TEMPERATURE
RANGE
؉1.5
؉1.0
؉0.5
1.0
–V
S
0
0.1
1k
10k
100k
1M
0
5
10
15
20
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
SOURCE RESISTANCE – ⍀
SUPPLY VOLTAGE – ؎Volts
Figure 5. Input Com m on-Mode
Voltage Range vs. Supply Voltage
Figure 6. Large Signal Frequency
Response
Figure 7. Offset Voltage Drift vs.
Source Resistance
4
3
60
200
SAMPLE SIZE: 375
–55؇C TO ؉125؇C
40
160
120
80
40
0
POSITIVE I
20
B
0
2
1
0
–20
NEGATIVE I
B
–40
–60
0
1
2
3
4
5
–15 –10
–5
0
5
10
15
–0.8
–0.4
0
0.4
0.8
OFFSET VOLTAGE DRIFT – V/؇C
WARM-UP TIME – Minutes
COMMON-MODE VOLTAGE – Volts
Figure 8. Typical Distribution of
Offset Voltage Drift
Figure 9. Change in Input Offset
Voltage vs. Warm -Up Tim e
Figure 10. Input Bias Current vs.
Com m on-Mode Voltage
–4–
REV. C
AD706
1000
100
10
1000
100
10
0.5V
100⍀
10k⍀
20M⍀
VOUT
1
1
5
0
10
1
10
100
1000
1
10
100
1000
TIME – Seconds
FREQUENCY – Hz
FREQUENCY – Hz
Figure 11. Input Noise Voltage
Spectral Density
Figure 12. Input Noise Current
Spectral Density
Figure 13. 0.1 Hz to 10 Hz Noise
Voltage
1000
900
+160
+140
+120
+100
+80
+60
+40
+20
0
180
160
140
120
100
800
+125؇C
– PSRR
80
+25؇C
+ PSRR
60
40
20
700
–55؇C
600
0
5
10
15
20
0.1
1
10
100 1k
10k 100k 1M
0.1
1
10
100 1k
10k 100k 1M
SUPPLY VOLTAGE – ؎ Volts
FREQUENCY – Hz
FREQUENCY – Hz
Figure 14. Quiescent Supply Current
vs. Supply Voltage
Figure 15. Com m on-Mode Rejection
Ratio vs. Frequency
Figure 16. Power Supply Rejection
Ratio vs. Frequency
0
140
120
100
80
10M
+V
S
30
–0.5
–1.0
–1.5
–55؇C
60
+25؇C
PHASE
90
+125؇C
60
120
150
180
210
240
1M
40
+1.5
+1.0
+0.5
GAIN
20
0
–V
S
–20
0.01 0.1
100k
1
2
4
6
8 10
100
1
10 100 1k 10k 100k 1M 10M
0
5
10
15
20
LOAD RESISTANCE – k⍀
FREQUENCY – Hz
SUPPLY VOLTAGE – ؎ Volts
Figure 18. Open-Loop Gain and
Phase Shift vs. Frequency
Figure 17. Open-Loop Gain vs. Load
Resistance vs. Load Resistance
Figure 19. Output Voltage Swing vs.
Supply Voltage
REV. C
–5–
AD706
–80
1000
100
10
–100
–120
–140
–160
AV = –1000
1
AV = + 1
0.1
0.01
I
= +1mA
OUT
0.001
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
Figure 20a. Crosstalk vs. Frequency
Figure 21. Magnitude of Closed-Loop Output Im pedance
vs. Frequency
+V 0.1F
S
R
F
+V
S
2
V
#1
OUT
1/2
1
0.1F
AD706
20V p-p
3
4
8
0.1F
V
OUT
R
L
2k⍀
1/2
AD706
SINE WAVE
GENERATOR
V
4
IN
R
2k⍀
–V
S
L
C
L
0.1F
20k⍀
SQUARE
WAVE
INPUT
–V
S
+V
S
Figure 22a. Unity Gain Follower (For Large Signal
Applications, Resistor RF Lim its the Current
Through the Input Protection Diodes)
1F
0.1F
2.21k⍀
8
6
5
V
#2
OUT
1/2
AD706
7
V
#2
#1
OUT
CROSSTALK = 20 LOG
–20dB
10
V
OUT
Figure 20b. Crosstalk Test Circuit
Figure 22b. Unity Gain Follower
Large Signal Pulse Response, RF =
10 kΩ, CL = 1,000 pF
Figure 22d. Unity Gain Follower
Sm all Signal Pulse Response, RF =
0 Ω, CL = 1000 pF
Figure 22c. Unity Gain Follower
Sm all Signal Pulse Response, RF =
0 Ω, CL = 100 pF
–6–
REV. C
AD706
10k⍀
+V
S
+
0.1F
10k⍀
V
–
1/2
AD706
IN
8
V
OUT
R
2.5k⍀
4
L
+
C
L
SQUARE
WAVE
0.1µF
INPUT
–V
S
Figure 23a. Unity Gain Inverter Connection
Figure 23b. Unity Gain Inverter Large
Signal Pulse Response, CL = 1,000 pF
Figure 23c. Unity Gain Inverter Sm all
Signal Pulse Response, CL = 100 pF
Figure 23d. Unity Gain Inverter Sm all
Signal Pulse Response, CL = 1000 pF
Figure 24 shows an in-amp circuit that has the obvious advan-
tage of requiring only one AD706, rather than three op amps,
with subsequent savings in cost and power consumption. T he
transfer function of this circuit (without RG) is:
increases with gain, once initial trimming is accomplished—but
CMR is still dependent upon the ratio matching of Resistors R1
through R4. Resistor values for this circuit, using the optional
gain resistor, RG, can be calculated using:
R
4
R1= R4 = 49.9 kΩ
VOUT = (V
− VIN #2 ) 1+
IN #1
R3
49.9 kΩ
R2 = R3 =
0.9 G −1
for R1 = R4 and R2 = R3
99.8 kΩ
Input resistance is high, thus permitting the signal source to
have an unbalanced output impedance.
RG =
0.06 G
where G = Desired Circuit Gain
R
(OPTIONAL)
R3
G
T able I provides practical 1% resistance values. (Note that
without resistor RG, R2 and R3 = 49.9 kΩ/G–1.)
R1
R2
R4
49.9k⍀
49.9k⍀
+V
S
Table I. O perating Gains of Am plifiers A1 and A2 and
P ractical 1% Resistor Values for the Circuit of Figure 24
0.1F
1/2
AD706
8
2
3
–
+
1
5
6
–
A1
R *
Circuit Gain Gain of A1 Gain of A2 R2, R3
R1, R4
P
A2
7
V
1/2
AD706
IN#1 1k⍀
OUTPUT
1.10
1.33
1.50
2.00
10.1
101.0
1001
11.00
4.01
3.00
2.00
1.11
1.01
1.001
1.10
1.33
1.50
2.00
10.10
101.0
1001
499 kΩ
150 kΩ
100 kΩ
49.9 kΩ 49.9 kΩ
5.49 kΩ 49.9 kΩ
49.9 kΩ
49.9 kΩ
49.9 kΩ
+
4
R *
P
0.1F
–V
V
1k⍀
S
IN#2
R4
R3
2R4
)
R
G
V
= (V
– V ) (1+
IN#2
) + (
OUT
IN#1
FOR R1 = R4, R2 = R3
499 Ω
49.9 Ω
49.9 kΩ
49.9 kΩ
*OPTIONAL INPUT PROTECTION RESISTOR FOR GAINS GREATER
THAN 100 OR INPUT VOLTAGES EXCEEDING THE SUPPLY VOLTAGE.
Figure 24. A Two Op-Am p Instrum entation Am plifier
For a much more comprehensive discussion of in-amp applica-
tions, refer to the Instrumentation Amplifier Applications Guide—
available free from Analog Devices, Inc.
Furthermore, the circuit gain may be fine trimmed using an
optional trim resistor, RG. Like the three op-amp circuit, CMR
REV. C
–7–
AD706
C1
+
+V
S
C3
R1
1M⍀
R2
1M⍀
0.1F
R3
1M⍀
R4
1M⍀
3
2
INPUT
1/2
8
1/2
AD706
–
C2
1
5
6
AD706
–
7
4
C4
OUTPUT
*WITHOUT THE NETWORK,
PINS 1 & 2, AND 6 & 7 OF THE
AD706 ARE TIED TOGETHER.
0.1F
–V
S
CAPACITORS C1 & C2
ARE SOUTHERN ELECTRONICS
MPCC, POLYCARB ؎5%, 50 VOLT
R6
2M⍀
C6
0.01F
R5
2M⍀
C5
0.01F
OPTIONAL BALANCE
RESISTOR NETWORKS*
Figure 25. A 1 Hz, 4-Pole Active Filter
A 1 H z, 4-P ole, Active Filter
180
Figure 25 shows the AD706 in an active filter application. An
important characteristic of the AD706 is that both the input bias
current, input offset current and their drift remain low over
most of the op amp’s rated temperature range. T herefore, for
most applications, there is no need to use the normal balancing
resistor. Adding the balancing resistor enhances performance at
high temperatures, as shown by Figure 26.
WITHOUT OPTIONAL
BALANCE RESISTOR, R3
120
60
0
WITH OPTIONAL BALANCE
RESISTOR, R3
–60
–120
–180
–40
0
+40
TEMPERATURE – ؇C
+80
+120
Figure 26. VOS vs. Tem perature Perform ance
of the 1 Hz Filter
Table II. 1 H z, 4-P ole, Low P ass Filter Recom m ended Com ponent Values
Section 1
Frequency
(H z)
Section 2
Frequency
(H z)
D esired Low
P ass Response
C1
(F)
C2
(F)
C3
(F)
C4
(F)
Q
Q
Bessel
Butterworth
0.1 dB Chebychev
0.2 dB Chebychev
0.5 dB Chebychev
1.0 dB Chebychev
1.43
1.00
0.648
0.603
0.540
0.492
0.522
0.541
0.619
0.646
0.705
0.785
1.60
1.00
0.948
0.941
0.932
0.925
0.806
1.31
2.18
2.44
2.94
3.56
0.116 0.107 0.160
0.172 0.147 0.416
0.304 0.198 0.733
0.341 0.204 0.823
0.416 0.209 1.00
0.508 0.206 1.23
0.0616
0.0609
0.0385
0.0347
0.0290
0.0242
NOT E
Specified Values are for a –3 dB point of 1.0 Hz. For other frequencies simply scale capacitors C1 through C4 directly, i.e.: for 3 Hz
Bessel response, C1 = 0.0387 µF, C2 = 0.0357 µF, C3 = 0.0533 µF, C4 = 0.0205 µF.
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
Cer dip
(Q -8)
SO IC
(R-8)
P lastic Mini-D IP
(N-8)
0.055 (1.4)
MAX
0.1968 (5.00)
0.1890 (4.80)
0.005 (0.13)
MIN
0.430 (10.92)
0.348 (8.84)
8
5
8
1
5
4
0.310 (7.87)
8
5
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
0.280 (7.11)
0.240 (6.10)
0.220 (5.59)
1
4
1
4
0.325 (8.25)
0.300 (7.62)
PIN 1
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.405 (10.29)
MAX
0.102 (2.59)
0.094 (2.39)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
x 45°
0.210 (5.33)
MAX
0.200 (5.08)
MAX
0.130
(3.30)
MIN
0.150
(3.81)
MIN
0.160 (4.06)
0.115 (2.93)
0.0098 (0.25)
0.0040 (0.10)
0.200 (5.08)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
8°
0°
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
SEATING
0.070 (1.78)
PLANE
0.0500 0.0192 (0.49)
(1.27)
BSC
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.0500 (1.27)
0.0160 (0.41)
0.023 (0.58)
0.100
(2.54)
BSC
15°
0°
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
0.0138 (0.35)
0.014 (0.36)
0.030 (0.76)
–8–
REV. C
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