AD7172-4_17 [ADI]
ADC with True Rail-to-Rail Buffers;型号: | AD7172-4_17 |
厂家: | ADI |
描述: | ADC with True Rail-to-Rail Buffers |
文件: | 总62页 (文件大小:848K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta
ADC with True Rail-to-Rail Buffers
AD7172-4
Data Sheet
FEATURES
GENERAL DESCRIPTION
Fast and flexible output rate: 1.25 SPS to 31.25 kSPS
Channel scan data rate of 6.21 kSPS/channel (161 μs settling)
Performance specifications
17.2 noise free bits at 31.25 kSPS
24 noise free bits at 5 SPS
INL: 2 ppm of FSR
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
User configurable input channels
4 fully differential channels or 8 single-ended channels
Crosspoint multiplexer
True rail-to-rail analog and reference input buffers
Internal or external clock
The AD7172-4 is a low noise, low power, multiplexed, Σ-Δ analog-
to-digital converter (ADC) with 4- or 8-channel (fully differential/
single-ended) inputs for low bandwidth signals. The AD7172-4
has a maximum channel scan rate of 6.21 kSPS (161 μs) for fully
settled data. The output data rates range from 1.25 SPS to 31.25 kSPS.
The AD7172-4 integrates key analog and digital signal condition-
ing blocks to allow users to configure an individual setup for
each analog input channel in use via the SPI. Integrated true rail-to-
rail buffers on the analog inputs and reference inputs provide easy
to drive high impedance inputs.
The digital filter allows simultaneous 50 Hz and 60 Hz rejection
at a 27.27 SPS output data rate. The user can switch between
different filter options according to the demands of each channel
in the application, with further digital processing functions such
as offset and gain calibration registers, which are configurable
on a per channel basis. General-purpose input/outputs (GPIOs)
control external multiplexers synchronous to the ADC conversion
timing. The specified temperature range is −40°C to +105°C.
The AD7172-4 is in a 5 mm × 5 mm, 32-lead LFCSP.
Power supply
AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V
Split supply with AVDD1 and AVSS at 2.5 V or 1.65 V
ADC current: 1.5 mA
Temperature range: −40°C to +105°C
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
Serial port interface (SPI), QSPI-, MICROWIRE-, and DSP-
compatible
Note that, throughout this data sheet, the dual function pin
names are referenced by the relevant function only.
APPLICATIONS
Process control: PLC/DCS modules
Temperature and pressure measurement
Medical and scientific multichannel instrumentation
Chromatography
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 REGCAPA REF– REF+
IOVDD REGCAPD
1.8V
CROSSPOINT
MULTIPLEXER
1.8V
LDO
RAIL-TO-RAIL
REFERENCE
INPUT
LDO
BUFFERS
RAIL-TO-RAIL
AIN0/REF2–
AIN1/REF2+
ANALOG
INPUT
AVDD
CS
BUFFERS
SCLK
DIN
SERIAL
INTERFACE
AND CONTROL
DIGITAL
Σ-∆ ADC
FILTER
DOUT/RDY
SYNC
ERROR
AIN7
AIN8
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
I/O AND EXTERNAL
MUX CONTROL
AVSS
AD7172-4
AVSS
PDSW
GPIO0 GPIO1 GPO2 GPO3
XTAL1 XTAL2/CLKIO
DGND
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD7172-4* PRODUCT PAGE QUICK LINKS
Last Content Update: 04/21/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
REFERENCE MATERIALS
Technical Articles
• Flexible Bandwidth 4 mA to 20 mA Current Input with
Easy HART Compatibility
EVALUATION KITS
Tutorials
• AD7172-4 Evaluation Board
• MT-022: ADC Architectures III: Sigma-Delta ADC Basics
DOCUMENTATION
Data Sheet
• MT-023: ADC Architectures IV: Sigma-Delta ADC
Advanced Concepts and Applications
• AD7172-4: Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta
ADC with True Rail-to-Rail Buffers Data Sheet
DESIGN RESOURCES
• AD7172-4 Material Declaration
• PCN-PDN Information
Technical Books
• The Data Conversion Handbook, 2005
User Guides
• Quality And Reliability
• Symbols and Footprints
• UG-763: Evaluating the AD7172-4 Low Power 24-Bit, 31.25
kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers
DISCUSSIONS
SOFTWARE AND SYSTEMS REQUIREMENTS
• AD717x Microcontroller No-OS
View all AD7172-4 EngineerZone Discussions.
SAMPLE AND BUY
• AD717x Eval+ Software
Visit the product page to see pricing options.
TOOLS AND SIMULATIONS
• AD7172 Digital Filter Frequency Response Model
• AD7172-4 IBIS Model
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
REFERENCE DESIGNS
• CN0292
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
• CN0364
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
AD7172-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
CRC Calculation......................................................................... 40
Integrated Functions...................................................................... 42
General-Purpose Input/Output................................................ 42
External Multiplexer Control ................................................... 42
Delay ............................................................................................ 42
16-Bit/24-Bit Conversions......................................................... 42
DOUT_RESET ........................................................................... 42
Synchronization.......................................................................... 42
Error Flags................................................................................... 43
DATA_STAT ............................................................................... 43
IOSTRENGTH ........................................................................... 43
Grounding and Layout .................................................................. 44
Register Summary .......................................................................... 45
Register Details ............................................................................... 47
Communications Register......................................................... 47
Status Register............................................................................. 48
ADC Mode Register................................................................... 49
Interface Mode Register ............................................................ 50
Register Check............................................................................ 51
Data Register............................................................................... 51
GPIO Configuration Register................................................... 52
ID Register................................................................................... 53
Channel Register 0 ..................................................................... 54
Channel Register 1 to Channel Register 7 .............................. 55
Setup Configuration Register 0 ................................................ 56
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Characteristics ................................................................ 7
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Noise Performance and Resolution.............................................. 17
Getting Started................................................................................ 18
Power Supplies ............................................................................ 19
Digital Communication............................................................. 19
AD7172-4 Reset.......................................................................... 20
Configuration Overview ........................................................... 20
Circuit Description......................................................................... 26
Buffered Analog Input ............................................................... 26
Crosspoint Multiplexer.............................................................. 26
AD7172-4 Reference.................................................................. 27
Buffered Reference Input........................................................... 28
Clock Source ............................................................................... 28
Digital Filters................................................................................... 29
Sinc5 + Sinc1 Filter..................................................................... 29
Sinc3 Filter................................................................................... 29
Single Cycle Settling................................................................... 30
Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 33
Operating Modes............................................................................ 35
Continuous Conversion Mode ................................................. 35
Continuous Read Mode............................................................. 36
Single Conversion Mode ........................................................... 37
Standby and Power-Down Modes............................................ 38
Calibration................................................................................... 38
Digital Interface .............................................................................. 39
Checksum Protection................................................................. 39
Setup Configuration Register 1 to Setup Configuration
Register 7 ..................................................................................... 57
Filter Configuration Register 0................................................. 58
Filter Configuration Register 1 to Filter Configuration
Register 7 ..................................................................................... 59
Offset Register 0 ......................................................................... 59
Offset Register 1 to Offset Register 7....................................... 59
Gain Register 0............................................................................ 60
Gain Register 1 to Gain Register 7........................................... 60
Outline Dimensions....................................................................... 61
Ordering Guide .......................................................................... 61
Rev. B | Page 2 of 61
Data Sheet
AD7172-4
REVISION HISTORY
4/2017—Rev. A to Rev. B
5/2015—Revision 0: Initial Version
Changes to Outline Dimensions ...................................................68
Changes to Ordering Guide...........................................................68
5/2016—Rev. 0 to Rev. A
Moved Revision History...................................................................3
Changes to Table 5 ............................................................................9
Changes to Figure 18 and Figure 19 .............................................13
Changes to Power Supplies Section ..............................................19
Rev. B | Page 3 of 61
AD7172-4
Data Sheet
SPECIFICATIONS
AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, MCLK = internal master
clock = 2 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR)
No Missing Codes1
Resolution
1.25
24
31,250
SPS
Bits
Excluding sinc3 filter ≥ 15 kSPS
See Table 6 and Table 7
Noise
See Table 6 and Table 7
ACCURACY
Integral Nonlinearity (INL)
Offset Error2
Offset Drift
Gain Error2
2
75
230
5
5.2
ppm of FSR
μV
nV/°C
ppm of FSR
ppm/°C
Internal short
Internal short
AVDD1 = 5 V
45
0.5
Gain Drift
0.2
REJECTION
Power Supply Rejection
Common-Mode Rejection
At DC
AVDD1, AVDD2, VIN = 1 V
VIN = 0.1 V
98
dB
95
dB
dB
At 50 Hz, 60 Hz1
20 Hz output data rate (postfilter), 50 Hz 120
1 Hz and 60 Hz 1 Hz
50 Hz 1 Hz and 60 Hz 1 Hz
Normal Mode Rejection1
Internal clock, 20 SPS ODR (postfilter)
External clock, 20 SPS ODR (postfilter)
71
85
90
90
dB
dB
ANALOG INPUTS
Differential Input Range
Absolute Voltage Limits1
Input Buffers Disabled
Input Buffers Enabled
Analog Input Current
Input Buffers Disabled
Input Current
VREF = (REF+) − (REF−)
VREF
V
AVSS − 0.05
AVSS
AVDD1 + 0.05
AVDD1
V
V
6
μA/V
Input Current Drift
Input Buffers Enabled
Input Current
Input Current Drift
Crosstalk
0.45
nA/V/°C
5.5
0.1
−120
nA
nA/°C
dB
1 kHz input
REFERENCE INPUTS
Differential Input Range
Absolute Voltage Limits1
Input Buffers Disabled
Input Buffers Enabled
REFIN Input Current
Input Buffers Disabled
Input Current
VREF = (REF+) − (REF−)
1
2.5
AVDD1
V
AVSS − 0.05
AVSS
AVDD1 + 0.05
AVDD1
V
V
9
μA/V
Input Current Drift
External clock
Internal clock
0.75
1
nA/V/°C
nA/V/°C
Input Buffers Enabled
Input Current
Input Current Drift
100
2.5
nA
nA/°C
Normal Mode Rejection1
Common-Mode Rejection
BURNOUT CURRENTS
Source/Sink Current
See the Rejection parameter
95
10
dB
μA
Analog input buffers must be enabled
Rev. B | Page 4 of 61
Data Sheet
AD7172-4
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
GPIO (GPIO0, GPIO1)
Input Mode Leakage Current1
Floating State Output
Capacitance
Output Voltage1
With respect to AVSS
−10
+10
μA
pF
5
High, VOH
Low, VOL
Input Voltage1
High, VIH
ISOURCE = 200 μA
ISINK = 800 μA
AVSS + 4
AVSS + 3
V
V
AVSS + 0.4
AVSS + 0.7
V
V
Low, VIL
CLOCK
Internal Clock
Frequency
Accuracy
Duty Cycle
Output Voltage
Low, VOL
2
MHz
%
%
−2.6%
+2.5%
0.4
50
V
V
High, VOH
Crystal
0.8 × IOVDD
14
Frequency
Startup Time
External Clock (CLKIO)
Duty Cycle1
LOGIC INPUTS
Input Voltage1
High, VINH
16
10
2
16.384
MHz
μs
MHz
%
2.048
70
30
50
2 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
2 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
IOVDD ≥ 2.7 V
0.65 × IOVDD
0.7 × IOVDD
V
V
V
V
V
V
μA
Low, VINL
0.35 × IOVDD
0.7
0.25
0.2
+10
Hysteresis1
0.08
0.04
−10
IOVDD < 2.7 V
Leakage Currents
RDY
LOGIC OUTPUT (DOUT/
Output Voltage1
High, VOH
)
IOVDD ≥ 4.5 V, ISOURCE = 1 mA
2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 μA
IOVDD < 2.7 V, ISOURCE = 200 μA
IOVDD ≥ 4.5 V, ISINK = 2 mA
2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA
IOVDD < 2.7 V, ISINK = 400 μA
Floating state
0.8 × IOVDD
0.8 × IOVDD
0.8 × IOVDD
V
V
V
V
V
V
μA
pF
Low, VOL
0.4
0.4
0.4
+10
Leakage Current
Output Capacitance
SYSTEM CALIBRATION1
−10
Floating state
10
Full-Scale (FS) Calibration Limit
Zero-Scale Calibration Limit
Input Span
1.05 × FS
2.1 × FS
V
V
V
−1.05 × FS
0.8 × FS
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 to AVSS
3.0
2
−2.75
2
5.5
5.5
0
5.5
6.35
V
V
V
V
V
AVDD2 to AVSS
AVSS to DGND
IOVDD to DGND
IOVDD to AVSS
For AVSS < DGND
Rev. B | Page 5 of 61
AD7172-4
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY CURRENTS
All outputs unloaded, digital inputs
connected to IOVDD or DGND
Full Operating Mode
AVDD1 Current
AVDD1 = 5 V Typical,
5.5 V Maximum
AIN and REF buffers disabled
0.23
0.29
2.15
mA
AIN and REF buffers enabled
Each buffer: AIN and REF
AIN and REF buffers disabled
1.7
0.38
0.15
mA
mA
mA
AVDD1 = 3.3 V Typical,
3.6 V Maximum1
0.2
1.9
AIN and REF buffers enabled
Each buffer: AIN and REF
1.45
0.33
1
0.33
0.61
0.98
32
mA
mA
mA
mA
mA
mA
μA
AVDD2 Current
IOVDD Current
1.1
0.5
0.82
External clock
Internal clock
External crystal
LDO on
Full power-down including LDO
Standby Mode
Power-Down Mode
POWER DISSIPATION
Full Operating Mode
1
10
μA
Unbuffered, external clock; AVDD1 =
3.3 V, AVDD2 = 2 V, IOVDD = 2 V
Unbuffered, external clock;
all supplies = 5 V
Unbuffered, external clock;
all supplies = 5.5 V
Fully buffered, internal clock; AVDD1 =
3.3 V, AVDD2 = 2 V, IOVDD = 2 V
Fully buffered, internal clock;
all supplies = 5 V
Fully buffered, internal clock;
all supplies = 5.5 V
All supplies = 5 V
Full power-down, all supplies = 5 V
Full power-down, all supplies = 5.5 V
3.16
7.8
mW
mW
mW
mW
mW
mW
10.4
8
16.6
22.4
55
Standby Mode
Power-Down Mode
160
5
μW
μW
μW
1 Specification is not production tested but is supported by characterization data at initial product release.
2 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale
calibration reduces the gain error to the order of the noise for the programmed output data rate.
Rev. B | Page 6 of 61
Data Sheet
AD7172-4
TIMING CHARACTERISTICS
IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Test Conditions/Comments1, 2
SCLK
t3
t4
25
25
ns min
ns min
SCLK high pulse width
SCLK low pulse width
READ OPERATION
t1
0
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
CS
RDY
falling edge to DOUT/
active time
15
40
0
12.5
25
2.5
20
0
IOVDD = 4.75 V to 5.5 V
IOVDD = 2 V to 3.6 V
SCLK active edge to data valid delay4
IOVDD = 4.75 V to 5.5 V
IOVDD = 2 V to 3.6 V
CS
Bus relinquish time after inactive edge
3
t2
t5
t6
CS
SCLK inactive edge to inactive edge
5
t7
10
RDY
SCLK inactive edge to DOUT/
high/low
WRITE OPERATION
t8
4
0
8
8
5
ns min
ns min
ns min
ns min
CS
falling edge to SCLK active edge setup time
t9
t10
t11
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS
rising edge to SCLK edge hold time
1 Sample tested during initial release to ensure compliance.
2 See Figure 2 and Figure 3.
3 This parameter is defined as the time required for the output to cross the VOL or VOH limits.
4 The SCLK active edge is the falling edge of SCLK.
5
RDY
while DOUT/
DOUT/
returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required,
RDY
is high, although care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is
enabled, the digital word can be read only once.
TIMING DIAGRAMS
CS (I)
t6
t1
t5
MSB
LSB
t7
DOUT/RDY (O)
t2
t3
SCLK (I)
t4
I = INPUT, O = OUTPUT
Figure 2. Read Cycle Timing Diagram
CS (I)
t11
t8
SCLK (I)
DIN (I)
t9
t10
MSB
LSB
I = INPUT, O = OUTPUT
Figure 3. Write Cycle Timing Diagram
Rev. B | Page 7 of 61
AD7172-4
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for a device soldered on a JEDEC test board for
surface-mount packages.
Table 3.
Parameter
Rating
AVDD1, AVDD2 to AVSS
AVDD1 to DGND
IOVDD to DGND
IOVDD to AVSS
AVSS to DGND
Analog Input Voltage to AVSS
Reference Input Voltage to AVSS
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Analog Input/Digital Input Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Lead Soldering, Reflow Temperature
ESD Rating (HBM)
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +7.5 V
−3.25 V to +0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
10 mA
−40°C to +105°C
−65°C to +150°C
150°C
260°C
4 kV
Table 4. Thermal Resistance
Package Type
θJA
Unit
32-Lead, 5 mm × 5 mm LFCSP
1-Layer JEDEC Board
4-Layer JEDEC Board
138 °C/W
63
41
°C/W
°C/W
4-Layer JEDEC Board with 9 Thermal Vias
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 8 of 61
Data Sheet
AD7172-4
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AIN0/REF2–
AIN1/REF2+
DNC
REGCAPA
AVSS
1
2
3
4
5
6
7
8
24 AIN3
23
22 GPO2
21 GPIO1
AIN2
AD7172-4
TOP VIEW
20
19
GPIO0
REGCAPD
(Not to Scale)
AVDD1
AVDD2
PDSW
18 DGND
17 IOVDD
NOTES
1. DNC = DO NOT CONNECT.
2. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON THE PCB UNDER THE
EXPOSED PAD TO CONFER MECHANICAL STRENGTH TO THE PACKAGE
AND FOR HEAT DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO
AVSS THROUGH THIS PAD ON THE PCB.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin
No.
Mnemonic
Type1 Description
1
AIN0/REF2−
AI
Analog Input 0/Reference 2 Negative Input Terminal. A reference can be applied between the REF2+ and
REF2− pins. REF2− can span from AVSS to AVDD1 − 1 V. Analog Input 0 is selectable through the crosspoint
multiplexer. Reference 2 can be selected through the REF_SELx bits in the setup configuration
(SETUPCONx) registers.
2
AIN1/REF2+
AI
Analog Input 1/Reference 2 Positive Input Terminal. A reference can be applied between the REF2+ and
REF2− pins. REF2+ can span from AVDD1 to AVSS + 1 V. Analog Input 1 is selectable through the crosspoint
multiplexer. Reference 2 can be selected through the REF_SELx bits in the setup configuration
(SETUPCONx) registers.
3
DNC
Do Not Connect. Do not connect to this pin.
4
5
6
7
8
9
REGCAPA
AVSS
AVDD1
AVDD2
PDSW
AO
P
P
P
AO
AI
Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 μF capacitor.
Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V.
Analog Supply Voltage 1. This voltage ranges from 3.0 V minimum to 5.5 V maximum with respect to AVSS.
Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS.
Power-Down Switch Connected to AVSS. This pin is controlled by the PDSW bit in the GPIOCON register.
Input 1 for Crystal.
XTAL1
10
XTAL2/CLKIO
AI/DI
Input 2 for Crystal/Clock Input or Output. See the CLOCKSEL bit settings in the ADCMODE register in Table 28 for
more information.
11
DOUT/RDY
DO
Serial Data Output/Data Ready Output. DOUT/RDY is a dual purpose pin. This pin is a serial data output pin
to access the output shift register of the ADC. The output shift register can contain data from any of the
on-chip data or control registers. The data-word/control word information is placed on the DOUT/RDY pin
on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is
tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a data ready pin, going
low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes
high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor,
indicating that valid data is available.
12
13
DIN
DI
DI
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the
control registers in the ADC, with the register address (RA) bits of the communications register identifying
the appropriate register. Data is clocked in on the rising edge of SCLK.
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK pin has a
Schmitt triggered input, making the interface suitable for opto-isolated applications.
SCLK
Rev. B | Page 9 of 61
AD7172-4
Data Sheet
Pin
No.
Mnemonic
Type1 Description
14
CS
DI
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC
in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to operate
in 3-wire mode with the SCLK, DIN, and DOUT pins interfacing with the device. When CS is high, the
DOUT/RDY output is tristated.
15
ERROR
DI/O
This pin can be used in one of the following three modes:
Active low error input mode: this mode sets the ADC_ERROR bit in the status register.
Active low, open-drain error output mode: the status register error bits are mapped to the ERROR pin. The
ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any
device can be observed.
General-purpose output mode: the status of the pin is controlled by the ERR_DAT bit in the GPIOCON register.
The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the
GPIO0 and GPIO1 pins. The ERROR pin has an active pull-up in this case.
16
17
SYNC
DI
P
Synchronization Input. This pin allows synchronization of the digital filters and analog modulators when
using multiple AD7172-4 devices.
Digital Input/Output Supply Voltage. The IOVDD voltage ranges from 2 V to 5 V. IOVDD is independent of
AVDD1 and AVDD2. For example, IOVDD can be operated at 3.3 V when AVDD1 or AVDD2 equals 5 V, or
vice versa. If AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V.
IOVDD
18
19
DGND
REGCAPD
P
AO
Digital Ground.
Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using
a 1 μF capacitor.
20
21
GPIO0
GPIO1
I/O
I/O
General-Purpose Input/Output. 0 The logic input/output on this this pin is referred to the AVDD1 and AVSS
supplies.
General-Purpose Input/Output 1. The logic input/output on this this pin is referred to the AVDD1 and AVSS
supplies.
22
23
24
25
26
27
28
29
30
31
GPO2
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GPO3
REF−
O
General-Purpose Output. The logic output on this this pin is referred to the AVDD1 and AVSS supplies.
Analog Input 2. Analog Input 2 is selectable through the crosspoint multiplexer.
Analog Input 3. Analog Input 3 is selectable through the crosspoint multiplexer.
Analog Input 4. Analog Input 4 is selectable through the crosspoint multiplexer.
Analog Input 5. Analog Input 5 is selectable through the crosspoint multiplexer.
Analog Input 6. Analog Input 6 is selectable through the crosspoint multiplexer.
Analog Input 7. Analog Input 7 is selectable through the crosspoint multiplexer.
Analog Input 8. Analog Input 8 is selectable through the crosspoint multiplexer.
General-Purpose Output. The logic output on this this pin is referred to the AVDD1 and AVSS supplies.
AI
AI
AI
AI
AI
AI
AI
O
AI
Reference 1 Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V. Reference 1 can be
selected through the REF_SELx bits in the setup configuration (SETUPCONx) registers.
32
REF+
EP
AI
P
Reference 1 Input Positive Terminal. A reference can be applied between REF+ and REF−. REF+ can span
from AVDD1 to AVSS + 1 V. Reference 1 can be selected through the REF_SELx bits in the setup
configuration (SETUPCONx) registers.
Exposed Pad. Solder the exposed pad to a similar pad on the printed circuit board (PCB) under the
exposed pad to confer mechanical strength to the package and for heat dissipation. The exposed pad must
be connected to AVSS through this pad on the PCB.
1 AI is analog input, AO is analog output, DI/O is bidirectional digital input/output, DO is digital output, DI is digital input, and P is power supply, I/O is input/output, and
O is output.
Rev. B | Page 10 of 61
Data Sheet
AD7172-4
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, TA = 25°C, unless otherwise noted.
8388492
8388490
8388488
8388486
8388484
8388482
8388480
8388478
1200
1000
800
600
400
200
0
0
200
400
600
800
1000
8388480 8388482 8388484 8388486 8388488 8388490 8388492
ADC CODE
SAMPLE NUMBER
Figure 5. Noise (Analog Input Buffers Disabled, VREF = 5 V,
Output Data Rate = 1.25 SPS)
Figure 8. Histogram (Analog Input Buffers Disabled, VREF = 5 V,
Output Data Rate = 1.25 SPS)
8388510
140
120
100
80
8388505
8388500
8388495
8388490
8388485
8388480
8388475
8388470
8388465
8388460
60
40
20
0
0
100 200 300 400 500 600 700 800 900 1000
SAMPLE NUMBER
ADC CODE
Figure 6. Noise (Analog Input Buffers Disabled, VREF = 5 V,
Output Data Rate = 2.6 kSPS)
Figure 9. Histogram (Analog Input Buffers Disabled, VREF = 5 V,
Output Data Rate = 2.6 kSPS)
8388540
100
90
80
70
60
50
40
30
20
10
0
8388530
8388520
8388510
8388500
8388490
8388480
8388470
8388460
8388450
8388440
0
100 200 300 400 500 600 700 800 900 1000
SAMPLE NUMBER
ADC CODE
Figure 7. Noise (Analog Input Buffers Disabled, VREF = 5 V,
Output Data Rate = 31.25 kSPS)
Figure 10. Histogram (Analog Input Buffers Disabled, VREF = 5 V,
Output Data Rate = 31.25 kSPS)
Rev. B | Page 11 of 61
AD7172-4
Data Sheet
8388495
8388493
8388491
8388489
8388487
8388485
8388483
1200
1000
800
600
400
200
0
8388481
0
200
400
600
800
1000
8388482 8388484 8388486 8388488 8388490 8388492 8388494
ADC CODE
SAMPLE NUMBER
Figure 11. Noise (Analog Input Buffers Enabled, VREF = 5 V,
Output Data Rate = 1.25 SPS)
Figure 14. Histogram (Analog Input Buffers Enabled, VREF = 5 V,
Output Data Rate = 1.25 SPS)
120
100
80
60
40
20
0
8388520
8388510
8388500
8388490
8388480
8388470
8388460
0
100 200 300 400 500 600 700 800 900 1000
SAMPLE NUMBER
ADC CODE
Figure 12. Noise (Analog Input Buffers Enabled, VREF = 5 V,
Output Data Rate = 2.6 kSPS)
Figure 15. Histogram (Analog Input Buffers Enabled, VREF = 5 V,
Output Data Rate = 2.6 kSPS)
8388560
120
100
80
60
40
20
0
8388540
8388520
8388500
8388480
8388460
8388440
8388420
8388400
0
100 200 300 400 500 600 700 800 900 1000
SAMPLE NUMBER
ADC CODE
Figure 13. Noise (Analog Input Buffers Enabled, VREF = 5 V,
Output Data Rate = 31.25 kSPS)
Figure 16. Histogram (Analog Input Buffers Enabled, VREF = 5 V,
Output Data Rate = 31.25 kSPS)
Rev. B | Page 12 of 61
Data Sheet
AD7172-4
0.000020
0.000018
0.000016
0.000014
0.000012
0.000010
0.000008
0.000006
0.000004
0.000002
0
–60
–70
ANALOG INPUT BUFFERS OFF
ANALOG INPUT BUFFERS ON
–80
–90
–100
–110
–120
–130
–140
1
10
100
1k
10k
100k
1M
10M
100M
1000 201000 401000 601000 80100010010001201000140100016010001801000
V
FREQUENCY (Hz)
IN
FREQUENCY (MHz)
Figure 17. Noise vs. External Master Clock Frequency,
Analog Input Buffers On and Off
Figure 20. Power Supply Rejection Ratio (PSRR) vs. VIN Frequency
6
0
–20
CRYSTAL BUFFERS OFF
CRYSTAL BUFFERS ON
CLK BUFFERS OFF
CLK BUFFERS ON
2.5V REFERENCE,
ANALOG INPUT BUFFERS OFF
4
–40
2
–60
0
–2
–4
–80
–100
–120
–140
2.5V REFERENCE, ANALOG INPUT BUFFERS ON
5V REFERENCE, ANALOG INPUT BUFFERS OFF
5V REFERENCE, ANALOG INPUT BUFFERS ON
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
V
(V)
IN
1
10
100
1k
10k
100k
1M
V
FREQUENCY (Hz)
IN
Figure 18. Common-Mode Rejection Ratio (CMRR) vs. VIN Frequency
(VIN = 0.1 V, Output Data Rate = 31.25 kSPS)
Figure 21. Integral Nonlinearity (INL) vs. VIN
(Differential Input)
35
30
25
20
15
10
5
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
0
0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25
INL (ppm)
10
20
30
V
40
50
60
70
FREQUENCY (Hz)
IN
Figure 22. INL Distribution Histogram (Differential Input, All Input Buffers
Enabled, VREF = 2.5 V External, 100 Units)
Figure 19. Common-Mode Rejection Ratio (CMRR) vs. VIN Frequency
(VIN = 0.1 V, 10 Hz to 70 Hz, Output Data Rate = 20 SPS, Enhanced Filter)
Rev. B | Page 13 of 61
AD7172-4
Data Sheet
40
35
30
25
20
15
10
5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
A
A
BUFFERS ON
BUFFERS OFF
IN
IN
0
0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
INL (ppm)
Figure 23. INL Distribution Histogram (Differential Input, All Input Buffers
Disabled, VREF = 2.5 V External, 100 Units)
Figure 26. INL vs. Temperature (Differential Input, VREF = 2.5 V External)
50
45
40
35
30
25
20
15
10
5
35
30
25
20
15
10
5
0
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.996 1.997 1.998 1.999
2.00
2.001 2.002 2.003
INL (ppm)
FREQUENCY (MHz)
Figure 24. INL Distribution Histogram (All Input Buffers Enabled, Differential
Input, VREF = 5 V External, 100 Units)
Figure 27. Internal Oscillator Frequency/Accuracy Distribution Histogram
(100 Units)
40
35
30
25
20
15
10
5
2.01
2.00
1.99
1.98
1.97
1.96
1.95
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
INL (ppm)
Figure 25. INL Distribution Histogram (All Input Buffers Disabled, Differential
Input, VREF = 5 V External, 100 Units)
Figure 28. Internal Oscillator Frequency vs. Temperature
Rev. B | Page 14 of 61
Data Sheet
AD7172-4
30
25
20
15
10
5
25
20
15
10
5
0
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
OFFSET (µV)
GAIN ERROR (ppm of FSR)
Figure 29. Offset Error Distribution Histogram (Internal Short, 100 Units)
Figure 32. Gain Error Distribution Histogram
(All Input Buffers Disabled, 100 Units)
14
12
10
8
35
30
25
20
15
10
5
6
4
2
0
0
–50–40–30–20–10
0
10 20 30 40 50 60 70 80 90 100110
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
OFFSET DRIFT (nV/°C)
GAIN DRIFT (ppm/°C)
Figure 30. Offset Error Drift Distribution Histogram (Internal Short, 100 Units)
Figure 33. Gain Drift Distribution Histogram
(All Input Buffers Enabled, 100 Units)
25
30
25
20
15
10
5
20
15
10
5
0
0
–8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
–0.05
0
0.05
0.10
0.15
0.20
0.25
GAIN ERROR (ppm of FSR)
GAIN DRIFT (ppm/°C)
Figure 31. Gain Error Distribution Histogram
(All Input Buffers Enabled, 100 Units)
Figure 34. Gain Drift Distribution Histogram
(All Input Buffers Disabled, 100 Units)
Rev. B | Page 15 of 61
AD7172-4
Data Sheet
700
600
500
400
300
200
100
0
10
5
–40°C, AIN–
–40°C, AIN+
+25°C, AIN–
+25°C, AIN+
+85°C, AIN–
+85°C, AIN+
+105°C, AIN–
0
–5
–10
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
INPUT VOLTAGE (V)
Figure 35. Current Consumption vs. Temperature (Standby Mode)
Figure 37. Analog Input Current vs. Input Voltage
(VCM = 2.5 V)
45
40
35
30
25
20
15
10
5
15
10
5
AIN+ = AVDD1 – 0.2V
AIN– = AVSS + 0.2V
AIN+ = AVDD1
AIN– = AVSS
0
–5
–10
–15
0
9.5 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 10.4 10.5
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
CURRENT (µA)
Figure 36. Burnout Current Distribution Histogram
(100 Units)
Figure 38. Analog Input Current vs. Temperature
Rev. B | Page 16 of 61
Data Sheet
AD7172-4
NOISE PERFORMANCE AND RESOLUTION
Table 6 and Table 7 show the rms noise, peak-to-peak noise,
effective resolution, and the noise free (peak-to-peak) resolution
of the AD7172-4 for various output data rates and filters. The
numbers given are for the bipolar input range with a 5 V
reference. These numbers are typical and are generated with a
differential input voltage of 0 V when the ADC is continuously
converting on a single channel. It is important to note that the
peak-to-peak resolution is calculated based on the peak-to-peak
noise. The peak-to-peak resolution represents the resolution for
which there is no code flicker.
Table 6. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate Using the Sinc5 + Sinc1 Filter (Default)1
Output Data Rate (SPS) RMS Noise (μV rms) Effective Resolution (Bits) Peak-to-Peak Noise (μV p-p) Peak-to-Peak Resolution (Bits)
Input Buffers Disabled
31,250
15,625
10,417
1007
59.52
49.68
8.2
7.0
6.0
2.2
0.48
0.47
0.25
0.088
20.2
20.4
20.7
22.2
24
24
24
24
66
52
45
15
3.2
3.1
1.6
0.32
17.2
17.5
17.8
19.3
21.6
21.6
22.6
24
16.63
1.25
Input Buffers Enabled
31,250
15,625
10,417
1007
59.52
49.68
16.63
1.25
9.5
8.2
7.1
2.6
0.62
0.53
0.32
0.089
20
74
63
53
16
3.6
3.3
1.7
0.35
17
20.2
20.4
21.9
24
24
24
17.3
17.5
19.3
21.4
21.5
22.2
24
24
1 Selected rates only, 1000 samples.
Table 7. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate Using the Sinc3 Filter1
Output Data Rate (SPS) RMS Noise (μV rms) Effective Resolution (Bits) Peak-to-Peak Noise (μV p-p) Peak-to-Peak Resolution (Bits)
Input Buffers Disabled
31,250
15,625
10,417
1008
59.98
50
211
27.2
7.9
15.5
18.5
20.3
22.6
24
24
24
24
1600
205
57
11
2.5
2.3
1.1
0.27
12.5
15.6
17.4
19.8
21.9
22
1.6
0.38
0.35
0.21
0.054
16.67
1.25
23.1
24
Input Buffers Enabled
31,250
15,625
10,417
1008
59.98
50
16.67
1.25
212
27.7
8.5
15.5
18.5
20.2
22.4
24
24
24
24
1600
210
63
13
2.8
2.5
1.2
0.29
12.5
15.5
17.3
19.6
21.8
22
1.8
0.45
0.44
0.24
0.073
23
24
1 Selected rates only, 1000 samples.
Rev. B | Page 17 of 61
AD7172-4
Data Sheet
GETTING STARTED
The AD7172-4 offers the user a fast settling, high resolution,
multiplexed ADC with high levels of configurability, including
the following features:
The AD7172-4 includes two separate linear regulator blocks for
both the analog and digital circuitry. The analog LDO regulator
regulates the AVDD2 supply to 1.8 V, supplying the ADC core.
Tie the AVDD1 and AVDD2 supplies together for the easiest
connection. If there is already a clean analog supply rail in the
system in the range of 2 V (minimum) to 5.5 V (maximum), the
user can choose to connect this supply to the AVDD2 input,
allowing lower power dissipation.
Four fully differential or eight single-ended analog inputs.
A crosspoint multiplexer that selects any analog input
combination as the input signals to be converted, routing
them to the modulator positive or negative input.
True rail-to-rail buffered analog and reference inputs.
Fully differential inputs or single-ended inputs relative to
any analog input.
Per channel configurability—up to eight different setups
can be defined. A separate setup can be mapped to each of
the channels. Each setup allows the user to configure
whether the buffers are enabled or disabled, gain and offset
correction, filter type, output data rate, and reference
source selection.
16MHz
CX2
CX1
SEE THE BUFFERED ANALOG INPUT SECTION
FOR FURTHER DETAILS.
OPTIONAL EXTERNAL
CRYSTAL CIRCUITRY
CAPACITORS
9
XTAL1
1
AIN0/REF2–
XTAL2/CLKIO 10
DOUT/RDY 11
CLKIN
OPTIONAL
EXTERNAL
CLOCK
DOUT/RDY
DIN
2
AIN1/REF2+
AIN6
INPUT
12
DIN
13
SCLK
SCLK
27
14
15
16
CS
ERROR
SYNC
CS
ERROR
SYNC
28
29
AIN7
AIN8
AD7172-4
IOVDD
0.1µF
17
18
IOVDD
DGND
VIN
1
3
REGCAPD 19
2
4
7
6
V
NC
IN
0.1µF
1µF
4.7µF
0.1µF
AVDD1
ADR44xBRZ
AVDD1
AVDD2
6
7
4
32
31
GND
5
V
REF+
REF–
0.1µF
OUT
AVDD2
0.1µF
4.7µF
0.1µF
8
0.1µF
REGCAPA
AVSS
5
0.1µF
1µF
Figure 39. Typical Connection Diagram
Rev. B | Page 18 of 61
Data Sheet
AD7172-4
The linear regulator for the digital IOVDD supply performs a
similar function, regulating the input voltage applied at the
IOVDD pin to 1.8 V for the internal digital filtering. The serial
interface signals always operate from the IOVDD supply at the
pin; meaning, if 3.3 V is applied to the IOVDD pin, the
interface logic inputs and outputs operate at this level.
The ADM660 and ADP7182 generate a clean negative rail for
AVSS in the bipolar configuration to provide optimal converter
performance.
ADP7118
LDO
5V
INPUT
+2.5V: AVDD1/AVDD2
ADP7118
LDO
+3.3V: IOVDD
The AD7172-4 can be used across a wide variety of applications,
providing high resolution and accuracy. A sample of these
scenarios is as follows:
–5V
ADM660
LDO
ADP7182
LDO
–2.5V: AVSS
Figure 41. Bipolar AD7172-4 Supply Rails
Fast scanning of analog input channels using the internal
multiplexer
Fast scanning of analog input channels using an external
multiplexer with automatic control from the GPIOs
High resolution at lower speeds in either channel scanning
or ADC per channel applications
Single ADC per channel: the fast low latency output allows
further application specific filtering in external micro-
controllers, DSPs, or FPGAs
Table 8. Recommended Power Management Devices
Product
ADP7118
ADP7182
ADM660
Description
20 V, 200 mA, low noise, CMOS LDO regulator
−28 V, −200 mA, low noise, linear regulator
CMOS switched capacitor voltage converter
DIGITAL COMMUNICATION
The AD7172-4 has a 3- or 4-wire SPI interface that is compatible
with QSPI™, MICROWIRE, and DSPs. The interface operates in
POWER SUPPLIES
CS
SPI Mode 3 and can be operated with tied low. In SPI Mode 3,
The AD7172-4 has three independent power supply pins: AVDD1,
AVDD2, and IOVDD. AVDD1 powers the crosspoint multiplexer
and integrated analog and reference input buffers. AVDD1 is
referenced to AVSS, and AVDD1 − AVSS = 3.3 V or 5 V.
AVDD1 and AVSS can be a single 3.3 V or 5 V supply, or a
1.65 V or 2.5 V split supply. The split supply operation allows
true bipolar inputs. When using split supplies, consider the
absolute maximum ratings (see the Absolute Maximum Ratings
section).
the SCLK pin idles high, the falling edge of SCLK is the drive
edge, and the rising edge of SCLK is the sample edge. This
means that data is clocked out on the falling/drive edge and data
is clocked in on the rising/sample edge.
DRIVE EDGE
SAMPLE EDGE
AVDD2 powers the internal 1.8 V analog LDO regulator. This
regulator powers the ADC core. AVDD2 is referenced to AVSS,
and AVDD2 to AVSS can range from 5.5 V (maximum) to 2 V
(minimum).
Figure 42. SPI Mode 3 SCLK Edges
Accessing the ADC Register Map
The communications register controls access to the full register
map of the ADC. This register is an 8-bit write only register. On
power-up or after a reset, the digital interface defaults to a state
where it is expecting a write to the communications register;
therefore, all communication begins by writing to the
communications register.
IOVDD powers the internal 1.8 V digital LDO regulator. This
regulator powers the digital logic of the ADC. IOVDD sets the
voltage levels for the SPI interface of the ADC. IOVDD is refer-
enced to DGND, and IOVDD to DGND can vary from 5.5 V
(maximum) to 2 V (minimum).
There are no specific requirements for a power supply sequence
on the AD7172-4. When all power supplies are stable, a device
reset is required; see the AD7172-4 Reset section for how to
reset the device.
The data written to the communications register determines
which register is being accessed and if the next operation is a read
or write. The RA bits (Bits[5:0] in Register 0x00) determine the
specific register to which the read or write operation applies.
Recommended Linear Regulators
When the read or write operation to the selected register is
complete, the interface returns to its default state, where it
expects a write operation to the communications register.
The ADP7118 provides the positive supply rails, creating either
a single 5 V or 3.3 V, or dual AVDD1/IOVDD, depending on
the required supply configuration. The ADP7118 can operate
from input voltages up to 20 V.
ADP7118
LDO
12V
INPUT
5V: AVDD1
ADP7118
LDO
3.3V: AVDD2/IOVDD
Figure 40. Single Supply Linear Regulator
Rev. B | Page 19 of 61
AD7172-4
Data Sheet
Figure 43 and Figure 44 illustrate writing to and reading from a
register by first writing the 8-bit command to the communications
register, followed by the data for that register.
8 BITS, 16 BITS,
CONFIGURATION OVERVIEW
After power-on or reset, the AD7172-4 default configuration is
as follows:
8-BIT COMMAND
OR 24 BITS OF DATA
Channel configuration. CH0 is enabled, AIN0 is selected
as the positive input, and AIN1 is selected as the negative
input. Setup 0 is selected.
CS
Setup configuration. The analog input buffers are disabled
and the reference input buffers are also disabled. The REF
pins are selected as the reference source.
COMMAND
DATA
DIN
Filter configuration. The sinc5 + sinc1 filter is selected and
the maximum output data rate of 31.25 kSPS is selected.
ADC mode. Continuous conversion mode and the internal
oscillator are enabled.
SCLK
Figure 43. Writing to a Register
(8-Bit Command with Register Address Followed by Data 8, 16, or 24 Bits; Data
Length on DIN Is Dependent on the Register Selected)
Interface mode. CRC and data + status output are disabled.
Note that only a few of the register setting options are shown;
this list is just an example. For full register information, see the
Register Details section.
8 BITS, 16 BITS,
OR 24 BITS OUTPUT
8-BIT COMMAND
CS
Figure 45 shows an overview of the suggested flow for changing
the ADC configuration, divided into the following three blocks:
COMMAND
DIN
Channel configuration (see Box A in Figure 45)
Setup configuration (see Box B in Figure 45)
ADC mode and interface mode configuration (see Box C
in Figure 45)
DOUT/RDY
DATA
Channel Configuration
SCLK
The AD7172-4 has eight independent channels and eight
independent setups. The user can select any of the analog input
pairs on any channel, as well as any of the eight setups for any
channel, giving the user full flexibility in the channel configuration.
This also allows per channel configuration when using
differential inputs and single-ended inputs because each
channel can have its own dedicated setup.
Figure 44. Reading from a Register
(8-Bit Command with Register Address Followed by Data of 8, 16, 24 Bits;
RDY
Data Length on DOUT/
Is Dependent on the Register Selected)
Reading the ID register is the recommended method for verifying
correct communication with the device. The ID register is a
read only register and contains the value 0x205X for the
AD7172-4. The communications register and the ID register
details are described in Table 9 and Table 10.
Channel Registers
The channel registers select which of the nine analog input pins
(AIN0 to AIN8) are used as either the positive analog input
(AIN+) or the negative analog input (AIN−) for that channel.
This register also contains a channel enable/disable bit and the
setup selection bits, which are used to select which of the eight
available setups to use for this setup channel.
AD7172-4 RESET
After a power-up cycle and when the power supplies are stable,
a device reset is required. In situations where interface synchro-
nization is lost, a device reset is also required. A write operation
of at least 64 serial clock cycles with DIN high returns the ADC to
its default state by resetting the entire device, including the register
When the AD7172-4 is operating with more than one channel
enabled, the channel sequencer cycles through the enabled
channels in sequential order, from Channel 0 to Channel 7. If a
channel is disabled, it is skipped by the sequencer. Details of the
channel register for Channel 0 are shown in Table 11.
CS
contents. Alternatively, if is being used with the digital interface,
CS
returning
high sets the digital interface to its default state and
halts any serial interface operation.
Rev. B | Page 20 of 61
Data Sheet
AD7172-4
A
B
C
CHANNEL CONFIGURATION
SELECT POSITIVE AND NEGATIVE INPUT FOR EACH ADC CHANNEL
SELECT ONE OF 8 SETUPS FOR ADC CHANNEL
SETUP CONFIGURATION
8 POSSIBLE ADC SETUPS
SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE
ADC MODE AND INTERFACE MODE CONFIGURATION
SELECT ADC OPERATING MODE, CLOCK SOURCE,
ENABLE CRC, DATA + STATUS, AND MORE
Figure 45. Suggested ADC Configuration Flow
Table 9. Communications Register
Reg.
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
Reset
RW
0x00
COMMS [7:0]
WEN
W
RA
0x00
W
R/
Table 10. ID Register
Reg.
Name
Bits
Bit 7
Bit 6
Bit 3
Reset
RW
0x07
ID
[15:8]
[7:0]
ID[15:8]
ID[7:0]
0x205X
R
Table 11. Channel Register 0
Reg.
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x10
CH0
[15:8] CH_EN0
[7:0]
SETUP_SEL0
Reserved
AINNEG0
AINPOS0[4:3]
0x8001
RW
AINPOS0[2:0]
Rev. B | Page 21 of 61
AD7172-4
Data Sheet
Setup Configuration Registers
ADC Setups
The setup configuration registers allow the user to select the output
coding of the ADC by selecting between bipolar mode and
unipolar mode. In bipolar mode, the ADC accepts negative
differential input voltages, and the output coding is offset binary. In
unipolar mode, the ADC accepts only positive differential voltages,
and the coding is straight binary. In either case, the input voltage
must be within the AVDD1/AVSS supply voltages. The user can
select the reference source using these registers. Three options are
available: a reference connected between the REF+ and REF− pins,
between REF2+ and REF2− pins , or using AVDD1 − AVSS.
The analog input and reference input buffers can also be
enabled or disabled using these registers.
The AD7172-4 has eight independent setups. Each setup
consists of the following four registers:
Setup configuration register
Filter configuration register
Gain register
Offset register
For example, Setup 0 consists of Setup Configuration Register 0,
Filter Configuration Register 0, Gain Register 0, and Offset
Register 0. Figure 46 shows the grouping of these registers The
setup is selectable from the channel registers (see the Channel
Configuration section), which allows each channel to be
assigned to one of eight separate setups. Table 12 through Table 15
show the four registers that are associated with Setup 0. This
structure is repeated for Setup 1 to Setup 7.
Filter Configuration Registers
The filter configuration registers select which digital filter is
used at the output of the ADC modulator. The order of the filter
and the output data rate are selected by setting the bits in these
registers. For more information, see the Digital Filters section.
SETUP CONFIG
REGISTERS
FILTER CONFIG
REGISTERS
GAIN REGISTERS*
OFFSET REGISTERS
SETUPCON0
SETUPCON1
SETUPCON2
SETUPCON3
SETUPCON4
SETUPCON5
SETUPCON6
SETUPCON7
FILTCON0
FILTCON1
FILTCON2
FILTCON3
FILTCON4
FILTCON5
FILTCON6
FILTCON7
GAIN0
GAIN1
GAIN2
GAIN3
GAIN4
GAIN5
GAIN6
GAIN7
OFFSET0
0x30
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
OFFSET1
0x31
OFFSET2
0x32
OFFSET3
0x33
OFFSET4
0x34
OFFSET5
0x35
OFFSET6
0x36
OFFSET7
0x37
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
SELECT DIGITAL
FILTER TYPE
GAIN CORRECTION
OPTIONALLY
OFFSET CORRECTION
OPTIONALLY PROGRAMMED
PER SETUP AS REQUIRED
AND OUTPUT DATA RATE
PROGRAMMED
PER SETUP AS REQUIRED
(*FACTORY CALIBRATED)
ANALOG INPUT BUFFERS
REFERENCE INPUT BUFFERS
BURNOUT
31.25kSPS TO 1.25SPS
SINC5 + SINC1
SINC3
SINC3 MAP
REFERENCE SOURCE
ENHANCED 50/60
Figure 46. ADC Setup Register Grouping
Table 12. Setup Configuration Register 0
Reg. Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x20 SETUPCON0 [15:8]
[7:0]
Reserved
BI_UNIPOLAR0 REFBUF0+ REFBUF0− AINBUF0+ AINBUF0− 0x1000
RW
BURNOUT_EN0 Reserved
REF_SEL0
Reserved
Table 13. Filter Configuration Register 0
Reg. Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x28 FILTCON0 [15:8] SINC3_MAP0
[7:0] Reserved
Reserved
ORDER0
ENHFILTEN0
ENHFILT0
0x0500
RW
ODR0
Table 14. Gain Register 0
Reg. Name
Bits
Bits[23:0]
Reset
RW
0x38 GAIN0
[23:0]
GAIN0[23:0]
0x5XXXX0 RW
Table 15. Offset Register 0
Reg. Name
Bits
Bits[23:0]
Reset
RW
0x30 OFFSET0
[23:0]
OFFSET0[23:0]
0x800000 RW
Rev. B | Page 22 of 61
Data Sheet
AD7172-4
ADC Mode and Interface Mode Configuration
Gain Registers
The ADC mode register and the interface mode register configure
the core peripherals for use by the AD7172-4 and the mode for
the digital interface.
The gain registers are 24-bit registers that hold the gain
calibration coefficient for the ADC. The gain registers are
read/write registers. These registers are configured at power-on
with factory calibrated coefficients. Therefore, every device has
different default coefficients. The default value is automatically
overwritten if the user initiates a system full-scale calibration or
writes to a gain register. For more information on calibration,
see the Operating Modes section.
ADC Mode Register
The ADC mode register primarily sets the conversion mode of
the ADC to either continuous or single conversion. The user
can also select the standby and power-down modes, as well as
any of the calibration modes. In addition, this register contains
the clock source select bits The reference select bits are
contained in the setup configuration registers (see the ADC
Setups section for more information). The details of this register
are shown in Table 16.
Offset Registers
The offset registers hold the offset calibration coefficient for the
ADC. The power-on reset value of the offset registers is 0x800000.
The offset registers are 24-bit read/write registers. The power-on
reset value is automatically overwritten if the user initiates an
internal or system zero-scale calibration or if the user writes to an
offset register.
Interface Mode Register
The interface mode register configures the digital interface
operation. This register allows the user to control data-word
length, CRC enable, data plus status read, and continuous read
mode. The details of this register are shown in Table 17. For more
information, see the Digital Interface section.
Table 16. ADC Mode Register
Reg. Name
0x01 ADCMODE [15:8] Reserved
[7:0] Reserved
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Reserved
Bit 2
CLOCKSEL
Bit 1
Delay
Reserved
Bit 0
Reset
RW
HIDE_DELAY SING_CYC
Mode
0x2000 RW
Table 17. Interface Mode Register
Reg.
Name
Bits
Bit 7
Bit 6
Reserved
CONTREAD DATA_STAT
Bit 5
Bit 4
ALT_SYNC IOSTRENGTH
Reserved CRC_EN
Bit 3
Bit 2
Bit 1
Reserved
Reserved
Bit 0
Reset
RW
0x02 IFMODE [15:8]
[7:0]
DOUT_RESET
WL16
0x0000 RW
REG_CHECK
Rev. B | Page 23 of 61
AD7172-4
Data Sheet
Understanding Configuration Flexibility
An alternative way to implement these four fully differential
inputs is to take advantage of four of the eight available setups.
Motivation for doing this includes having a different speed/noise
requirement on each of the differential inputs, or a specific
offset or gain correction may be needed for each channel. Figure 48
shows how each of the differential inputs can use a separate
setup, allowing full flexibility in the configuration of each channel.
The most straightforward implementation of the AD7172-4 is
to use four differential inputs with adjacent analog inputs and
run all of them with the same setup, gain correction, and offset
correction registers. In this case, the user selects the following
differential inputs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, and
AIN6/AIN7. In Figure 47, the registers shown in black font
must be programmed for such a configuration. The registers
that are shown in gray font are redundant in this configuration.
Programming the gain and offset registers is optional for any
use case, as indicated by the dashed lines between the register
blocks.
CHANNEL
REGISTERS
SETUP CONFIG
REGISTERS
FILTER CONFIG
REGISTERS
GAIN REGISTERS*
OFFSET REGISTERS
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
CH0
SETUPCON0
FILTCON0
GAIN0
0x38
OFFSET0
0x30
0x10
0x20
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
CH1
CH2
CH3
CH4
CH5
CH6
CH7
SETUPCON1
SETUPCON2
SETUPCON3
SETUPCON4
SETUPCON5
SETUPCON6
SETUPCON7
FILTCON1
FILTCON2
FILTCON3
FILTCON4
FILTCON5
FILTCON6
FILTCON7
GAIN1
GAIN2
GAIN3
GAIN4
GAIN5
GAIN6
GAIN7
OFFSET1
0x31
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x11
0x12
0x13
0x14
0x15
0x16
0x17
OFFSET2
0x32
OFFSET3
0x33
OFFSET4
0x34
OFFSET5
0x35
OFFSET6
0x36
OFFSET7
0x37
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
GAIN CORRECTION
OPTIONALLY
PROGRAMMED
OFFSET CORRECTION
OPTIONALLY PROGRAMMED
PER SETUP AS REQUIRED
PER SETUP AS REQUIRED
(*FACTORY CALIBRATED)
SELECT ANALOG INPUT PARTS
ENABLE THE CHANNEL
SELECT SETUP 0
ANALOG INPUT BUFFERS
REFERENCE INPUT BUFFERS
BURNOUT
31.25kSPS TO 1.25SPS
SINC5 + SINC1
SINC3
REFERENCE SOURCE
SINC3 MAP
ENHANCED 50/60
Figure 47. Four Fully Differential Inputs, Using a Single Setup (SETUPCON0, FILTCON0, GAIN0, OFFSET0)
CHANNEL
REGISTERS
SETUP CONFIG
REGISTERS
FILTER CONFIG
REGISTERS
GAIN REGISTERS*
OFFSET REGISTERS
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
CH0
SETUPCON0
FILTCON0
0x28
GAIN0
0x38
OFFSET0
0x30
0x10
0x20
CH1
CH2
CH3
CH4
CH5
CH6
CH7
SETUPCON1
SETUPCON2
SETUPCON3
SETUPCON4
SETUPCON5
SETUPCON6
SETUPCON7
FILTCON1
FILTCON2
FILTCON3
FILTCON4
FILTCON5
FILTCON6
FILTCON7
GAIN1
GAIN2
GAIN3
GAIN4
GAIN5
GAIN6
GAIN7
OFFSET1
0x31
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x11
0x12
0x13
0x14
0x15
0x16
0x17
OFFSET2
0x32
OFFSET3
0x33
OFFSET4
0x34
OFFSET5
0x35
OFFSET6
0x36
OFFSET7
0x37
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
GAIN CORRECTION
OPTIONALLY
PROGRAMMED
OFFSET CORRECTION
OPTIONALLY PROGRAMMED
PER SETUP AS REQUIRED
PER SETUP AS REQUIRED
(*FACTORY CALIBRATED)
SELECT ANALOG INPUT PARTS
ENABLE THE CHANNEL
SELECT SETUP 0
ANALOG INPUT BUFFERS
REFERENCE INPUT BUFFERS
BURNOUT
31.25kSPS TO 1.25SPS
SINC5 + SINC1
SINC3
REFERENCE SOURCE
SINC3 MAP
ENHANCED 50/60
Figure 48. Four Fully Differential Inputs with One Setup per Channel
Rev. B | Page 24 of 61
Data Sheet
AD7172-4
Figure 49 shows an example of how the channel registers span
between the analog input pins and the setup configurations
downstream. In this example, three differential inputs and two
single-ended inputs are required. The single-ended inputs are the
AIN4/AIN8 and AIN7/AIN8 combinations. The differential input
pairs are AIN0/AIN1 and AIN2/AIN3, both using Setup 0, and
AIN5/AIN6 using Setup 2. The two single-ended input pairs are
set up as diagnostics, and in this example use separate setups,
namely Setup 1 and Setup 4. Given that five setups are selected
for use, the SETUPCON0 to SETUPCON4 registers are pro-
grammed as required, and the FILTCON0 to FILTCON4 registers
are programmed as required. Optional gain and offset
correction can be employed on a per setup basis by
programming GAIN0 and GAIN1 and OFFSET0 and
OFFSET1.
In the example shown in Figure 49, the CH0 to CH4 registers
are used. Setting the MSB in each of these registers, the CH_EN0
to CH_EN4 bits enable the five combinations via the crosspoint
mux. When the AD7172-4 converts, the sequencer transitions
in ascending sequential order from CH0 through CH4 before
looping back to CH0 to repeat the sequence.
CHANNEL
REGISTERS
SETUP CONFIG
REGISTERS
FILTER CONFIG
REGISTERS
GAIN REGISTERS*
OFFSET REGISTERS
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
CH0
SETUPCON0
FILTCON0
GAIN0
0x38
OFFSET0
0x30
0x10
0x20
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
CH1
CH2
CH3
CH4
CH5
CH6
CH7
SETUPCON1
SETUPCON2
SETUPCON3
SETUPCON4
SETUPCON5
SETUPCON6
SETUPCON7
FILTCON1
FILTCON2
FILTCON3
FILTCON4
FILTCON5
FILTCON6
FILTCON7
GAIN1
GAIN2
GAIN3
GAIN4
GAIN5
GAIN6
GAIN7
OFFSET1
0x31
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x11
0x12
0x13
0x14
0x15
0x16
0x17
OFFSET2
0x32
OFFSET3
0x33
OFFSET4
0x34
OFFSET5
0x35
OFFSET6
0x36
OFFSET7
0x37
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
GAIN CORRECTION
OPTIONALLY
PROGRAMMED
OFFSET CORRECTION
OPTIONALLY PROGRAMMED
PER SETUP AS REQUIRED
PER SETUP AS REQUIRED
(*FACTORY CALIBRATED)
SELECT ANALOG INPUT PARTS
ENABLE THE CHANNEL
SELECT SETUP 0
ANALOG INPUT BUFFERS
REFERENCE INPUT BUFFERS
BURNOUT
31.25kSPS TO 1.25SPS
SINC5 + SINC1
SINC3
REFERENCE SOURCE
SINC3 MAP
ENHANCED 50/60
Figure 49. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups
Rev. B | Page 25 of 61
AD7172-4
Data Sheet
CIRCUIT DESCRIPTION
AVDD1
BUFFERED ANALOG INPUT
AIN0
AIN1
The AD7172-4 has true rail-to-rail, integrated, precision unity-
gain buffers on both ADC analog inputs. The buffers provide
high input impedance with only 5.5 nA typical input current,
allowing high impedance sources to be connected directly to
the analog inputs. The buffers fully drive the internal ADC
switch capacitor sampling network, simplifying the analog
front-end circuit requirements while consuming a very efficient
0.38 mA typical per buffer. Each analog input buffer amplifier is
fully chopped, meaning that it minimizes the offset error drift
and 1/f noise of the buffer. The 1/f noise profile of the ADC and
buffer combined is shown in Figure 50.
AVSS
AVDD1
Ø1
+IN
CS1
CS2
AVSS
Ø2
Ø2
AVDD1
AIN2
AVSS
–IN
AVDD1
Ø1
AIN3
AIN4
0
AVSS
AVDD1
–50
–100
–150
–200
–250
AVSS
Figure 51. Simplified Analog Input Circuit
The CS1 and CS2 capacitors have a magnitude in the order of a
number of picofarads each. This capacitance is the combination
of both the sampling capacitance and the parasitic capacitance.
Fully Differential Inputs
Because the AIN0 to AIN8 analog inputs are connected to a
crosspoint multiplexer, any combination of signals can create an
analog input pair. This allows the user to select four fully
differential inputs or eight single-ended inputs.
0.1
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 50. Shorted Input Fast Fourier Transform (FFT), Analog Input
Buffers Enabled
If four fully differential input paths are connected to the
AD7172-4, using adjacent analog inputs for the differential input
pair, such as AIN2/AIN3, is recommended. This is due to the
relative locations of these pins to each other. Decouple all analog
inputs to AVSS.
The analog input buffers do not suffer from linearity degradation
when operating at the rails, unlike many discrete amplifiers.
When operating at or close to the AVDD1 and AVSS supply
rails, there is an increase in input current. This increase is most
notable at higher temperatures. Figure 37 and Figure 38 show
the input current for various conditions. With the analog input
buffers disabled, the average input current to the AD7172-4
changes linearly with the differential input voltage at a rate of
6 μA/V.
Single-Ended Inputs
The user can also choose to measure eight different single-
ended analog inputs. In this case, each of the analog inputs is
converted as the difference between the single-ended input to be
measured and a set analog input common pin. Because there is
a crosspoint multiplexer, the user can set any of the analog inputs
as the common pin. An example of such a scenario is to connect
the AIN4 pin to AVSS and then select this input when configuring
the crosspoint multiplexer. When using the AD7172-4 with
single-ended inputs, INL degrades.
CROSSPOINT MULTIPLEXER
There are nine analog input pins: AIN0 to AIN8. Each of these
pins connects to the internal crosspoint multiplexer. The
crosspoint multiplexer enables any of these inputs to be configured
as an input pair, either single-ended or fully differential. The
AD7172-4 can have up to eight active channels. When more than
one channel is enabled, the channels are automatically sequenced
in order from the lowest enabled channel number to the highest
enabled channel number. The output of the multiplexer is
connected to the input of the integrated true rail-to-rail buffers.
These buffers can be bypassed and the multiplexer output can
be directly connected to the switched capacitor input of the ADC.
The simplified analog input circuit is shown in Figure 51.
Rev. B | Page 26 of 61
Data Sheet
AD7172-4
Standard low noise, low drift voltage references, such as the
AD7172-4 REFERENCE
ADR445, ADR444, and ADR441, are recommended for use.
Apply the reference to the AD7172-4 reference pins as shown in
Figure 52. Decouple the output of the reference to AVSS. As
shown in Figure 52, the ADR441 output is decoupled with a
0.1 μF capacitor at its output for stability purposes. The output
is then connected to a 4.7 μF capacitor, which acts as a reservoir
for any dynamic charge required by the ADC, and followed by a
0.1 μF decoupling capacitor at the REF+ input. This capacitor is
placed as close as possible to the REF+ and REF− pins. e
REF− pin is connected directly to the AVSS potential.
The AD7172-4 offers the user the option of either supplying a
reference to the REF or REF2 pins of the device or using
AVDD1 – AVSS. Select the reference source to be used by the
analog input by setting the REF_SELx bits (Bits[5:4]) in the setup
configuration registers appropriately. The structure of the Setup
Configuration 0 register is shown in Table 18. The AD7172-4
defaults on power-up to use the REF+ and REF− reference
inputs, REF+ and REF−.
AD7172-4
3V TO 18V
ADR4412
32
31
REF+
REF–
2.5V V
0.1µF
1
0.1µF
4.7µF
0.1µF
REF
1
1
1
1
1
2
ALL DECOUPLING IS TO AVSS.
ANY OF THE ADR44x FAMILY OF REFERENCES CAN BE USED.
THE ADR441 ENABLES REUSE OF THE 3.3V ANALOG SUPPLY
NEEDED FOR AVDD1 TO POWER THE REFERENCE V
.
IN
Figure 52. ADR441 Connected to AD7172-4 REF Pins
Table 18. Setup Configuration 0 Register
Reg. Name
Bits
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x20 SETUPCON0 [15:8]
[7:0]
Reserved
BI_UNIPOLAR0 REFBUF0+ REFBUF0− AINBUF0+ AINBUF0− 0x1000 RW
BURNOUT_EN0 Reserved
REF_SEL0
Reserved
Table 19. ADC Mode Register
Reg.
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CLOCKSEL
Bit 1
Delay
Reserved
Bit 0
Reset
RW
0x01
ADCMODE [15:8]
[7:0]
Reserved HIDE_DELAY
Reserved
SING_CYC
Mode
Reserved
0x2000
RW
Rev. B | Page 27 of 61
AD7172-4
Data Sheet
IOSTRENGTH bit is set at higher IOVDD levels (see Table 29
for more information).
BUFFERED REFERENCE INPUT
The AD7172-4 has true rail-to-rail, integrated, precision unity
gain buffers on both ADC reference inputs. The buffers provide
the benefit of providing high input impedance and allowing
high impedance external sources to be directly connected to the
reference inputs. The integrated reference buffers can fully drive
the internal reference switch capacitor sampling network,
simplifying the reference circuit requirements while consuming
a very efficient 0.38 mA typical per buffer. Each reference input
buffer amplifier is fully chopped, meaning that it minimizes the
offset error drift and 1/f noise of the buffer. When using a
reference, such as the ADR445, ADR444, or ADR441, these
buffers are not required because these references, with proper
decoupling, can drive the reference inputs directly.
External Crystal
If higher precision, lower jitter clock sources are required, the
AD7172-4 can use an external crystal to generate the master clock.
The crystal is connected to the XTAL1 and XTAL2/CLKIO pins.
A recommended crystal for use is the FA-20H, a 16 MHz,
10 ppm, 9 pF crystal from Epson-Toyocom that is available in a
surface-mount package. As shown in Figure 53, insert two
capacitors (CX1 and CX2) from the traces connecting the
crystal to the XTAL1 and XTAL2/CLKIO pins. These capacitors
allow circuit tuning. Connect these capacitors to the DGND
pin. The value for these capacitors depends on the length and
capacitance of the trace connections between the crystal and the
XTAL1 and XTAL2/CLKIO pins. Therefore, the values of these
capacitors differ depending on the PCB layout and the crystal
employed.
CLOCK SOURCE
The AD7172-4 uses a nominal master clock of 2 MHz. The
AD7172-4 can source its sampling clock from one of three
sources:
AD7172-4
CX1
1
An internal oscillator
9
XTAL1
An external crystal (use a 16 MHz crystal automatically
divided internally to set the 2 MHz clock)
An external clock source
XTAL2/CLKIO 10
CX2
1
All output data rates listed in the data sheet relate to a master
clock rate of 2 MHz. Using a lower clock frequency from, for
instance, an external source scales any listed data rate propor-
tionally. To achieve the specified data rates, particularly rates for
rejection of 50 Hz and 60 Hz, use a 2 MHz clock. The source of
the master clock is selected by setting the CLOCKSEL bits
(Bits[3:2]) in the ADC mode register as shown in Table 19. The
default operation on power-up and reset of the AD7172-4 is to
operate with the internal oscillator. It is possible to fine tune the
output data rate and filter notch at low output data rates using
the SINC3_MAPx bit. See the Sinc3 Filter section for more
information.
1
DECOUPLE TO DGND.
Figure 53. External Crystal Connections
The external crystal circuitry can be sensitive to the SCLK
edges, depending on the SCLK frequency, IOVDD voltage,
crystal circuitry layout, and the crystal used. During crystal startup,
any disturbances caused by the SLCK edges may cause double
edges on the crystal input, resulting in invalid conversions until
the crystal voltage has reached a high enough level such that
any interference from the SCLK edges is insufficient to cause
double clocking. This double clocking can be avoided by
ensuring that the crystal circuitry has reached a sufficient
voltage level after startup before applying any SCLK.
Internal Oscillator
Due to the nature of the crystal circuitry, it is therefore
recommended that empirical testing of the circuit be performed
under the required conditions, with the final PCB layout and
crystal, to ensure correct operation.
The internal oscillator runs at 16 MHz and is internally divided
down to 2 MHz for the modulator and can be used as the ADC
master clock. The internal oscillator is the default clock source for
the AD7172-4 and is specified with an accuracy of −2.6% to
+2.5%.
External Clock
The AD7172-4 can also use an externally supplied clock. In
systems where this is desirable, the external clock is routed to
the XTAL2/CLKIO pin. In this configuration, the XTAL2/
CLKIO pin accepts the externally sourced clock and routes it to
the modulator. The logic level of this clock input is defined by
the voltage applied to the IOVDD pin.
There is an option to allow the internal clock oscillator to be output
on the XTAL2/CLKIO pin. The clock output is driven to the
IOVDD logic level. This option can affect the dc performance of
the AD7172-4 due to the disturbance introduced by the output
driver. The extent to which the performance is affected depends
on the IOVDD voltage supply. Higher IOVDD voltages create a
wider logic output swing from the driver and affect performance
to a greater extent. This effect is further exaggerated if the
Rev. B | Page 28 of 61
Data Sheet
AD7172-4
DIGITAL FILTERS
The AD7172-4 has three flexible filter options to allow
optimization of noise, settling time, and rejection:
SINC3 FILTER
The sinc3 filter achieves the best single-channel noise performance
at lower rates and is, therefore, most suitable for single-channel
applications. The sinc3 filter always has a settling time equal to
The sinc5 + sinc1 filter
The sinc3 filter
Enhanced 50 Hz and 60 Hz rejection filters
t
SETTLE = 3/Output Data Rate
Figure 56 shows the frequency domain filter response for the
sinc3 filter. The sinc3 filter has good roll-off over frequency and
has wide notches for good notch frequency rejection.
50Hz AND 60Hz
POSTFILTER
SINC1
SINC5
SINC3
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
Figure 54. Digital Filter Block Diagram
The filter and output data rate are configured by setting the
appropriate bits in the filter configuration register for the
selected setup. Each channel can use a different setup and
therefore, a different filter and output data rate. See the Register
Details section for more information.
SINC5 + SINC1 FILTER
The sinc5 + sinc1 filter is targeted at multiplexed applications
and achieves single cycle settling at output data rates of 2.6 kSPS
and less. The sinc5 block output is fixed at the maximum rate of
31.25 kSPS, and the sinc1 block output data rate can be varied to
control the final ADC output data rate. Figure 55 shows the
frequency domain response of the sinc5 + sinc1 filter at a 50 SPS
output data rate. The sinc5 + sinc1 filter has a slow roll-off over
frequency and narrow notches.
–120
0
50
100
FREQUENCY (Hz)
150
Figure 56. Sinc3 Filter Response
The output data rates with the accompanying settling time and
rms noise for the sinc3 filter are shown in Table 22 and Table 23. It
is possible to fine tune the output data rate for the sinc3 filter by
setting the SINC3_MAPx bit in the filter configuration registers.
If this bit is set, the mapping of the filter register changes to directly
program the decimation rate of the sinc3 filter. All other options
are eliminated. The data rate when on a single channel can be
calculated using the following equation:
0
–20
–40
fMOD
Output Data Rate
–60
32 FILTCONx[14:0]
where:
–80
f
MOD is the modulator rate (MCLK/2) and is equal to 1 MHz.
FILTCONx[14:0] are the contents on the filter configuration
registers, excluding the MSB.
–100
–120
For example, an output data rate of 50 SPS can be achieved with
SINC3_MAPx enabled by setting the FILTCONx[14:0] bits to a
value of 625.
0
50
100
FREQUENCY (Hz)
150
Figure 55. Sinc5 + Sinc1 Filter Response at 50 SPS ODR
The output data rates with the accompanying settling time and
rms noise for the sinc5 + sinc1 filter are shown in Table 20 and
Table 21.
Rev. B | Page 29 of 61
AD7172-4
Data Sheet
Figure 58 shows the same step on the analog input but with
single cycle settling enabled. The analog input requires at least a
single cycle for the output to be fully settled. The output data
SINGLE CYCLE SETTLING
The AD7172-4 can be configured by setting the SING_CYC bit
in the ADC mode register so that only fully settled data is output,
thus effectively putting the ADC into a single cycle settling mode.
This mode achieves single cycle settling by reducing the output
data rate to be equal to the settling time of the ADC for the selected
output data rate. This bit has no effect with the sinc5 + sinc1 filter
at output data rates of 2.6 kSPS and less.
RDY
rate, as indicated by the
signal, is now reduced to equal the
settling time of the filter at the selected output data rate.
ANALOG
INPUT
FULLY
SETTLED
ADC
OUTPUT
Figure 57 shows a step on the analog input with single cycle
settling mode disabled and the sinc3 filter selected. The analog
input requires at least three cycles after the step change for the
output to reach the final settled value.
tSETTLE
Figure 58. Step Input with Single Cycle Settling
ANALOG
INPUT
FULLY
SETTLED
ADC
OUTPUT
1/ODR
Figure 57. Step Input Without Single Cycle Settling
Table 20. Output Data Rate, Settling Time, and Noise Using the Sinc5 + Sinc1 Filter with Input Buffers Disabled
Default Output
Data Rate (SPS);
SING_CYC = 0 and
Single Channel
Enabled1
Output Data Rate
(SPS/Channel);
SING_CYC = 1 or with
Multiple Channels
Enabled1
Effective
Peak-to-Peak
Resolution with
5 V Reference
(Bits)
Notch
Frequency
(Hz)
Resolution with
5 V Reference
(Bits)
Settling
Time1
Noise
(μV rms)
Noise
(μV p-p)2
31,250
15,625
10,417
5208
2597
1007
503.8
381
200.3
100.2
59.52
49.68
20.01
16.63
10
6211
5181
4444
3115
2597
1007
503.8
381
200.3
100.2
59.52
49.68
20.01
16.63
10
161 μs
193 μs
225 μs
321 μs
385 μs
993 μs
1.99 ms
2.63 ms
4.99 ms
9.99 ms
16.8 ms
20.13 ms
49.98 ms
60.13 ms
100 ms
200 ms
400 ms
800 ms
31,250
15,625
10,417
5208
3906
1157
539
401
206
102
59.98
50
20
16.67
10
5
2.5
8.2
7.0
6.0
4.5
3.9
2.2
1.5
1.3
0.88
0.64
0.48
0.47
0.27
0.25
0.2
0.14
0.091
0.088
20.2
20.4
20.7
21.1
21.3
22.2
22.6
22.9
23.3
23.8
24
24
24
24
24
24
24
24
66
52
45
33
29
15
10
9.1
6.1
4.2
3.2
3.1
1.7
1.6
1.1
0.75
0.32
0.32
17.2
17.5
17.8
18.2
18.4
19.3
19.9
20.1
20.6
21.2
21.6
21.6
22.4
22.6
23.1
24
5
2.5
1.25
5
2.5
1.25
24
24
1.25
1 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
2 1000 samples.
Rev. B | Page 30 of 61
Data Sheet
AD7172-4
Table 21. Output Data Rate, Settling Time, and Noise Using the Sinc5 + Sinc1 Filter with Input Buffers Enabled
Default Output Data
Rate (SPS);
SING_CYC = 0 and
Single Channel
Enabled1
Output Data Rate
(SPS/Channel);
SING_CYC = 1 or
with Multiple
Effective
Peak-to-Peak
Resolution with
5 V Reference
(Bits)
Notch
Frequency
(Hz)
Resolution with
5 V Reference
(Bits)
Settling
Time1
Noise
(μV rms)
Noise
Channels Enabled1
(μV p-p)2
31,250
15,625
10,417
5208
2597
1007
503.8
381
200.3
100.2
59.52
49.68
20.01
16.63
10
6211
5181
4444
3115
2597
1007
503.8
381
200.3
100.2
59.52
49.68
20.01
16.63
10
161 μs
193 μs
225 μs
321 μs
385 μs
993 μs
1.99 ms
2.63 ms
4.99 ms
9.99 ms
16.8 ms
20.13 ms
49.98 ms
60.13 ms
100 ms
200 ms
400 ms
800 ms
31,250
15,625
10,417
5208
3906
1157
539
401
206
102
59.98
50
20
16.67
10
5
2.5
9.5
8.2
7.1
5.3
4.7
2.6
1.8
1.6
20
74
63
53
39
29
16
12
11
7.5
5.1
3.6
3.3
1.8
1.7
1.2
0.83
0.35
0.35
17
20.2
20.4
20.9
21
21.9
22.4
22.6
23.1
23.6
24
24
24
24
24
24
24
24
17.3
17.5
18
18.4
19.3
19.7
19.8
20.3
21
21.4
21.5
22.4
22.5
23
1.1
0.75
0.62
0.53
0.32
0.32
0.25
0.18
0.11
0.089
5
2.5
1.25
5
2.5
1.25
23.5
24
24
1.25
1 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
2 1000 samples.
Rev. B | Page 31 of 61
AD7172-4
Data Sheet
Table 22. Output Data Rate, Settling Time, and Noise Using the Sinc3 Filter with Input Buffers Disabled
Default Output
Data Rate (SPS);
SING_CYC = 0 and
Single Channel
Enabled1
Output Data Rate
(SPS/Channel);
SING_CYC = 1 or with
Multiple Channels
Enabled1
Effective
Peak-to-Peak
Resolution with
5 V Reference
(Bits)
Notch
Frequency
(Hz)
Resolution with
5 V Reference
(Bits)
Settling
Time1
Noise
(μV rms)
Noise
(μV p-p)2
31,250
15,625
10,417
5,208
2,604
1,008
504
400.6
200.3
100.2
59.98
50
20.01
16.67
10
5
2.5
10,309
5,181
3,460
1,733
867.3
335.9
167.98
133.5
66.67
33.39
19.99
16.67
6.67
97 μs
193 μs
289 μs
577 μs
1.15 ms
2.98 ms
5.95 ms
7.49 ms
14.98 ms
29.95 ms
50.02 ms
60 ms
31,250
15,625
10,417
5,208
2,604
1,008
504
400.6
200.3
100.2
59.98
50
211
27.2
7.9
3.7
2.5
15.5
18.5
20.3
21.4
21.9
22.6
23.1
23.3
23.7
24
24
24
24
24
24
24
24
24
1600
205
57
27
17
11
7.5
6.7
4.6
3.1
2.5
2.3
1.2
12.5
15.6
17.4
18.5
19.2
19.8
20.3
20.5
21
1.6
1.1
0.99
0.68
0.47
0.38
0.35
0.21
0.21
0.18
0.18
0.16
0.054
21.6
21.9
22
149.95 ms 20.01
23
5.56
3.33
1.67
0.83
180 ms
300 ms
600 ms
1.2 sec
2.4 sec
16.67
10
5
2.5
1.25
1.1
23.1
23.5
24
24
24
0.83
0.56
0.41
0.27
1.25
0.42
1 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
2 1000 samples.
Table 23. Output Data Rate, Settling Time, and Noise Using the Sinc3 Filter with Input Buffers Enabled
Default Output
Data Rate (SPS);
SING_CYC = 0 and
Single Channel
Enabled1
Output Data Rate
(SPS/Channel);
SING_CYC = 1 or with
Multiple Channels
Enabled1
Effective
Peak-to-Peak
Resolution with
5 V Reference
(Bits)
Notch
Frequency
(Hz)
Resolution with
5 V Reference
(Bits)
Settling
Time1
Noise
(μV rms)
Noise
(μV p-p)2
31,250
15,625
10,417
5,208
2,604
1,008
504
400.6
200.3
100.2
59.98
50
20.01
16.67
10
5
2.5
10,309
5,181
3,460
1,733
867.3
335.9
167.98
133.5
66.67
33.39
19.99
16.67
6.67
97 μs
193 μs
289 μs
577 μs
31,250
15,625
10,417
5,208
2,604
1,008
504
400.6
200.3
100.2
59.98
50
20.01
16.67
10
5
2.5
212
27.7
8.5
4.3
3.0
1.8
1.3
1.2
0.82
0.57
0.45
0.44
0.26
0.24
0.19
0.12
0.098
0.073
15.5
18.5
20.2
21.2
21.7
22.4
22.9
23
23.5
24
24
24
24
1600
210
63
28
20
13
8.9
8.2
5.6
3.8
2.8
2.5
1.3
12.5
15.5
17.3
18.4
19
19.6
20.1
20.2
20.8
21.3
21.8
22
22.9
23
23.4
24
24
24
1.15 ms
2.98 ms
5.95 ms
7.49 ms
14.98 ms
29.95 ms
50.02 ms
60 ms
149.95 ms
180 ms
300 ms
600 ms
1.2 sec
5.56
3.33
1.67
0.83
24
24
24
24
1.2
0.91
0.62
0.45
0.29
1.25
0.42
2.4 sec
1.25
24
1 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
2 1000 samples.
Rev. B | Page 32 of 61
Data Sheet
AD7172-4
selected when using the enhanced filters to achieve the specified
settling time and noise performance. Table 24 shows the output
data rates with the accompanying settling time, rejection, and
rms noise. Figure 59 to Figure 66 show the frequency domain
plots of the responses from the enhanced filters.
ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS
The enhanced filters provide rejection of 50 Hz and 60 Hz
simultaneously and allow the user to trade off settling time and
rejection. These filters can operate up to 27.27 SPS or can reject
up to 90 dB of 50 Hz 1 Hz and 60 Hz 1 Hz interference.
These filters are operated by postfiltering the output of the sinc5 +
sinc1 filter. For this reason, the sinc5 + sinc1 filter must be
Table 24. Enhanced Filters Output Data Rate, Noise, Settling Time, and Rejection Using the Enhanced Filters
Settling Simultaneous Rejection of Noise Peak-to-Peak
Output Data Rate (SPS) Time (ms) 50 Hz 1 Hz and 60 Hz 1 Hz(dB)1
(μV rms) Resolution (Bits) Comments
27.27
25
20
36.67
40.0
50.0
60.0
47
62
85
90
0.45
0.44
0.41
0.417
21.4
21.4
21.7
21.7
See Figure 59 and Figure 62
See Figure 60 and Figure 63
See Figure 61 and Figure 64
See Figure 65 and Figure 66
16.667
1 Master clock = 2.00 MHz.
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
100
200
300
400
500
600
0
100
200
300
400
500
600
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 59. 27.27 SPS ODR, 36.67 ms Settling Time
Figure 61. 20 SPS ODR, 50 ms Settling Time
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–100
0
100
200
300
400
500
600
40
45
50
55
60
65
70
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 60. 25 SPS ODR, 40 ms Settling Time
Figure 62. 27.27 SPS ODR, 36.67 ms Settling Time (40 Hz to 70 Hz)
Rev. B | Page 33 of 61
AD7172-4
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
40
–100
45
50
55
60
65
70
0
100
200
300
400
500
600
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 63. 25 SPS ODR, 40 ms Settling Time (40 Hz to 70 Hz)
Figure 65. 16.667 SPS ODR, 60 ms Settling Time
0
0
–10
–20
–30
–40
–50
–60
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–70
–80
–90
–100
40
45
50
55
60
65
70
40
45
50
55
60
65
70
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 64. 20 SPS ODR, 50 ms Settling Time (40 Hz to 70 Hz)
Figure 66. 16.667 SPS ODR, 60 ms Settling Time (40 Hz to 70 Hz)
Rev. B | Page 34 of 61
Data Sheet
AD7172-4
OPERATING MODES
The AD7172-4 has a number of operating modes that can be set
from the ADC mode register and interface mode register (see
Table 28 and Table 29). These modes are as follows and are
described in the following sections:
register. When the data-word has been read from the data register,
RDY
the DOUT/
pin goes high. The user can read this register
additional times, if required. However, ensure that the data
register is not being accessed at the completion of the next
conversion; otherwise, the new conversion word is lost.
Continuous conversion mode
Continuous read mode
Single conversion mode
Standby mode
Power-down mode
Calibration modes (three)
When several channels are enabled, the ADC automatically
sequences through the enabled channels, performing one
conversion on each channel. When all the channels have been
converted, the sequence starts again with the first channel. The
channels are converted in order from the lowest enabled channel
to the highest enabled channel. The data register is updated as
CONTINUOUS CONVERSION MODE
RDY
soon as each conversion is available. The
output pulses
low each time a conversion is available. The user can then read
the conversion while the ADC converts the next enabled channel.
Continuous conversion mode is the default power-up mode.
RDY
The AD7172-4 converts continuously, and the
status register goes low each time a conversion is complete. If
RDY
bit in the
CS
If the DATA_STAT bit in the interface mode register is set to 1,
the contents of the status register, along with the conversion data,
are output each time the data register is read. The status register
indicates the channel to which the conversion corresponds.
is low, the
output also goes low when a conversion is
complete. To read a conversion, write to the communications
register to indicate that the next operation is a read of the data
CS
0x44
0x44
DIN
DATA
DATA
DOUT/RDY
SCLK
Figure 67. Continuous Conversion Mode
Rev. B | Page 35 of 61
AD7172-4
Data Sheet
To enable continuous read mode, set the CONTREAD bit in the
interface mode register. When this bit is set, the only serial interface
operations possible are reads from the data register. To exit con-
tinuous read mode, issue a dummy read of the ADC data register
CONTINUOUS READ MODE
In continuous read mode, it is not required to write to the
communications register before reading ADC data; apply only
RDY
the required number of SCLKs after the
indicate the end of a conversion. When the conversion is read,
RDY
output goes low to
RDY
command (0x44) while the
output is low. Alternatively, apply
CS
a software reset, that is, 64 SCLKs with
= 0 and DIN = 1.
the
output returns high until the next conversion is
This resets the ADC and all register contents. These are the only
commands that the interface recognizes after it is placed in
continuous read mode. Hold DIN low in continuous read mode
until an instruction is to be written to the device.
available. In this mode, the data can be read only once. Ensure
that the data-word is read before the next conversion is
complete. If the user has not read the conversion before the
completion of the next conversion or if insufficient serial clocks
are applied to the AD7172-4 to read the data-word, the serial
output register is reset shortly before the next conversion is
complete, and the new conversion is placed in the output serial
register. The ADC must be configured for continuous
conversion mode to use continuous read mode.
If multiple ADC channels are enabled, each channel is output
in turn, with the status bits being appended to the data if the
DATA_STAT bit is set in the interface mode register. The status
register indicates the channel to which the conversion corresponds.
CS
0x02
0x0080
DIN
DATA
DATA
DATA
DOUT/RDY
SCLK
Figure 68. Continuous Read Mode
Rev. B | Page 36 of 61
Data Sheet
AD7172-4
output goes low. The ADC then selects the next channel and
SINGLE CONVERSION MODE
begins a conversion. The user can read the present conversion
while the next conversion is being performed. When the next
conversion is complete, the data register is updated; therefore,
the user has a limited period in which to read the conversion.
When the ADC has performed a single conversion on each of
the selected channels, it returns to standby mode.
In single conversion mode, the AD7172-4 performs a single
conversion and is placed in standby mode after the conversion
RDY
is complete. The
of a conversion. When the data-word has been read from the
RDY
output goes low to indicate the completion
data register, the
output goes high. The data register can be
RDY
read several times, if required, even when the
high.
output has gone
If the DATA_STAT bit in the interface mode register is set to 1,
the contents of the status register, along with the conversion, are
output each time the data register is read. The two LSBs of the
status register indicate the channel to which the conversion
corresponds.
If several channels are enabled, the ADC automatically
sequences through the enabled channels and performs a
conversion on each channel. When a conversion is started, the
RDY
output goes high and remains high until a valid conversion is
CS
RDY
available and is low. When the conversion is available, the
CS
0x01
0x8010
0x44
DIN
DATA
DOUT/RDY
SCLK
Figure 69. Single Conversion Mode
Rev. B | Page 37 of 61
AD7172-4
Data Sheet
To start a calibration, write the relevant value to the mode bits
STANDBY AND POWER-DOWN MODES
RDY
RDY
in the ADC mode register. The DOUT/
pin and the
bit
In standby mode, most blocks are powered down. The LDO
regulators remain active so that the registers maintain their
contents. The crystal oscillator remains active if selected. To
power down the clock in standby mode, set the CLOCKSEL bits
in the ADC mode register to 00 (internal oscillator mode).
in the status register go high when the calibration initiates. When
the calibration is complete, the contents of the corresponding offset
RDY
or gain register are updated, the
bit in the status register is
RDY
CS
is low), and the
reset and the
output pin returns low (if
AD7172-4 reverts to standby mode.
In power-down mode, all blocks are powered down, including
the LDO regulators. All registers lose their contents, and the GPIO
outputs are placed in three-state. To prevent accidental entry to
power-down mode, the ADC must first be placed in standby
During an internal offset calibration, the selected positive
analog input pin is disconnected, and both modulator inputs
are connected internally to the selected negative analog input
pin. Therefore, it is necessary to ensure that the voltage on the
selected negative analog input pin does not exceed the allowed
limits and is free from excessive noise and interference.
CS
mode. Exiting power-down mode requires 64 SCLKs with
= 0
and DIN = 1, that is, a serial interface reset. A delay of 500 μs is
recommended before issuing a subsequent serial interface
command to allow the LDO regulator to power up.
However, for system calibrations the system zero-scale (offset)
and system full-scale (gain) voltages must be applied to the
ADC pins before initiating the calibration modes. As a result,
errors external to the ADC are removed.
CALIBRATION
The AD7172-4 allows a two-point calibration to be performed
to eliminate any offset and gain errors. Three calibration modes
are used to eliminate these offset and gain errors on a per setup
basis:
From an operational point of view, treat a calibration like
another ADC conversion. An offset calibration, if required,
must always be performed before a full-scale calibration. Set the
Internal zero-scale calibration mode
System zero-scale calibration mode
System full-scale calibration mode
RDY
system software to monitor the
bit in the status register or
output to determine the end of a calibration via a
RDY
the
polling sequence or an interrupt driven routine. All calibrations
require a time equal to the settling time of the selected filter and
output data rate to be completed.
There is no internal full-scale calibration mode because this is
calibrated in the factory at the time of production.
An internal offset calibration, system zero-scale calibration, and
system full-scale calibration can be performed at any output data
rate. Using lower output data rates results in better calibration
accuracy and is accurate for all output data rates. A new offset
calibration is required for a given channel if the reference source
for that channel is changed.
Only one channel can be active during calibration. After each
conversion, the ADC conversion result is scaled using the ADC
calibration registers before being written to the data register.
The default value of the offset register is 0x800000, and the
nominal value of the gain register is 0x555555. The calibration
range of the ADC gain is from 0.4 × VREF to 1.05 × VREF. The
following equations show the calculations that are used. In
unipolar mode, the ideal relationship—that is, not taking into
account the ADC gain error and offset error—is as follows:
The offset error is typically 75 μV and an offset calibration
reduces the offset error to the order of the noise. The gain error
is factory calibrated at ambient temperature. Following this
calibration, the gain error is typically 5 ppm of FSR.
0.75VIN
VREF
Data
223 (Offset0x800000)
The AD7172-4 provides the user with access to the on-chip
calibration registers, allowing the microprocessor to read the
calibration coefficients of the device and to write its own
calibration coefficients. A read or write of the offset and gain
registers can be performed at any time except during an internal
or self calibration.
Gain
2
0x400000
In bipolar mode, the ideal relationship—that is, not taking into
account the ADC gain error and offset error—is as follows:
0.75 VIN
VREF
Data
223 (Offset 0x800000)
Gain
0x400000
0x800000
Rev. B | Page 38 of 61
Data Sheet
AD7172-4
DIGITAL INTERFACE
The programmable functions of the AD7172-4 are controlled via
the SPI. The serial interface of the AD7172-4 consists of four
For CRC checksum calculations during a write operation, the
following polynomial is always used:
CS
RDY
signals: , DIN, SCLK, and DOUT/
. The DIN input
x8 + x2 + x + 1
transfers data into the on-chip registers, and the DOUT output
accesses data from the on-chip registers. SCLK is the serial clock
input for the device, and all data transfers (either on the DIN input
or on the DOUT output) occur with respect to the SCLK signal.
During read operations, the user can select between this
polynomial and a simpler exclusive OR (XOR) function. The
XOR function requires less time to process on the host
microcontroller than the polynomial-based checksum. The
CRC_EN bits in the interface mode register enable and disable
the checksum and allow the user to select between the
polynomial check and the simple XOR check.
RDY
The DOUT/
the output going low if
available in the data register. The
a read operation from the data register is complete. The
output also goes high before updating the data register to
indicate when not to read from the device to ensure that a data
read is not attempted while the register is being updated. Take
pin also functions as a data ready signal, with
CS
is low when a new data-word is
RDY
output is reset high when
RDY
The checksum is appended to the end of each read and write
transaction. The checksum calculation for the write transaction
is calculated using the 8-bit command word and the 8-bit to
24-bit data. For a read transaction, the checksum is calculated
using the command word and the 8-bit to 32-bit data output.
Figure 70 and Figure 71 show SPI write and read transactions,
respectively.
RDY
care to avoid reading from the data register when the
output is about to go low. The best method to ensure that no data
RDY
read occurs is to always monitor the
output. Start reading
output goes low, and
ensure a sufficient SCLK rate, such that the read is completed
CS
RDY
the data register as soon as the
8-BIT COMMAND
UP TO 24-BIT INPUT
8-BIT CRC
CS
CS
is used to select a device.
before the next conversion result.
can decode the AD7172-4 in systems where several components
are connected to the serial bus.
CS
DATA
CRC
DIN
Figure 2 and Figure 3 show timing diagrams for interfacing to
SCLK
CS
the AD7172-4 using
to decode the device. Figure 2 shows
the timing for a read operation from the AD7172-4, and Figure 3
shows the timing for a write operation to the AD7172-4. It is
possible to read from the data register several times even though
Figure 70. SPI Write Transaction with CRC
UP TO 32-BIT
8-BIT COMMAND
OUTPUT
8-BIT CRC
CS
RDY
the
output returns high after the first read operation.
However, take care to ensure that the read operations are complete
before the next output update occurs. In continuous read mode,
the data register can be read only once.
CMD
DIN
CS
DOUT/
RDY
Operate the serial interface in 3-wire mode by tying
low. In
pins are used to
communicate with the AD7172-4. The end of the conversion
RDY
DATA
CRC
RDY
this case, the SCLK, DIN, and DOUT/
SCLK
can also be monitored using the
bit in the status register.
CS
The AD7172-4 can be reset by writing 64 SCLKs with
= 0
Figure 71. SPI Read Transaction with CRC
and DIN = 1. A reset returns the interface to the state in which it
expects a write to the communications register. This operation
resets the contents of all registers to their power-on values.
Following a reset, allow a period of 500 μs before addressing the
serial interface.
If checksum protection is enabled when continuous read mode
is active, an implied read data command of 0x44 before every
data transmission must be accounted for when calculating the
checksum value. This implied read data command ensures a
nonzero checksum value even if the ADC data equals 0x000000.
CHECKSUM PROTECTION
The AD7172-4 has a checksum mode that can improve
interface robustness. Using the checksum ensures that only
valid data is written to a register and allows data read from a
register to be validated. If an error occurs during a register
write, the CRC_ERROR bit is set in the status register. However,
to ensure that the register write is successful, read back the
register and verify the checksum.
Rev. B | Page 39 of 61
AD7172-4
Data Sheet
aligned so that the MSB is adjacent to the leftmost Logic 1 of the
data. An XOR function is applied to the data to produce a new,
shorter number. The polynomial is again aligned so that its MSB is
adjacent to the leftmost Logic 1 of the new result, and the procedure
is repeated. This process repeats until the original data is reduced to
a value less than the polynomial. This is the 8-bit checksum.
CRC CALCULATION
Polynomial
The checksum, which is eight bits wide, is generated using the
polynomial
x8 + x2 + x + 1
To generate the checksum, the data is left shifted by eight bits to
create a number ending in eight Logic 0s. The polynomial is
Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data)
An example of generating the 8-bit checksum using the polynomial based checksum is as follows:
Initial value
011001010100001100100001
01100101010000110010000100000000
left shifted eight bits
polynomial
x8 + x2 + x + 1
=
100000111
100100100000110010000100000000
100000111
XOR result
polynomial
XOR result
polynomial
XOR result
polynomial value
XOR result
polynomial value
XOR result
polynomial value
XOR result
polynomial value
XOR result
polynomial value
XOR result
polynomial value
XOR result
polynomial value
XOR result
polynomial value
XOR result
polynomial value
XOR result
polynomial value
checksum = 0x86
100011000110010000100000000
100000111
11111110010000100000000
100000111
1111101110000100000000
100000111
111100000000100000000
100000111
11100111000100000000
100000111
1100100100100000000
100000111
100101010100000000
100000111
101101100000000
100000111
1101011000000
100000111
101010110000
100000111
1010001000
100000111
10000110
Rev. B | Page 40 of 61
Data Sheet
AD7172-4
XOR Calculation
The checksum, which is 8 bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes.
Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data)
Using the previous example, divide into three bytes: 0x65, 0x43, and 0x21
01100101
01000011
00100110
00100001
00000111
0x65
0x43
XOR result
0x21
CRC
Rev. B | Page 41 of 61
AD7172-4
Data Sheet
INTEGRATED FUNCTIONS
The AD7172-4 has integrated functions that improve the
usefulness of a number of applications as well as serve
diagnostic purposes in safety conscious applications.
The effect on the noise performance depends on the delay time
compared to the conversion time. It is possible to absorb the
delay only for output data rates less than 2.6 kSPS with the
exception of the following four rates, which cannot absorb any
delay: 381 SPS, 59.52 SPS, 49.68 SPS, and 16.66 SPS.
GENERAL-PURPOSE INPUT/OUTPUT
The AD7172-4 has two digital GPIO pins (GPIO0 and GPIO1)
and two general-purpose digital output pins (GPO2 and
GPO3). As the naming convention suggests, the GPIO0 and
GPIO1 pins can be configured as inputs or outputs, but GPO2
and GPO3 are outputs only. The GPIOx and GPOx pins are
enabled using the following bits in the GPIOCON register:
IP_EN0, IP_EN1 (or OP_EN0, OP_EN1) for GPIO0 and
GPIO1, and OP_EN2_3 for GPO2 and GPO3.
16-BIT/24-BIT CONVERSIONS
By default, the AD7172-4 generates 24-bit conversions.
However, the width of the conversions can be reduced to 16 bits.
Setting the WL16 bit in the interface mode register to 1 rounds
all data conversions to 16 bits. Clearing this bit sets the width of
the data conversions to 24 bits.
DOUT_RESET
When the GPIO0 pin or the GPIO1 pin is enabled as an input,
the logic level at the pin is contained in the GP_DATA0 or
GP_DATA1 bit, respectively. When the GPIO0, GPIO1, GPO2,
or GPO3 pin is enabled as an output, the GP_DATA0, GP_DATA1,
GP_DATA2, or GP_DATA3 bit, respectively, determine the logic
level output at the pin. The logic levels for these pins are referenced
to AVDD1 and AVSS.
RDY
The serial interface uses a shared DOUT/
pin. By default,
signal. During a data read, this pin
outputs the data from the register being read. After the read is
RDY
RDY
this pin outputs the
complete, the pin reverts to outputting the
fixed period of time (t7). However, this time may be too short for
CS
signal after a short
some microcontrollers and can be extended until the
brought high by setting the DOUT_RESET bit in the interface
CS
pin is
ERROR
The
When the ERR_EN bits in the GPIOCON register are set to 11,
ERROR
pin can also be used as a general-purpose output.
mode register to 1. This setting means that
must frame each
read operation and compete the serial interface transaction.
the
pin operates as a general-purpose output. In this
SYNCHRONIZATION
Normal Synchronization
configuration, the ERR_DAT bit in the GPIOCON register
determines the logic level output at the pin. The logic level for
the pin is referenced to IOVDD and DGND.
When the SYNC_EN bit in the GPIOCON register is set to 1,
SYNC
SYNC
the
pin functions as a synchronization input. The
All general-purpose outputs have an active pull-up.
input allows the user to reset the modulator and the digital filter
without affecting any of the setup conditions on the device. This
feature allows the user to start to gather samples of the analog
EXTERNAL MULTIPLEXER CONTROL
If an external multiplexer is used to increase the channel count,
the multiplexer logic pins can be controlled via the AD7172-4
GPIOx pins. With the MUX_IO bit, the GPIOx timing is controlled
by the ADC; therefore, the channel change is synchronized with
the ADC, eliminating any need for external synchronization.
SYNC
input from a known point, the rising edge of the
input.
SYNC
The
input must be low for at least one master clock cycle
to ensure that synchronization occurs.
If multiple AD7172-4 devices are operated from a common master
clock, they can be synchronized so that their analog inputs are
sampled simultaneously. This synchronization is typically
completed after each AD7172-4 device has performed its own
calibration or has calibration coefficients loaded into its
DELAY
It is possible to insert a programmable delay before the AD7172-4
begins to take samples. This delay allows an external amplifier
or multiplexer to settle and can also alleviate the specification
requirements for the external amplifier or multiplexer. Eight
programmable settings, ranging from 0 μs to 8 ms, can be set using
the delay bits in the ADC mode register (Register 0x01, Bits[10:8]).
SYNC
calibration registers. A falling edge on the
digital filter and the analog modulator and places the AD7172-4
SYNC
input resets the
into a consistent known state. While the
input is low, the
SYNC
AD7172-4 is maintained in this known state. On the
If a delay greater than 0 μs is selected and the HIDE_DELAY bit
in the ADC mode register is set to 0, this delay is added to the
conversion time, regardless of the selected output data rate.
input rising edge, the modulator and filter are taken out of this
reset state, and on the next master clock edge, the device starts to
gather input samples again.
When using the sinc5 + sinc1 filter, it is possible to hide this
delay such that the output data rate remains the same as the output
data rate without the delay enabled. If the HIDE_DELAY bit is
set to 1 and the selected delay is less than half of the conversion
time, the delay can be absorbed by reducing the number of
averages the digital filter performs, which keeps the conversion
time the same but can affect the noise performance.
The device is taken out of reset on the master clock falling edge
SYNC
following the
multiple devices are being synchronized, take the
high on the master clock rising edge to ensure that all devices
SYNC
input low to high transition. Therefore, when
SYNC
input
are released on the master clock falling edge. If the
input
is not taken high in sufficient time, a difference of one master
Rev. B | Page 42 of 61
Data Sheet
AD7172-4
clock cycle between the devices is possible; that is, the instant at
which conversions are available differs from device to device by
a maximum of one master clock cycle.
the on-chip registers. If a bit changes, the REG_ERROR bit is
set to 1. Therefore, for writes to the on-chip registers, set the
REG_CHECK bit to 0. When the registers have been updated,
the REG_CHECK bit can be set to 1. The AD7172-4 calculates a
checksum of the on-chip registers. If one of the register values
has changed, the REG_ERROR bit is set to 1. If an error is
flagged, the REG_CHECK bit must be set to 0 to clear the
REG_ERROR bit in the status register. The register check
function does not monitor the data register, status register, or
interface mode register.
SYNC
The
command for a single channel when in normal synchronization
SYNC
input can also be used as a start conversion
mode. In this mode, the rising edge of the
RDY
input starts a
output indicates
conversion, and the falling edge of the
when the conversion is complete. The settling time of the filter is
required for each data register update. After the conversion is
SYNC
complete, bring the
conversion start signal.
input low in preparation for the next
ERROR
Input/Output
ERROR
The
pin functions as an error input/output pin or as a
Alternate Synchronization
general-purpose output pin. The ERR_EN bits in the GPIOCON
register determine the function of the pin.
SYNC
In alternate synchronization mode, the
input operates as a
start conversion command when several channels of the AD7172-4
are enabled. Setting the ALT_SYNC bit in the interface mode
register to 1 enables an alternate synchronization scheme. When
ERROR
When ERR_EN is set to 10, the
open-drain error output. The three error bits in the status
register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are
pin functions as an
SYNC
the
on the current channel, selects the next channel in the sequence,
SYNC
input is taken low, the ADC completes the conversion
ERROR
OR’ed, inverted, and mapped to the
output. Therefore, the
output indicates that an error has occurred. The status
register must be read to identify the error source.
ERROR
ERROR
and then waits until the
input is taken high to start the
output goes low when the conversion is
complete on the current channel, and the data register is updated
SYNC
RDY
conversion. The
When ERR_EN is set to 01, the
error input. The error output of another component can be
ERROR
pin functions as an
with the corresponding conversion. Therefore, the
input
does not interfere with the sampling on the currently selected
channel but allows the user to control the instant at which the
conversion begins on the next channel in the sequence.
connected to the AD7172-4
indicates when an error occurs on either itself or the external
ERROR
input so that the AD7172-4
component. The value on the
input is inverted and OR’ed
with the errors from the ADC conversion, and the result is
indicated via the ADC_ERROR bit in the status register. The value
Alternate synchronization mode can be used only when several
channels are enabled. It is not recommended to use this mode
when a single channel is enabled.
ERROR
of the
GPIO onfiguration register.
ERROR
input is reflected in the ERR_DAT bit in the
ERROR FLAGS
The
input/output is disabled when ERR_EN is set to 00.
The status register contains three error bits (ADC_ERROR,
CRC_ERROR, and REG_ERROR) that flag errors with the
ADC conversion, errors with the CRC check, and errors caused
ERROR
When the ERR_EN bits are set to 11, the
as a general-purpose output.
pin operates
ERROR
by changes in the registers, respectively. In addition, the
output can indicate that an error has occurred.
DATA_STAT
The contents of the status register can be appended to each con-
version on the AD7172-4 using the DATA_STAT bit in the
IFMODE register. This function is useful if several channels are
enabled. Each time a conversion is output, the contents of the
status register are appended. The two LSBs of the status register
indicate to which channel the conversion corresponds. In
addition, the user can determine if any errors are being flagged
by the error bits.
ADC_ERROR
The ADC_ERROR bit in the status register flags any errors that
occur during the conversion process. The flag is set when an over-
range or underrange result is output from the ADC. The ADC
also outputs all 0s or all 1s when an undervoltage or overvoltage
occurs. This flag is reset only when the overvoltage or undervoltage
is removed. This flag is not reset by a read of the data register.
IOSTRENGTH
CRC_ERROR
The serial interface can operate with a power supply as low as
If the CRC value that accompanies a write operation does not
correspond with the information sent, the CRC_ERROR flag is
set. The flag is reset when the status register is explicitly read.
RDY
2 V. However, at this low voltage, the DOUT/
pin may not
have sufficient drive strength if there is moderate parasitic
capacitance on the board or if the SCLK frequency is high. The
IOSTRENGTH bit in the interface mode register increases the
REG_ERROR
The REG_ERROR flag is used in conjunction with the
REG_CHECK bit in the interface mode register. When the
REG_CHECK bit is set, the AD7172-4 monitors the values in
RDY
drive strength of the DOUT/
pin.
Rev. B | Page 43 of 61
AD7172-4
Data Sheet
GROUNDING AND LAYOUT
The analog inputs and reference inputs are differential and,
therefore, most of the voltages in the analog modulator are
common-mode voltages. The high common-mode rejection of
the device removes common-mode noise on these inputs. The
analog and digital supplies to the AD7172-4 are independent
and connected to separate pins to minimize coupling between the
analog and digital sections of the device. The digital filter
provides rejection of broadband noise on the power supplies,
except at integer multiples of the master clock frequency.
supply lines to the AD7172-4 must use as wide a trace as
possible to provide low impedance paths and reduce glitches on
the power supply line. Shield fast switching signals like clocks
with digital ground to prevent radiating noise to other sections
of the board and never run clock signals near the analog inputs.
Avoid crossover of digital and analog signals. Run traces on
opposite sides of the board at right angles to each other. This
technique reduces the effects of feedthrough on the board. A
microstrip technique is by far the best but is not always possible
with a double-sided board.
The digital filter also removes noise from the analog and
reference inputs, provided that these noise sources do not
saturate the analog modulator. As a result, the AD7172-4 is
more immune to noise interference than a conventional high
resolution converter. However, because the resolution of the
AD7172-4 is high and the noise levels from the converter are so
low, take care with regard to grounding and layout.
Good decoupling is important when using high resolution ADCs.
The AD7172-4 has three power supply pins: AVDD1, AVDD2,
and IOVDD. The AVDD1 and AVDD2 pins are referenced to
AVSS, and the IOVDD pin is referenced to DGND. Decouple
AVDD1 and AVDD2 with a 10 μF capacitor in parallel with a
0.1 μF capacitor to AVSS on each pin. Place the 0.1 μF capacitor
as close as possible to the device on each supply, ideally right up
against the device. Decouple IOVDD with a 10 μF capacitor in
parallel with a 0.1 μF capacitor to DGND. Decouple all analog
inputs to AVSS. Decouple the REF and REF2 pins to AVSS.
The PCB that houses the ADC must be designed such that the
analog and digital sections are separated and confined to
certain areas of the board. A minimum etch technique is
generally best for ground planes because it results in the best
shielding.
The AD7172-4 also has two on-board LDO regulators, one that
regulates the AVDD2 supply and one that regulates the IOVDD
supply. For the REGCAPA pin, use 1 μF and 0.1 μF capacitors to
AVSS. Similarly, for the REGCAPD pin, use 1 μF and 0.1 μF
capacitors to DGND.
In any layout, the user must consider the flow of currents in the
system, ensuring that the paths for all return currents are as close as
possible to the paths the currents took to reach their destinations.
Avoid running digital lines under the device because this
couples noise onto the die. Allow the analog ground plane to
run under the AD7172-4 to prevent noise coupling. The power
If using the AD7172-4 for split supply operation, a separate
plane must be used for AVSS.
Rev. B | Page 44 of 61
Data Sheet
AD7172-4
REGISTER SUMMARY
Table 25. Register Summary
Reg. Name
Bits
Bit 7
RA
Bit 0
Reset
RW
0x00 COMMS
[7:0]
WEN
R/W
0x00
W
0x00 STATUS
[7:0]
RDY
HIDE_DELAY
SING_CYC
MODE
CHANNEL
DELAY
RESERVED
0x80
R
0x01 ADCMODE
[15:8]
[7:0]
RESERVED
RESERVED
RESERVED
0x2000
RW
CLOCKSEL
IOSTRENGTH
0x02 IFMODE
[15:8]
[7:0]
RESERVED
ALT_SYNC
REGISTER_CHECK[23:0]
DATA[23:0]
ID[15:8]
ID[7:0]
RESERVED
DOUT_RESET 0x0000
WL16
RW
CONTREAD
0x03 REGCHECK
0x04 DATA
[23:0]
[23:0]
[15:8]
[7:0]
0x000000
R
0x000000
0x0800
R
0x06 GPIOCON
RESERVED
GP_DATA3
ERR_DAT
RW
GP_DATA0
0x07 ID
[15:8]
[7:0]
0x205X
0x8001
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
R
0x10 CH0
[15:8]
[7:0]
CH_EN0
CH_EN1
CH_EN2
CH_EN3
CH_EN4
CH_EN5
CH_EN6
CH_EN7
SETUP_SEL0
SETUP_SEL1
SETUP_SEL2
SETUP_SEL3
SETUP_SEL4
RESERVED
AINNEG0
RESERVED
AINNEG1
RESERVED
AINNEG2
RESERVED
AINNEG3
AINPOS0[4:3]
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
AINPOS0[2:0]
AINPOS1[2:0]
AINPOS2[2:0]
AINPOS3[2:0]
0x11 CH1
[15:8]
[7:0]
AINPOS1[4:3]
AINPOS2[4:3]
AINPOS3[4:3]
AINPOS4[4:3]
AINPOS5[4:3]
AINPOS6[4:3]
AINPOS7[4:3]
0x12 CH2
[15:8]
[7:0]
0x13 CH3
[15:8]
[7:0]
0x14 CH4
[15:8]
[7:0]
RESERVED
AINPOS4[2:0]
AINNEG4
0x15 CH5
[15:8]
[7:0]
SETUP_SEL5
SETUP_SEL6
SETUP_SEL7
RESERVED
AINPOS5[2:0]
AINPOS6[2:0]
AINNEG5
RESERVED
AINNEG6
RESERVED
AINNEG7
0x16 CH6
[15:8]
[7:0]
0x17 CH7
[15:8]
[7:0]
AINPOS7[2:0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0x20 SETUPCON0
0x21 SETUPCON1
0x22 SETUPCON2
0x23 SETUPCON3
0x24 SETUPCON4
0x25 SETUPCON5
0x26 SETUPCON6
0x27 SETUPCON7
0x28 FILTCON0
0x29 FILTCON1
0x2A FILTCON2
0x2B FILTCON3
0x2C FILTCON4
0x2D FILTCON5
0x2E FILTCON6
[15:8]
[7:0]
REF_SEL0
REF_SEL1
REF_SEL2
REF_SEL3
REF_SEL4
REF_SEL5
REF_SEL6
REF_SEL7
ENHFILTEN0
ENHFILTEN1
ENHFILTEN2
ENHFILTEN3
ENHFILTEN4
ENHFILTEN5
ENHFILTEN6
AINBUF0− 0x1000
AINBUF1− 0x1000
AINBUF2− 0x1000
AINBUF3− 0x1000
AINBUF4− 0x1000
AINBUF5− 0x1000
AINBUF6− 0x1000
AINBUF7− 0x1000
0x0500
BURNOUT_EN0
BURNOUT_EN1
BURNOUT_EN2
BURNOUT_EN3
BURNOUT_EN4
BURNOUT_EN5
BURNOUT_EN6
RESERVED
[15:8]
[7:0]
RESERVED
[15:8]
[7:0]
RESERVED
[15:8]
[7:0]
RESERVED
[15:8]
[7:0]
RESERVED
[15:8]
[7:0]
RESERVED
[15:8]
[7:0]
RESERVED
[15:8]
[7:0]
BURNOUT_EN7
SINC3_MAP0
RESERVED
RESERVED
[15:8]
[7:0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ENHFILT0
ENHFILT1
ENHFILT2
ENHFILT3
ENHFILT4
ENHFILT5
ORDER0
ODR0
ODR1
ODR2
ODR3
ODR4
ODR5
ODR6
[15:8]
[7:0]
SINC3_MAP1
RESERVED
0x0500
ORDER1
ORDER2
ORDER3
ORDER4
ORDER5
ORDER6
[15:8]
[7:0]
SINC3_MAP2
RESERVED
0x0500
[15:8]
[7:0]
SINC3_MAP3
RESERVED
0x0500
[15:8]
[7:0]
SINC3_MAP3
RESERVED
0x0500
[15:8]
[7:0]
SINC3_MAP3
RESERVED
0x0500
[15:8]
[7:0]
SINC3_MAP3
RESERVED
0x0500
Rev. B | Page 45 of 61
AD7172-4
Data Sheet
Reg. Name
Bits
Bit 7
RESERVED
ORDER7
ENHFILTEN7
ODR7
ENHFILT7
Bit 0
Reset
RW
0x2F FILTCON7
[15:8]
[7:0]
SINC3_MAP3
RESERVED
0x0500
RW
0x30 OFFSET0
0x31 OFFSET1
0x32 OFFSET2
0x33 OFFSET3
0x34 OFFSET4
0x35 OFFSET5
0x36 OFFSET6
0x37 OFFSET7
0x38 GAIN0
0x39 GAIN1
0x3A GAIN2
0x3B GAIN3
0x3C GAIN4
0x3D GAIN5
0x3E GAIN6
0x3F GAIN7
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
OFFSET0[23:0]
OFFSET1[23:0]
OFFSET2[23:0]
OFFSET3[23:0]
OFFSET5[23:0]
OFFSET6[23:0]
OFFSET6[23:0]
OFFSET7[23:0]
GAIN0[23:0]
GAIN1[23:0]
GAIN2[23:0]
GAIN3[23:0]
GAIN4[23:0]
GAIN5[23:0]
GAIN6[23:0]
GAIN7[23:0]
0x800000 RW
0x800000 RW
0x800000 RW
0x800000 RW
0x800000 RW
0x800000 RW
0x800000 RW
0x800000 RW
0x5XXXX0 RW
0x5XXXX0 RW
0x5XXXX0 RW
0x5XXXX0 RW
0x5XXXX0 RW
0x5XXXX0 RW
0x5XXXX0 RW
0x5XXXX0 RW
Rev. B | Page 46 of 61
Data Sheet
AD7172-4
REGISTER DETAILS
COMMUNICATIONS REGISTER
Address: 0x00, Reset: 0x00, Name: COMMS
All access to the on-chip registers must start with a write to the communications register. This write determines what register is accessed
next and whether the operation is a write or a read.
Table 26. Bit Descriptions for COMMS
Bits
Bit Name
Settings
Description
Reset
0x0
Access
W
7
WEN
This bit must be low to begin communications with the ADC.
6
W
This bit determines if the command is a read or write operation.
0x0
W
R/
0
Write command
1
Read command
[5:0]
RA
The register address bits determine which register is to be read from or written to as part of the current communication.
0x00
W
000000 Status register
000001 ADC mode register
000010 Interface mode register
000011 Register check register
000100 Data register
000110 GPIO configuration register
000111 ID register
010000 Channel Register 0
010001 Channel Register 1
010010 Channel Register 2
010011 Channel Register 3
010100 Channel Register 4
010101 Channel Register 5
010110 Channel Register 6
010111 Channel Register 7
100000 Setup Configuration Register 0
100001 Setup Configuration Register 1
100010 Setup Configuration Register 2
100011 Setup Configuration Register 3
100100 Setup Configuration Register 4
100101 Setup Configuration Register 5
100110 Setup Configuration Register 6
100111 Setup Configuration Register 7
101000 Filter Configuration Register 0
101001 Filter Configuration Register 1
101010 Filter Configuration Register 2
101011 Filter Configuration Register 3
101100 Filter Configuration Register 4
101101 Filter Configuration Register 5
101110 Filter Configuration Register 6
101111 Filter Configuration Register 7
110000 Offset Register 0
110001 Offset Register 1
110010 Offset Register 2
110011 Offset Register 3
110100 Offset Register 4
110101 Offset Register 5
110110 Offset Register 6
110111 Offset Register 7
111000 Gain Register 0
111001 Gain Register 1
111010 Gain Register 2
111011 Gain Register 3
111100 Gain Register 4
111101 Gain Register 5
111110 Gain Register 6
111111 Gain Register 7
Rev. B | Page 47 of 61
AD7172-4
Data Sheet
STATUS REGISTER
Address: 0x00, Reset: 0x80, Name: STATUS
The status register is an 8-bit register that contains ADC and serial interface status information. It can optionally be appended to the data
register by setting the DATA_STAT bit in the interface mode register.
Table 27. Bit Descriptions for STATUS
Bits
Bit Name
Settings
Description
Reset
Access
7
RDY
The status of RDY is output to the DOUT/RDYpin whenever CS is low and a 0x1
register is not being read. This bit goes low when the ADC has written a
new result to the data register. In ADC calibration modes, this bit goes low
when the ADC has written the calibration result. RDY is brought high
automatically by a read of the data register.
R
0
1
New data result available
Awaiting new data result
6
ADC_ERROR
This bit by default indicates if an ADC overrange or underrange has
occurred. The ADC result is clamped to 0xFFFFFF for overrange errors and
0x000000 for underrange errors. This bit is updated when the ADC result is
written and is cleared at the next update after removing the overrange or
underrange condition.
0x0
R
0
1
No error
Error
5
4
CRC_ERROR
REG_ERROR
This bit indicates if a CRC error has taken place during a register write. For
register reads, the host microcontroller determines if a CRC error has
occurred. This bit is cleared by a read of this register.
No error
CRC error
0x0
0x0
R
R
0
1
This bit indicates if the content of one of the internal registers has
changed from the value calculated when the register integrity check was
activated. The check is activated by setting the REG_CHECK bit in the
interface mode register. This bit is cleared by clearing the REG_CHECK bit.
0
1
No error
Error
3
RESERVED
CHANNEL
These bits are reserved.
0x0
0x0
R
R
[2:0]
These bits indicate which channel was active for the ADC conversion
whose result is currently in the data register. This may be different from
the channel currently being converted. The mapping is a direct map from
the channel register; therefore, Channel 0 results in 0x0 and Channel 7
results in 0x7.
000 Channel 0
001 Channel 1
010 Channel 2
011 Channel 3
100 Channel 4
101 Channel 5
110 Channel 6
111 Channel 7
Rev. B | Page 48 of 61
Data Sheet
AD7172-4
ADC MODE REGISTER
Address: 0x01, Reset: 0x2000, Name: ADCMODE
The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets
the filter and the bits and starts a new conversion or calibration.
RDY
Table 28. Bit Descriptions for ADCMODE
Bits
Bit Name
Settings
Description
Reset
0x0
Access
RW
15
RESERVED
HIDE_DELAY
Reserved
14
If a programmable delay is set using the DELAY bits, this bit allows the
delay to be hidden by absorbing the delay into the conversion time for
selected data rates with the sinc5 + sinc1 filter. See the Delay section for
more information.
0x0
RW
0
1
Enabled
Disabled
13
SING_CYC
This bit can be used when only a single channel is active to set the ADC
to only output at the settled filter data rate.
0x1
RW
0
1
Disabled
Enabled
[12:11] RESERVED
These bits are reserved; set these bits to 0.
0x0
0x0
R
[10:8]
DELAY
These bits allow a programmable delay to be added after a channel
switch to allow settling of external circuitry before the ADC starts
processing its input.
RW
000 0 μs
001 32 μs
010 128 μs
011 320 μs
100 800 μs
101 1.6 ms
110 4 ms
111 8 ms
7
RESERVED
MODE
This bit is reserved; set this bit to 0.
0x0
0x0
R
[6:4]
These bits control the operating mode of the ADC. See the Operating
Modes section for more information.
RW
000 Continuous conversion mode
001 Single conversion mode
010 Standby mode
011 Power-down mode
100 Internal offset calibration
110 System offset calibration
111 System gain calibration
[3:2]
[1:0]
CLOCKSEL
RESERVED
This bit is used to select the ADC clock source. Selecting internal
oscillator also enables the internal oscillator.
00 Internal oscillator
01 Internal oscillator output on the XTAL2/CLKIO pin
10 External clock input on the XTAL2/CLKIO pin
11 External crystal on the XTAL1 and XTAL2/CLKIO pins
These bits are reserved; set these bits to 0.
0x0
0x0
RW
R
Rev. B | Page 49 of 61
AD7172-4
Data Sheet
INTERFACE MODE REGISTER
Address: 0x02, Reset: 0x0000, Name: IFMODE
The interface mode register configures various serial interface options.
Table 29. Bit Descriptions for IFMODE
Bits
Bit Name
Settings
Description
Reset
0x0
Access
R
[15:13] RESERVED
These bits are reserved; set these bits to 0.
12
11
ALT_SYNC
This bit enables a different behavior of the SYNC pin to allow the use of
SYNC as a control for conversions when cycling channels (see the
description of the SYNC_EN bit in the GPIO Configuration Register section
for details).
Disabled
Enabled
0x0
RW
0
1
IOSTRENGTH
This bit controls the drive strength of the DOUT/RDY pin. Set this bit when 0x0
reading from the serial interface at high speed with a low IOVDD supply
and moderate capacitance.
RW
0
1
Disabled (default)
Enabled
[10:9]
8
RESERVED
These bits are reserved; set these bits to 0.
0x0
0x0
R
DOUT_RESET
See the DOUT_RESET section for more information.
RW
0
1
Disabled
Enabled
7
6
CONTREAD
DATA_STAT
This enables a continuous read of the ADC data register. The ADC must be 0x0
configured in continuous conversion mode to use continuous read. For
more details, see the Operating Modes section.
Disabled
Enabled
RW
RW
0
1
This enables the status register to be appended to the data register when
read so that the channel and status information are transmitted with the
data. This is the only way to ensure that the channel bits read from the
status register correspond to the data in the data register.
0x0
0
1
Disabled
Enabled
5
REG_CHECK
This bit enables a register integrity checker, which can be used to monitor 0x0
any change in the value of the user registers. To use this feature, configure
all other registers as desired, with this bit cleared. Then write to this register to
set the REG_CHECK bit to 1. If the contents of any of the registers change,
the REG_ERROR bit is set in the status register. To clear the error, set the
REG_CHECK bit to 0. Neither the interface mode register nor the ADC data
or status registers are included in the registers that are checked. If a
register must have a new value written, this bit must first be cleared;
otherwise, an error is flagged when the new register contents are written.
RW
0
1
Disabled
Enabled
4
RESERVED
CRC_EN
This bit is reserved; set this bit to 0.
0x0
R
[3:2]
Enables CRC protection of register reads/writes. CRC increases the
number of bytes in a serial interface transfer by one. See the CRC
Calculation section for more details.
0x00
RW
00 Disabled
01 XOR checksum enabled for register read transactions; register writes still
use CRC with these bits set
10 CRC checksum enabled for read and write transactions
This bit is reserved; set this bit to 0.
1
RESERVED
0x0
R
Rev. B | Page 50 of 61
Data Sheet
AD7172-4
Bits
Bit Name
Settings
Description
Reset
Access
0
WL16
This bit changes the ADC data register to 16 bits. The ADC is not reset by a 0x0
write to the interface mode register; therefore, the ADC result is not
rounded to the correct word length immediately after writing to this bit.
The first new ADC result is correct.
RW
0
1
24-bit data
16-bit data
REGISTER CHECK
Address: 0x03, Reset: 0x000000, Name: REGCHECK
The register check register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK bit
in the interface mode register must be set for this register to operate; otherwise, the register reads 0.
Table 30. Bit Descriptions for REGCHECK
Bits
Bit Name
Settings
Description
Reset
Access
[23:0]
REGISTER_CHECK
This register contains the 24-bit checksum of user registers when the
REG_CHECK bit is set in the interface mode register.
0x000000
R
DATA REGISTER
Address: 0x04, Reset: 0x000000, Name: DATA
The data register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the
RDY RDY
output high ifthey
BI_UNIPOLARx bits in the setup configuration registers. Reading the data register brings the
bit and the
output has been brought high, it is not possible to know if
RDY
are low. The ADC result can be read multiple times; however, because the
another ADC result is imminent. After the command to read the ADC register is received, the ADC does not write a new result into the
data register.
Table 31. Bit Descriptions for DATA
Bits
Bit Name
Settings
Description
Reset
Access
[23:0]
DATA
This register contains the ADC conversion result. If DATA_STAT is set in
the interface mode register, the status register is appended to this
register when read, making this a 32-bit register. If WL16 is set in the
interface mode register, this register is reduced to 16 bits.
0x000000
R
Rev. B | Page 51 of 61
AD7172-4
Data Sheet
GPIO CONFIGURATION REGISTER
Address: 0x06, Reset: 0x0800, Name: GPIOCON
The GPIO configuration register controls the general-purpose input/output pins of the ADC.
Table 32. Bit Descriptions for GPIOCON
Bits
Bit Name
RESERVED
PDSW
Settings Description
Reset
0x0
Access
R
15
These bits are reserved; set these bits to 0.
14
This bit enables/disables the power-down switch function. Setting the bit allows
the pin to sink current. This function can be used for bridge sensor applications
where the switch controls the power-up/power-down of the bridge.
0x0
RW
13
12
OP_EN2_3
MUX_IO
This bit enables the GPO2 and GPO3 pins. Outputs are referenced between AVDD1 0x0
and AVSS.
RW
RW
This bit allows the ADC to control an external multiplexer, using GPIO0/GPIO1/ GPO2 in 0x0
sync with the internal channel sequencing. The analog input pins used for a channel
can still be selected on a per channel basis. Therefore, it is possible to have a 8-
channel multiplexer in front of each analog input pair (AIN0/AIN1 to AIN6/AIN7),
giving a total of 32 differential channels. However, only 8 channels at a time can be
automatically sequenced. Following the sequence of 8 channels, the user must employ
an SPI command to change the selected analog input pair before it sequences through
the next 8 channels supplied by the external multiplexer.
There is a delay function that allows extra time for the analog input to settle, in
conjunction with any switching from an external multiplexer (see the delay bits in the
ADC Mode Register section).
11
SYNC_EN
This bit enables the SYNC pin as a sync input. When the pin is low, this bit holds
the ADC and filter in reset until the SYNC pin goes high. An alternative operation
of the SYNC pin is available when the ALT_SYNC bit in the interface mode register
is set. This mode only works when multiple channels are enabled. In this case, a
low on the SYNC pin does not immediately reset the filter/modulator. Instead, if
the SYNC pin is low when the channel is due to be switched, the modulator and
filter are prevented from starting a new conversion. Bringing SYNC high begins the
next conversion. This alternative sync mode allows SYNC to be used while cycling
through channels.
0x1
RW
0
1
Disabled.
Enabled.
[10:9]
ERR_EN
These bits enable the ERROR pin as an error input/output.
0x0
RW
00 Disabled.
01 ERROR is an error input. The (inverted) readback state is OR'ed with other error
sources and is available in the ADC_ERROR bit in the status register. The ERROR pin
state can also be read from the ERR_DAT bit in this register.
10 ERROR is an open-drain error output. The status register error bits are OR'ed,
inverted, and mapped to the ERROR pin. The ERROR pins of multiple devices can
be wired together to a common pull-up resistor so that an error on any device can
be observed.
11 ERROR is a general-purpose output. The status of the pin is controlled by the
ERR_DAT bit in this register. This output is referenced between IOVDD and DGND,
as opposed to the AVDD1 and AVSS levels used by the GPIO pins. The ERROR pin
has an active pull-up in this case.
8
ERR_DAT
This bit determines the logic level at the ERROR pin if the pin is enabled as a
general-purpose output. This bit reflects the readback status of the pin if the pin is
enabled as an input.
0x0
RW
7
6
5
GP_DATA3
GP_DATA2
IP_EN1
This bit is the write data for GPO3.
0x0
0x0
0x0
W
This bit is the write data for GPO2.
W
This bit turns GPIO1 into an input. Inputs are referenced to AVDD1 or AVSS.
RW
0
1
Disabled.
Enabled.
Rev. B | Page 52 of 61
Data Sheet
AD7172-4
Bits
Bit Name
Settings Description
This bit turns GPIO0 into an input. Inputs are referenced to AVDD1 or AVSS.
Disabled.
Enabled.
Reset
Access
4
IP_EN0
0x0
RW
0
1
3
2
OP_EN1
OP_EN0
This bit turns GPIO1 into an output. Outputs are referenced between AVDD1 and AVSS. 0x0
Disabled.
Enabled.
RW
RW
0
1
This bit turns GPIO0 into an output. Outputs are referenced between AVDD1 and AVSS. 0x0
0
1
Disabled.
Enabled.
1
0
GP_DATA1
GP_DATA0
This bit is the readback or write data for GPIO1.
This bit is the readback or write data for GPIO0.
0x0
0x0
RW
RW
ID REGISTER
Address: 0x07, Reset: 0x205X, Name: ID
The ID register returns a 16-bit ID. For the AD7172-4, this ID is 0x205X.
Table 33. Bit Descriptions for ID
Bits
Bit Name
Settings
Description
Reset
Access
[15:0]
ID
The ID register returns a 16-bit ID code that is specific to the ADC.
0x205X
R
0x205X AD7172-4
Rev. B | Page 53 of 61
AD7172-4
Data Sheet
CHANNEL REGISTER 0
Address: 0x10, Reset: 0x8001, Name: CH0
The channel registers are 16-bit registers that select which channels are currently active, which inputs are selected for each channel, and
which setup is used to configure the ADC for that channel.
Table 34. Bit Descriptions for CH0
Bits
Bit Name
Settings Description
Reset Access
15
CH_EN0
This bit enables Channel 0. If more than one channel is enabled, the ADC
0x1
RW
automatically sequences between them.
Disabled
Enabled (default)
0
1
[14:12] SETUP_SEL0
These bits identify which of the eight setups are used to configure the ADC for this
channel. A setup comprises a set of four registers: the setup configuration register, the
filter configuration register, the offset register, and the gain register. All channels can
use the same setup, in which case the same 2-bit value must be written to these bits on
all active channels, or up to eight channels can be configured differently.
0x0
RW
000 Setup 0
001 Setup 1
010 Setup 2
011 Setup 3
100 Setup 4
101 Setup 5
110 Setup 6
111 Setup 7
[11:10] RESERVED
[9:5] AINPOS0
These bits are reserved; set these bits to 0.
0x0
0x0
R
These bits select which input is connected to the positive input of the ADC for this
channel.
RW
00000 AIN0 (default)
00001 AIN1
00010 AIN2
00011 AIN3
00100 AIN4
00101 AIN5
00110 AIN6
00111 AIN7
01000 AIN8
10011 ((AVDD1 − AVSS)/5)+ (analog input buffers must be enabled)
10100 ((AVDD1 − AVSS)/5)− (analog input buffers must be enabled)
10101 REF+
10110 REF−
[4:0]
AINNEG0
These bits select which input is connected to the negative input of the ADC for this
channel.
0x1
RW
00000 AIN0
00001 AIN1 (default)
00010 AIN2
00011 AIN3
00100 AIN4
00101 AIN5
00110 AIN6
00111 AIN7
01000 AIN8
10011 ((AVDD1 − AVSS)/5)+
10100 ((AVDD1 − AVSS)/5)−
10101 REF+
10110 REF−
Rev. B | Page 54 of 61
Data Sheet
AD7172-4
CHANNEL REGISTER 1 TO CHANNEL REGISTER 7
Address: 0x11 to 0x17, Reset: 0x0001, Name: CH1 to CH7
The remaining seven channel registers share the same layout as Channel Register 0.
Table 35. CH1 to CH7 Register Map
Reg.
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x11
CH1
[15:8]
[7:0]
CH_EN1
SETUP_SEL1
RESERVED
AINPOS1[4:3]
0x0001
RW
AINPOS1[2:0]
AINNEG1
RESERVED
AINNEG2
RESERVED
AINNEG3
RESERVED
AINNEG4
RESERVED
AINNEG5
RESERVED
AINNEG6
RESERVED
AINNEG7
0x12
0x13
0x14
0x15
0x16
0x17
CH2
CH3
CH4
CH5
CH6
CH7
[15:8]
[7:0]
CH_EN2
CH_EN3
CH_EN4
CH_EN5
CH_EN6
CH_EN7
SETUP_SEL2
SETUP_SEL3
SETUP_SEL4
SETUP_SEL5
SETUP_SEL6
SETUP_SEL7
AINPOS2[4:3]
AINPOS3[4:3]
AINPOS4[4:3]
AINPOS5[4:3]
AINPOS6[4:3]
AINPOS7[4:3]
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
RW
RW
RW
RW
RW
RW
AINPOS2[2:0]
AINPOS3[2:0]
AINPOS4[2:0]
AINPOS5[2:0]
AINPOS6[2:0]
AINPOS7[2:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
Rev. B | Page 55 of 61
AD7172-4
Data Sheet
SETUP CONFIGURATION REGISTER 0
Address: 0x20, Reset: 0x1000, Name: SETUPCON0
The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC.
Table 36. Bit Descriptions for SETUPCON0
Bits
Bit Name
Settings
Description
Reset
0x0
Access
R
[15:13] RESERVED
These bits are reserved; set these bits to 0.
This bit sets the output coding of the ADC for Setup 0.
Unipolar coded output
Bipolar coded output (offset binary)
This bit enables or disables the REF+ input buffer.
REF+ buffer disabled
12
11
10
9
BI_UNIPOLAR0
0x1
RW
0
1
REFBUF0+
REFBUF0−
AINBUF0+
AINBUF0−
BURNOUT_EN0
0x0
0x0
0x0
0x0
0x00
RW
RW
RW
RW
R
0
1
REF+ buffer enabled
This bit enables or disables the REF− input buffer.
REF− buffer disabled
REF− buffer enabled
0
1
This bit enables or disables the AIN+ input buffer.
AIN+ buffer disabled
AIN+ buffer enabled
0
1
8
This bit enables or disables the AIN− input buffer.
AIN− buffer disabled
AIN− buffer enabled
0
1
7
This bit enables a 10 μA current source on the positive analog input
selected and a 10 μA current sink on the negative analog input selected.
The burnout currents are useful in diagnosis of an open wire, whereby
the ADC result goes to full scale. Enabling the burnout currents during
measurement results in an offset voltage on the ADC. The best strategy
for diagnosing an open wire is turning on the burnout currents at
intervals, before or after precision measurements.
6
RESERVED
REF_SEL0
These bits are reserved; set these bits to 0.
0x00
0x0
R
[5:4]
These bits allow the user to select the reference source for ADC
conversion on Setup 0.
RW
00 External reference supplied to the REF+ and REF− pins.
01 External Reference 2 supplied to AIN1/REF2+ and AIN0/REF2− pins.
11 AVDD1 − AVSS. This can be used to as a diagnostic to validate other
reference values.
[3:0]
RESERVED
These bits are reserved; set these bits to 0.
0x0
R
Rev. B | Page 56 of 61
Data Sheet
AD7172-4
SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7
Address: 0x21 to 0x27, Reset: 0x1000, Name: SETUPCON1 to SETUPCON7
The remaining seven setup configuration registers share the same layout as Setup Configuration Register 0.
Table 37. SETUPCON1 to SETUPCON7 Register Map
Reg.
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x21
SETUPCON1
[15:8]
[7:0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BI_UNIPOLAR1
REFBUF1+
REFBUF1−
AINBUF1+
AINBUF1−
0x1000
RW
RW
RW
RW
RW
RW
RW
BURNOUT_EN1
BURNOUT_EN2
BURNOUT_EN3
BURNOUT_EN4
BURNOUT_EN5
BURNOUT_EN6
BURNOUT_EN7
REF_SEL1
BI_UNIPOLAR2
REF_SEL2
BI_UNIPOLAR3
REF_SEL3
BI_UNIPOLAR4
REF_SEL4
BI_UNIPOLAR5
REF_SEL5
BI_UNIPOLAR6
REF_SEL6
BI_UNIPOLAR7
REF_SEL7
RESERVED
0x22
0x23
0x24
0x25
0x26
0x27
SETUPCON2
SETUPCON3
SETUPCON4
SETUPCON5
SETUPCON6
SETUPCON7
[15:8]
[7:0]
REFBUF2+
REFBUF3+
REFBUF4+
REFBUF5+
REFBUF6+
REFBUF7+
REFBUF2−
REFBUF3−
AINBUF2+
AINBUF2−
AINBUF3−
AINBUF4−
AINBUF5−
AINBUF6−
AINBUF7−
0x1000
0x1000
0x1000
0x1000
0x1000
0x1000
RESERVED
[15:8]
[7:0]
AINBUF3+
RESERVED
[15:8]
[7:0]
REFBUF4−
AINBUF4+
RESERVED
[15:8]
[7:0]
REFBUF5−
AINBUF5+
RESERVED
[15:8]
[7:0]
REFBUF6−
AINBUF6+
RESERVED
[15:8]
[7:0]
REFBUF7− AINBUF7+
RESERVED
Rev. B | Page 57 of 61
AD7172-4
Data Sheet
FILTER CONFIGURATION REGISTER 0
Address: 0x28, Reset: 0x0500, Name: FILTCON0
The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers
resets any active ADC conversion and restarts converting at the first channel in the sequence.
Table 38. Bit Descriptions for FILTCON0
Bits
Bit Name
Settings
Description
Reset
Access
15
SINC3_MAP0
If this bit is set, the mapping of the filter register changes to directly
program the decimation rate of the sinc3 filter for Setup 0. All other
options are eliminated. This allows fine tuning of the output data rate and
filter notch for rejection of specific frequencies. The data rate when on a
single channel equals fMOD/(32 × FILTCON0[14:0]).
0x0
RW
[14:12] RESERVED
These bits are reserved; set these bits to 0.
0x0
R
11
ENHFILTEN0
This bit enables various postfilters for enhanced 50 Hz and 60 Hz rejection 0x0
for Setup 0. The ORDER0 bits must be set to 00 to select the sinc5 + sinc1
filter for this to work.
RW
0
1
Disabled
Enabled
[10:8]
ENHFILT0
These bits select between various postfilters for enhanced 50 Hz and
60 Hz rejection for Setup 0.
0x5
RW
010 27 SPS, 47 dB rejection, 36.7 ms settling
011 21.25 SPS, 62 dB rejection, 40 ms settling
101 20 SPS, 86 dB rejection, 50 ms settling
110 16.67 SPS, 92 dB rejection, 60 ms settling
This bit is reserved; set this bit to 0.
7
RESERVED
ORDER0
0x0
0x0
R
[6:5]
These bits control the order of the digital filter that processes the
modulator data for Setup 0.
RW
00 Sinc5 + sinc1 (default)
11 Sinc3
[4:0]
ODR0
These bits control the output data rate of the ADC and, therefore, the
settling time and noise for Setup 0. Rates shown are for the sinc5 + sinc1
filter. See Table 20 to Table 23.
0x0
RW
00000 31,250
00001 31,250
00010 31,250
00011 31,250
00100 31,250
00101 31,250
00110 15,625
00111 10,417
01000 5208
01001 2597
01010 1007
01011 503.8
01100 381
01101 200.3
01110 100.2
01111 59.52
10000 49.68
10001 20.01
10010 16.63
10011 10
10100
5
10101 2.5
10110 1.25
Rev. B | Page 58 of 61
Data Sheet
AD7172-4
FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7
Address: 0x29 to 0x2F, Reset: 0x0500, Name: FILTCON1 to FILTCON7
The remaining seven filter configuration registers share the same layout as Filter Configuration Register 0.
Table 39. FILTCON1 to FILTCON7 Register Map
Reg.
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ODR1
Bit 1
ENHFILT1
Bit 0
Reset
RW
0x29
FILTCON1
[15:8]
[7:0]
SINC3_MAP1
RESERVED
RESERVED
ENHFILTEN1
0x0500
RW
ORDER1
RESERVED
ORDER2
RESERVED
ORDER3
RESERVED
ORDER4
RESERVED
ORDER5
RESERVED
ORDER6
RESERVED
ORDER7
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
FILTCON2
FILTCON3
FILTCON4
FILTCON5
FILTCON6
FILTCON7
[15:8]
[7:0]
SINC3_MAP2
RESERVED
ENHFILTEN2
ENHFILTEN3
ENHFILTEN4
ENHFILTEN5
ENHFILTEN6
ENHFILTEN7
ENHFILT2
ENHFILT3
ENHFILT4
ENHFILT5
ENHFILT6
ENHFILT7
0x0500
0x0500
0x0500
0x0500
0x0500
0x0500
RW
RW
RW
RW
RW
RW
ODR2
ODR3
ODR4
ODR5
ODR6
ODR7
[15:8]
[7:0]
SINC3_MAP3
RESERVED
[15:8]
[7:0]
SINC3_MAP4
RESERVED
[15:8]
[7:0]
SINC3_MAP5
RESERVED
[15:8]
[7:0]
SINC3_MAP6
RESERVED
[15:8]
[7:0]
SINC3_MAP7
RESERVED
OFFSET REGISTER 0
Address: 0x30, Reset: 0x800000, Name: OFFSET0
The offset (zero-scale) registers are 24-bit registers that compensate for any offset error in the ADC or in the system.
Table 40. Bit Descriptions for OFFSET0
Bits
Bit Name
Settings
Description
Reset
Access
[23:0]
OFFSET0
Offset calibration coefficient for Setup 0.
0x800000 RW
OFFSET REGISTER 1 TO OFFSET REGISTER 7
Address: 0x31 to 0x33, Reset: 0x800000, Name: OFFSET1 to OFFSET7
The remaining seven offset registers share the same layout as Offset Register 0.
Table 41. OFFSET1 to OFFSET7 Register Map
Reg. Name
Bits
Reset
RW
0x31 OFFSET1 [23:0]
0x32 OFFSET2 [23:0]
0x33 OFFSET3 [23:0]
0x34 OFFSET4 [23:0]
0x35 OFFSET5 [23:0]
0x36 OFFSET6 [23:0]
0x37 OFFSET7 [23:0]
OFFSET1[23:0]
OFFSET2[23:0]
OFFSET3[23:0]
OFFSET4[23:0]
OFFSET5[23:0]
OFFSET6[23:0]
OFFSET7[23:0]
0x800000 RW
0x800000 RW
0x800000 RW
0x800000 RW
0x800000 RW
0x800000 RW
0x800000 RW
Rev. B | Page 59 of 61
AD7172-4
Data Sheet
GAIN REGISTER 0
Address: 0x38, Reset: 0x5XXXX0, Name: GAIN0
The gain (full-scale) registers are 24-bit registers that compensate for any gain error in the ADC or in the system.
Table 42. Bit Descriptions for GAIN0
Bits
Bit Name
Settings
Description
Reset
Access
[23:0]
GAIN0
Gain calibration coefficient for Setup 0.
0x5XXXX0 RW
GAIN REGISTER 1 TO GAIN REGISTER 7
Address: 0x39 to 0x3F, Reset: 0x5XXXX0, Name: GAIN1 to GAIN7
The remaining seven gain registers share the same layout as Gain Register 0.
Table 43. GAIN1 to GAIN7 Register Map
Reg. Name
0x39 GAIN1
0x3A GAIN2
0x3B GAIN3
0x3C GAIN4
0x3D GAIN5
0x3E GAIN6
0x3F GAIN7
Bits
Reset
RW
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
GAIN1[23:0]
GAIN2[23:0]
GAIN3[23:0]
GAIN4[23:0]
GAIN5[23:0]
GAIN6[23:0]
GAIN7[23:0]
0x5XXXX0 RW
0x5XXXX0 RW
0x5XXXX0 RW
0x5XXXX0 RW
0x5XXXX0 RW
0x5XXXX0 RW
0x5XXXX0 RW
Rev. B | Page 60 of 61
Data Sheet
AD7172-4
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
IONS
INDIC ATOR AREA OPT
(SEE DETAIL A)
25
32
24
1
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.
Figure 72. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
AD7172-4BCPZ
AD7172-4BCPZ-RL
AD7172-4BCPZ-RL7
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
CP-32-12
CP-32-12
CP-32-12
1 Z = RoHS Compliant Part.
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12676-0-4/17(B)
Rev. B | Page 61 of 61
相关型号:
AD7175-2BRUZ
24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers
ADI
AD7175-2BRUZ-RL
24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers
ADI
AD7175-2BRUZ-RL7
24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers
ADI
AD7175-8BCPZ-RL7
24-Bit, 8-/16-Channel, 250 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers
ADI
AD7176-2
The AD7176-2 is a fast settling, highly accurate, high resolution, multiplexed Σ-Πanalog-to-digital converter (ADC) for low band-width input signals.
ADI
©2020 ICPDF网 联系我们和版权申明