AD7366-5 [ADI]
True Bipolar Input, Dual 1 レs, 12-/14-Bit, 2-Channel SAR ADCs; 真双极性输入，双1レS， 12 / 14位，双通道SAR型ADC
| 型号： | AD7366-5 |
| 厂家： | 
ADI |
| 描述： | True Bipolar Input, Dual 1 レs, 12-/14-Bit, 2-Channel SAR ADCs |
| 文件： | 总28页 (文件大小：634K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
True Bipolar Input, Dual 1 μs,
12-/14-Bit, 2-Channel SAR ADCs
AD7366/AD7367
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
D
A
AV
DV
CC
DD
CAP
CC
Dual 12-bit/14-bit, 2-channel ADC
True bipolar analog inputs
Programmable input ranges:
10 V, 5 V, 0 V to 10 V
BUF
REF
AD7366/AD7367
12 V with 3 V external reference
Throughput rate: 1 MSPS
Simultaneous conversion with read in less than 1μs
High analog input impedance
Low current consumption:
V
V
A1
12-/14-BIT
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
MUX
T/H
D
A
OUT
A2
SCLK
CNVST
8.3 mA typical in normal mode
320nA typical in shutdown mode
AD7366
72 dB SNR at 50 kHz input frequency
12-bit no missing codes
CS
BUSY
ADDR
RANGE0
RANGE1
REFSEL
CONTROL
LOGIC
V
V
B1
V
DRIVE
AD7367
76 dB SNR at 50 kHz input frequency
14-bit no missing codes
Accurate on-chip reference: 2.5 V 0.2%
–40°C to +85°C operation
MUX
T/H
12-/14-BIT
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
D
B
OUT
B2
BUF
High speed serial interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
iCMOS® process technology
Available in a 24-lead TSSOP
AGND AGND
V
D
B
DGND
SS
CAP
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7366/AD73671 are dual, 12/14-bit, high speed, low
power, successive approximation analog-to-digital converters
(ADCs) that feature throughput rates up to 1 MSPS. The device
contains two ADCs, each preceded by a 2-channel multiplexer,
and a low noise, wide bandwidth track-and-hold amplifier.
1. The AD7366/AD7367 can accept true bipolar analog input
signals, as well as ±1ꢀ ꢁ, ±± ꢁ, ±12 ꢁ (with external refer-
ence), and ꢀ ꢁ to +1ꢀ ꢁ unipolar signals.
2. Two complete ADC functions allow simultaneous
sampling and conversion of two channels.
The AD7366/AD7367 are fabricated on the Analog Devices,
Inc. industrial CMOS process (iCMOS®2), which is a technology
platform combining the advantages of low and high voltage
CMOS. The process allows the AD7366/AD7367 to accept high
voltage bipolar signals in addition to reducing power consump-
tion and package size. The AD7366/AD7367 can accept true
bipolar analog input signals in the ±1ꢀ ꢁ range, ±± ꢁ range,
and ꢀ ꢁ to 1ꢀ ꢁ range.
3. 1 MSPS serial interface; SPI-/QSPI-/DSP-/MICROWIRE-
compatible interface.
Table 1. Related Products
Throughput
Rate
Number of
Channels
Device
Resolution
12-Bit
AD7366
AD7366-5
AD7367
AD7367-5
1 MSPS
Dual, 2-channel
Dual, 2-channel
Dual, 2-channel
Dual, 2-channel
12-Bit
500 kSPS
1 MSPS
14-Bit
The AD7366/AD7367 have an on-chip 2.± ꢁ reference that
can be disabled to allow the use of an external reference. If a
3 ꢁ reference is applied to the DCAPA andDCAPB pins, the
AD7366/AD7367 can accept a true bipolar ±12 ꢁ analog input.
Minimum ±12 ꢁ ꢁDD and ꢁSS supplies are required for the
±12 ꢁ input range.
14-Bit
500 kSPS
1 Protected by U.S. Patent No. 6,731,232.
2 iCMOS Process Technology. For analog systems designers within
industrial/instrumentation equipment OEMs who need high performance
ICs at higher voltage levels, iCMOS is a technology platform that enables the
development of analog ICs capable of 30 V and operating at 15 V supplies
while allowing dramatic reductions in power consumption and package size,
and increased ac and dc performance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD7366/AD7367
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Connection Diagram ................................................... 18
Driver Amplifier Choice ........................................................... 19
Reference ..................................................................................... 19
Modes of Operation ....................................................................... 2ꢀ
Normal Mode.............................................................................. 2ꢀ
Shutdown Mode ......................................................................... 21
Power-Up Times......................................................................... 21
Serial Interface ................................................................................ 22
Microprocessor Interfacing........................................................... 24
AD7366/AD7367 to ADSP-218x.............................................. 24
AD7366/AD7367 to ADSP-BF±3x........................................... 24
AD7366/AD7367 to TMS32ꢀꢁC±±ꢀ6..................................... 2±
AD7366/AD7367 to DSP±63xx................................................ 2±
Application Hints ........................................................................... 27
Layout and Grounding .............................................................. 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 16
Circuit Information.................................................................... 16
Converter Operation.................................................................. 16
Analog Inputs.............................................................................. 16
Transfer Function....................................................................... 17
REVISION HISTORY
5/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7366/AD7367
SPECIFICATIONS
TA = −4ꢀ°C to +8±°C, AꢁCC = DꢁCC = 4.7± ꢁ to ±.2± ꢁ, ꢁDD = 11.± ꢁ to 16.± ꢁ, ꢁSS = −16.± ꢁ to −11.± ꢁ, ꢁDRIꢁE = 2.7 ꢁ to ±.2± ꢁ,
SAMPLE = 1.12 MSPS, fSCLK = 48 MHz, ꢁREF = 2.± ꢁ internal/external, TA = TMIN to TMAX, unless otherwise noted.
f
Table 2. AD7366
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)1
Signal-to-Noise + Distortion Ratio (SINAD)1
Total Harmonic Distortion (THD)1
Spurious-Free Dynamic Range (SFDR)1
Intermodulation Distortion (IMD)1
Second-Order Terms
fIN = 50 kHz sine wave
70
70
72
dB
dB
dB
dB
71
−85
−87
−78
−78
fa = 49 kHz, fb = 51 kHz
−88
−88
−90
dB
dB
dB
Third-Order Terms
Channel-to-Channel Isolation1
SAMPLE AND HOLD
Aperture Delay2
10
ns
Aperture Jitter2
40
ps
Aperture Delay Matching2
100
ps
Full Power Bandwidth
35
8
MHz
MHz
@ 3 dB, 10 V range
@ 0.1 dB, 10 V range
DC ACCURACY
Resolution
12
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Positive Full-Scale Error1
0.5
1
0.25
1
0.5
7
Guaranteed no missed codes to 12 bits
5 V and 10 V analog input range
1
6
0 V to 10 V analog input range
Positive Full-Scale Error Match1
Zero Code Error1
1.5
0.1
0.5
1
Matching from ADC A to ADC B
Channel to channel matching for ADC A and ADC B
5 V and 10 V analog input range
3
6
0 V to 10 V analog input range
Zero Code Error Match1
Negative Full-Scale Error1
Negative Full-Scale Error Match1
1.5
0.1
1
Matching from ADC A to ADC B
Channel-to-channel matching for ADC A and ADC B
5 V and 10 V analog input range
7
6
1
0 V to 10 V analog input range
1.5
0.1
Matching from ADC A to ADC B
Channel-to-channel matching for ADC A and ADC B
ANALOG INPUT
Input Voltage Ranges
(Programmed via RANGE Pins)
10
V
5
V
0 to 10
1
V
DC Leakage Current
Input Capacitance
0.01
μA
pF
pF
kΩ
MΩ
kΩ
MΩ
9
When in track, 10 V range
When in track, 5 V or 0 V to 10 V range
For 10 V @1 MSPS
13
Input Impedance
260
2.5
125
1.2
For 10 V @100 kSPS
For 5 V/ 0 V to 10 V @1 MSPS
For 5 V/ 0 V to 10 V @100 kSPS
Rev. 0 | Page 3 of 28
AD7366/AD7367
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE INPUT/OUTPUT
Reference Output Voltage3
Long-Term Stability
2.495
2.5
150
50
2.505
V
0.2% max @ 25°C
For 1000 hours
ppm
ppm
V
Output Voltage Hysteresis1
Reference Input Voltage Range
DC Leakage Current
2.5
3.0
1
0.01
μA
External reference applied to Pin DCAPA/Pin DCAP
5 V and 10 V analog input range
B
Input Capacitance
25
17
7
pF
pF
0 V to 10 V analog input range
DCAPA, DCAPB Output Impedance
Reference Temperature Coefficient
VREF Noise
Ω
6
25
ppm/°C
μV rms
20
Bandwidth = 3 kHz
VIN = 0 V or VDRIVE
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 × VDRIVE
V
0.01
+0.8
1
V
μA
pF
2
Input Capacitance, CIN
6
8
1
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance2
CONVERSION RATE
VDRIVE − 0.2
V
0.4
1
V
0.01
μA
pF
Conversion Time
Track/Hold Acquisition Time2
610
140
1.12
ns
ns
Full-scale step input
Throughput Rate
MSPS
MSPS
For 4.75 V ≤ VDRIVE ≤ 5.25 V, fSCLK = 48 MHz
For 2.7 V ≤ VDRIVE < 4.75 V, fSCLK = 35 MHz
Digital Inputs = 0 V or VDRIVE
See Table 7
See Table 7
See Table 7
POWER REQUIREMENTS
VCC
4.75
+11.5
−16.5
2.7
5.25
V
V
V
V
VDD
+16.5
−11.5
5.25
VSS
VDRIVE
Normal Mode (Static)
IDD
370
40
550
60
μA
μA
mA
VDD = +16.5 V
ISS
VSS = −16.5 V
ICC
1.5
1.8
VCC = 5.5 V
Normal Mode (Operational)
fS = 1.12 MSPS
IDD
1.8
1.5
5
2.0
1.6
5.6
mA
mA
mA
VDD = +16.5 V
ISS
VSS = −16.5 V
ICC
VCC = 5.25 V, internal reference enabled
Shutdown Mode
IDD
0.01
0.01
0.3
1
1
2
μA
μA
μA
VDD = +16.5 V
VSS = −16.5 V
VCC = 5.25 V
ISS
ICC
Power Dissipation
Normal Mode (Operational)
88.8
mW
VDD = +16.5 V, VSS = −16.5 V, VCC = 5.25 V,
fS = 1.12 MSPS
50
70
1.9
mW
mW
μW
10 V input range, fS = 1.12 MSPS,
5 V and 0 V to 10 V input range, fS = 1.12 MSPS
VDD = +16.5 V, VSS = −16.5 V, VCC = 5.25 V
Shutdown Mode
43.5
1 See the Terminology section.
2 Sample tested during initial release to ensure compliance.
3 Refers to Pin DCAPA or Pin DCAPB specified for 25oC.
Rev. 0 | Page 4 of 28
AD7366/AD7367
TA = −4ꢀ°C to +8±°C, AꢁCC = DꢁCC = 4.7± ꢁ to ±.2± ꢁ, ꢁDD = 11.± ꢁ to 16.± ꢁ, ꢁSS = −16.± ꢁ to −11.± ꢁ, ꢁDRIꢁE = 2.7 ꢁ to ±.2± ꢁ,
SAMPLE = 1 MSPS, fSCLK = 48 MHz, ꢁREF = 2.± ꢁ internal/external, TA = TMIN to TMAX, unless otherwise noted.
f
Table 3. AD7367
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)1
Signal-to-Noise + Distortion Ratio (SINAD)1
Total Harmonic Distortion (THD)1
Spurious-Free Dynamic Range (SFDR)1
Intermodulation Distortion (IMD)1
Second-Order Terms
fIN = 50 kHz sine wave
fa = 49 kHz, fb = 51 kHz
74
73
76
75
−84
−87
dB
dB
dB
dB
−78
−79
−91
−89
−90
dB
dB
dB
Third-Order Terms
Channel-to-Channel Isolation1
SAMPLE AND HOLD
Aperture Delay2
10
ns
ps
ps
Aperture Jitter2
40
100
Aperture Delay Matching2
Full Power Bandwidth
35
8
MHz
MHz
@ 3 dB, 10 V range
@ 0.1 dB, 10 V range
DC ACCURACY
Resolution
14
Bits
LSB
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Positive Full-Scale Error1
2
0.5
4
5
3
0.2
3.5
0.90
20
20
Guaranteed no missed codes to 14 bits
5 V and 10 V analog input range
0 V to 10 V analog input range
Positive Full-Scale Error Match1
Matching from ADC A to ADC B
Channel to channel matching for ADC A and
ADC B
5 V and 10 V analog input range
0 V to 10 V analog input range
Matching from ADC A to ADC B
Channel to channel matching for ADC A and
ADC B
5 V and 10 V analog input range
0 V to 10 V analog input range
Matching from ADC A to ADC B
Zero Code Error1
1
5
3
0.2
10
20
LSB
LSB
LSB
LSB
Zero Code Error Match1
Negative Full-Scale Error1
4
5
3
0.2
20
20
LSB
LSB
LSB
LSB
Negative Full-Scale Error Match1
Channel-to-channel matching for ADC A and
ADC B
ANALOG INPUT
Input Voltage Ranges
(Programmed via RANGE Pins)
10
5
V
V
0 to 10
1
V
See Table 7
DC Leakage Current
Input Capacitance
0.01
μA
pF
pF
kΩ
MΩ
kΩ
MΩ
9
When in track, 10 V range
When in track, 5 V or 0 V to 10 V range
For 10 V @ 1 MSPS
For 10 V @ 100 kSPS
For 5 V/0 V to 10 V @ 1 MSPS
For 5 V/0 V to 10 V @ 100 kSPS
13
Input Impedance
260
2.5
125
1.2
Rev. 0 | Page 5 of 28
AD7366/AD7367
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE INPUT/OUTPUT
Reference Output Voltage3
Long-Terꢁ Stability
Output Voltage Hysteresis1
Reference Input Voltage Range
DC Leakage Current
2.495
2.5
150
50
2.505
V
0.2ꢀ ꢁaꢂ ꢃ 25ꢄC
For 1000 hours
ppꢁ
ppꢁ
V
μA
pF
pF
Ω
ppꢁ/ꢄC
μV rꢁs
2.5
3.0
1
0.01
Eꢂternal reference applied to DCAPA/Pin DCAP
5 V and 10 V analog input range
0 V to 10 V analog input range
B
Input Capacitance
25
17
7
6
20
DCAPA, DCAPB Output Iꢁpedance
Reference Teꢁperature Coefficient
VREF Noise
25
Bandwidth = 3 kHz
VIN = 0 V or VDRIVE
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 × VDRIVE
V
V
μA
pF
0.8
1
0.01
2
Input Capacitance, CIN
6
8
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance2
CONVERSION RATE
VDRIVE − 0.2
V
V
μA
pF
0.4
1
0.01
Conversion Tiꢁe
680
140
1
ns
ns
MSPS
kSPS
Track/Hold Acquisition Tiꢁe2
Full-scale step input;
Throughput Rate
For 4.75 V ≤ VDRIVE ≤ 5.25 V, fSCLK = 48 MHz
For 2.7 V ≤ VDRIVE < 4.75 V, fSCLK = 35 MHz
Digital Inputs = 0 V or VDRIVE
See Table 7
See Table 7
See Table 7
900
POWER REQUIREMENTS
VCC
VDD
VSS
4.75
+11.5
−16.5
2.7
5.25
V
V
V
V
+16.5
−11.5
5.25
VDRIVE
Norꢁal Mode (Static)
IDD
ISS
ICC
370
40
1.5
550
60
1.8
μA
μA
ꢁA
VDD = +16.5 V
VSS = −16.5 V
VCC = 5.5 V
Norꢁal Mode (Operational)
fS = 1 MSPS
IDD
ISS
ICC
1.8
1.5
5
2.0
1.6
5.6
ꢁA
ꢁA
ꢁA
VDD = +16.5 V
VSS = −16.5 V
VCC = 5.25 V, internal reference enabled
Shutdown Mode
IDD
ISS
ICC
0.01
0.01
0.3
1
1
2
μA
μA
μA
VDD = +16.5 V
VSS = −16.5 V
VCC = 5.25 V
Power Dissipation
Norꢁal Mode (Operational)
80.7
50
70
88.8
43.5
ꢁW
ꢁW
ꢁW
μW
VDD = +16.5 V, VSS = −16.5 V, VCC = 5.25 V
10 V input range, fS = 1 MSPS
5 V and 0 V to 10 V input range, fS = 1 MSPS
VDD = +16.5 V, VSS = −16.5 V, VCC = 5.25 V
Shutdown Mode
1.9
1 See the Terꢁinology section.
2 Saꢁple tested during initial release to ensure coꢁpliance.
3 Refers to Pin DCAPA or Pin DCAPB.
Rev. 0 | Page 6 of 28
AD7366/AD7367
TIMING SPECIFICATIONS
AꢁCC = DꢁCC = 4.7± ꢁ to ±.2± ꢁ, ꢁDD = 11.± ꢁ to 16.± ꢁ, ꢁSS = −16.± ꢁ to −11.± ꢁ, ꢁDRIꢁE = 2.7 ꢁ to ±.2± ꢁ, TA = TMIN to TMAX, unless
otherwise noted.1
Table 4.
Limit at TMIN, TMAX
Parameter
Unit
Test Conditions/Comments
2.7 V ≤ VDRIVE < 4.75 V 4.75 V ≤ VDRIVE ≤ 5.25 V
tCONVERT
Conversion time, internal clock. CONVST falling edge to
BUSY falling edge
680
610
10
35
30
680
610
10
48
30
ns max
ns max
kHz min
MHz max
ns min
For the AD7367
For the AD7366
Frequency of serial read clock
fSCLK
tQUIET
Minimum quiet time required between the end of serial
read and the start of the next conversion
t1
t2
t3
10
40
0
10
40
0
ns min
ns min
ns min
Minimum CONVST low pulse
CONVST falling edge to BUSY rising edge
BUSY falling edge to MSB valid once CS is low for t4 prior to
BUSY going low
t4
10
10
ns max
Delay from CS falling edge until Pin 1 (DOUTA) and Pin 23
(DOUTB) are three-state disabled
Data access time after SCLK falling edge
SCLK to data valid hold time
SCLK low pulse width
SCLK high pulse width
2
t5
t6
t7
t8
20
7
0.3 × tSCLK
0.3 × tSCLK
10
14
7
0.3 × tSCLK
0.3 × tSCLK
10
ns max
ns min
ns min
ns min
ns max
ꢀs
t9
CS rising edge to DOUTA, DOUTB, high impedance
tPOWER-UP
70
70
Power up time from shutdown mode; time required
between CONVST rising edge and CONVST falling edge
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the
Terminology section and Figure 25.
2 The time required for the output to cross is 0.4 V or 2.4 V.
Rev. 0 | Page 7 of 28
AD7366/AD7367
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
VDD to AGND, DGND
VSS to AGND, DGND
VDRIVE to DGND
VDD to AVCC
AVCC to AGND, DGND
DVCC to AVCC
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V to +16.5 V
−16.5 V to +0.3 V
−0.3 V to DVCC
(VCC − 0.3 V) to +16.5 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +7 V
ESD CAUTION
DVCC to DGND
VDRIVE to AGND
−0.3 V to DVCC
AGND to DGND
−0.3 V to +0.3 V
VSS − 0.3 V to VDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to A VCC + 0.3 V
10 mA
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to GND
DCAPB, DCAPB Input to AGND
Input Current to Any Pin Except
Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
TSSOP Package
−40°C to +85°C
−65°C to +150°C
150°C
θJA Thermal Impedance
θJC Thermal Impedance
Pb-free Temperature, Soldering
Reflow
128°C/W
42°C/W
260(+0)°C
1.5 kV
ESD
1 Transient currents of up to 100 mA will not cause latch-up.
Rev. 0 | Page 8 of 28
AD7366/AD7367
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D
V
A
1
2
24 DGND
OUT
23
22
D
B
DRIVE
OUT
BUSY
DV
CC
3
AD7366/
AD7367
4
21 CNVST
20 SCLK
19 CS
RANGE1
RANGE0
ADDR
5
TOP VIEW
6
(Not to Scale)
AGND
7
18 REFSEL
17 AGND
AV
CC
8
D
A
D
B
CAP
16
15
14
13
9
CAP
V
10
11
12
V
SS
DD
V
V
V
A1
A2
B1
B2
V
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 23
DOUTA, DOUT
B
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input and 12 SCLK cycles are required to access the data from the AD7366 while 14
SCLK cycle are required for the AD7367. The data simultaneously appears on both pins from the simultaneous
conversions of both ADCs. The data stream consists of the 12 bits of conversion data for the AD7366 and 14 bits
for the AD7367 and is provided MSB first. If CS is held low for a further 12 SCLK cycles for the AD7366 or 14 SCLK
cycles for the AD7367, on either DOUTA or DOUTB, the data from the other ADC follows on that DOUT pin. This
allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or
D
OUTB using only one serial port. See the Serial Interface section for more information.
2
3
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different to
the voltage at AVCC and DVCC, but should never exceed either by more than 0.3 V. To achieve a throughput rate
of 1.12 MSPS for the AD7366 or 1 MSPS for the AD7367, VDRIVE must be greater than or equal to 4.75 V.
Digital Supply Voltage, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential.
For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the
voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled
to DGND. Place 10 μF and 100 nF decoupling capacitors on the DVCC pin.
DVCC
4, 5
6
RANGE1,
RANGE0
ADDR
Analog Input Range Selection, Logic Inputs. The polarity on these pins determines the input range of the analog
input channels. See the Analog Inputs section and Table 8 for details.
Multiplexer Select, Logic Input. This input is used to select the pair of channels to be simultaneously converted,
either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADCB. The logic state on this pin is
latched on the rising edge of BUSY to set up the multiplexer for the next conversion.
7, 17
8
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7366/AD7367. All analog input signals
and any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and DVCC voltages
should ideally be at the same potential. For best performance, it is recommended that the DVCC and AVCC pins be
shorted together, to ensure that the voltage difference between them never exceeds 0.3 V even on a transient
basis. This supply should be decoupled to AGND. Place 10 μF and 100 nF decoupling capacitors on the AVCC pin.
AVCC
9, 16
10
DCAPA, DCAP
B
Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference buffer
for each respective ADC. For best performance, it is recommended to use a 680 nF decoupling capacitor on
these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and applied
externally to the rest of a system.
Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure
of the AD7366/AD7367. The supply must be less than a maximum voltage of −11.5 V for all input ranges. See
Table 7 for further details. Place 10 μF and 100 nF decoupling capacitors on the VSS pin.
VSS
11, 12
13, 14
15
VA1, VA2
VB2, VB1
VDD
Analog Inputs of ADC A. These are both single-ended analog inputs. The analog input range on these channels
is determined by the RANGE0 and RANGE1 pins.
Analog Inputs of ADC B. These are both single-ended analog inputs. The analog input range on these channels
is determined by the RANGE0 and RANGE1 pins.
Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure
AD7366/AD7367. The supply must be greater than a minimum voltage of 11.5 V for all the analog input ranges.
See Table 7 for further details. Place 10 μF and 100 nF decoupling capacitors on the VDD pin.
Rev. 0 | Page 9 of 28
AD7366/AD7367
Pin No.
Mnemonic
Description
18
REFSEL
Internal/External Reference Selection, Logic Input. If this pin is tied to logic high, the on-chip 2.5 V reference is
used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to
decoupling capacitors. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7366/
AD7367 through the DCAPA and/or DCAPB pins.
CS
19
Chip Select, Active Low Logic Input. This input frames the serial data transfer. When CS is logic low, the output
bus is enabled and the conversion result is output on DOUTA and DOUTB.
20
21
SCLK
CNVST
Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7366/AD7367.
Conversion Start; Logic Input. This pin is edge triggered. On the falling edge of this input, the track/hold goes
into hold mode and the conversion is initiated. If CNVST is low at the end of a conversion, the part goes into
power-down mode. In this case, the rising edge of CNVST instructs the part to power up again.
22
24
BUSY
Busy Output. BUSY transitions high when a conversion is started and remains high until the conversion
is complete.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7366/AD7367. The DGND pin
should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
DGND
Rev. 0 | Page 10 of 28
AD7366/AD7367
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 2±°C, unless otherwise noted.
1.0
0.8
0.6
0.4
0.2
0
–76
–78
0V TO 10V RANGE
±10V RANGE
±5V RANGE
–80
–82
–0.2
–0.4
AV
V
= 5V, DV = 5V
CC
CC
DD
AV
V
= 5V, DV = 5V
CC
= 15V, V = –15V
SS
CC
–0.6
–0.8
–1.0
–84
–86
= 15V, V = –15V
SS
V
= 3V
DD
fSDR=IV1EMSPS
V
= 3V
fSDR=IV1EMSPS
T
= 25°C
A
INTERNAL REFERENCE
INTERNAL REFERENCE
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
10
100
1000
ANALOG INPUT FREQUENCY (kHz)
Figure 3. AD7367 Typical DNL
Figure 6. THD vs. Analog Input Frequency
2.0
1.5
AV
DD
= 5V, DV = 5V
–66
–71
–76
–81
–86
CC
CC
V
V
= 15V, V = –15V
SS
= 3V
fSD=RIV1EMSPS
INTERNAL REFERENCE
±5V RANGE
R
= 2000Ω
IN
1.0
0.5
R
= 1300Ω
IN
R
= 3000Ω
IN
0
R
= 470Ω
IN
R
= 5100Ω
IN
–0.5
–1.0
–1.5
–2.0
AV
DD
= 5V, DV = 5V
CC
CC
V
= 15V, V = –15V
SS
V
= 3V
R
= 240Ω
fSDR=IV1EMSPS
IN
R
= 56Ω
IN
T
= 25°C
A
R
= 3900Ω
INTERNAL REFERENCE
IN
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
10
100
1000
ANALOG INPUT FREQUENCY (kHz)
Figure 4. AD7367 Typical INL
Figure 7. THD vs. Analog Input Frequency for Various Source Impedances
0
–20
–40
–60
–80
AV
DD
= 5V, DV = 5V
CC
CC
77
V
= 15V, V = –15V
SS
V
= 3V
DRIVE
fS = 1MSPS,
INTERNAL REFERENCE
SNR = 76dB, SINAD = 73dB
f
= 50kHz
IN
±10V RANGE
75
0V TO 10V RANGE
73
71
69
67
–100
–120
–140
–160
AV
DD
= 5V, DV = 5V
CC
CC
V
V
= 15V, V = –15V
SS
= 3V
fSD=RIV1EMSPS
±5V RANGE
INTERNAL REFERENCE
10
100
1000
0
5000 10000 15000 20000 25000 30000 35000 40000 45000 50000
FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
Figure 5. AD7367 FFT
Figure 8. SINAD vs. Analog Input Frequency
Rev. 0 | Page 11 of 28
AD7366/AD7367
–70
–75
–80
–70
–80
V
, ADC A
CC
100mV p-p SINE WAVE ON AV
CC
NO DECOUPLING CAPACITOR
V
= 15V, V = –15V
DD
SS
V
, ADC B
CC
V
= 3V
fSDR=IV1EMSPS
±5V RANGE
–85
–90
–90
V
ADC B
DD,
0V TO 10V RANGE
±10V RANGE
–100
–110
–120
–95
V , ADC B
SS
V
, ADC A
DD
–100
–105
–110
AV
DD
= 5V, DV = 5V
CC
CC
V
= 15V, V = –15V
SS
V
= 3V
fSDR=IV1EMSPS
V
, ADC A
800
SS
INTERNAL REFERENCE
0
100
200
300
400
500
600
0
200
400
600
1000
1200
FREQUENCY OF INPUT NOISE (kHz)
SUPPLY RIPPLE FREQUENCY (kHz)
Figure 9. Channel-to-Channel Isolation
Figure 11. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
110000
100000
90000
80000
70000
60000
50000
40000
30000
20000
10000
0
80
106091 CODES
AV
V
= 5V, DV = 5V
CC
CC
DD
31 CODES
344 CODES
= 15V, V = –15V
SS
V
= 0V TO 10V
IN
V
= 3V
fSD=RIV1EMSPS
INTERNAL REFERENCE
60
40
V
= +5V
IN
V
= +10V
IN
20
0
–20
V
= –10V
IN
V
= –5V
800
IN
700
THROUGHPUT RATE (kSPS)
–40
100
8191
8192
8193
CODE
8194
8195
8196
200
300
400
500
600
900 1000
Figure 10. Histogram of Codes for 200k Samples
Figure 12. Analog Input Current vs. Throughput Rate
Rev. 0 | Page 12 of 28
AD7366/AD7367
2.5050
2.5045
2.5040
2.5035
2.5030
2.5025
2.5020
2.5015
2.5010
2.5005
2.5000
AV
V
= 5V, DV = 5V
CC
0V TO 10V RANGE
CC
DD
= 15V, V = –15V
65
55
45
SS
V
= 3V
fSD=RIV1EMSPS
INTERNAL REFERENCE
±5V RANGE
±10V RANGE
35
25
AV
V
DRIVE
= 5V, DV = 5V
CC
CC
DD
= 15V, V = –15V
SS
V
= 3V,
15
0
10
20
30
40
50
60
70
80
90
100
200
300
400
500
600
700
800
900 1000
CURRENT LOAD (µA)
SAMPLING FREQUENCY (kSPS)
Figure 13. VREF vs. Reference Output Current Drive
Figure 15. Power vs. Sampling Frequency in Normal Mode
0.300
0.250
0.200
0.150
0.100
0.50
0
SOURCE CURRENT
SINK CURRENT
AV
DD
= 5V, DV = 5V
CC
CC
V
= 15V, V = 15V
SS
V
= 3V, fS = 1MSPS
DRIVE
INTERNAL REFERENCE
0
500
1000
1500
2000
2500
CURRENT (µA)
Figure 14. DOUT Source Current vs. (VCC − VOUT ) and
DOUT Sink Current vs. VOUT
Rev. 0 | Page 13 of 28
AD7366/AD7367
TERMINOLOGY
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7366/AD7367, it is defined as:
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
2
2
2
2
2
Integral Nonlinearity (INL)
V2 +V3 +V4 +V5 +V6
THD(dB) = 20log
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a single (1)
LSB point below the first code transition and full scale, a point
1 LSB above the last code transition.
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Zero Code Error
Peak Harmonic or Spurious Noise
It is the deviation of the midscale transition (all 1s to all ꢀs)
from the ideal ꢁIN voltage, that is, AGND – ½ LSB for bipolar
ranges and 2 × ꢁREF − 1 LSB for the unipolar range.
Peak harmonic, or spurious noise, is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum. However, for
ADCs where the harmonics are buried in the noise floor, it is
a noise peak.
Positive Full-Scale Error
It is the deviation of the last code transition (ꢀ11…11ꢀ) to
(ꢀ11…111) from the ideal (that is, +4 × ꢁREF − 1 LSB or +2 ×
ꢁREF – 1 LSB) after the zero code error has been adjusted out.
Negative Full-Scale Error
Channel-to-Channel Isolation
This is the deviation of the first code transition (1ꢀ…ꢀꢀꢀ) to
(1ꢀ…ꢀꢀ1) from the ideal (that is, −4 × ꢁREF + 1 LSB, −2 × ꢁREF
+ 1 LSB, or AGND + 1 LSB) after the zero code error has been
adjusted out.
Channel-to-channel isolation is a measure of the level of cross-
talk between any two channels when operating in any of the
input ranges. It is measured by applying a full-scale, 1±ꢀ kHz
sine wave signal to all unselected input channels and determin-
ing how much that signal is attenuated in the selected channel
with a ±ꢀ kHz signal. The figure given is the typical across all
four channels for the AD7366/AD7367 (see the Typical
Performance Characteristics section for more information).
Zero Code Error Match
This is the difference in zero code error across all 12 channels.
Positive Full-Scale Error Match
The difference in positive full-scale error across all channels.
Intermodulation Distortion
Negative Full-Scale Error Match
The difference in negative full-scale error across all channels.
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion prod-
ucts at the sum, and different frequencies of mfa ± nfb where m,
n = ꢀ, 1, 2, 3, and so on. Intermodulation distortion terms are
those for which neither m nor n is equal to zero. For example, the
second-order terms include (fa + fb) and (fa − fb), while the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and
(fa − 2fb).
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of a conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±½ LSB, after the end of conversion.
Signal-to-Noise (+ Distortion) Ratio (SINAD)
This ratio is the measured ratio of signal-to-noise (+ distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitiza-
tion process: the more levels, the smaller the quantization noise.
The theoretical signal-to-noise (+ distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
The AD7366/AD7367 is tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second-order terms are usually dis-
tanced in frequency from the original sine waves, while the
third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in decibels.
Signal-to-Noise (+ Distortion) = (6.ꢀ2N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Rev. 0 | Page 14 of 28
AD7366/AD7367
Power Supply Rejection Ration (PSRR)
It is expressed in ppm using the following equation:
REF (2±°C) −VREF (T _ HYS)
ꢁariations in power supply affect the full-scale transition but
not the converter’s linearity. PSRR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value (see Figure 11).
V
V
HYS (ppm) =
× 1ꢀ6
V
REF (2±°C)
where:
V
V
REF(2±°C) is ꢁREF at 2±°C.
REF(T_HYS) is the maximum change of ꢁREF at T_HYS+ or
Thermal Hysteresis
Thermal hysteresis is defined as the absolute maximum change
of reference output voltage after the device is cycled through
temperature from either
T_HYS−.
T_HYS+ = +2±°C to TMAX to +2±°C
or
T_HYS− = +2±°C to TMIN to +2±°C
Rev. 0 | Page 15 of 28
AD7366/AD7367
THEORY OF OPERATION
CIRCUIT INFORMATION
CONVERTER OPERATION
The AD7366/AD7367 have two successive approximation
ADCs, each based around two capacitive DACs. Figure 16 and
Figure 17 show simplified schematics of an ADC in acquisition
and conversion phases. The ADC is comprised of control logic,
a SAR, and a capacitive DAC. In Figure 16 (the acquisition phase),
SW2 is closed and SW1 is in Position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the signal on the input.
The AD7366/AD7367 are fast, dual, 2-channel, 12-/14-bit,
bipolar input, simultaneous sampling, serial ADCs. The
AD7366/AD7367 can accept bipolar input ranges of ±1ꢀ ꢁ
and ±± ꢁ. It can also accept a ꢀ ꢁ to 1ꢀ ꢁ unipolar input range.
The AD7366/AD7367 requires ꢁDD and ꢁSS dual supplies for
the high voltage analog input structure. These supplies must
be equal to or greater than 11.± ꢁ. See Table 7 for the minimum
requirements on these supplies for each analog input range. The
AD7366/AD7367 require a low voltage of 4.7± ꢁ to ±.2± ꢁ ꢁCC
supply to power the ADC core.
CAPACITIVE
DAC
A
Table 7. Reference and Supply Requirements for Each
Analog Input Range
V
IN
CONTROL
LOGIC
SW1
B
SW2
Selected
Analog Input Reference
Range (V)
Full-Scale
Input
Range (V)
COMPARATOR
Minimum
VDD/VSS (V)
Voltage (V)
AVCC (V)
AGND
10
2.5
3.0
2.5
3.0
2.5
3.0
10
12
5
5
5
5
5
5
11.5
12
Figure 16. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 17), SW2
opens and SW1 moves to Position B, causing the comparator
to become unbalanced. The control logic and the charge redis-
tribution DAC is used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is
balanced again, the conversion is complete. The control logic
generates the ADC output code.
5
5
11.5
11.5
11.5
12
6
0 to 10
0 to 10
0 to 12
The AD7366/AD7367 contain two on-chip, track-and-hold
amplifiers, two successive approximation ADCs, and a serial
interface with two separate data output pins. It is housed in a
24-lead TSSOP, offering the user considerable space-saving
advantages over alternative solutions. The AD7366/AD7367
require a
edge of
and the conversions are initiated. The BUSY signal goes high to
indicate that the conversions are taking place. The clock source
for each successive approximation ADC is provided by an internal
oscillator. The BUSY signal goes low to indicate the end of
conversion. On the falling edge of BUSY, the track-and-hold
returns to track mode. Once the conversion is finished, the
serial clock input accesses data from the part.
CAPACITIVE
DAC
CNꢁST
signal to start conversion. On the falling
CNꢁST
both track-and-holds are placed into hold mode
A
V
IN
CONTROL
LOGIC
SW1
B
SW2
COMPARATOR
AGND
Figure 17. ADC Conversion Phase
ANALOG INPUTS
Each ADC in the AD7366/AD7367 has two single-ended
analog inputs. Figure 18 shows the equivalent circuit of the
analog input structure of the AD7366/AD7367. The two diodes
provide ESD protection. Care must be taken to ensure that the
analog input signals never exceed the supply rails by more than
3ꢀꢀ mꢁ. This causes these diodes to become forward-biased
and starts conducting current into the substrate. These diodes
can conduct up to 1ꢀ mA without causing irreversible damage
to the part. The resistors are lumped components made up of
the on resistance of the switches. The value of these resistors is
typically about 17ꢀ Ω. Capacitor C1 can primarily be attributed
to pin capacitance while Capacitor C2 is the sampling capacitor
of the ADC. The total lumped capacitance of C1 and C2 is
approximately 9 pF for the ±1ꢀ ꢁ input range and approxi-
mately 13 pF for all other input ranges.
The AD7366/AD7367 have an on-chip 2.± ꢁ reference that
can be disabled when an external reference is preferred. If
the internal reference is to be used elsewhere in a system, then
the output from DCAPA and DCAPB must first be buffered. On
power-up, the REFSEL pin must be tied to either a high or low
logic state to select either the internal or external reference option.
If the internal reference is the preferred option, the user must
tie the REFSEL pin logic high. Alternatively, if REFSEL is tied to
GND then an external reference can be supplied to both ADCs
through DCAPA and DCAPB pins.
The analog inputs are configured as two single-ended inputs for
each ADC. The various different input voltage ranges can be
selected by programming the RANGE bits as shown in Table 8.
Rev. 0 | Page 16 of 28
AD7366/AD7367
V
Table 10. LSB Sizes for Each Analog Input Range
AD7366 AD7367
DD
D
C2
R1
Input
Full-Scale
LSB Size
(mV)
Full-Scale
LSB Size
(mV)
V
0
IN
Range
C1
Range
Range
D
10 V
5 V
0 V to 10 V
20 V/4096
10 V/4096
10 V/4096
4.88
2.44
2.44
20 V/16384
10 V/16384
10 V/16384
1.22
0.61
0.61
V
SS
Figure 18. Equivalent Analog Input Structure
The AD7366/AD7367 can handle true bipolar input voltages.
The analog input can be set to one of three ranges: ±1ꢀ ꢁ, ±± ꢁ,
or ꢀ ꢁ to 1ꢀ ꢁ. The logic levels on Pin RANGEꢀ and Pin RANGE1
determine which input range is selected as outlined in Table 8.
These range bits should not be changed during the acquisition
time prior to a conversion, but can change at any other time.
011...111
011...110
000...001
000...000
111...111
Table 8. Analog Input Range Selection
RANGE1
RANGE0
Range Selected
100...010
100...001
100...000
0
0
1
1
0
1
0
1
10 V
5 V
0 V to 10 V
Do not program
–FSR/2 + 1LSB
+FSR/2 – 1LSB
0V
ANALOG INPUT
Figure 19. Transfer Characteristic
The AD7366/AD7367 require ꢁDD and ꢁSS dual supplies for the
high voltage analog input structures. These supplies must be
equal to or greater than ±11.± ꢁ. See Table 7 for the require-
ments on these supplies. The AD7366/AD7367 require a low
voltage 4.7± ꢁ to ±.2± ꢁ AꢁCC supply to power the ADC core,
a 4.7± ꢁ to ±.2± ꢁ DꢁCC supply for digital power, and a 2.7 ꢁ
to ±.2± ꢁ ꢁDRIꢁE supply for interface power.
Track-and-Hold
The track-and-hold on the analog input of the AD7366/AD7367
allows the ADC to accurately convert an input sine wave of full-
scale amplitude to 12-/14-bit accuracy. The input bandwidth of
the track-and-hold is greater than the Nyquist rate of the ADC.
The AD7366/AD7367 can handle frequencies up to 3± MHz.
The track-and-hold enters its tracking mode once the BUSY
signal goes low after the
Channel selection is made via the ADDR pin as shown in
Table 9. The logic level on the ADDR pin is latched on the
rising edge of the BUSY signal for the next conversion, not
the one in progress. When power is first supplied to the
AD7366/AD7367 the default channel selection is ꢁA1 and ꢁB1.
CS
falling edge. The time required to
acquire an input signal depends on how quickly the sampling
capacitor is charged. With zero source impedance, 14ꢀ ns is suffi-
cient to acquire the signal to the 12-bit for the AD7366 and the
14-bit level for the AD7367. The acquisition time for the ±1ꢀ ꢁ,
±± ꢁ, and ꢀ ꢁ to +1ꢀ ꢁ ranges to settle to within ±½ LSB is
typically 14ꢀ ns. The ADC goes back into hold mode on the
Table 9. Channel Selection
ADDR
Channels Selected
CNꢁST
falling edge of
.
0
1
VA1, VB1
VA2, VB2
The acquisition time required is calculated using the following
formula:
TRANSFER FUNCTION
t
ACQ = 1ꢀ × ((RSOURCE + R) C)
The output coding of the AD7366/AD7367 is twos complement.
The designed code transitions occur at successive integer LSB
values (that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent
on the analog input range selected. The ideal transfer charac-
teristic is shown in Figure 19.
where:
C is the sampling capacitance.
R is the resistance seen by the track-and-hold amplifier looking
at the input.
RSOURCE should include any extra source impedance on the
analog input.
Rev. 0 | Page 17 of 28
AD7366/AD7367
Unlike other bipolar ADCs, the AD7366/AD7367 do not have
a resistive analog input structure. On the AD73667/AD7366,
the bipolar analog signal is sampled directly onto the sampling
capacitor. This gives the AD7366/AD7367 high analog input
impedance. The analog input impedance can be calculated from
the following formula:
TYPICAL CONNECTION DIAGRAM
Figure 2ꢀ shows a typical connection diagram for the AD7366/
AD7367. In this configuration, the AGND pin is connected
to the analog ground plane of the system, and the DGND pin
is connected to the digital ground plane of the system. The
analog inputs on the AD7366/AD7367 accept bipolar single-
ended signals. The AD7366/AD7367 can operate with either
an internal or an external reference. In Figure 2ꢀ, the AD7366/
AD7367 is configured to operate with the internal 2.± ꢁ reference.
A 68ꢀ nF decoupling capacitor is required when operating with
the internal reference.
Z = 1/(fS × CS)
where:
fS is the sampling frequency.
CS is the sampling capacitor value.
CS depends on the analog input range chosen (see the Analog
Inputs section). When operating at 1 MSPS, the analog input
impedance is typically 26ꢀ kꢂ for the ±1ꢀ ꢁ range. As the
sampling frequency is reduced, the analog input impedance
further increases. As the analog input impedance increases, the
current required to drive the analog input therefore decreases
(see Figure 7 for more information).
The AꢁDD and DꢁDD pins are connected to a ± ꢁ supply voltage.
The ꢁDD and ꢁSS are the dual supplies for the high voltage analog
input structures. The voltage on these pins must be equal to
or greater than ±11.± ꢁ (see Table 8 for more information). The
ꢁDRIꢁE pin is connected to the supply voltage of the micro-
processor. The voltage applied to the ꢁDRIꢁE input controls the
voltage of the serial interface. ꢁDRIꢁE can be set to 3 ꢁ or ± ꢁ.
+
0.1µF
+5V SUPPLY
+11.5V TO +16.5V
SUPPLY
+
+
+
+
10µF
0.1µF
0.1µF
10µF
V
DV
AV
CC CC
+3V OR +5V SUPPLY
+
DD
V
DRIVE
+
V
V
A1
0.1µF
10µF
AD7366/
AD7367
A2
CS
ANALOG INPUTS ±10V,
±5V, AND 0V TO +10V
SCLK
CNVST
D
D
A
B
OUT
V
V
B1
OUT
BUSY
ADDR
B2
V
REFSEL
DGND
DRIVE
D
D
A
B
V
CAP
SERIAL
INTERFACE
+
680nF
CAP
+
680nF
AGND
SS
–16.5V TO –11.5V
SUPPLY
0.1µF
10µF
+
+
Figure 20. Typical Connection Diagram Using Internal Reference
Rev. 0 | Page 18 of 28
AD7366/AD7367
VDRIVE
DRIVER AMPLIFIER CHOICE
The AD7366/AD7367 also have a ꢁDRIꢁE feature to control the
voltage at which the serial interface operates. ꢁDRIꢁE allows the
ADC to easily interface to both 3 ꢁ and ± ꢁ processors. For
example, if the AD7366/AD7367 was operated with a ꢁCC of
± ꢁ, the ꢁDRIꢁE pin could be powered from a 3 ꢁ supply, allow-
ing a large dynamic range with low voltage digital processors.
Thus, the AD7366/AD7367 could be used with the ±1ꢀ ꢁ input
range while still being able to interface to 3 ꢁ digital parts.
The AD7366/AD7367 have a total of four analog inputs, which
operate in single-ended mode. Both ADC’s analog inputs can
be programmed to one of the three analog input ranges. In
applications where the signal source is high impedance, it is
recommended to buffer the signal before applying it to the
ADC analog inputs. Figure 21 shows the configuration of the
AD7366/AD7367 in single-ended mode.
In applications where the THD and SNR are critical specifi-
cations, the analog input of the AD7366/AD7367 should be
driven from a low impedance source. Large source impedances
significantly affect the ac performance of the ADC and can
necessitate the use of an input buffer amplifier.
To achieve the maximum throughput rate of 1.12 MSPS for the
AD7366 or 1 MSPS for the AD7367, ꢁDRIꢁE must be greater than
or equal to 4.7± ꢁ, see Table 2 and Table 3. The maximum
throughput rate with the ꢁDRIꢁE voltage set to less than 4.7± ꢁ
and greater than 2.7 ꢁ is 1 MSPS for the AD7366 and 9ꢀꢀ kSPS
for the AD7367.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of THD that can be tolerated
in the application. The THD increases as the source impedance
increases and performance degrades. Figure 7 shows THD vs.
the analog input frequency for various source impedances.
Depending on the input range and analog input configuration
selected, the AD7366/AD7367 can handle source impedances as
illustrated in Figure 7.
REFERENCE
The AD7366/AD7367 can operate with either the internal 2.± ꢁ
on-chip reference or an externally applied reference. The logic
state of the REFSEL pin determines whether the internal refer-
ence is used. The internal reference is selected for both ADC
when the REFSEL pin is tied to logic high. If the REFSEL pin is
tied to GND then an external reference can be supplied through
the DCAPA and DCAPB pins. On power-up, the REFSEL pin must
be tied to either a low or high logic state for the part to operate.
Suitable reference sources for the AD7366/AD7367 include
AD78ꢀ, AD1±82, ADR431, REF193, and ADR391.
Due to the programmable nature of the analog inputs on the
AD7366/AD7367, the choice of op amp used to drive the
inputs is a function of the particular application and depends
on the analog input voltage ranges selected.
The internal reference circuitry consists of a 2.± ꢁ band gap
reference and a reference buffer. When operating the AD7366/
AD7367 in internal reference mode, the 2.± ꢁ internal reference
is available at the DCAPA and DCAPB pins, which should be
decoupled to AGND using a 68ꢀ nF capacitor. It is recom-
mended that the internal reference be buffered before applying
it elsewhere in the system. The internal reference is capable of
sourcing up to 1±ꢀ μA with an analog input range of ±1ꢀ ꢁ
and 7ꢀ μA for both the ±± ꢁ and ꢀ ꢁ to 1ꢀ ꢁ ranges.
The driver amplifier must be able to settle for a full-scale step
to a 14-bit level, ꢀ.ꢀꢀ61%, in less than the specified acquisition
time of the AD7366/AD7367. An op amp such as the AD8ꢀ21
meets this requirement when operating in single-ended mode.
The AD8ꢀ21 needs an external compensating NPO type of
capacitor. The AD8ꢀ22 can also be used in high frequency
applications where a dual version is required. For lower fre-
quency applications, recommended op amps are the AD797,
AD84±, and AD861ꢀ.
V+
If the internal reference operation is required for the ADC con-
version, the REFSEL pin must be tied to logic high on power-
up. The reference buffer requires 7ꢀ ꢃs to power up and charge
the 68ꢀ nF decoupling capacitor during the power-up time.
10µF
+5V
+10V/+5V
0.1µF
+
AGND
AD8021
V
A1
The AD7366/AD7367 is specified for a 2.± ꢁ to 3 ꢁ reference
range. When a 3 ꢁ reference is selected, the ranges are ±12 ꢁ,
±6 ꢁ, and ꢀ ꢁ to +12 ꢁ. For these ranges, the ꢁDD and ꢁSS
supply must be equal to or greater than the +12 ꢁ and −12 ꢁ
respectively.
V
V
CC
DD
–10V/–5V
1kꢀ
AD7366/
AD7367*
15pF
V
1kꢀ
SS
0.1µF
10µF
C
= 10pF
COMP
V–
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 21. Typical Connection Diagram with the AD8021 for Driving the
Analog Input
Rev. 0 | Page 19 of 28
AD7366/AD7367
MODES OF OPERATION
The mode of operation of the AD7366/AD7367 is selected by
CNꢁST
three-state, subsequently 12 SCLK cycles are required to read
the conversion result from the AD7366 while 14 SCLK cycles
are required to read from the AD7367. The DOUT lines return
the (logic) state of the
signal at the end of a conversion.
There are two possible modes of operation: normal mode and
shutdown mode. These modes of operation are designed to
provide flexible power management options, which can be
chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
CS
CS
to three-state when
is brought high only. If
is left low
for a further 12 SCLK cycles for the AD7366 or 14 SCLK cycles
for the AD7367, the result from the other on chip ADC is also
accessed on the same DOUT line, as shown in Figure 27 and
Figure 28 (see the Serial Interface section).
NORMAL MODE
Once 24 SCLK cycles have elapsed for the AD7366 and 28
SCLK cycles for the AD7367, the DOUT line returns to three-
Normal mode is intended for applications needing fast
throughput rates because the user does not have to worry
about any power-up times (with the AD7366/AD7367
remaining fully powered at all times). Figure 22 shows the
general mode of operation of the AD7366 in normal mode,
while Figure 23 illustrates normal mode for the AD7367.
th
th
CS
state when
falling edge. If
returns to three-state at that point. Thus,
is brought high and not on the 24 or 28 SCLK
CS
is brought high prior to this, the DOUT line
CS
must be brought
high once the read is completed, as the bus does not auto-
matically return to three-state upon completion of the dual
result read.
CNꢁST
The conversion is initiated on the falling edge of
described in the Circuit Information section. To ensure that
CNꢁST
as
Once a data transfer is complete and DOUTA and DOUTB have
returned to three-state, another conversion can be initiated after
the part remains fully powered up at all times,
must be
CNꢁST
at logic state high prior to the BUSY signal going low. If
CNꢁST
the quiet time, tQUIET, has elapsed by bringing
low again.
is at logic state low when the BUSY signal goes low, the analog
circuitry powers down and the part ceases converting. The
BUSY signal remains high for the duration of the conversion.
CS
The
pin must be brought low to bring the data bus out of
t1
CNVST
tQUIET
t2
BUSY
tCONVERT
t3
CS
SCLK
SERIAL READ OPERATION
1
12
Figure 22. Normal Mode Operation for the AD7366
t1
CNVST
BUSY
tQUIET
t2
tCONVERT
t3
CS
SCLK
SERIAL READ OPERATION
1
14
Figure 23. Normal Mode Operation for the AD7367
Rev. 0 | Page 20 of 28
AD7366/AD7367
SHUTDOWN MODE
POWER-UP TIMES
Shutdown mode is intended for use in applications where slow
throughput rates are required. Shutdown mode is suited to
applications where a series of conversions performed at a
relatively high throughput rate are followed by a long period
of inactivity and thus, shutdown. When the AD7366/AD7367
is in full power-down, all analog circuitry is powered down.
The AD7366/AD7367 have one power down mode, which has
already been described in detail in the Shutdown Mode section.
This section deals with the power-up time required when coming
out of this mode. It should be noted that the power-up times (as
explained in this section) apply with the recommended capaci-
tors in place on the DCAPA and DCAPB pins. To power up from
CNꢁST
CNꢁST
The falling edge of
initiates the conversion. The BUSY
shutdown,
must be brought high and remain high for a
output subsequently goes high to indicate that the conversion is
in progress. Once the conversion is completed, the BUSY output
minimum of 7ꢀ μs, as shown in Figure 24.
When power supplies are first applied to the AD7366/AD7367,
CNꢁST
returns low. If the
signal is at logic low when BUSY goes
CNꢁST
the ADC can power up with
logic state. Before attempting a valid conversion,
be brought high and remain high for the recommended power-
CNꢁST
in either the low or high
low then the part enters shutdown at the end of the conversion
phase. While the part is in shutdown mode the digital output
code from the last conversion on each ADC can still be read
CNꢁST
must
up time of 7ꢀ μs. Then
can be brought low to initiate a
CS
from the DOUT pins. To read the DOUT data,
low as described in the Serial Interface section. The DOUT pins
CS
must be brought
conversion. With the AD7366/AD7367 no dummy conversion
is required before valid data can be read from the DOUT pins.
If it is intended to place the part in shutdown mode when the
supplies are first applied, then the AD7366/AD7367 must be
powered up and a conversion initiated. However,
remain in the logic low state and when the BUSY signal goes
return to three-state once
To exit full power-down and to power up the AD7366/AD7367,
CNꢁST
is brought back to logic high.
CNꢁST
should
a rising edge of
time has elapsed,
is required. After the required power-up
CNꢁST
may be brought low again to initiate
low, the part enters shutdown.
another conversion, as shown in Figure 24 (see the Power-Up
Times section for power-up times associated with the AD7366/
AD7367).
Once supplies are applied to the AD7366/AD7367, sufficient
time must be allowed for any external reference to power up and
to charge the various reference buffer decoupling capacitors to
their final values.
tPOWER-UP
ENTERS SHUTDOWN
CNVST
BUSY
t2
tCONVERT
t3
CS
SCLK
SERIAL READ OPERATION
12
1
Figure 24. Autoshutdown Mode for AD7366
Rev. 0 | Page 21 of 28
AD7366/AD7367
SERIAL INTERFACE
CS
On the rising edge of
D
, the conversion is terminated and
CS
Figure 2± and Figure 26 show the detailed timing diagram
for serial interfacing to the AD7366 and the AD7367. On the
OUTA and DOUTB go back into three-state. If
high, but is instead held low for a further 12 SCLK cycles for the
AD7366 or 14 SCLK cycles for the AD7367, on either DOUTA or
OUTB, the data from the other ADC follows on the DOUT pin.
This is illustrated in Figure 27 and Figure 28 where the case for
OUTA is shown. In this case, the DOUT line in use goes back into
three-state on the rising edge of
is not brought
CNꢁST
falling edge of
converts the selected channels. These conversions are performed
CNꢁST
the AD7366/AD7367 simultaneously
D
using the on-chip oscillator. After the falling edge of
the BUSY signal goes high, indicating the conversion has started.
It returns low once the conversion has been completed. The data
can now be read from the DOUT pins.
D
CS
.
If the falling edge of SCLK coincides with the falling edge of
CS
CS
and SCLK signals are required to transfer data from the
, then the falling edge of SCLK is not acknowledged by the
AD7366/AD7367, and the next falling edge of the SCLK is the
CS
AD7366/AD7367. The AD7366/AD7367 have two output pins
corresponding to each ADC. Data can be read from the AD7366/
AD7367 using both DOUTA and DOUTB. Alternatively, a single
output pin of the user’s choice can be used. The SCLK input
first registered after the falling edges of the
CS
low indicating the end of a conversion. Once
.
The
pin can be brought low before the BUSY signal goes
CS
CS
signal provides the clock source for the serial interface. The
goes low to access data from the AD7366/AD7367. The falling
CS
is at a logic low
state the data bus is brought out of three-state. This feature can
be utilized to ensure that the MSB is valid on the falling edge of
edge of
takes the bus out of three-state and clocks out the
MSB of the conversion result. The data stream consists of
12 bits of data for the AD7366 and 14 bits of data for the
AD7367, MSB first. The first bit of the conversion result is
CS
BUSY by bring
low a minimum of t4 nanoseconds before the
CS
BUSY signal goes low. The dotted
Figure 23 illustrates this.
line in Figure 22 and
CS
valid on the first SCLK falling edge after the
falling edge.
CS
Alternatively, the
pin can be tied to a low logic state continu-
The subsequent 11-/13-bits of data for the AD7366/AD7367
respectively are clocked out on the falling edge of the SCLK
signal. A minimum of 12 clock pulses must be provided to
AD7366 to access each conversion result, while a minimum
of 14 clock pulses must be provided to AD7367 to access the
conversion result. Figure 2± shows how a 12 SCLK read is used
to access the conversion results while Figure 26 illustrates the
case for the AD7367 with a 14 SCLK read.
ously. Now the DOUT pins never enter three-state and the data
bus is continuously active. Under these conditions, the MSB of
the conversion result for the AD7366/AD7367 is available on
the falling edge of the BUSY signal. The next most significant
bit is available on the first SCLK falling edge after the BUSY
signal has gone low. This mode of operation enables the user to
read the MSB as soon as it is made available by the converter.
CS
t8
3
4
5
12
SCLK
1
2
t9
t7
t5
t6
t4
D
D
A
B
OUT
DB10
DB9
DB8
DB2
DB1
DB0
THREE-STATE
OUT
THREE-
STATE
DB11
Figure 25. Serial Interface Timing Diagram for the AD7366
CS
t8
3
4
5
14
SCLK
1
2
t9
t7
t5
t6
t4
D
A
OUT
DB12
DB11
DB10
DB2
DB1
DB0
D
B
THREE-STATE
OUT
THREE-
STATE
DB13
Figure 26. Serial Interface Timing Diagram for the AD7367
Rev. 0 | Page 22 of 28
AD7366/AD7367
CS
t8
SCLK
3
4
5
1
2
10
11
12
13
24
t7
t4
t5
t6
DB10A
DB9A
DB1A
DB0A
DB11B
DB10B
DB1B
DB0B
D
A
OUT
THREE-
STATE
THREE-
STATE
DB11A
Figure 27. Reading Data from Both ADCs on One DOUT Line with 24 SCLKs for the AD7366
CS
t8
SCLK
3
4
5
1
2
12
13
14
15
28
t7
t3
t5
t6
DB12A
DB11A
DB1A
DB0A
DB13B
DB12B
DB1B
DB0B
D
A
OUT
THREE-
STATE
THREE-
STATE
DB13A
Figure 28. Reading Data from Both ADCs on One DOUT Line with 28 SCLKs for the AD7367
Rev. 0 | Page 23 of 28
AD7366/AD7367
MICROPROCESSOR INTERFACING
The serial interface on the AD7366/AD7367 allows the parts
to be directly connected to a range of different microprocessors.
This section explains how to interface the AD7366/AD7367
with some more common microcontrollers and DSP serial
interface protocols.
ADSP-218x*
SCLK0
AD7366/
AD7367*
SCLK
SCLK1
TFS0
RFS0
RFS1
DR0
CS
AD7366/AD7367 TO ADSP-218x
D
D
A
The ADSP-218x family of DSPs interfaces directly to the
AD7366/AD7367 without any glue logic required. The ꢁDRIꢁE
pin of the AD7366/AD7367 takes the same supply voltage as
that of the ADSP-218x. This allows the ADC to operate at a
higher supply voltage than its serial interface and therefore, the
ADSP-218x, if necessary. This example shows both DOUTA and
OUT
B
DR1
IRQ
OUT
BUSY
CNVST
FLO
V
DRIVE
D
OUTB of the AD7366/AD7367 connected to both serial ports
V
DD
*ADDITIONAL PINS OMITTED FOR CLARITY.
of the ADSP-218x. The SPORTꢀ and SPORT1 control registers
should be set up as shown in Table 11 and Table 12.
Figure 29. Interfacing the AD7366/AD7367 to the ADSP-218x
The AD7366/AD7367 BUSY line provides an interrupt to
the ADSP-218x when the conversion is complete. The conver-
sion results can then be read from the AD7366/AD7367 using
Table 11. SPORT0 Control Register Setup
Setting
Description
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
Alternate framing
Active low frame signal
Right justify data
IRQ
a read operation. When an interrupt is received on
from
the BUSY signal, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and, hence,
the reading of data.
SLEN = 1111
16-bit data-word (or can be set to 1101
for 14-bit data-word)
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
Internal serial clock
Frame every word
AD7366/AD7367 TO ADSP-BF53x
The ADSP-BF±3x family of DSPs interfaces directly to the
AD7366/AD7367 without any glue logic required. The avail-
ability of secondary receive registers on the serial ports of the
Blackfin® DSPs means only one serial port is necessary to read
from both DOUTA and DOUTB pins simultaneously. Figure 3ꢀ
shows both DOUTA and DOUTB of the AD7366/AD7367 con-
nected to Serial Port ꢀ of the ADSP-BF±3x. The SPORTꢀ
Receive Configuration 1 register and SPORTꢀ Receive
Configuration 2 register should be set up as outlined in
Table 13 and Table 14.
ITFS = 1
Table 12. SPORT1 Control Register Setup
Setting
Description
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
Alternate framing
Active low frame signal
Right justify data
16-bit data-word (or can be set to 1101
for 14-bit data-word)
SLEN = 1111
ISCLK = 0
TFSR = RFSR = 1
IRFS = 0
External serial clock
Frame every word
ADSP-BF53x*
SPORT0
AD7366/
AD7367*
SERIAL
DEVICE A
(PRIMARY)
D
A
DR0PRI
RCLK0
OUT
ITFS = 1
SCLK
CS
BUSY
RFS0
The connection diagram is shown in Figure 29. The ADSP-218x
has the TFSꢀ and RFSꢀ of the SPORTꢀ and the RFS1 of SPORT1
tied together. TFSꢀ is set as an output, and both RFSꢀ and RFS1
are set as inputs. The DSP operates in alternate framing mode,
and the SPORT control register is set up as described in
Table 13 and Table 14. The frame synchronization signal
RXINTS
CNVST
PF
N
D
B
DR0SEC
OUT
SERIAL
DEVICE B
(SECONDARY)
V
DRIVE
CS
generated on the TFS is tied to
.
V
DD
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 30. Interfacing the AD7366/AD7367 to the ADSP-BF53x
Rev. 0 | Page 24 of 28
AD7366/AD7367
TMS320VC5506*
AD7366/
AD7367*
Table 13. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
SCLK
CLKX0
CLKR0
CLKX1
CLKR1
DR0
Setting
Description
RCKFE = 1
LRFS = 1
RFSR = 1
Sample data with falling edge of RSCLK
Active low frame signal
Frame every word
Internal RFS used
D
D
A
B
OUT
DR1
OUT
IRFS = 1
CS
FSX0
FSR0
FSR1
INTn
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
Receive MSB first
Zero fill
Internal receive clock
Receive enabled
16-bit data-word (or can be set to 1101 for
14-bit data-word)
BUSY
CNVST
XF
V
DRIVE
TFSR = RFSR = 1
V
*ADDITIONAL PINS OMITTED FOR CLARITY.
DD
Figure 31. Interfacing the AD7366/AD7367 to the TMS320VC5506
Table 14. The SPORT0 Receive Configuration 2 Register
(SPORT0_RCR2)
As with the previous interfaces, conversion can be initiated
from the TMS32ꢀꢁC±±ꢀ6 or from an external source, and the
processor is interrupted when the conversion sequence is
completed.
Setting
Description
RXSE = 1
Secondary side enabled
SLEN = 1111
16-bit data-word (or can be set to 1101 for
14-bit data-word)
AD7366/AD7367 TO DSP563xx
AD7366/AD7367 TO TMS320VC5506
The connection diagram in Figure 32 shows how the AD7366/
AD7367 can be connected to the enhanced synchronous serial
interface (ESSI) of the DSP±63xx family of DSPs from Motorola.
There are two on-board ESSIs, and each is operated in synchro-
nous mode (Bit SYN = 1 in the CRB register) with internally
generated word length frame sync for both TX and RX (Bit
FSL1 = ꢀ and Bit FSLꢀ = ꢀ in the CRB register).
The serial interface on the TMS32ꢀꢁC±±ꢀ6 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
CS
AD7366/AD7367. The
input allows easy interfacing between
the TMS32ꢀꢁC±±ꢀ6 and the AD7366/AD7367 without any glue
logic required. The serial ports of the TMS32ꢀꢁC±±ꢀ6 are set
up to operate in burst mode with internal CLKXꢀ (TX serial
clock on Serial Port ꢀ) and FSXꢀ (TX frame sync from Serial
Port ꢀ). The serial port control registers (SPC) must be setup
as shown in Table 1±.
Normal operation of the ESSI is selected by making MOD = ꢀ
in the CRB register. Set the word length to 16 by setting Bit
WL1 = 1 and Bit WLꢀ = ꢀ in the CRA register. The FSP bit in
the CRB register should be set to 1 so that the frame sync is
negative.
Table 15. Serial Port Control Register Set Up
SPC
FO
FSM
MCM
TXM
SPC0
SPC1
0
0
1
1
1
0
1
0
The connection diagram is shown in Figure 31. The ꢁDRIꢁE pin
of the AD7366/AD7367 takes the same supply voltage as that
of the TMS32ꢀꢁC±±ꢀ6. This allows the ADC to operate at a
higher voltage than its serial interface and, therefore, the
TMS32ꢀꢁC±±ꢀ6, if necessary.
Rev. 0 | Page 25 of 28
AD7366/AD7367
In the example shown in Figure 32, the serial clock is taken
from the ESSIꢀ so the SCKꢀ pin must be set as an output
(SCKD = 1) while the SCK1 pin is set as an input (SCKD = ꢀ).
The frame sync signal is taken from SCꢀ2 on ESSIꢀ, so SCD2 = 1,
while on ESSI1, SCD2 = ꢀ; therefore, SC12 is configured as an
input. The ꢁDRIꢁE pin of the AD7366/AD7367 takes the same
supply voltage as that of the DSP±63xx. This allows the ADC
to operate at a higher voltage than its serial interface and,
therefore, the DSP±63xx, if necessary.
DSP563xx*
SCK0
AD7366/
AD7367*
SCLK
SCK1
SRD0
SRD1
SC02
SC12
D
D
A
OUT
B
OUT
CS
BUSY
IRQ
N
CNVST
PB
N
V
DRIVE
V
*ADDITIONAL PINS OMITTED FOR CLARITY.
DD
Figure 32. Interfacing the AD7366/AD7367 to the DSP563xx
Rev. 0 | Page 26 of 28
AD7366/AD7367
APPLICATION HINTS
To avoid radiating noise to other sections of the board, com-
ponents, such as clocks, with fast switching signals should be
shielded with digital ground and should never be run near the
analog inputs. Avoid crossover of digital and analog signals. To
reduce the effects of feedthrough within the board, traces should
be run at right angles to each other. A microstrip technique is
the best method, but its use may not be possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes, and signals are placed on the
other side.
LAYOUT AND GROUNDING
The printed circuit board that houses the AD7366/AD7367
should be designed so that the analog and digital sections are
confined to their own separate areas of the board. This design
facilitates the use of ground planes that can be easily separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally the best option. All AGND pins on
the AD7366/AD7367 should be connected to the AGND plane.
Digital and analog ground pins should be joined in only one
place. If the AD7366/AD7367 are in a system where multiple
devices require an AGND and DGND connection, the connec-
tion should still be made at only one point. A star point should
be established as close as possible to the ground pins on the
AD7366/AD7367.
Good decoupling is also important. All analog supplies should
be decoupled with 1ꢀ ꢃF tantalum capacitors in parallel with
ꢀ.1 ꢃF capacitors to AGND. To achieve the best results from
these decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
ꢀ.1 ꢃF capacitors should have a low effective series resistance
(ESR) and low effective series inductance (ESI), such as is typical
of common ceramic and surface mount types of capacitors. These
low ESR, low ESI capacitors provide a low impedance path to
ground at high frequencies to handle transient currents due to
internal logic switching.
Good connections should be made to the power and ground
planes. This can be done with a single via or multiple vias for
each supply and ground pin.
Avoid running digital lines under the AD7366/AD7367 devices
because this couples noise onto the die. However, the analog
ground plane should be allowed to run under the AD7366/
AD7367 to avoid noise coupling. The power supply lines to
the AD7366/AD7367 should use as large a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line.
Rev. 0 | Page 27 of 28
AD7366/AD7367
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
RU-24
RU-24
AD7366BRUZ1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
24-Lead Thin Shrink Small Outline Package
24-Lead Thin Shrink Small Outline Package
24-Lead Thin Shrink Small Outline Package
24-Lead Thin Shrink Small Outline Package
24-Lead Thin Shrink Small Outline Package
24-Lead Thin Shrink Small Outline Package
Evaluation Board
AD7366BRUZ-RL71
AD7366BRUZ-500RL71
AD7367BRUZ1
AD7367BRUZ-500RL71
AD7367BRUZ-RL71
EVAL-AD7366CBZ
EVAL-AD7367CBZ
EVAL-CONTROL BRD2
RU-24
RU-24
RU-24
RU-24
Evaluation Board
Control Board
1 Z = RoHS Compliant Part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06703-0-5/07(0)
Rev. 0 | Page 28 of 28
相关型号：
AD7366BRUZ-5500RL7
2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24, ROHS COMPLIANT, MO-153AD, TSSOP-24
ADI
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