AD7400AYRWZ [ADI]
Isolated Sigma-Delta Modulator;
| 型号： | AD7400AYRWZ |
| 厂家： | 
ADI |
| 描述： | Isolated Sigma-Delta Modulator 光电二极管 |
| 文件： | 总21页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Isolated Sigma-Delta Modulator
Data Sheet
AD7400A
FEATURES
GENERAL DESCRIPTION
10 MHz clock rate
Second-order modulator
16 bits, no missing codes
2 LSB INL typical at 16 bits
1.5 µV/°C typical offset drift
On-board digital isolator
On-board reference
The AD7400A1 is a second-order, Σ-Δ modulator that converts
an analog input signal into a high speed, 1-bit data stream with
on-chip digital isolation based on Analog Devices, Inc., iCoupler®
technology. The AD7400A operates from a 5 V power supply
and accepts a differential input signal of 250 mV ( 320 mV
full scale). The analog input is sampled continuously by the
analog modulator, eliminating the need for external sample-
and-hold circuitry. The input information is contained in the
output stream as a density of ones with a data rate of 10 MHz.
The original information can be reconstructed with an appropriate
digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2).
250 mV analog input range
Low power operation: 15.5 mA typical at 5.5 V
−40°C to +125°C operating range
16-lead SOIC package
AD7401A, external clock version in 16-lead SOIC
Safety and regulatory approvals
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
The serial interface is digitally isolated. High speed CMOS,
combined with monolithic air core transformer technology,
means the on-chip isolation provides outstanding performance
characteristics superior to alternatives such as optocoupler
devices. The part contains an on-chip reference and has an
operating temperature range of −40°C to +125°C. The AD7400A
is offered in a 16-lead SOIC package.
V
IORM = 891 V peak
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
APPLICATIONS
AC motor controls
Shunt current monitoring
Data acquisition systems
Analog-to-digital and opto-isolator replacements
FUNCTIONAL BLOCK DIAGRAM
V
V
DD2
DD1
AD7400A
V
V
+
IN
T/H
Σ-Δ ADC
–
IN
UPDATE
WATCHDOG
ENCODE
DECODE
BUF
MDAT
REF
CONTROL LOGIC
UPDATE
WATCHDOG
ENCODE
MCLKOUT
DECODE
GND
GND
1
2
Figure 1.
Rev. D
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AD7400A* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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REFERENCE MATERIALS
Press
• Analog Devices Achieves Major Milestone by Shipping 1
Billionth Channel of iCoupler Digital Isolation
EVALUATION KITS
Product Selection Guide
• AD7400A Evaluation Board
• Digital Isolator Product Selection and Resource Guide
Technical Articles
DOCUMENTATION
Data Sheet
• Inside iCoupler® Technology:ADuM347x PWM Controller
and Transformer Driver with Quad-Channel Isolators
Design Summary
• AD7400A: Isolated Sigma-Delta Modulator Data Sheet
• NAppkin Note: Lowering the Power of the ADuM524x
SOFTWARE AND SYSTEMS REQUIREMENTS
• CED1Z FPGA Project for AD7400A with Nios driver
DESIGN RESOURCES
• AD7400A Material Declaration
• PCN-PDN Information
TOOLS AND SIMULATIONS
• AD7400/AD7401 IBIS Model
• Quality And Reliability
• Symbols and Footprints
REFERENCE DESIGNS
• CN0185
DISCUSSIONS
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AD7400A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology.................................................................................... 12
Theory of Operation ...................................................................... 13
Circuit Information.................................................................... 13
Analog Input ............................................................................... 13
Differential Inputs ...................................................................... 14
Current Sensing Applications................................................... 14
Voltage Sensing Applications.................................................... 14
Digital Filter ................................................................................ 15
Applications Information .............................................................. 17
Grounding and Layout .............................................................. 17
Evaluating the AD7400A Performance................................... 17
Insulation Lifetime..................................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Insulation and Safety-Related Specifications............................ 5
Regulatory Information............................................................... 5
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
REVISION HISTORY
11/12—Rev. C to Rev. D
Changed UL Recognition from 3750 V rms to 5000 V rms
(Table 4) ..............................................................................................5
Changes to Note 1 (Table 4).............................................................5
Deleted 8-Lead PDIP .........................................................Universal
Change to Note 1 .............................................................................. 1
Deleted Figure 5 and Renumbered Sequentially.......................... 8
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 18
9/08—Rev. 0 to Rev. A
Added 16-Lead SOIC.........................................................Universal
Changes to General Description Section .......................................1
Changes to Table 1, Test Conditions/Comments Column ..........3
Changes to Timing Specifications Table Summary ......................4
Changes to Table 4, Note 2...............................................................5
Added Figure 6; Renumbered Sequentially ...................................8
Changes to Terminology Section ................................................. 12
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide.......................................................... 18
7/11—Rev. B to Rev. C
Changes to Minimum External Air Gap (Clearance) Parameter,
Table 3 and Minimum External Tracking (Creepage) Parameter,
Table 3 ................................................................................................ 5
Changes to Figure 6; Pin 1 Description, Table 8; and Pin 7
Description, Table 8.......................................................................... 8
1/11—Rev. A to Rev. B
Changed UL Recognition from 3750 V rms to 5000 V rms....... 1
Changes to Input-to-Output Momentary Withstand Voltage
Value (Table 3) .................................................................................. 5
5/08—Revision 0: Initial Version
Rev. D | Page 2 of 20
Data Sheet
AD7400A
SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, except where specified, and VIN− = 0 V (single-ended);
TA = −40°C to +125°C, except where specified; fMCLK = 10 MHz, tested with Sinc3 filter, 256 decimation rate, as defined by Verilog code,
unless otherwise noted.
Table 1.
Y Version1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
16
Bits
LSB
LSB
LSB
LSB
Filter output truncated to 16 bits
Integral Nonlinearity2
2
4
4
12
16
22
0.9
VIN+ = 200 mV, TA = −40°C to +125°C
VIN+ = 250 mV, TA = −40°C to +85°C
VIN+ = 250 mV, TA = −40°C to +125°C
Guaranteed no missing codes to 16 bits
Differential Nonlinearity2
Offset Error2
Offset Drift vs. Temperature
Offset Drift vs. VDD1
Gain Error2
50
1.5
120
500 μV
4
µV/°C −40°C to +125°C
µV/V
mV
mV
1.5
2
−40°C to +85°C
−40°C to +125°C
Gain Error Drift vs. Temperature
Gain Error Drift vs. VDD1
ANALOG INPUT
23
110
µV/°C −40°C to +125°C
µV/V
Input Voltage Range
Dynamic Input Current
−250
+250 mV
For specified performance, full range = 320 mV
VIN+ = 400 mV, VIN− = 0 V
VIN+ = 500 mV, VIN− = 0 V
7
9
0.5
10
8
µA
µA
µA
pF
10
VIN+ = VIN− = 0 V
Input Capacitance
DYNAMIC SPECIFICATIONS
VIN+ = 35 Hz
Signal-to-Noise and Distortion (SINAD) Ratio2
70
68
73
72
78
78
80
80
−84
−82
−86
−84
12.5
12.5
30
dB
dB
dB
dB
dB
dB
dB
dB
VIN+ = 200 mV
VIN+ = 250 mV
VIN+ = 200 mV
VIN+ = 250 mV
VIN+ = 200 mV
VIN+ = 250 mV
VIN+ = 200 mV
VIN+ = 250 mV
VIN+ = 200 mV
VIN+ = 250 mV
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Effective Number of Bits (ENOB)2
11.5
11
25
Bits
Bits
kV/µs
Isolation Transient Immunity2
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
POWER REQUIREMENTS
VDD1
VDD2 − 0.1
V
V
IO = −200 µA
IO = +200 µA
0.4
4.5
3
5.5
5.5
13
6
V
V
mA
mA
mA
VDD2
3
IDD1
IDD2
11
4.5
3
VDD1 = 5.5 V
VDD2 = 5.5 V
VDD2 = 3.3 V
4
3.5
1 All voltages are relative to their respective ground.
2 See the Terminology section.
3 See Figure 14.
4 See Figure 15.
Rev. D | Page 3 of 20
AD7400A
Data Sheet
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +125°C, except where specified.1
Table 2.
Parameter
Limit at tMIN, tMAX
Unit
Description
2
fMCLKOUT
10
9/11
40
10
0.4 × tMCLKOUT
0.4 × tMCLKOUT
MHz typ
MHz min/MHz max
ns max
ns min
ns min
Master clock output frequency
Master clock output frequency
Data access time after MCLK rising edge
Data hold time after MCLK rising edge
Master clock low time
3
t1
t2
3
t3
t4
ns min
Master clock high time
1 Sample tested during initial release to ensure compliance.
2 Mark space ratio for clock output is 40/60 to 60/40.
3 Measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
200µA
I
OL
TO OUTPUT
PIN
+1.6V
C
L
25pF
200µA
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
t4
MCLKOUT
MDAT
t1
t2
t3
Figure 3. Data Timing
Rev. D | Page 4 of 20
Data Sheet
AD7400A
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 3.
Parameter
Symbol
VISO
L(I01)
Value
Unit
Conditions
Input-to-Output Momentary Withstand Voltage
Minimum External Air Gap (Clearance)
5000 min
8.1 min
V rms 1-minute duration
mm
mm
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material group (DIN VDE 0110, 1/89, Table 1)
Minimum External Tracking (Creepage)
L(I02)
CTI
7.46 min
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.017 min
>175
IIIa
mm
V
REGULATORY INFORMATION
Table 4.
UL1
CSA
VDE2
Recognized Under 1577
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Component Recognition Program1
5000 V rms isolation voltage
Reinforced insulation per CSA 60950-1-03 and
IEC 60950-1, 630 V rms maximum working voltage
Reinforced insulation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12, 891 V peak
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL 1577, each AD7400A is proof tested by applying an insulation test voltage ≥6000 V rms for 1 sec (current leakage detection limit = 15 µA).
2 In accordance with DIN V VDE V 0884-10, each AD7400A is proof tested by applying an insulation test voltage ≥1671 V peak for 1 sec (partial discharge detection limit = 5 pC).
Rev. D | Page 5 of 20
AD7400A
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 5.
Parameter
Symbol Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 450 V rms
I to IV
I to II
For Rated Mains Voltage ≤ 600 V rms
I to II
CLIMATIC CLASSIFICATION
40/105/21
2
POLLUTION DEGREE (DIN VDE 0110, Table 1)
MAXIMUM WORKING INSULATION VOLTAGE
INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC
INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A
After Environmental Test Subgroup 1
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/Safety Test Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec)
SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, ALSO SEE Figure 4)
Case Temperature
VIORM
891
V peak
V peak
V peak
V peak
V peak
VPR
VPR
1671
1426
1069
6000
VTR
TS
IS1
IS2
RS
150
265
335
>109
°C
Side 1 Current
Side 2 Current
mA
mA
Ω
INSULATION RESISTANCE AT TS, VIO = 500 V
350
300
250
SIDE 2
200
150
SIDE 1
100
50
0
0
50
100
150
200
CASE TEMPERATURE (°C)
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. D | Page 6 of 20
Data Sheet
AD7400A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
Rating
VDD1 to GND1
VDD2 to GND2
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to VDD1 + 0.3 V
−0.3 V to VDD2 + 0.3 V
10 mA
−40°C to +125°C
−65°C to +150°C
150°C
Analog Input Voltage to GND1
Output Voltage to GND2
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
SOIC Package
Table 7. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage,
Bipolar Waveform
565
V peak
50-year minimum
lifetime
AC Voltage,
Unipolar Waveform
891
891
V peak
V
Maximum CSA/VDE
approved working
voltage
Maximum CSA/VDE
approved working
voltage
θJA Thermal Impedance2
θJC Thermal Impedance2
Resistance (Input-to-Output), RI-O
89.2°C/W
55.6°C/W
1012 Ω
DC Voltage
3
Capacitance (Input-to-Output), CI-O
1.7 pF typ
1 Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
RoHS-Compliant Temperature, Soldering
Reflow
ESD
260 (+0)°C
2.5 kV
ESD CAUTION
1 Transient currents of up to 100 mA do not cause SCR to latch-up.
2 JEDEC 2S2P standard board.
3 f = 1 MHz.
Rev. D | Page 7 of 20
AD7400A
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
2
DD1
V
+
NC
V
IN
AD7400A
V
–
IN
DD2
TOP VIEW
NC
NC
NC
MCLKOUT
NC
(Not to Scale)
MDAT
NC
V
/NC
DD1
GND
GND
2
1
NC = NO CONNECT
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD1
Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7400A and is
relative to GND1.
2
3
VIN+
VIN−
NC
VDD1/NC
Positive Analog Input. Specified range of 250 mV.
Negative Analog Input. Normally connected to GND1.
No Connect.
Supply Voltage. 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7400A and is
relative to GND1.
4 to 6, 10, 12, 15
7
No Connect (NC). If desired, Pin 7 of the SOIC device may be allowed to float. It should not be tied
to ground. The AD7400A will operate normally provided that the supply voltage is applied to Pin 1.
8
9, 16
11
GND1
GND2
MDAT
Ground 1. This is the ground reference point for all circuitry on the isolated side.
Ground 2. This is the ground reference point for all circuitry on the nonisolated side.
Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The
bits are clocked out on the rising edge of the MCLKOUT output and are valid on the following
MCLKOUT rising edge.
13
14
MCLKOUT
VDD2
Master Clock Logic Output (10 MHz Typical). The bit stream from the modulator is valid on the
rising edge of MCLKOUT.
Supply Voltage, 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2.
Rev. D | Page 8 of 20
Data Sheet
AD7400A
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, using 20 kHz brickwall filter, unless otherwise noted.
110
100
90
80
70
60
50
40
30
20
–85
–80
–75
–70
–65
–60
V
= V = 5V
DD2
DD1
NO DECOUPLING CAPACITOR
V
V
T
= V = 5V
DD2
10
0
DD1
= 25°C
= 200mV SINE WAVE ON V
RIPPLE
DD1
A
100
1k
10k
100k
1M
10M
50
100
150
200
250
300
350
SUPPLY RIPPLE FREQUENCY (Hz)
INPUT AMPLITUDE (mV)
Figure 9. SINAD vs. VIN
Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
(1 MHz Filter Used)
0.5
0.4
–90
–80
–70
V
V
+ = –200mV TO +200mV
– = 0V
IN
IN
0.3
V
= V = 4.5V
DD2
DD1
–60
–50
–40
–30
–20
–10
0
0.2
0.1
0
V
= V = 5.5V
DD2
DD1
V
= V = 5V
DD2
DD1
–0.1
–0.2
–0.3
–0.4
0
500
1000
1500
2000
2500
3000
3500
4000
0
10,000
20,000
30,000
CODE
40,000
50,000
60,000
INPUT FREQUENCY (Hz)
Figure 7. SINAD vs. Analog Input Frequency for Various Supply Voltages
Figure 10. Typical DNL, 200 mV Range
(Using Sinc3 Filter, 256 Decimation Rate)
0
0.8
0.6
V
V
+ = –200mV TO +200mV
– = 0V
8192 POINT FFT
fIN = 35Hz
SINAD = 79.6991dB
IN
IN
–20
THD = –92.6722dB
DECIMATION BY 256
–40
0.4
–60
0.2
–80
–100
–120
–140
–160
–180
0
–0.2
–0.4
–0.6
0
2
4
6
8
10
12
14
16
18
20
0
10,000
20,000
30,000
CODE
40,000
50,000
60,000
FREQUENCY (kHz)
Figure 8. Typical FFT, 200 mV Range
(Using Sinc3 Filter, 256 Decimation Rate)
Figure 11. Typical INL, 200 mV Range
(Using Sinc3 Filter, 256 Decimation Rate)
Rev. D | Page 9 of 20
AD7400A
Data Sheet
500
450
400
350
300
250
200
150
100
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
+125°C
+85°C
+25°C
–40°C
50
0
V
= V = 5V
DD2
= 25°C
DD1
V
= V
= 5V
DD2
DD1
T
A
–60
–40
–20
0
20
40
60
80
100
120
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
TEMPERATURE (°C)
V
DC INPUT VOLTAGE (V)
IN
Figure 12. Offset Drift vs. Temperature
Figure 15. IDD2 vs. VIN at Various Temperatures
0.20
0.15
0.10
0.05
0
–30
–40
–50
–60
–70
–80
–90
–100
V
= V = 4.5V
DD2
DD1
V
= V = 5V
DD2
DD1
–0.05
–0.10
–0.15
–0.20
V
= V = 5.5V
DD2
DD1
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105
TEMPERATURE (°C)
100
1k
10k
100k
1M
10M
COMMON-MODE RIPPLE FREQUENCY (Hz)
Figure 13 . Gain Error Drift vs. Temperature for Various Supply Voltages
Figure 16. CMRR vs. Common-Mode Ripple Frequency
11.0
1.0
0.8
0.6
0.4
0.2
0
+125°C
+85°C
BANDWIDTH = 100kHz
10.5
+25°C
10.0
–40°C
9.5
9.0
V
= V
DD1
= 5V
0.39
DD2
8.5
–0.33
–0.21
–0.09
0.03
0.15
0.27
V
DC INPUT VOLTAGE (V)
IN
V
DC INPUT (V)
IN
Figure 17. RMS Noise Voltage vs. VIN DC Input
Figure 14. IDD1 vs. VIN at Various Temperatures
Rev. D | Page 10 of 20
Data Sheet
AD7400A
11.0
10.8
10.6
10.4
V
= V = 4.5V
DD2
DD1
10.2
10.0
9.8
V
DD1
= V = 5.25V
DD2
9.6
9.4
V
= V = 5V
DD2
DD1
9.2
9.0
TEMPERATURE (°C)
Figure 18. MCLKOUT vs. Temperature for Various Supplies
Rev. D | Page 11 of 20
AD7400A
Data Sheet
TERMINOLOGY
Differential Nonlinearity
Total Harmonic Distortion (THD)
Differential nonlinearity is the difference between the measured
and the ideal 1 LSB change between any two adjacent codes in
the ADC.
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7400A, it is defined as
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD(dB) = 20 log
Integral Nonlinearity
V1
Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are specified negative
full scale, −250 mV (VIN+ − VIN−), Code 7169, and specified
positive full scale, +250 mV (VIN+ − VIN−), Code 58,366 for
the 16-bit level.
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Offset Error
Peak harmonic or spurious noise is defined as the ratio of the rms
value of the next largest component in the ADC output spectrum
(up to fS/2, excluding dc) to the rms value of the fundamental.
Normally, the value of this specification is determined by the
largest harmonic in the spectrum, but for ADCs where the
harmonics are buried in the noise floor, it is a noise peak.
Offset is the deviation of the midscale code (Code 32,768 for
the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V).
Gain Error
Gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (58,366 for the
16-bit level) from the ideal VIN+ − VIN− (+250 mV) after the
offset error is adjusted out. Negative full-scale gain error is the
deviation of the specified negative full-scale code (7169 for the
16-bit level) from the ideal VIN+ − VIN− (−250 mV) after the
offset error is adjusted out. Gain error includes reference error.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
250 mV frequency, f, to the power of a 250 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency fS as
CMRR (dB) = 10 log(Pf/PfS)
where:
Signal-to-Noise and Distortion (SINAD) Ratio
This ratio is the measured ratio of signal-to-noise and distortion
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-noise and distortion ratio for an ideal N-bit
converter with a sine wave input is given by
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the converter linearity. PSRR is the maximum change in the
specified full-scale ( 250 mV) transition point due to a change
in power supply voltage from the nominal value (see Figure 6).
Signal-to-Noise and Distortion = (6.02N + 1.76) dB
Isolation Transient Immunity
Therefore, for a 12-bit converter, SINAD is 74 dB.
The isolation transient immunity specifies the rate of rise/fall of
a transient pulse applied across the isolation boundary beyond
which clock or data is corrupted. (The AD7400A was tested using
a transient pulse frequency of 100 kHz.)
Effective Number of Bits (ENOB)
The ENOB is defined by
ENOB = (SINAD − 1.76)/6.02
Rev. D | Page 12 of 20
Data Sheet
AD7400A
THEORY OF OPERATION
A differential input of 320 mV ideally results in a stream of all
1s. This is the absolute full-scale range of the AD7400A, while
250 mV is the specified full-scale range, as shown in Table 9.
CIRCUIT INFORMATION
The AD7400A isolated Σ-Δ modulator converts an analog input
signal into a high speed (10 MHz typical), single-bit data stream;
the time average of the single-bit data from the modulator is
directly proportional to the input signal. Figure 21 shows a
typical application circuit where the AD7400A is used to provide
isolation between the analog input, a current sensing resistor,
and the digital output, which is then processed by a digital filter
to provide an N-bit word.
Table 9. Analog Input Range
Analog Input
Voltage Input
+640 mV
+320 mV
+250 mV
+200 mV
0 mV
Full-Scale Range
Positive Full Scale
Positive Typical Input Range
Positive Specified Input Range
Zero
ANALOG INPUT
Negative Specified Input Range
Negative Typical Input Range
Negative Full Scale
−200 mV
−250 mV
−320 mV
The differential analog input of the AD7400A is implemented
with a switched capacitor circuit. This circuit implements a
second-order modulator stage that digitizes the input signal
into a 1-bit output stream. The sample clock (MCLKOUT)
provides the clock signal for the conversion process as well as
the output data-framing clock. This clock source is internal on
the AD7400A. The analog input signal is continuously sampled
by the modulator and compared to an internal voltage reference. A
digital stream that accurately represents the analog input over
time appears at the output of the converter (see Figure 19).
To reconstruct the original information, this output needs
to be digitally filtered and decimated. A Sinc3 filter is recom-
mended because this is one order higher than that of the
AD7400A modulator. If a 256 decimation rate is used, the
resulting 16-bit word rate is 39 kHz, assuming a 10 MHz
internal clock frequency. Figure 20 shows the transfer function
of the AD7400A relative to the 16-bit output.
MODULATOR OUTPUT
+FS ANALOG INPUT
65535
–FS ANALOG INPUT
53248
ANALOG INPUT
Figure 19. Analog Input vs. Modulator Output
SPECIFIED RANGE
A differential signal of 0 V ideally results in a stream of 1s and
0s at the MDAT output pin. This output is high 50% of the time
and low 50% of the time. A differential input of 200 mV produces
a stream of 1s and 0s that are high 81.25% of the time (for a
+250 mV input, the output stream is high 89.06% of the time).
A differential input of −200 mV produces a stream of 1s and 0s
that are high 18.75% of the time (for a −250 mV input, the output
stream is high 10.94% of the time).
12288
0
–320mV
–200mV
ANALOG INPUT
+200mV +320mV
Figure 20. Filtered and Decimated 16-Bit Transfer Characteristic
ISOLATED
5V
NONISOLATED
5V/3V
AD7400A
V
V
V
DD
DD1
DD2
3
SINC FILTER*
Σ-Δ
MOD/
CS
V
V
+
–
MDAT
MDAT
MCLK
IN
ENCODER
DECODER
ENCODER
+
SCLK
INPUT
CURRENT
MCLKOUT
IN
SDAT
R
SHUNT
DECODER
GND
GND
GND
1
2
*THIS FILTER IS IMPLEMENTED
WITH AN FPGA OR DSP.
Figure 21. Typical Application Circuit
Rev. D | Page 13 of 20
AD7400A
Data Sheet
DIFFERENTIAL INPUTS
CURRENT SENSING APPLICATIONS
The analog input to the modulator is a switched capacitor
design. The analog signal is converted into charge by highly
linear sampling capacitors. A simplified equivalent circuit
diagram of the analog input is shown in Figure 22. A signal
source driving the analog input must be able to provide the
charge onto the sampling capacitors every half MCLKOUT cycle
and settle to the required accuracy within the next half cycle.
The AD7400A is ideally suited for current sensing applications
where the voltage across a shunt resistor is monitored. The load
current flowing through an external shunt resistor produces a
voltage at the input terminals of the AD7400A. The AD7400A
provides isolation between the analog input from the current
sensing resistor and the digital outputs. By selecting the appropriate
shunt resistor value, a variety of current ranges can be monitored.
φA
Choosing RSENSE
1kΩ
φB
V
+
IN
2pF
2pF
The shunt resistor values used in conjunction with the AD7400A
are determined by the specific application requirements in terms of
voltage, current, and power. Small resistors minimize power
dissipation, while low inductance resistors prevent any induced
voltage spikes, and good tolerance devices reduce current
variations. The final values chosen are a compromise between
low power dissipation and good accuracy. Low value resistors
have less power dissipated in them, but higher value resistors
may be required to use the full input range of the ADC, thus
achieving maximum SNR performance.
φA
φB
1kΩ
V
–
IN
φA φB φA φB
MCLKOUT
Figure 22. Analog Input Equivalent Circuit
Because the AD7400A samples the differential voltage across its
analog inputs, low noise performance is attained with an input
circuit that provides low common-mode noise at each input.
The amplifiers used to drive the analog inputs play a critical
role in attaining the high performance available from the
AD7400A.
When the peak sense current is known, the voltage range of the
AD7400A ( 200 mV) is divided by the maximum sense current
to yield a suitable shunt value. If the power dissipation in the shunt
resistor is too large, the shunt resistor can be reduced, in which
case, less of the ADC input range is used. Using less of the ADC
input range results in performance that is more susceptible to noise
and offset errors because offset errors are fixed and are thus more
significant when smaller input ranges are used.
When a capacitive load is switched onto the output of an op
amp, the amplitude drops momentarily. The op amp tries to
correct the situation and, in the process, hits its slew rate limit.
This nonlinear response, which can cause excessive ringing, can
lead to distortion. To remedy the situation, a low-pass RC filter
can be connected between the amplifier and the input to the
AD7400A. The external capacitor at each input aids in supplying
the current spikes created during the sampling process, and the
resistor isolates the op amp from the transient nature of the load.
R
SENSE must be able to dissipate the I2R power losses. If the power
dissipation rating of the resistor is exceeded, its value may drift
or the resistor may be damaged, resulting in an open circuit.
This can result in a differential voltage across the terminals of
the AD400A in excess of the absolute maximum ratings (see
Table 6.). If ISENSE has a large high frequency component, take
care to choose a resistor with low inductance.
The recommended circuit configuration for driving the differential
inputs to achieve best performance is shown in Figure 23. A
capacitor between the two input pins sources or sinks charge
to allow most of the charge that is needed by one input to be
effectively supplied by the other input. The series resistor again
isolates any op amp from the current spikes created during the
sampling process. Recommended values for the resistors and
capacitor are 22 Ω and 47 pF, respectively.
VOLTAGE SENSING APPLICATIONS
The AD7400A can also be used for isolated voltage monitoring.
For example, in motor control applications, it can be used to
sense bus voltage. In applications where the voltage being
monitored exceeds the specified analog input range of the
AD7400A, a voltage divider network can be used to reduce
the voltage being monitored to the required range.
R
V
+
IN
C
AD7400A
R
V
–
IN
Figure 23. Differential Input RC Network
Rev. D | Page 14 of 20
Data Sheet
AD7400A
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [15:0]
reg [7:0]
diff2;
DIGITAL FILTER
diff3;
The overall system resolution and throughput rate is deter-
mined by the filter selected and the decimation rate used. The
higher the decimation rate, the greater the system accuracy, as
illustrated in Figure 24. However, there is a tradeoff between
accuracy and throughput rate and, therefore, higher decimal-
tion rates result in lower throughput solutions.
diff1_d;
diff2_d;
DATA;
word_count;
reg word_clk;
reg init;
A Sinc3 filter is recommended for use with the AD7400A. This
filter can be implemented on an FPGA or a D S P.
DR
/*Perform the Sinc ACTION*/
3
(
1− Z
)
H(z) =
1− Z −1
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0;
to a -1 for 2's comp */
else
/* change from a 0
where DR is the decimation rate.
90
3
2
SINC
80
70
60
50
40
30
20
10
0
ip_data1 <= 1;
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
SINC
MCLKOUT
ACC1+
+
ACC2+
+
ACC3+
IP_DATA1
Z
Z
Z
1
SINC
+
Figure 25. Accumulator
Z = one sample delay
MCLKOUT = modulators conversion bit rate
*/
1
10
100
DECIMATION RATE
1k
always @ (negedge mclk1 or posedge reset)
if (reset)
Figure 24. SNR vs. Decimation Rate for Different Filter Types
begin
The following Verilog code provides an example of a Sinc3 filter
implementation on a Xilinx® Spartan-II 2.5 V FPGA. This code
can possibly be compiled for another FPGA, such as an Altera®
device. Note that the data is read on the negative clock edge in
this case, although it can be read on the positive edge, if preferred.
Figure 24 shows the effect of using different decimation rates
with various filter types.
/*initialize acc registers on reset*/
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end
else
begin
/*perform accumulation process*/
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
input mclk1;
input reset;
input mdata1;
filtered*/
/*used to clk filter*/
/*used to reset filter*/
/*ip data to be
/*DECIMATION STAGE (MCLKOUT/ WORD_CLK)
*/
always @ (posedge mclk1 or posedge reset)
if (reset)
word_count <= 0;
else
output [15:0] DATA;
/*filtered op*/
integer location;
integer info_file;
word_count <= word_count + 1;
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
ip_data1;
acc1;
always @ (word_count)
word_clk <= word_count[7];
acc2;
acc3;
acc3_d1;
acc3_d2;
diff1;
Rev. D | Page 15 of 20
AD7400A
Data Sheet
/*DIFFERENTIATOR (including decimation
stage)
Perform the differentiation stage (FIR) at a
lower speed.
diff2_d <= diff2;
end
/* Clock the Sinc output into an output
register
DIFF1
DIFF2
DIFF3
+
–
+
–
+
–
WORD_CLK
ACC3
–1
–1
–1
Z
Z
Z
DIFF3
DATA
Figure 27. Clocking Sinc Output into an Output Register
WORD_CLK
WORD_CLK = output word rate
*/
Figure 26. Differentiator
Z = one sample delay
WORD_CLK = output word rate
*/
always @ (posedge word_clk)
begin
DATA[15] <= diff3[23];
DATA[14] <= diff3[22];
DATA[13] <= diff3[21];
DATA[12] <= diff3[20];
DATA[11] <= diff3[19];
DATA[10] <= diff3[18];
DATA[9] <= diff3[17];
DATA[8] <= diff3[16];
DATA[7] <= diff3[15];
DATA[6] <= diff3[14];
DATA[5] <= diff3[13];
DATA[4] <= diff3[12];
DATA[3] <= diff3[11];
DATA[2] <= diff3[10];
DATA[1] <= diff3[9];
DATA[0] <= diff3[8];
always @ (posedge word_clk or posedge reset)
if(reset)
begin
acc3_d2 <= 0;
diff1_d <= 0;
diff2_d <= 0;
diff1 <= 0;
diff2 <= 0;
diff3 <= 0;
end
else
begin
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
end
endmodule
Rev. D | Page 16 of 20
Data Sheet
AD7400A
APPLICATIONS INFORMATION
GROUNDING AND LAYOUT
INSULATION LIFETIME
All insulation structures subjected to sufficient time and/or
voltage are vulnerable to breakdown. In addition to the testing
performed by the regulatory agencies, Analog Devices has carried
out an extensive set of evaluations to determine the lifetime of
the insulation structure within the AD7400A.
Supply decoupling with a value of 100 nF is strongly recom-
mended on both VDD1 and VDD2. Decoupling on one or
both VDDx pins does not significantly affect performance. In
applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, the board layout should be designed so that
any coupling that occurs equally affects all pins on a given
component side. Failure to ensure this may cause voltage
differentials between pins to exceed the absolute maximum
ratings of the device, thereby leading to latch-up or permanent
damage. Any decoupling used should be placed as close to the
supply pins as possible.
These tests subjected populations of devices to continuous
cross-isolation voltages. To accelerate the occurrence of failures,
the selected test voltages were values exceeding those of normal
use. The time to failure values of these units were recorded and
used to calculate acceleration factors. These factors were then
used to calculate the time to failure under normal operating
conditions. The values shown in Table 7 are the lesser of the
following two values:
Series resistance in the analog inputs should be minimized to
avoid any distortion effects, especially at high temperatures. If
possible, equalize the source impedance on each analog input to
minimize offset. Beware of mismatch and thermocouple effects
on the analog input PCB tracks to reduce offset drift.
•
The value that ensures at least a 50-year lifetime of
continuous use.
•
The maximum CSA/VDE approved working voltage.
Note that the lifetime of the AD7400A varies according to
the waveform type imposed across the isolation barrier. The
iCoupler insulation structure is stressed differently depending
on whether the waveform is bipolar ac, unipolar ac, or dc.
Figure 28, Figure 29, and Figure 30 illustrate the different
isolation voltage waveforms.
EVALUATING THE AD7400A PERFORMANCE
An AD7400A evaluation board is available with split ground
planes and a board split beneath the AD7400A package to
ensure isolation. This board allows access to each pin on the
device for evaluation purposes.
RATED PEAK VOLTAGE
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from the PC via the EVAL-CED1Z. The
software also includes a SINC3 filter implemented on an FPGA.
The evaluation board is used in conjunction with the EVAL-CED1Z
board and can be used as a standalone board. The software
allows the user to perform ac (fast Fourier transform) and dc
(histogram of codes) tests on the AD7400A. The software and
documentation are on a CD that ships with the evaluation board.
0V
Figure 28. Bipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 29. Unipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 30. DC Waveform
Rev. D | Page 17 of 20
AD7400A
Data Sheet
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 31. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Package
Option
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
AD7400AYRWZ
AD7400AYRWZ-RL
EVAL-AD7400AEDZ
EVAL-CED1Z
16-Lead Standard Small Outline Package (SOIC_W)
16-Lead Standard Small Outline Package (SOIC_W)
Standalone Evaluation Board
RW-16
RW-16
Development Board
1 Z = RoHS Compliant Part.
Rev. D | Page 18 of 20
Data Sheet
NOTES
AD7400A
Rev. D | Page 19 of 20
AD7400A
NOTES
Data Sheet
©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07077-0-11/12(D)
Rev. D | Page 20 of 20
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