AD7401YRW-REEL7 [ADI]
SPECIALTY ANALOG CIRCUIT, PDSO16, MS-013-AA, SOIC-16;
| 型号： | AD7401YRW-REEL7 |
| 厂家： | 
ADI |
| 描述： | SPECIALTY ANALOG CIRCUIT, PDSO16, MS-013-AA, SOIC-16 光电二极管 |
| 文件： | 总20页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Isolated Sigma-Delta Modulator
AD7401
FEATURES
GENERAꢀ DESCRIPTION
20 MHz maximum external clock rate
Second-order modulator
16 bits no missing codes
2 ꢀSB INꢀ typical at 16 bits
3.5 μV/°C maximum offset drift
On-board digital isolator
The AD74011 is a second-order, sigma-delta (Σ-Δ) modulator
that converts an analog input signal into a high speed, 1-bit data
stream with on-chip digital isolation based on Analog Devices,
Inc. iCoupler® technology. The AD7401 operates from a 5 V
power supply and accepts a differential input signal of ±±00 mV
(±ꢀ±0 mV full scale). The analog input is continuously sampled
by the analog modulator, eliminating the need for external
sample-and-hold circuitry. The input information is contained
in the output stream as a density of ones with a data rate up to
±0 MHz. The original information can be reconstructed with an
appropriate digital filter. The serial I/O can use a 5 V or a ꢀ V
supply (VDD±).
On-board reference
ꢀow power operation: 20 mA maximum at 5.25 V
−40°C to +105°C operating range
16-lead SOIC package
Safety and regulatory approvals
Uꢀ recognition
5000 V rms for 1 minute per Uꢀ 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
The serial interface is digitally isolated. High speed CMOS,
combined with monolithic air core transformer technology,
means the on-chip isolation provides outstanding performance
characteristics, superior to alternatives such as optocoupler
devices. The part contains an on-chip reference. The AD7401
is offered in a 16-lead SOIC and has an operating temperature
range of −40°C to +105°C.
V
IORM = 891 V peak
APPꢀICATIONS
AC motor controls
Data acquisition systems
A/D + opto-isolator replacements
An internal clock version, AD7400, is also available.
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
FUNCTIONAꢀ BꢀOCK DIAGRAM
V
V
DD2
DD1
AD7401
V
V
+
IN
T/H
Σ-∆ ADC
–
IN
UPDATE
WATCHDOG
ENCODE
DECODE
BUF
MDAT
REF
CONTROL LOGIC
WATCHDOG
UPDATE
DECODE
MCLKIN
ENCODE
GND
GND
1
2
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
AD7401
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................9
Terminology.................................................................................... 1±
Theory of Operation ...................................................................... 1ꢀ
Circuit Information.................................................................... 1ꢀ
Analog Input ............................................................................... 1ꢀ
Differential Inputs...................................................................... 14
Digital Filter ................................................................................ 15
Applications Information.............................................................. 17
Grounding and Layout .............................................................. 17
Evaluating the AD7401 Performance...................................... 17
Insulation Lifetime..................................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... ±
Specifications..................................................................................... ꢀ
Timing Specifications .................................................................. 4
Insulation and Safety-Related Specifications............................ 5
Regulatory Information............................................................... 5
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
REVISION HISTORY
7/11—Rev. C to Rev. D
9/07—Rev. A to Rev. B
Changes to Minimum External Air Gap (Clearance) Parameter,
Table ꢀ and Minimum External Tracking (Creepage) Parameter,
Table ꢀ ................................................................................................ 5
Changes to Figure 5; Pin 1 Description, Table 8; and Pin 7
Description, Table 8.......................................................................... 8
Updated VDE Certification Throughout ......................................1
Changes to Table 6.............................................................................7
12/06—Rev. 0 to Rev. A
Changes to Features and General Description..............................1
Changes to Table 1.............................................................................ꢀ
Changes to Table ±.............................................................................4
Changes to Table 6.............................................................................7
Changes to Table 8.............................................................................8
Changes to Circuit Information Section ..................................... 1ꢀ
Changes to Figure ±7...................................................................... 15
1/11—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Changes to Input-to-Output Momentary Withstand Voltage
Parameter, Table ꢀ, UL Column, Table 4, and Note 1, Table 4..........5
Changes to Ordering Guide...................................................................18
1/06—Revision 0: Initial Version
Rev. D | Page 2 of 20
AD7401
SPECIFICATIONS
VDD1 = 4.5 V to 5.±5 V, VDD± = ꢀ V to 5.5 V, VIN+ = −±00 mV to +±00 mV, and VIN− = 0 V (single-ended); TA = TMIN to TMAX
,
f
MCLK = 16 MHz maximum, tested with Sincꢀ filter, ±56 decimation rate, as defined by Verilog code, unless otherwise noted.
Table 1.
Parameter
YVersion1, 2
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
16
15
25
55
0.9
Bits min
LSB max
LSB max
LSB max
LSB max
Filter output truncated to 16 bits
Integral Nonlinearity3
−40°C to +85°C; 2 LSB typical; fMCLK = 20 MHz maximum4
>85°C to 105°C
fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV
Differential Nonlinearity3
Offset Error3
Guaranteed no missed codes to 16 bits;
fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV
0.6
50
3.5
1
120
1.6
2
mV max
μV typ
fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV
TA = 25°C
−40°C to +105°C
Offset Drift vs. Temperature
μV/°C max
μV/°C typ
μV/V typ
mV max
mV max
mV typ
Offset Drift vs. VDD1
Gain Error3
−40°C to +85°C
>85°C to 105°C
fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV
1
Gain Error Drift vs. Temperature
Gain Error Drift vs. VDD1
ANALOG INPUT
23
110
μV/°C typ
μV/V typ
−40°C to +105°C
Input Voltage Range
Dynamic Input Current
DC Leakage Current
200
9
0.5
10
mV min/mV max For specified performance; full range 320 mV
μA max
μA max
pF typ
VIN+ = 400 mV, VIN− = 0 V
Input Capacitance
DYNAMIC SPECIFICATIONS
VIN+ = 5 kHz, 400 mV p-p sine
Signal-to-(Noise + Distortion) Ratio (SINAD)3 70
dB min
dB min
dB min
dB min
dB typ
dB min
dB min
dB typ
dB typ
Bits
−40°C to +85°C; fMCLK = 9 MHz to 20 MHz4
−40°C to +85°C; fMCLK = 5 MHz to <9 MHz
>85°C to 105°C
68
65
65
81
80
80
fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV
Signal-to-Noise Ratio (SNR)
−40°C to +105°C; 82 dB typ
fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV
fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV
Total Harmonic Distortion (THD)3
Peak Harmonic or Spurious Noise (SFDR)3 −92
Effective Number of Bits (ENOB)3
Isolation Transient Immunity3
−92
11.5
25
30
kV/μs min
kV/μs typ
LOGIC INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
0.8 × VDD2
0.2 × VDD2
0.5
V min
V max
μA max
pF max
5
Input Capacitance, CIN
10
Rev. D | Page 3 of 20
AD7401
Parameter
YVersion1, 2
Unit
Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
POWER REQUIREMENTS
VDD1
VDD2 − 0.1
0.4
V min
V max
IO = −200 μA
IO = +200 μA
4.5/5.25
V min/V max
V min/V max
mA max
mA max
mA max
VDD2
3/5.5
12
8
6
IDD1
IDD2
VDD1 = 5.25 V
VDD2 = 5.5 V
VDD2 = 3.3 V
7
4
1 Temperature range is −40°C to +85°C.
2 All voltages are relative to their respective ground.
3 See the Terminology section.
4 For fMCLK > 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, VDD1 = VDD2 = 5 V 5ꢀ, and TA = −40°C to +85°C.
5 Sample tested during initial release to ensure compliance.
6 See Figure 15.
7 See Figure 17.
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.±5 V, VDD± = ꢀ V to 5.5 V, TA = TMAX to TMIN, unless otherwise noted.1
Table 2.
Parameter
ꢀimit at TMIN, TMAX
Unit
Description
2, 3
fMCLKIN
20
5
25
15
MHz max
MHz min
ns max
ns min
ns min
ns min
Master clock input frequency
Master clock input frequency
Data access time after MCLK rising edge
Data hold time after MCLK rising edge
Master clock low time
4
t1
t2
4
t3
t4
0.4 × tMCLKIN
0.4 × tMCLKIN
Master clock high time
1 Sample tested during initial release to ensure compliance
2 Mark space ratio for clock input is 40/60 to 60/40 for fMCLKIN to 16 MHz and 48/52 to 52/48 for fMCLKIN > 16 MHz to 20 MHz.
3 VDD1 = VDD2 = 5 V 5ꢀ for fMCLKIN > 16 MHz to 20 MHz.
4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
25pF
200µA
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
t4
MCLKIN
MDAT
t1
t2
t3
Figure 3. Data Timing
Rev. D | Page 4 of 20
AD7401
INSUꢀATION AND SAFETY-REꢀATED SPECIFICATIONS
Table 3.
Parameter
Symbol Value
Unit
Conditions
Input-to-Output Momentary Withstand Voltage
Minimum External Air Gap (Clearance)
VISO
L(I01)
5000 min V rms
1-minute duration
Measured from input terminals to output
terminals, shortest distance through air
8.1 min
mm
Minimum External Tracking (Creepage)
L(I02)
7.46 min
mm
Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.017 min mm
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table I)
CTI
>175
IIIa
V
REGUꢀATORY INFORMATION
Table 4.
Uꢀ1
CSA
Approved under CSA Component
VDE2
Recognized under 1577
Certified according to DIN V VDE V 0884-10 (VDE V 0884-
10):2006-122
Component Recognition Program1 Acceptance Notice #5A
5000 V rms Isolation Voltage
Reinforced insulation per CSA
60950-1-03 and IEC 60950-1, 630 V
rms maximum working voltage
Reinforced insulation per DIN V VDE V 0884-10 (VDE V 0884-
10):2006-12, 891V peak
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL 1577, each AD7401 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 μA).
2 In accordance with DIN V VDE V 0884-10, each AD7401 is proof tested by applying an insulation test voltage ≥ 1671 V peak for 1 second (partial discharge detection
limit = 5 pC).
Rev. D | Page 5 of 20
AD7401
DIN V VDE V 0884-10 (VDE V 0884-10) INSUꢀATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 5.
Description
Symbol Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms
I–IV
For Rated Mains Voltage ≤ 450 V rms
I–II
For Rated Mains Voltage ≤ 600 V rms
I–II
CLIMATIC CLASSIFICATION
40/105/21
2
POLLUTION DEGREE (DIN VDE 0110, TABLE I)
MAXIMUM WORKING INSULATION VOLTAGE
INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100ꢀ Production Test, tm = 1 sec, Partial Discharge < 5 pC
INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A
After Environmental Test Subgroup 1
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/3
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec)
SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, ALSO SEE Figure 4)
Case Temperature
VIORM
891
V peak
V peak
V peak
V peak
V peak
VPR
VPR
1671
1426
1069
6000
VTR
TS
IS1
IS2
RS
150
265
335
>109
°C
Side 1 Current
Side 2 Current
mA
mA
Ω
INSULATION RESISTANCE AT TS, VIO = 500 V
350
300
250
SIDE #2
200
150
SIDE #1
100
50
0
0
50
100
150
200
CASE TEMPERATURE (°C)
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. D | Page 6 of 20
AD7401
ABSOLUTE MAXIMUM RATINGS
TA = ±5°C, unless otherwise noted. All voltages are relative to
their respective ground.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
Rating
VDD1 to GND1
VDD2 to GND2
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to VDD1 + 0.3 V
−0.3 V to VDD1 + 0.5 V
−0.3 V to VDD2 + 0.3 V
10 mA
−40°C to +105°C
−65°C to +150°C
150°C
Analog Input Voltage to GND1
Digital Input Voltage to GND2
Output Voltage to GND2
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
SOIC Package
Table 7. Maximum Continuous Working Voltage1
Parameter
Max Unit Constraint
AC Voltage,
Bipolar Waveform
AC Voltage,
Unipolar Waveform
565
891
891
VPK
VPK
V
50-year minimum lifetime
Maximum CSA/VDE
approved working voltage
Maximum CSA/VDE
DC Voltage
approved working voltage
θJA Thermal Impedance
θJC Thermal Impedance
Resistance (Input to Output), RI-O
89.2°C/W
55.6°C/W
1012 Ω
1 Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
2
Capacitance (Input to Output), CI-O
1.7 pF typ
Pb-Free Temperature , Soldering
ESD CAUTION
Reflow
ESD
260 (+0)°C
1.5 kV
1 Transient currents of up to 100 mA do not cause SCR to latch-up.
2 f = 1 MHz.
Rev. D | Page 7 of 20
AD7401
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
16 GND
15 NC
DD1
2
V
+
IN
IN
V
–
14 V
DD2
AD7401
TOP VIEW
(Not to Scale)
NC
NC
NC
/NC
13 MCLKIN
12 NC
11 MDAT
10 NC
V
DD1
GND
9
GND
2
1
NC = NO CONNECT
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
VDD1
VIN+
VIN−
Supply Voltage. 4.5 V to 5.25 V. This is the supply voltage for the isolated side of the AD7401 and is relative to GND1.
Positive Analog Input. Specified range of 200 mV.
Negative Analog Input. Normally connected to GND1.
No Connect.
4 to 6, 10, NC
12, 15
7
VDD1/NC
Supply Voltage. 4.5 V to 5.25 V. This is the supply voltage for the isolated side of the AD7401 and is relative to GND1.
No Connect (NC). If desired, Pin 7 may be allowed to float. It should not be tied to ground. The AD7401 will
operate normally provided that the supply voltage is applied to Pin 1.
8
9, 16
11
GND1
GND2
MDAT
Ground 1. This is the ground reference point for all circuitry on the isolated side.
Ground 2. This is the ground reference point for all circuitry on the nonisolated side.
Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are
clocked out on the rising edge of the MCLKIN input and valid on the following MCLKIN rising edge.
13
14
MCLKIN
VDD2
Master Clock Logic Input. 20 MHz maximum. The bit stream from the modulator is valid on the rising edge of MCLKIN.
Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2.
Rev. D | Page 8 of 20
AD7401
TYPICAL PERFORMANCE CHARACTERISTICS
TA = ±5°C, using a ±5 kHz brick wall filter, unless otherwise noted.
100
90
–90
–85
–80
–75
–70
–65
–60
–55
–50
V
= V = 5V
DD2
DD1
MCLKIN = 10MHz
80
MCLKIN = 16MHz
70
60
50
MCLKIN = 16MHz
MCLKIN = 5MHz
MCLKIN = 10MHz
40
30
20
200mV p-p SINE WAVE ON V
NO DECOUPLING
DD1
10
0
V
= V
= 5V
DD1
DD2
1MHz CUTOFF FILTER
0
100 200 300 400 500 600 700 800 900 1000
SUPPLY RIPPLE FREQUENCY (kHz)
0.17 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 0.31 0.32 0.33
± INPUT AMPLITUDE (V)
Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
Figure 9. SINAD vs. VIN
–90
0.4
V
= V = 5V
DD2
DD1
0.3
0.2
–85
–80
–75
–70
–65
–60
–55
–50
MCLKIN = 16MHz
0.1
0
MCLKIN = 10MHz
–0.1
–0.2
–0.3
–0.4
–0.5
MCLKIN = 5MHz
V
V
+ = –200mV TO +200mV
– = 0V
IN
IN
0
1k
2k
3k
4k
5k
6k
7k
8k
9k
10k
0
10k
20k
30k
40k
50k
60k
INPUT FREQUENCY (Hz)
CODE
Figure 7. SINAD vs. Analog Input Frequency
Figure 10. Typical DNL ( 200 mV Range)
20
0.8
0.6
0.4
0.2
0
4096 POINT FFT
fIN = 5kHz
V
V
+ = –200mV TO +200mV
– = 0V
IN
IN
0
–20
SINAD = 81.984dB
THD = –96.311dB
DECIMATION BY 256
–40
–60
–80
–100
–120
–140
–160
–180
–0.2
–0.4
0
5
10
15
20
25
30
0
10k
20k
30k
40k
50k
60k
FREQUENCY (kHz)
CODE
Figure 11. Typical INL ( 200 mV Range)
Figure 8. Typical FFT ( 200 mV Range)
Rev. D | Page 9 of 20
AD7401
250
200
150
100
50
0.0105
0.0100
0.0095
0.0090
0.0085
0.0080
0.0075
0.0070
V
= V = 5V
DD2
DD1
V
= V
DD2
= 4.5V
V
= V = 4.5V
DD2
MCLKIN = 16MHz
= +85°C
DD1
DD1
MCLKIN = 16MHz
MCLKIN = 10MHz
T
A
MCLKIN = 16MHz
= –40°C
MCLKIN = 16MHz
= +105°C
V
= V = 4.5V
V
DD1
= V = 5V
T
T
A
DD1
DD2
DD2
MCLKIN = 5MHz
A
MCLKIN = 5MHz
V
= V
= 5V
DD1
DD2
MCLKIN = 16MHz
MCLKIN = 10MHz
= –40°C
MCLKIN = 10MHz
T
T
= +105°C
A
A
0
–50
–100
–150
–200
–250
MCLKIN = 10MHz
= +85°C
T
A
V
= V
DD2
= 5.25V
V
= V = 5.25V
DD2
DD1
DD1
MCLKIN = 16MHz
MCLKIN = 10MHz
MCLKIN = 5MHz
= –40°C
V
= V = 5V
V
DD1
= V = 5.25V
DD1
DD2
DD2
MCLKIN = 5MHz
T
A
MCLKIN = 5MHz
= +85°C
MCLKIN = 5MHz
MCLKIN = 10MHz
0.0065
0.0060
T
T = +105°C
A
A
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105
TEMPERATURE (°C)
–0.33 –0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28 0.33
V
DC INPUT VOLTAGE (V)
IN
Figure 15. IDD1 vs. VIN at Various Temperatures
Figure 12. Offset Drift vs. Temperature for Various Supply Voltages
0.0070
0.0065
0.0060
0.0055
0.0050
0.0045
0.0040
0.0035
0.0030
0.0025
0.0020
200.5
V
T
= V = 5V
DD2
V
= V
DD2
= 4.5V
V
= V = 4.5V
DD2
DD1
= 25°C
DD1
DD1
MCLKIN = 16MHz
MCLKIN = 16MHz
MCLKIN = 10MHz
A
200.4
200.3
200.2
200.1
200.0
199.9
199.8
199.7
199.6
199.5
V
= V = 4.5V
V
DD1
= V = 5V
DD1
DD2
DD2
MCLKIN = 5MHz
MCLKIN = 5MHz
V
= V
= 5V
V
= V
= 5.25V
DD1
DD2
DD1
DD2
MCLKIN = 16MHz
MCLKIN = 10MHz
V
= V
= 5.25V
V
= V = 5.25V
DD1
DD2
DD1
DD2
MCLKIN = 16MHz
MCLKIN = 5MHz
MCLKIN = 10MHz
MCLKIN = 5MHz
V
= V
= 5V
DD1
DD2
MCLKIN = 10MHz
–0.225
–0.125
–0.025
0.075
0.175
0.275
–0.325
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105
TEMPERATURE (°C)
–0.275 –0.175
–0.075
0.025
0.125
0.225
0.325
V
DC INPUT VOLTAGE (V)
IN
Figure 13. Gain Error Drift vs. Temperature for Various Supply Voltages
Figure 16. IDD2 vs. VIN DC Input Voltage
0.0105
0.0070
0.0065
0.0060
0.0055
0.0050
0.0045
0.0040
0.0035
0.0030
0.0025
0.0020
V
= V = 5V
DD2
V
= V = 5V
DD2
DD1
DD1
= 25°C
T
A
0.0100
0.0095
0.0090
0.0085
0.0080
0.0075
0.0070
0.0065
MCLKIN = 16MHz
= +105°C
T
A
MCLKIN = 16MHz
MCLKIN = 16MHz
= –40°C
MCLKIN = 16MHz
= +85°C
T
T
A
A
MCLKIN = 10MHz
= –40°C
MCLKIN = 10MHz
T
T
= +105°C
A
A
MCLKIN = 10MHz
MCLKIN = 10MHz
= +85°C
T
A
MCLKIN = 5MHz
= –40°C
T
A
MCLKIN = 5MHz
MCLKIN = 5MHz
MCLKIN = 5MHz
= +85°C
T
= +105°C
T
A
A
–0.225
–0.125
–0.025
–0.075
0.075
0.175
0.225
0.275
–0.325
–0.33 –0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28 0.33
–0.275 –0.175
0.025
0.125
0.325
V
DC INPUT VOLTAGE (V)
V
IN
DC INPUT VOLTAGE (V)
IN
Figure 17. IDD2 vs. VIN at Various Temperatures
Figure 14. IDD1 vs. VIN DC Input Voltage
Rev. D | Page 10 of 20
AD7401
8
6
1.0
0.8
0.6
0.4
0.2
0
V
= V = 4.5V TO 5.25V
DD2
V
= V = 5V
DD2
DD1
DD1
50kHz BRICK WALL FILTER
MCLKIN = 16MHz
MCLKIN = 10MHz
4
2
MCLKIN = 5MHz
0
–2
–4
–6
–8
MCLKIN = 5MHz
MCLKIN = 10MHz
MCLKIN = 16MHz
V
DC INPUT (V)
V
– DC INPUT (V)
IN
IN
Figure 20. RMS Noise Voltage vs. VIN DC Input
Figure 18. IIN vs. VIN− DC Input
0
V
= V
DD2
=5V
DD1
–20
–40
–60
MCLKIN = 5MHz
MCLKIN = 10MHz
–80
MCLKIN = 16MHz
100 1000
–100
–120
0.1
1
10
RIPPLE FREQUENCY (kHz)
Figure 19. CMRR vs. Common-Mode Ripple Frequency
Rev. D | Page 11 of 20
AD7401
TERMINOLOGY
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7401, it is defined as
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
and the ideal 1 LSB change between any two adjacent codes in
the ADC.
V2± +V3± +V4± +V5± +V6
±
THD(dB) = ±0log
Integral Nonlinearity
V1
Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are specified negative
full-scale, −±00 mV (VIN+ − VIN−), Code 1±,±88 for the 16-bit
level, and specified positive full-scale, +±00 mV (VIN+ − VIN−),
Code 5ꢀ,±48 for the 16-bit level.
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/±, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Offset Error
Offset error is the deviation of the midscale code (Code ꢀ±,768
for the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V).
Gain Error
Gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (5ꢀ,±48 for the
16-bit level) from the ideal VIN+ − VIN− (+±00 mV) after the
offset error is adjusted out. Negative full-scale gain error is the
deviation of the specified negative full-scale code (1±,±88 for
the 16-bit level) from the ideal VIN+ − VIN− (−±00 mV) after the
offset error is adjusted out. Gain error includes reference error.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
±±00 mV frequency, f, to the power of a ±00 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency fS, expressed as
CMRR (dB) = 10log(Pf/PfS)
Signal-to-(Noise + Distortion) Ratio
where:
This ratio is the measured ratio of signal-to-(noise + distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/±), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
converter with a sine wave input is given by
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not converter linearity. PSRR is the maximum change in the
specified full-scale (±±00 mV) transition point due to a change
in power supply voltage from the nominal value (see Figure 6).
Signal-to-(Noise + Distortion) = (6.0± N + 1.76) dB
Isolation Transient Immunity
The isolation transient immunity specifies the rate of rise/fall of
a transient pulse applied across the isolation boundary beyond
which clock or data is corrupted. (It was tested using a transient
pulse frequency of 100 kHz.)
Therefore, for a 1±-bit converter, this is 74 dB.
Effective Number of Bits (ENOB)
The ENOB is defined by
ENOB = (SINAD − 1.76)/6.0±
Rev. D | Page 12 of 20
AD7401
THEORY OF OPERATION
A differential input of ꢀ±0 mV results in a stream of, ideally, all
1s. This is the absolute full-scale range of the AD7401, while
±00 mV is the specified full-scale range, as shown in Table 9.
CIRCUIT INFORMATION
The AD7401 isolated Σ-Δ modulator converts an analog input
signal into a high speed (±0 MHz maximum), single-bit data
stream; the time average of the modulator’s single-bit data is
directly proportional to the input signal. Figure ±ꢀ shows a
typical application circuit where the AD7401 is used to provide
isolation between the analog input, a current sensing resistor,
and the digital output, which is then processed by a digital filter
to provide an N-bit word.
Table 9. Analog Input Range
Analog Input
Voltage Input
+640 mV
+320 mV
+200 mV
0 mV
Full-Scale Range
Positive Full-Scale
Positive Specified Input Range
Zero
Negative Specified Input Range
Negative Full-Scale
−200 mV
−320 mV
ANAꢀOG INPUT
The differential analog input of the AD7401 is implemented
with a switched capacitor circuit. This circuit implements a
second-order modulator stage that digitizes the input signal
into a 1-bit output stream. The sample clock (MCLKIN)
provides the clock signal for the conversion process as well as
the output data-framing clock. This clock source is external on
the AD7401. The analog input signal is continuously sampled
by the modulator and compared to an internal voltage reference.
A digital stream that accurately represents the analog input over
time appears at the output of the converter (see Figure ±1).
To reconstruct the original information, this output needs to be
digitally filtered and decimated. A Sincꢀ filter is recommended
because this is one order higher than that of the AD7401 modu-
lator. If a ±56 decimation rate is used, the resulting 16-bit word
rate is 6±.5 kHz, assuming a 16 MHz external clock frequency.
Figure ±± shows the transfer function of the AD7401 relative to
the 16-bit output.
65535
MODULATOR OUTPUT
+FS ANALOG INPUT
53248
SPECIFIED RANGE
–FS ANALOG INPUT
ANALOG INPUT
Figure 21. Analog Input vs. Modulator Output
12288
A differential signal of 0 V results (ideally) in a stream of 1s and
0s at the MDAT output pin. This output is high 50% of the time
and low 50% of the time. A differential input of ±00 mV pro-
duces a stream of 1s and 0s that are high 81.±5% of the time. A
differential input of −±00 mV produces a stream of 1s and 0s
that are high 18.75% of the time.
0
–320mV
–200mV
ANALOG INPUT
+200mV +320mV
Figure 22. Filtered and Decimated 16-Bit Transfer Characteristic
ISOLATED
5V
NONISOLATED
5V/3V
AD7401
V
V
V
DD
DD1
DD2
3
SINC FILTER
Σ-∆
MOD/
CS
V
V
+
–
MDAT
MDAT
IN
ENCODER
DECODER
ENCODER
+
SCLK
INPUT
CURRENT
MCLKIN
MCLK
IN
SDAT
R
SHUNT
DECODER
GND
GND
GND
1
2
Figure 23. Typical Application Circuit
Rev. D | Page 13 of 20
AD7401
When a capacitive load is switched onto the output of an op
amp, the amplitude momentarily drops. The op amp tries to
correct the situation and, in the process, hits its slew rate limit.
This nonlinear response, which can cause excessive ringing, can
lead to distortion. To remedy the situation, a low-pass RC filter
can be connected between the amplifier and the input to the
AD7401. The external capacitor at each input aids in supplying
the current spikes created during the sampling process, and the
resistor isolates the op amp from the transient nature of the load.
DIFFERENTIAꢀ INPUTS
The analog input to the modulator is a switched capacitor
design. The analog signal is converted into charge by highly
linear sampling capacitors. A simplified equivalent circuit
diagram of the analog input is shown in Figure ±4. A signal
source driving the analog input must be able to provide the
charge onto the sampling capacitors every half MCLKIN cycle and
settle to the required accuracy within the next half cycle.
φA
The recommended circuit configuration for driving the differ-
ential inputs to achieve best performance is shown in Figure ±5. A
capacitor between the two input pins sources or sinks charge to
allow most of the charge that is needed by one input to be
effectively supplied by the other input. The series resistor again
isolates any op amp from the current spikes created during the
sampling process. Recommended values for the resistors and
capacitor are ±± Ω and 47 pF, respectively.
1kΩ
φB
V
+
IN
2pF
2pF
φA
φB
1kΩ
V
–
IN
φA φB φA φB
MCLKIN
Figure 24. Analog Input Equivalent Circuit
R
V
+
IN
Because the AD7401 samples the differential voltage across its
analog inputs, low noise performance is attained with an input
circuit that provides low common-mode noise at each input.
The amplifiers used to drive the analog inputs play a critical role
in attaining the high performance available from the AD7401.
C
AD7401
R
V
–
IN
Figure 25. Differential Input RC Network
Rev. D | Page 14 of 20
AD7401
DIGITAꢀ FIꢀTER
MCLKIN
A Sincꢀ filter is recommended for use with the AD7401. This
filter can be implemented on an FPGA or possibly a DSP. The
following Verilog code provides an example of a Sincꢀ filter
implementation on a Xylinx® Spartan-II ±.5 V FPGA. This code
can possibly be compiled for another FPGA, such as an Altera®
device. Note that the data is read on the negative clock edge in
this case, although it can be read on the positive edge if preferred.
Figure ±9 shows the effect of using different decimation rates
with various filter types.
ACC1+
+
ACC2+
+
ACC3+
IP_DATA1
Z
Z
Z
+
Figure 26. Accumulator
Z = one sample delay
MCLKIN = modulators conversion bit rate
*/
always @ (posedge mclk1 or posedge reset)
if (reset)
begin
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
/*initialize acc registers on reset*/
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
input mclk1;
input reset;
input mdata1;
filtered*/
/*used to clk filter*/
/*used to reset filter*/
/*ip data to be
end
else
begin
output [15:0] DATA;
/*filtered op*/
/*perform accumulation process*/
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
integer location;
integer info_file;
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [15:0]
reg [7:0]
ip_data1;
acc1;
/*DECIMATION STAGE (MCLKIN/ WORD_CLK)
*/
acc2;
always @ (negedge mclk1 or posedge reset)
if (reset)
word_count <= 0;
else
acc3;
acc3_d1;
acc3_d2;
diff1;
word_count <= word_count + 1;
always @ (word_count)
diff2;
word_clk <= word_count[7];
diff3;
/*DIFFERENTIATOR (including decimation stage)
diff1_d;
diff2_d;
DATA;
Perform the differentiation stage (FIR) at a
lower speed.
DIFF1
DIFF2
DIFF3
+
–
+
–
+
–
ACC3
word_count;
–1
–1
–1
Z
Z
Z
reg word_clk;
reg init;
WORD_CLK
Figure 27. Differentiator
/*Perform the Sinc ACTION*/
Z = one sample delay
WORD_CLK = output word rate
*/
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0;
to a -1 for 2's comp */
else
/* change from a 0
ip_data1 <= 1;
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
Rev. D | Page 15 of 20
AD7401
always @ (posedge word_clk or posedge reset)
if(reset)
DATA[9] <= diff3[17];
DATA[8] <= diff3[16];
DATA[7] <= diff3[15];
DATA[6] <= diff3[14];
DATA[5] <= diff3[13];
DATA[4] <= diff3[12];
DATA[3] <= diff3[11];
DATA[2] <= diff3[10];
DATA[1] <= diff3[9];
DATA[0] <= diff3[8];
begin
acc3_d2 <= 0;
diff1_d <= 0;
diff2_d <= 0;
diff1 <= 0;
diff2 <= 0;
diff3 <= 0;
end
end
endmodule
else
90
3
2
SINC
SINC
begin
80
70
60
50
40
30
20
10
0
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end
1
SINC
/* Clock the Sinc output into an output
register
WORD_CLK
DIFF3
DATA
1
10
100
DECIMATION RATE
1k
Figure 28. Clocking Sinc Output into an Output Register
WORD_CLK = output word rate
*/
Figure 29. SNR vs. Decimation Rate for Different Filter Types
Figure ±9 shows a plot of SNR performance vs. decimation rate
with different filter types. Note that, for a given bandwidth
requirement, a higher MCLKIN frequency can allow higher
decimation rates to be used, resulting in higher SNR performance.
always @ (posedge word_clk)
begin
DATA[15] <= diff3[23];
DATA[14] <= diff3[22];
DATA[13] <= diff3[21];
DATA[12] <= diff3[20];
DATA[11] <= diff3[19];
DATA[10] <= diff3[18];
Rev. D | Page 16 of 20
AD7401
APPLICATIONS INFORMATION
GROUNDING AND ꢀAYOUT
These tests subjected populations of devices to continuous
cross-isolation voltages. To accelerate the occurrence of failures,
the selected test voltages were values exceeding those of normal
use. The time-to-failure values of these units were recorded and
used to calculate acceleration factors. These factors were then
used to calculate the time to failure under normal operating
conditions. The values shown in Table 7 are the lesser of the
following two values:
Supply decoupling with a value of 100 nF is strongly recom-
mended on both VDD1 and VDD±. Decoupling on one or both
VDD1 pins does not affect performance significantly. In applications
involving high common-mode transients, care should be taken
to ensure that board coupling across the isolation barrier is
minimized. Furthermore, the board layout should be designed
so that any coupling that occurs equally affects all pins on a
given component side. Failure to ensure this may cause voltage
differentials between pins to exceed the absolute maximum
ratings of the device, thereby leading to latch-up or permanent
damage. Any decoupling used should be placed as close to the
supply pins as possible.
•
The value that ensures at least a 50-year lifetime of
continuous use
•
The maximum CSA/VDE approved working voltage
It should also be noted that the lifetime of the AD7401 varies
according to the waveform type imposed across the isolation
barrier. The iCoupler insulation structure is stressed differently
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure ꢀ0, Figure ꢀ1, and Figure ꢀ± illustrate the different
isolation voltage waveforms.
Series resistance in the analog inputs should be minimized to
avoid any distortion effects, especially at high temperatures. If
possible, equalize the source impedance on each analog input to
minimize offset. Beware of mismatch and thermocouple effects
on the analog input PCB tracks to reduce offset drift.
RATED PEAK VOLTAGE
EVAꢀUATING THE AD7401 PERFORMANCE
0V
A simple standalone AD7401 evaluation board is available with
split ground planes and a board split beneath the AD7401
package to ensure isolation. This board allows access to each
pin on the device for evaluation purposes. External supplies and
all other circuitry (such as a digital filter) must be provided by
the user.
Figure 30. Bipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 31. Unipolar AC Waveform
INSUꢀATION ꢀIFETIME
RATED PEAK VOLTAGE
All insulation structures, subjected to sufficient time and/or
voltage, are vulnerable to breakdown. In addition to the testing
performed by the regulatory agencies, Analog Devices has
carried out an extensive set of evaluations to determine the
lifetime of the insulation structure within the AD7401.
0V
Figure 32. DC Waveform
Rev. D | Page 17 of 20
AD7401
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.
25 (0.0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 33. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
RW-16
RW-16
RW-16
RW-16
AD7401YRW
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
Evaluation Board
AD7401YRW-REEL
AD7401YRW-REEL7
AD7401YRWZ
AD7401YRWZ-REEL
AD7401YRWZ-REEL7
EVAL-AD7401EDZ
EVAL-CED1Z
RW-16
RW-16
Development Board
1 Z = RoHS Compliant Part.
Rev. D | Page 18 of 20
AD7401
NOTES
Rev. D | Page 19 of 20
AD7401
NOTES
©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05851-0-7/11(D)
Rev. D | Page 20 of 20
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