AD7606C-18BSTZ-RL [ADI]
8-Channel DAS with 18-Bit, 1 MSPS Bipolar Input, Simultaneous Sampling ADC;
| 型号： | AD7606C-18BSTZ-RL |
| 厂家： | 
ADI |
| 描述： | 8-Channel DAS with 18-Bit, 1 MSPS Bipolar Input, Simultaneous Sampling ADC |
| 文件： | 总75页 (文件大小：1488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Channel DAS with 18-Bit, 1 MSPS Bipolar
Input, Simultaneous Sampling ADC
AD7606C-18
Data Sheet
FEATURES
CALIBRATION AND DIAGNOSTICS
18-bit ADC with 1 MSPS on all channels
Per channel system phase, offset, and gain calibration
Input buffer with 1 MΩ minimum analog input impedance (RIN)
Single 5 V analog supply and 1.71 V to 5.25 V VDRIVE
Per channel selectable analog input ranges
Bipolar single-ended: 12.5 V, 10 V, 6.25 V, 5 V, 2.5 V
Unipolar single-ended: 0 V to 12.5 V, 0 V to 10 V, 0 V to 5 V
Bipolar differential: 20 V, 12.5 V, 10 V, 5 V
Two bandwidth options: 25 kHz and 220 kHz, per channel
Flexible digital filter, oversampling ratio up to 256
−40°C to +125°C operating range
21 V input clamp protection with 6 kV ESD
Pin to pin compatible to the AD7606B, AD7608, and AD7609
Performance
93 dB SNR
102 dB SNR, oversampling by 32
Analog input open circuit detection feature
Self diagnostics and monitoring features
CRC error checking on read and write data and registers
APPLICATIONS
Power line monitoring
Protective relays
Multiphase motor control
Instrumentation and control systems
Data acquisition systems
COMPANION PRODUCTS
Voltage References: ADR4525, LT6657, LTC6655
Digital Isolators: ADuM142E, ADuM6422A, ADuM5020,
ADuM5028
AD7606x Family Software Model
Additional companion products on the AD7606C-18 product
page
−100 dB THD
TUE = 0.05% of FSR maximum, external reference
1 ppm/°C positive and negative FS error drift
3 ppm/°C reference temperature coefficient
FUNCTIONAL BLOCK DIAGRAM
5V
5V
1.71V TO 5.25V
1µF
100nF
100nF
100nF
1µF
V
AV
AV
CC
REGCAP
REGCAP
DRIVE
CC
ALDO
LPF
DLDO
1MΩ
1MΩ
V1+
V1–
CLAMP
CLAMP
CONVST
CLK OSC
PGA
PGA
SAR
SAR
RESET
RANGE
CONTROL
INPUTS
OS0 TO OS2
1MΩ
1MΩ
V8+
V8–
BUSY
CLAMP
CLAMP
PROGRAMMABLE
DIGITAL FILTER
FRSTDATA
LPF
OPTIONAL
RC FILTER
SERIAL
D
A TO D H
OUT OUT
ADC, PGA, AND
CHANNEL
SDI
REFCAPA
SCLK
CS
CONFIGURATION
PARALLEL/
10µF
+
SERIAL
INTERFACE
OPTIONAL EXTERNAL
REFERENCE
CC
PARALLEL
DB0 TO DB17
GAIN, OFFSET
AND PHASE
CALIBRATION
REFCAPB
AV
RD
INTERNAL
REFERENCE
REFIN/REFOUT
+2.5V
WR
V
V
OUT
IN
+
100nF
2.5V
REF
DIAGNOSTICS
AND SENSOR
DISCONNECT
PAR/SER SEL
ADR4525
GND
1µF
0.1µF
REFSELECT
REFGND
AD7606C-18
AGND
Figure 1.
Rev. 0
Document Feedback
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AD7606C-18
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Padding Oversampling.............................................................. 37
External Oversampling Clock .................................................. 37
System Calibration Features ......................................................... 38
System Phase Calibration.......................................................... 38
System Gain Calibration ........................................................... 38
System Offset Calibration ......................................................... 38
Analog Input Open Circuit Detection .................................... 39
Digital Interface.............................................................................. 41
Parallel Interface......................................................................... 42
Serial Interface............................................................................ 45
Diagnostics...................................................................................... 50
Reset Detection........................................................................... 50
Digital Error................................................................................ 50
Diagnostics Multiplexer ............................................................ 53
Typical Connection Diagram ....................................................... 54
Applications Information ............................................................. 56
Layout Guidelines ...................................................................... 56
Register Summary .......................................................................... 58
Register Details ............................................................................... 59
Outline Dimensions....................................................................... 75
Ordering Guide .......................................................................... 75
Calibration and Diagnostics ........................................................... 1
Applications ...................................................................................... 1
Companion Products....................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications .................................................................................... 4
Timing Specifications .................................................................. 7
Absolute Maximum Ratings ......................................................... 11
Thermal Resistance.................................................................... 11
Electrostatic Discharge (ESD) Ratings.................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions .......................... 12
Typical Performance Characteristics........................................... 16
Terminology.................................................................................... 27
Theory of Operation ...................................................................... 29
Analog Front-End ...................................................................... 29
SAR ADC..................................................................................... 30
Reference ..................................................................................... 32
Operation Modes........................................................................ 32
Digital Filter .................................................................................... 35
REVISION HISTORY
10/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 75
Data Sheet
AD7606C-18
GENERAL DESCRIPTION
The AD7606C-18 is an 18-bit, simultaneous sampling, analog-
to-digital data acquisition system (DAS) with eight channels.
Each channel contains analog input clamp protection, a
programmable gain amplifier (PGA), a low-pass filter (LPF),
and an 18-bit successive approximation register (SAR) analog-
to-digital converter (ADC). The AD7606C-18 also contains a
flexible digital filter, a low drift, 2.5 V precision reference, a
reference buffer to drive the ADC, and flexible parallel and
serial interfaces.
throughput rates, the AD7606C-18 flexible digital filter can be
used to improve noise performance.
In hardware mode, the AD7606C-18 is fully compatible with
the AD7608 and AD7609. In software mode, the following
advanced features are available:
•
Analog input range selectable per channel with added
ranges available
•
•
High bandwidth mode (220 kHz) selectable per channel
Additional oversampling options with an oversampling ratio
up to 256
The AD7606C-18 operates from a single 5 V supply and
accommodates the following input ranges when sampling at
throughput rates of 1 MSPS for all channels:
•
System gain, system offset, and system phase calibration,
per channel
•
•
•
Bipolar single-ended: 12.5 V, 10 V, 6.25 V, 5 V, and
2.5 V
Unipolar single-ended: 0 V to 12.5 V, 0 V to 10 V, and 0 V
to 5 V
Bipolar differential: 20 V, 12.5 V, 10 V, and 5 V
•
•
•
Analog input open circuit detector
Diagnostic multiplexer
Monitoring functions (serial peripheral interface (SPI)
invalid read and write, cyclic redundancy check (CRC),
busy stuck monitor, and reset detection)
The input clamp protection tolerates voltages up to 21 V. The
single supply operation, on-chip filtering, and high input
impedance eliminate the need for external driver op amps,
which require bipolar supplies. For applications with lower
Note that throughout this data sheet, multifunction pins, such
RD
name or by a single function of the pin, for example, the SCLK pin,
when only that function is relevant.
as the
/SCLK pin, are referred to either by the entire pin
Table 1. Bipolar Input, Simultaneous Sampling, Pin to Pin Compatible Family of Devices
Input Type
Resolution (Bits)
RIN1 = 1 MΩ, 200 kSPS RIN = 5 MΩ, 800 kSPS
RIN = 1 MΩ, 1 MSPS
AD7606C-182
Number of Channels
Single-Ended
18
16
AD7608
8
8
6
4
8
8
AD7606
AD7606-6
AD7606-4
AD7607
AD7609
AD7606B2
14
18
True Differential
AD7606C-182
1 RIN is input impedance.
2 This state-of-the-art device is recommended for newer designs as an alternative to the AD7606, AD7608, and AD7609.
Rev. 0 | Page 3 of 75
AD7606C-18
Data Sheet
SPECIFICATIONS
Voltage reference (VREF) = 2.5 V external and internal, analog supply voltage (AVCC) = 4.75 V to 5.25 V, logic supply voltage (VDRIVE) =
1.71 V to 5.25 V, sample frequency (fSAMPLE) = 1 MSPS, TA = −40°C to +125°C, and all input voltage ranges, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Input frequency (fIN) = 1 kHz sine wave, unless
otherwise noted
Signal-to-Noise Ratio (SNR)
Low Bandwidth Mode
±±0 V bipolar differential range
±±0 V bipolar differential range, oversampling by 3±,
fIN = 50 Hz
91
93
10±
dB
dB
±1±.5 V bipolar differential range
±10 V bipolar differential range
±5 V bipolar differential range
90
90
89
90
90.5
89
89
86.5
88.5
88
9±
91.5
91
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
±1±.5 V bipolar single-ended range
±10 V bipolar single-ended range
±6.±5 V bipolar single-ended range
±5 V bipolar single-ended range
±±.5 V bipolar single-ended range
0 V to 1±.5 V unipolar single-ended range
0 V to 10 V unipolar single-ended range
0 V to 5 V unipolar single-ended range
±±0 V bipolar differential range
9±
9±.5
91.5
91
88
90
90
86.5
89
87.5
87
83.5
87.5
87
84.5
High Bandwidth Mode
±1±.5 V bipolar differential range
±10 V bipolar differential range
±5 V bipolar differential range
±1±.5 V bipolar single-ended range
±10 V bipolar single-ended range
±6.±5 V bipolar single-ended range
±5 V bipolar single-ended range
±±.5 V bipolar single-ended range
0 V to 1±.5 V unipolar single-ended range
0 V to 10 V unipolar single-ended range
0 V to 5 V unipolar single-ended range
84.5
83.5
8±
83
8±
80
Total Harmonic Distortion (THD)
Unipolar ranges
All other ranges
−97
−100 −95
−105
−110
80
dB
dB
dB
dB
μs
Spurious-Free Dynamic Range (SFDR)
Channel to Channel Isolation
Full-Scale (FS) Step Settling Time
fIN on unselected channels up to ±00 kHz
0.01% of FS, low bandwidth mode
0.01% of FS, high bandwidth mode
15
μs
ANALOG INPUT FILTER
−3 dB Full Power Bandwidth
Low bandwidth mode
High bandwidth mode
High bandwidth mode, ±.5 V bipolar, 0 V to 5 V unipolar
Low bandwidth mode
High bandwidth mode
±5
±±0
150
3.9
±5
±0
8
kHz
kHz
kHz
kHz
kHz
kHz
µs
−0.1dB Full Power Bandwidth
High bandwidth mode, ±.5 V bipolar, 0 V to 5 V unipolar
Low bandwidth mode
Phase Delay
High bandwidth mode
±
µs
Phase Delay Matching
Low bandwidth mode
High bandwidth mode
150
±0
ns
ns
Rev. 0 | Page 4 of 75
Data Sheet
AD7606C-18
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
High bandwidth mode, ±2.5 V range, 0 V to 5 V unipolar
30
ns
DC ACCURACY
Resolution
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
No missing codes
18
Bits
±0.5
±2
±±
±0.99
±7
LSB1
LSB1
LSB
Bipolar input ranges
Unipolar input ranges
Total Unadjusted Error (TUE)2
External reference
External reference, ±2.5 V range
±25
±25
±130
±180
LSB
LSB
Bipolar Ranges
Positive and Negative FS Error3
Positive and Negative FS Error
Drift
±20
±1
±120
±5
LSB
ppm/°C
Positive and Negative FS Error
Matching
15
60
LSB
Bipolar Zero Code Error
2.5 V range
All other input ranges
±10
±10
±0.2
20
±160
±80
±2
LSB1
LSB1
Bipolar Zero Code Error Drift
Bipolar Zero Code Error Matching
Unipolar Ranges
ppm/°C
LSB1
90
FS Error
FS Error Drift
FS Error Matching
±±0
±1
20
±1±0
±3
60
LSB
ppm/°C
LSB
Zero Scale Error
±±0
±1
20
±120
±3
60
LSB
ppm/°C
LSB
Zero Scale Error Drift
Zero Scale Error Matching
ANALOG INPUT
Input Voltage (VIN) Ranges
VIN = Vx+ − Vx−
±20 V bipolar differential range
±12.5 V bipolar differential range
±10 V bipolar differential range
±5 V bipolar differential range
±12.5 V bipolar single-ended range
±10 V bipolar single-ended range
±6.25 V bipolar single-ended range
±5 V bipolar single-ended range
±2.5 V bipolar single-ended range
0 V to 12.5 V unipolar single-ended range
0 V to 10 V unipolar single-ended range
0 V to 5 V unipolar single-ended range
Vx− − AGND
−20
−12.5
−10
−5
−12.5
−10
−6.25
−5
+20
+12.5
+10
+5
+12.5
+10
+6.25
+5
V
V
V
V
V
V
V
V
V
V
V
V
−2.5
0
0
+2.5
12.5
10
0
5
Absolute Voltage Negative Input
±12.5 V bipolar single-ended range
±10 V bipolar single-ended range
±6.25 V bipolar single-ended range
±5 V bipolar single-ended range
±2.5 V bipolar single-ended range
0 V to 12.5 V unipolar single-ended range
0 V to 10 V unipolar single-ended range
0 V to 5 V unipolar single-ended range
±20 V bipolar differential range
±12.5 V bipolar differential range
±10 V bipolar differential range
−1
+1.6
+1.9
+2.5
+2.7
+3
+1.2
+1.7
+±
V
V
V
V
V
V
V
V
V
V
V
V
−0.6
−0.±
−0.1
−0.05
−6.5
−±.9
−2.3
−10
−7.8
−6
Common-Mode Input Range
+10
+7.8
+7
±5 V bipolar differential range
−3
+5
Rev. 0 | Page 5 of 75
AD7606C-18
Data Sheet
Parameter
Input Impedance (RIN)4
Test Conditions/Comments
Min
Typ
Max
Unit
MΩ
1
1.2
Analog Input Current
(VIN − 2)/RIN
µA
Input Capacitance (CIN)5
Input Impedance Drift
REFERENCE INPUT AND OUTPUT
Reference Input Voltage
DC Leakage Current
5
1
pF
ppm/°C
25
REF SELECT = 0, external reference
2.495
2.5
2.505
0.12
V
µA
Input Capacitance (CIN)
Reference Output Voltage
Reference Temperature Coefficient
Reference Voltage to the ADC
LOGIC INPUTS
7.5
2.5
3
pF
V
ppm/°C
V
REF SELSECT = 1, internal reference, TA = 25°C
REFCAPA (Pin 44) and REFCAPB (Pin 45)
2.497
2.503
15
4.41
4.39
Input High Voltage (VINH
Input Low Voltage (VINL)
Input Current (IIN)
Input Capacitance (CIN)
LOGIC OUTPUTS
)
0.7 × VDRIVE
V
V
µA
pF
0.2 × VDRIVE
1
5
Output High Voltage (VOH)
Output Low Voltage (VOL)
Floating State Leakage Current
Output Capacitance5
Output Coding Bipolar Ranges
Output Coding Unipolar Ranges
CONVERSION RATE
Conversion Time
Source current (ISOURCE) = 100 µA
Sink current (ISINK) = 100 µA
VDRIVE − 0.2
V
V
µA
pF
0.2
20
1
5
Twos complement
Straight binary
See Table 3
Per channel
550
450
ns
ns
kSPS
Acquisition Time
Throughput Rate
1000
POWER REQUIREMENTS
AVCC
VDRIVE
4.75
1.71
5
5.25
5.25
V
V
AVCC Current (IAVCC
)
Normal Mode (Static)
Normal Mode (Operational)
9
11
50
10
6
mA
mA
mA
mA
µA
fSAMPLE = 1 MSPS
fSAMPLE = 10 kSPS
45
8.5
5
Standby
Shutdown Mode
0.5
3
VDRIVE Current (IVDRIVE
)
Normal Mode (Static)
Normal Mode (Operational)
2.8
1.8
21
2.5
0.5
5
µA
mA
µA
µA
µA
fSAMPLE = 1 MSPS
fSAMPLE = 10 kSPS
1.9
24
4
Standby
Shutdown Mode
1.5
Power Dissipation
Normal Mode (Static)
Normal Mode (Operational)
47
245
45
26
5
58
272
52
32
24
mW
mW
mW
mW
µW
fSAMPLE = 1 MSPS
fSAMPLE = 10 kSPS
Standby
Shutdown Mode
1 LSB means least significant bit. With a 2.5 V input range, 1 LSB = 76.293 µV. With a 5 V input range, 1 LSB = 152.58 µV. With a 10 V input range, 1 LSB = 305.175 µV.
2 TUE (% FSR) = TUE (LSB)/218 × 100. For example, 130 LSBs = 0.05 % of FSR.
3 These specifications include the full temperature range variation and contribution from the reference buffer.
4 Input impedance variation is factory trimmed and accounted for in the System Gain Calibration section.
5 Not production tested. Sample tested during initial release to ensure compliance.
Rev. 0 | Page 6 of 75
Data Sheet
AD7606C-18
TIMING SPECIFICATIONS
Universal Timing Specifications
AVCC = 4.75 V to 5.25 V, VDRIVE = 1.71 V to 5.25 V, VREF = 2.5 V external reference and internal reference, and TA = −40°C to +125°C,
unless otherwise noted. Interface timing tested using a load capacitance of 20 pF, dependent on VDRIVE and load capacitance for the serial
interface.
Table 3.
Parameter
tCYCLE
Min
1
Typ Max Unit Description
µs
ns
ns
ns
ns
Minimum time between consecutive CONVST rising edges (excluding oversampling modes)1
tLP_CNV
10
10
CONVST low pulse width
tHP_CNV
CONVST high pulse width
tD_CNV_BSY
tS_BSY
22
25
CONVST high to BUSY high delay time
0
Minimum time from BUSY falling edge to RD falling edge setup time (in parallel interface) or
to MSB being available on the DOUTx line (in serial interface)
tD_BSY
ns
Maximum time between last RD falling edge (in parallel interface) or last LSB being clocked out
(serial interface) and the following BUSY falling edge, read during conversion
tACQ
0.35
0.5
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
Acquisition time
tCONV
0.65
1.75
3.8
Conversion time, no oversampling
Oversampling by 2
1.7
3.6
Oversampling by 4
7.6
7.85
16
Oversampling by 8
15.5
31.0
62.75
126
252
Oversampling by 16
Oversampling by 32
Oversampling by 64
Oversampling by 128
Oversampling by 256
32.5
65.0
130
256
tRESET
Partial
Reset
55
2000 ns
Partial RESET high pulse width
Full Reset
tDEVICE_SETUP
Partial
Reset
3200
ns
µs
ns
Full RESET high pulse width
Time between RESET falling edge and first CONVST rising edge
50
Full Reset
tWAKE-UP
Standby
Shutdown 10
tPOWER-UP 10
274
µs
Wake-up time after standby and shutdown mode (see Figure 86)
Time between stable AVCC and VDRIVE and assert of RESET
1
µs
ms
ms
1 Applies to serial mode when all eight DOUTx lines are selected.
Rev. 0 | Page 7 of 75
AD7606C-18
Data Sheet
Universal Timing Diagram
AV
CC
DRIVE
V
tPOWER-UP
tRESET
RESET
tCYCLE
tHP_CNV
tDEVICE_SETUP
tLP_CNV
tACQ
CONVST
BUSY
tCONV
tD_CNV_BSY
tS_BSY
tD_BSY
D
x
OUT
DBx
Figure 2. Universal Timing Diagram
Parallel Mode Timing Specifications
Table 4.
Parameter
Min
Typ
Max
Unit
Description
tS_
0
ns
CS falling edge to RD falling edge setup time
RD rising edge to CS rising edge hold time
RD high pulse width
_
CS RD
tH_
0
ns
ns
ns
ns
ns
_
RD CS
tHP_
10
10
10
RD
tLP_
RD low pulse width
RD
tHP_
CS high pulse width
CS
tD_
35
Delay from CS until DBx three-state disabled
Data access time after falling edge of RD
_DB
CS
tD_
_DB
RD
30
25
ns
ns
ns
VDRIVE > 2.7 V
VDRIVE < 2.7 V
Data hold time after falling edge of RD
tH_
12
30
_DB
RD
tDHZ_
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS rising edge to DBx high impedance
RD falling edge to next RD falling edge
Delay from CS falling edge until FRSTDATA three-state disabled
Delay from RD falling edge until FRSTDATA high
Delay from RD falling edge until FRSTDATA low
Delay from CS rising edge until FRSTDATA three-state enabled
CS to WR setup time
_DB
CS
tCYC_
RD
tD_
tD_
tD_
20
30
30
25
_FD
CS
RD
RD
_FDH
_FDL
tDHZ_
_FD
CS
tS_
0
_
CS WR
tHP_
2
WR high pulse width
WR
WR
tLP_
tH_
35
0
WR low pulse width
WR hold time
_
WR CS
tS_DB_
5
Configuration data to WR setup time
Configuration data to WR hold time
WR
tH_
5
_DB
WR
tCYC_
180
Configuration data settle time, WR rising edge to next WR rising edge
WR
Rev. 0 | Page 8 of 75
Data Sheet
AD7606C-18
Parallel Mode Timing Diagrams
CS
tS_CS_RD
tHP_RD
tH_RD_CS
tLP_RD
RD
tD_RD_DB
tCYC_RD
tH_RD_DB
tH_CS_DB
tDHZ_CS_DB
tD_CS_DB
ADC DATA
ADC DATA
ADC DATA
ADC DATA
ADC DATA
ADC DATA
ADC DATA ADC DATA
DB0 TO DB17
tD_CS_FD
x
tD_RD_FDL
tD_RD_FDH
tDHZ_CS_F
D
FRSTDATA
CS
RD
Pulses
Figure 3. Parallel Mode Read, Separate and
tCYC_RD
tHP_CS
CS AND RD
tLP_RD
tH_CS_DB
tDHZ_CS_DB
tD_RD_DB
DB0 TO DB17
ADC DATA
ADC DATA
ADC DATA
ADC DATA
ADC DATA
ADC DATA
ADC DATA ADC DATA
tD_CS_FD
tDHZ_CS_FD
tD_RD_FDL
FRSTDATA
CS
RD
Pulses
Figure 4. Parallel Mode Read, Linked and
CS
tHP_WR
tH_WR_CS
tS_CS_WR
tCYC_WR
WR
tLP_WR
tS_DB_WR
tH_WR_DB
DB0 TO DB17
Figure 5. Parallel Mode Write Operation
Serial Mode Timing Specifications
Table 5.
Parameter Min
Typ Max Unit Description
fSCLK
SCLK frequency, fSCLK = 1/tSCLK
60
40
MHz VDRIVE > 2.7 V
MHz VDRIVE < 2.7 V
tSCLK
1/fSCLK
2
μs
ns
Minimum SCLK period
CS to SCLK falling edge setup time
tS_
_SCK
CS
tH_SCK_
2
ns
SCLK to CS rising edge hold time
CS
tLP_SCK
tHP_SCK
tD_
0.4 × tSCLK
0.4 × tSCLK
ns
ns
ns
SCLK low pulse width
SCLK high pulse width
Delay from CS until DOUTx three-state disabled
18
_DO
CS
tD_SCK_DO
Data out access time after SCLK rising edge
VDRIVE > 2.7 V
VDRIVE < 2.7 V
17
25
ns
ns
tH_SCK_DO
Data out hold time after SCLK rising edge
VDRIVE > 2.7 V
VDRIVE < 2.7 V
Data in setup time before SCLK falling edge
Data in hold time after SCLK falling edge
7
10
9
ns
ns
ns
ns
tS_SDI_SCK
tH_SCK_SDI
0
Rev. 0 | Page 9 of 75
AD7606C-18
Data Sheet
Parameter Min
Typ Max Unit Description
tDHZ_
25
ns
ns
ns
CS rising edge to DOUTx high impedance
_DO
CS
tWR
tD_
25
Time between writing and reading the same register or between two writes, if fSCLK >50 MHz
Delay from CS until DOUTx three-state disabled or delayed from CS until MSB valid
16
_FD
CS
tD_SCK_FDL
tDHZ_FD
18
20
ns
ns
18th SCLK falling edge to FRSTDATA low
CS rising edge until FRSTDATA three-state enabled
Serial Mode Timing Diagrams
CS
tHP_SCK
tH_SCK_CS
tS_CS_SCK
tSCLK
SCLK
1
2
3
16
17
18
t
LP_SCK
tD_CS_DO
tDHZ_CS_DO
tD_SCK_DO
tH_SCK_DO
D
x
DB17
DB16
DB15
DB2
DB1
DB0
OUT
tD_SCK_FDL
tD_CS_FD
tDHZ_FD
FRSTDATA
Figure 6. Serial Timing Diagram, ADC Mode (Channel 1)
CS
tSCLK
tS_CS_SCK
tHP_SCK
tH_SCK_CS
1
2
3
8
9
16
SCLK
tLP_SCK
tH_SCK_SDI
tS_SDI_SCK
tWR
ADD5
ADD0
DIN7
D
DIN0
D
SDI
WEN
R/W
tD_CS_DO
tD_SCK_DO
D
x
7
0
OUT
OUT
OUT
Figure 7. Serial Timing Interface, Register Map Read and Write Operations
Rev. 0 | Page 10 of 75
Data Sheet
AD7606C-18
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit
board (PCB) design and operating environment. Close
attention to PCB thermal design is required.
Table 6.
Parameter
Rating
AVCC to AGND
VDRIVE to AGND
Analog Input Voltage to AGND1
Digital Input Voltage to AGND
Digital Output Voltage to AGND
REFIN to AGND
−0.3 V to +6.5 V
−0.3 V to AVCC + 0.3 V
21 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to AVCC + 0.3 V
10 mA
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 7. Thermal Resistance
Package Type
1
θJA
θJC
Unit
Input Current to Any Pin Except Supplies1
Temperature
ST-64-2
40
7
°C/W
Operating Range
Storage Range
Junction
Pb/Sn, Soldering Reflow
(10 sec to 30 sec)
−40°C to +125°C
−65°C to +150°C
150°C
1 Simulated data based on JEDEC 2s2p thermal test PCB in a JEDEC natural
convention environment.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
240 (+0)°C
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Pb-Free, Soldering Reflow
260 (+0)°C
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
1 Transient currents of up to 100 mA do not cause silicon controlled
rectifier (SCR) latch-up.
Field induced charged device model (FICDM) per ANSI/ESDA/
JEDEC JS-002.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
ESD Ratings for AD7606C-18
Table 8. AD7606C-18, 64-Lead LQFP
ESD Model
Withstand Threshold (V)
Class
HBM
3A
Analog Inputs Only
All Other Pins
FICDM
6000
4000
750
C4
ESD CAUTION
Rev. 0 | Page 11 of 75
AD7606C-18
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
AV
48
47
46
45
44
43
42
41
40
AV
CC
CC
ANALOG INPUT
PIN 1
2
3
AGND
AGND
OS 0
DECOUPLING CAP PIN
POWER SUPPLY
GROUND PIN
REFGND
REFCAPB
REFCAPA
REFGND
REFIN/REFOUT
AGND
4
OS 1
OS 2
5
6
DATA OUTPUT
PAR/SER SEL
AD7606C-18
7
STBY
TOP VIEW
DIGITAL OUTPUT
DIGITAL INPUT
(Not to Scale)
8
RANGE
9
AGND
CONVST
WR
REFERENCE INPUT/OUTPUT
10
11
12
13
39 REGCAP
38 AV
CC
RESET
RD/SCLK
CS
AV
37
36
CC
REGCAP
BUSY 14
35 AGND
34
FRSTDATA 15
REF SELECT
33 DB17/DB1
DB2
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 8. Pin Configuration
Table 9. Pin Function Description
Pin No.
Type1
Mnemonic
Description
1, 37, 38, 48
P
AVCC
Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end
amplifiers and to the ADC core. Decouple these supply pins to AGND.
2, 26, 35, 40,
41, 47
P
AGND
Analog Ground. The AGND pins are the ground reference points for all analog circuitry on the
AD7606C-18. All analog input signals and external reference signals must be referred to the
AGND pins. All six of the AGND pins must connect to the AGND plane of a system.
3 to 5
6
DI
DI
OS0 to OS2
PAR/SER SEL
Oversampling Mode Pins. OS0 to OS2 select the oversampling ratio or enable software mode
(see Table 14 for oversampling bit decoding). See the Digital Filter section for more details about
the oversampling mode of operation.
Parallel/Serial Interface Selection Input. If the PAR/SER SEL pin is tied to a logic low, the parallel
interface is selected. If the PAR/SER SEL pin is tied to a logic high, the serial interface is selected.
See the Digital Interface section for more information on each interface available.
7
DI
STBY
Standby Mode Input. In hardware mode, the STBY pin, in combination with the RANGE pin,
places the AD7606C-18 into one of two power-down modes: standby mode or shutdown mode.
In software mode, the STBY pin is ignored. Therefore, it is recommended to connect the STBY pin
to logic high. See the Power-Down Modes section for more information on both hardware mode
and software mode.
8
9
DI
DI
RANGE
Analog Input Range Selection Input. In hardware mode, the RANGE pin determines the input
range of the analog input channels (see Table 10). If the STBY pin is at logic low, the RANGE pin
determines the power-down mode (see Table 16). In software mode, the RANGE pin is ignored.
However, the RANGE pin must be tied high or low.
Conversion Start Input. When the CONVST pin transitions from low to high, the analog input is
sampled on all eight SAR ADCs. In software mode, the CONVST pin can be configured as an
external oversampling clock. Providing a low jitter external clock helps improve the SNR
performance for large oversampling ratios. See the External Oversampling Clock section for
further details.
CONVST
10
DI
WR
Parallel Write Control Input. In hardware mode, the WR pin has no function. Therefore, the WR
pin can be tied high, tied low, or shorted to CONVST. In software mode, the WR pin is the active
low write pin for writing registers using the parallel interface. See the Parallel Interface section
for more information.
Rev. 0 | Page 12 of 75
Data Sheet
AD7606C-18
Pin No.
Type1
Mnemonic
Description
11
DI
RESET
Reset Input, Active High. Full and partial reset options are available. The type of reset is
determined by the length of the reset pulse. It is recommended that the device receives a full
reset pulse after power-up. See the Reset Functionality section for further details.
12
13
DI
RD/SCLK
CS
Parallel Data Read Control Input when the Parallel Interface is Selected (RD).
Serial Clock Input when the Serial Interface is Selected (SCLK). See the Digital Interface section for
more details.
Chip Select. The CS pin is the active low chip select input for ADC data reads or register data
reads and writes, in both the serial and parallel interfaces. See the Digital Interface section for more
details.
DI
14
15
DO
DO
BUSY
Busy Output. The BUSY pin transitions to a logic high along with the CONVST rising edge. The
BUSY output remains high until the conversion process for all channels is complete.
First Data Output. The FRSTDATA output signal indicates when the first channel, V1, is being read
back on the parallel interface (see Figure 3) or the serial interface (see Figure 6). See the Digital
Interface section for more details.
FRSTDATA
16 to 18
DO/DI
DB2 to DB4
Parallel Output/Input Data Bits. When using the parallel interface, the DB2 to DB4 pins act as
three-state parallel digital input and output pins (see the Parallel Interface section). When CS and
RD are low, the DB2 to DB4 pins are used to output DB2 to DB4 of the conversion result during
the first RD pulse and zeros during the second RD pulse (see Figure 98). When using the serial
interface, tie the DB2 to DB4 pins to AGND.
19
DO/DI
DB5/DOUT
DB6/DOUT
DB7/DOUT
DB8/DOUT
E
Parallel Output/Input Data Bit 5/Serial Interface Data Output Pin. When using the parallel
interface, the DB5/DOUTE pin acts as a three-state parallel digital input/output pin. When CS and
RD are low, the DB5/DOUTE pin is used to output DB5 of the conversion result during the first RD
pulse and zero during the second RD pulse (see Figure 98). When using the serial interface, the
DB5/DOUTE pin functions as DOUTE. See Table 23 for more details on each data interface and
operation mode.
Parallel Output/Input Data Bit 6/Serial Interface Data Output Pin. When using the parallel
interface, the DB6/DOUTF pin acts as a three-state parallel digital input/output pin. When CS and
RD are low, the DB6/DOUTF pin is used to output DB6 of the conversion result during the first RD
pulse and zero during the second RD pulse (see Figure 98). When using the serial interface, the
DB6/DOUTF pin functions as DOUTF. See Table 23 for more details on each data interface and
operation mode.
Parallel Output/Input Data Bit 7/Serial Interface Data Output Pin. When using the parallel
interface, the DB7/DOUTG pin acts as a three-state parallel digital input/output pin. When CS and
RD are low, the DB7/DOUTG pin is used to output DB7 of the conversion result during the first RD
pulse and zero during the second RD pulse (see Figure 98). When using the serial interface, the
DB7/DOUTG pin functions as DOUTG. See Table 23 for more details on each data interface and
operation mode.
Parallel Output/Input Data Bit 8/Serial Interface Data Output Pin. When using the parallel
interface, the DB8/DOUTH pin acts as a three-state parallel digital input/output pin. When CS and
RD are low, the DB8/DOUTH pin is used to output DB8 of the conversion result during the first RD
pulse and zero during the second RD pulse (see Figure 98). When using the serial interface, the
DB8/DOUTH pin functions as DOUTH. See Table 23 for more details on each data interface and
operation mode.
20
21
22
DO/DI
DO/DI
DO/DI
F
G
H
23
24
P
VDRIVE
Logic Power Supply Input. The voltage (1.71 V to 5.25 V) supplied at the VDRIVE pin determines the
operating voltage of the interface. The VDRIVE pin is nominally at the same supply as the supply of
the host interface, that is, the data signal processor (DSP) and field programmable gate array (FPGA).
Parallel Output/Input Data Bit 9/Serial Interface Data Output Pin. When using the parallel
interface, the DB9/DOUTA pin acts as a three-state parallel digital input/output pin. When CS and
RD are low, the DB9/DOUTA pin is used to output DB9 of the conversion result during the first RD
pulse and zero during the second RD pulse (see Figure 98). When using the serial interface, the
DB9/DOUTA pin functions as DOUTA. See Table 23 for more details on each data interface and
operation mode.
DO/DI
DB9/DOUT
A
25
DO/DI
DB10/DOUT
B
Parallel Output/Input Data Bit 10/Serial Interface Data Output Pin. When using the parallel
interface, the DB10/DOUTB pin acts as a three-state parallel digital input and output pin. When CS
and RD are low, the DB10/DOUTB pin is used to output DB10 of the conversion result during the
first RD pulse and zero during the second RD pulse (see Figure 98). When using the serial
interface, the DB10/DOUTB pin functions as DOUTB. See Table 23 for more details on each data
interface and operation mode.
Rev. 0 | Page 13 of 75
AD7606C-18
Data Sheet
Pin No.
Type1
Mnemonic
Description
27
DO/DI
DB11/DOUT
DB12/DOUT
DB13/SDI
C
Parallel Output/Input Data Bit 11/Serial Interface Data Output Pin. When using the parallel
interface, the DB11/DOUTC pin acts as a three-state parallel digital input and output pin. When CS
and RD are low, the DB11/DOUTC pin is used to output DB11 of the conversion result during the
first RD pulse and zero during the second RD pulse (see Figure 98). When using the serial
interface, the DB11/DOUTC pin functions as DOUTC if in software mode and using the 4 DOUTx line option
or 8 DOUTx line option. See Table 23 for more details on each data interface and operation mode.
Parallel Output/Input Data Bit 12/Serial Interface Data Output Pin. When using the parallel
interface, the DB12/DOUTD pin acts as a three-state parallel digital input/output pin. When CS and
RD are low, the DB12/DOUTD pin is used to output DB12 of the conversion result during the first
RD pulse and zero during the second RD pulse (see Figure 98). When using serial interface, the
28
DO/DI
D
DB12/DOUTD pin functions as DOUTD if in software mode and using the 4 DOUTx line option or 8 DOUT
x
line option. See Table 23 for more details on each data interface and operation mode.
Parallel Output/Input Data Bit 13/Serial Data Input. When using parallel interface, the DB13/SDI pin
29
DO/DI
DO/DI
DO/DI
DO/DI
acts as a three-state parallel digital input and output pin. When CS and RD are low, the DB13/SDI
pin is used to output DB13 of the conversion result during the first RD pulse and zero during the
second RD pulse (see Figure 98). When using the serial interface in software mode, the DB13/SDI
pin functions as SDI. See Table 23 for more details on each data interface and operation mode.
Parallel Output/Input Data Bits. When using the parallel interface, the DB14 and DB15 pins act as
three-state parallel digital input and output pins (see the Parallel Interface section). When CS and
RD are low, the DB14 and DB15 pins are used to output DB14 and DB15 of the conversion result
during the first RD pulse and zeros during the second RD pulse (see Figure 98). When using the
serial interface, tie the DB14 and DB15 pins to AGND.
Parallel Output/Input Data Bits. When using the parallel interface, the DB16/DB0 pin acts as a
three-state parallel digital input and output pin (see the Parallel Interface section). When CS and
RD are low, the DB16/DB0 pin is used to output DB16 of the conversion result during the first RD
pulse and DB0 of the same conversion result during the second RD pulse (see Figure 98). When
using the serial interface, tie the DB16/DB0 pin to AGND.
Parallel Output/Input Data Bits. When using the parallel interface, the DB17/DB1 pin acts as a
three-state parallel digital input and output pin (see the Parallel Interface section). When CS and
RD are low, the DB17/DB1 pin is used to output DB17 of the conversion result during the first RD
pulse and DB1 of the same conversion result during the second RD pulse (see Figure 98). When
using the serial interface, tie the DB17/DB1 pin to AGND.
30, 31
32
DB14, DB15
DB16/DB0
DB17/DB1
33
34
DI
P
REF SELECT
REGCAP
Internal/External Reference Selection Logic Input. If the REF SELECT pin is set to logic high, the
internal reference is selected and enabled. If the REF SELECT pin is set to logic low, the internal
reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin.
Decoupling Capacitor Pin for Voltage Output from 1.9 V Internal Regulator, Analog Low
Dropout (ALDO) and Digital Low Dropout (DLDO). The REGCAP output pins must be decoupled
separately to AGND using a 1 μF capacitor. The voltage on the REGCAP pins is in the range of
1.875 V to 1.93 V.
36, 39
42
REF
REFIN/REFOUT Reference Input/Reference Output. The internal 2.5 V reference is available on the REFOUT pin
for external use while the REF SELECT pin is set to logic high. Alternatively, by setting the REF
SELECT pin to logic low, the internal reference is disabled and an external reference of 2.5 V must be
applied to this input (REFIN). A 100 nF capacitor must be applied from the REFIN pin to ground, close
to the REFGND pins, for both internal and external reference options. See the Reference section
for more details.
43, 46
44, 45
REF
REF
REFGND
REFCAPA,
REFCAPB
Reference Ground Pins. The REFGND pins must be connected to AGND.
Reference Buffer Output Force and Sense Pins. The REFCAPA and REFCAPB pins must be
connected together and decoupled to AGND using a low effective series resistance (ESR), 10 μF
ceramic capacitor. The voltage on the REFCAPA and REFCAPB pins is typically 4.4 V.
49
50
51
52
53
54
55
56
57
AI
AI
AI
AI
AI
AI
AI
AI
AI
V1+
V1−
V2+
V2−
V3+
V3−
V4+
V4−
V5+
Channel 1 Positive Analog Input Pin.
Channel 1 Negative Analog Input Pin.
Channel 2 Positive Analog Input Pin.
Channel 2 Negative Analog Input Pin.
Channel 3 Positive Analog Input Pin.
Channel 3 Negative Analog Input Pin.
Channel 4 Positive Analog Input Pin.
Channel 4 Negative Analog Input Pin.
Channel 5 Positive Analog Input Pin.
Rev. 0 | Page 14 of 75
Data Sheet
AD7606C-18
Pin No.
58
59
60
61
62
63
64
Type1
Mnemonic
V5−
V6+
V6−
V7+
V7−
V8+
V8−
Description
AI
AI
AI
AI
AI
AI
AI
Channel 5 Negative Analog Input Pin.
Channel 6 Positive Analog Input Pin.
Channel 6 Negative Analog Input Pin.
Channel 7 Positive Analog Input Pin.
Channel 7 Negative Analog Input Pin.
Channel 8 Positive Analog Input Pin.
Channel 8 Negative Analog Input Pin.
1 P is power supply, DI is digital input, DO is digital output, REF is reference input/output, AI is analog input, and GND is ground.
Rev. 0 | Page 15 of 75
AD7606C-18
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–20
±20V DIFFERENTIAL RANGE
±20V DIFFERENTIAL RANGE
fSAMPLE = 1MSPS
fIN = 1kHz
131072 POINT FFT
SNR = 89.4dB
THD = –100.4dB
fSAMPLE = 1MSPS
–20
fIN = 1kHz
131072 POINT FFT
SNR = 92.7dB
–40
–40
THD = –103.5dB
–60
–60
–80
–100
–120
–140
–160
–180
–80
–100
–120
–140
–160
–180
0.1
1
10
100
0.1
1
10
100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 9. Fast Fourier Transform (FFT), 20 V Differential Range,
Low Bandwidth Mode
Figure 12. FFT, 20 V Differential Range, High Bandwidth Mode
0
0
±10V SINGLE-ENDED RANGE
±10V SINGLE-ENDED RANGE
fSAMPLE = 1MSPS
fSAMPLE = 1MSPS
–20
–20
fIN = 1kHz
fIN = 1kHz
131072 POINT FFT
SNR = 92.2dB
131072 POINT FFT
SNR = 86.9dB
–40
–40
THD = –104dB
THD = –100.3dB
–60
–60
–80
–100
–120
–140
–160
–180
–80
–100
–120
–140
–160
–180
0.1
1
10
100
0.1
1
10
100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 10. FFT, 10 V Single-Ended Range, Low Bandwidth Mode
Figure 13. FFT, 10 V Single-Ended Range, High Bandwidth Mode
0
0
0V TO 10V SINGLE-ENDED RANGE
0V TO 10V SINGLE-ENDED RANGE
fSAMPLE = 1MSPS
fSAMPLE = 1MSPS
–20
–20
fIN = 1kHz
fIN = 1kHz
131072 POINT FFT
SNR = 89.9dB
131072 POINT FFT
SNR = 82dB
–40
–40
THD = –98.2dB
THD = –100.4dB
–60
–60
–80
–100
–120
–140
–160
–180
–80
–100
–120
–140
–160
–180
0.1
1
10
100
0.1
1
10
100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 11. FFT, 0 V to 10 V Single-Ended Range, Low Bandwidth Mode
Figure 14. FFT, 0 V to 10 V Single-Ended Range, High Bandwidth Mode
Rev. 0 | Page 16 of 75
Data Sheet
AD7606C-18
110
106
103
99
110
106
103
99
NO OS
OS 2
OS 4
OS 8
OS 16
OS 32
OS 64
OS 128
OS 256
NO OS
OS 32
OS 64
OS 128
OS 256
OS 2
OS 4
OS 8
OS 16
95
95
91
91
88
88
fSAMPLE = 1MSPS/OSR
±20V DIFFERENTIAL RANGE
LOW BW MODE
fSAMPLE = 1MSPS/OSR
±20V DIFFERENTIAL RANGE
84
84
INTERNAL OS CLOCK
HIGH BW MODE, INTERNAL OS CLOCK
0.1
INPUT FREQUENCY (kHz)
80
80
0.01
0.01
0.1
1
10
50
1
10
30
INPUT FREQUENCY (kHz)
Figure 15. SNR vs. Input Frequency for Different Oversampling Ratio (OSR)
Values, 20 V Differential Range, Low Bandwidth Mode, Internal
Oversampling Clock (OS = Oversampling)
Figure 18. SNR vs. Input Frequency for Different OSR Values, 20 V
Differential Range, High Bandwidth Mode, Internal Oversampling Clock
110
110
NO OS
OS 2
OS 4
OS 8
OS 16
OS 32
OS 64
OS 128
OS 256
NO OS
OS 2
OS 4
OS 8
OS 16
OS 32
OS 64
OS 128
OS 256
105
100
95
105
100
95
90
90
85
85
fSAMPLE = 1MSPS/OSR
±10V SINGLE-ENDED RANGE
LOW BW MODE
80
80
fSAMPLE = 1MSPS/OSR
±10V SINGLE-ENDED RANGE
INTERNAL OS CLOCK
HIGH BW MODE, INTERNAL OS CLOCK
75
75
0.01
0.1
1
10
50
0.01
0.1
1
10
50
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 16. SNR vs. Input Frequency for Different OSR Values, 10 V Single-
Ended Range, Low Bandwidth Mode, Internal Oversampling Clock
Figure 19. SNR vs. Input Frequency for Different OSR Values, 10 V Single-
Ended Range, High Bandwidth Mode, Internal Oversampling Clock
110
110
fSAMPLE = 1MSPS/OSR
0V TO 10V SINGLE-ENDED RANGE
105 HIGH BW MODE, INTERNAL OS CLOCK
NO OS
OS 2
OS 4
OS 32
OS 64
OS 128
OS 256
NO OS
OS 2
OS 4
105
100
95
OS 8
OS 8
OS 16
OS 16
OS 32
OS 64
OS 128
OS 256
100
95
90
85
80
75
90
85
80
fSAMPLE = 1MSPS/OSR
0V TO 10V SINGLE-ENDED RANGE
LOW BW MODE, INTERNAL OS CLOCK
75
0.01
0.1
1
10
50
0.01
0.1
1
10
50
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 17. SNR vs. Input Frequency for Different OSR Values, 0 V to 10 V
Single-Ended Range, Low Bandwidth Mode, Internal Oversampling Clock
Figure 20. SNR vs. Input Frequency for Different OSR Values, 0 V to 10 V
Single-Ended Range, High Bandwidth Mode, Internal Oversampling Clock
Rev. 0 | Page 17 of 75
AD7606C-18
Data Sheet
110
105
100
95
110
105
100
95
fSAMPLE = 1MSPS/OSR
±20V DIFFERENTIAL RANGE
HIGH BW MODE, EXTERNAL OS CLOCK
90
90
85
85
NO OS
OS 2
OS 4
OS 32
OS 64
OS 128
OS 256
fSAMPLE = 1MSPS/OSR
±20V DIFFERENTIAL RANGE
LOW BW MODE
80
80
NO OS
OS 2
OS 4
OS 8
OS 16
OS 32
OS 64
OS 128
OS 256
OS 8
EXTERNAL OS CLOCK
OS 16
75
0.01
75
0.01
0.1
1
10
50
0.1
1
10
50
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 21. SNR vs. Input Frequency for Different OSR Values, 20 V
Differential Range, Low Bandwidth Mode, External Oversampling Clock
Figure 24. SNR vs. Input Frequency for Different OSR Values, 20 V
Differential Range, High Bandwidth Mode, External Oversampling Clock
110
105
100
95
110
105
100
95
90
90
85
85
NO OS
OS 2
OS 4
OS 32
OS 64
OS 128
OS 256
NO OS
OS 2
OS 4
OS 32
OS 64
OS 128
OS 256
fSAMPLE = 1MSPS/OSR
±10V SINGLE-ENDED RANGE
LOW BW MODE
fSAMPLE = 1MSPS/OSR
±10V SINGLE-ENDED RANGE
HIGH BW MODE
80
80
OS 8
OS 8
EXTERNAL OS CLOCK
EXTERNAL OS CLOCK
OS 16
OS 16
75
75
0.01
0.1
1
10
50
0.01
0.1
1
10
50
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 22. SNR vs. Input Frequency for Different OSR Values, 10 V Single-
Ended Range, Low Bandwidth Mode, External Oversampling Clock
Figure 25. SNR vs. Input Frequency for Different OSR Values, 10 V Single-
Ended Range, High Bandwidth Mode, External Oversampling Clock
110
110
fSAMPLE = 1MSPS/OSR
0V TO 10V SINGLE-ENDED RANGE
fSAMPLE = 1MSPS/OSR
0V TO 10V SINGLE-ENDED RANGE
HIGH BW MODE, EXTERNAL OS CLOCK
LOW BW MODE, EXTERNAL OS CLOCK
105
100
95
105
100
95
90
90
85
85
80
80
NO OS
OS 2
OS 4
OS 8
OS 16
OS 32
OS 64
OS 128
OS 256
NO OS
OS 2
OS 4
OS 8
OS 16
OS 32
OS 64
OS 128
OS 256
75
0.01
75
0.01
0.1
1
10
50
0.1
1
10
50
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 23. SNR vs. Input Frequency for Different OSR Values, 0 V to 10 V
Single-Ended Range, Low Bandwidth Mode, External Oversampling Clock
Figure 26. SNR vs. Input Frequency for Different OSR Values, 0 V to 10 V
Single-Ended Range, High Bandwidth Mode, External Oversampling Clock
Rev. 0 | Page 18 of 75
Data Sheet
AD7606C-18
–70
–70
–75
±20V DIFFERENTIAL RANGE
LOW BW MODE
±20V DIFFERENTIAL RANGE
HIGH BW MODE
–75
–80
–80
1kHz INPUT FREQUENCY
10kHz INPUT FREQUENCY
50kHz INPUT FREQUENCY
100kHz INPUT FREQUENCY
1kHz INPUT FREQUENCY
10kHz INPUT FREQUENCY
–85
–85
–90
–90
–95
–95
–100
–105
–110
–115
–120
–100
–105
–110
–115
–120
–25
–20
–15
–10
–5
0
–25
–20
–15
–10
–5
0
INPUT LEVEL (dBFS)
INPUT LEVEL (dBFS)
Figure 27. THD vs. Input Level, 20 V Differential Range, Low Bandwidth Mode
Figure 30. THD vs. Input Level, 20 V Differential Range, High Bandwidth Mode
–70
–70
±10V SINGLE-ENDED RANGE
±10V SINGLE-ENDED RANGE
LOW BW MODE
HIGH BW MODE
–75
–80
–75
–80
1kHz INPUT FREQUENCY
1kHz INPUT FREQUENCY
10kHz INPUT FREQUENCY
10kHz INPUT FREQUENCY
50kHz INPUT FREQUENCY
100kHz INPUT FREQUENCY
–85
–85
–90
–90
–95
–95
–100
–105
–110
–115
–120
–100
–105
–110
–115
–120
–25
–20
–15
–10
–5
0
–25
–20
–15
–10
–5
0
INPUT LEVEL (dBFS)
INPUT LEVEL (dBFS)
Figure 28. THD vs. Input Level, 10 V Single-Ended Range, Low Bandwidth Mode
Figure 31. THD vs. Input Level, 10 V Single-Ended Range, High Bandwidth Mode
–70
–70
0V TO 10V SINGLE-ENDED RANGE
0V TO 10V SINGLE-ENDED RANGE
LOW BW MODE
HIGH BW MODE
–75
–80
–75
–80
1kHz INPUT FREQUENCY
1kHz INPUT FREQUENCY
10kHz INPUT FREQUENCY
10kHz INPUT FREQUENCY
50kHz INPUT FREQUENCY
100kHz INPUT FREQUENCY
–85
–85
–90
–90
–95
–95
–100
–105
–110
–115
–120
–100
–105
–110
–115
–120
–25
–20
–15
–10
–5
0
–25
–20
–15
–10
–5
0
INPUT LEVEL (dBFS)
INPUT LEVEL (dBFS)
Figure 29. THD vs. Input Level, 0 V to 10 V Single-Ended Range,
Low Bandwidth Mode
Figure 32. THD vs. Input Level, 0 V to 10 V Single-Ended Range,
High Bandwidth Mode
Rev. 0 | Page 19 of 75
AD7606C-18
Data Sheet
–75
–75
–80
±20V DIFFERENTIAL RANGE
HIGH BW MODE
±20V DIFFERENTIAL RANGE
0Ω
LOW BW MODE
fSAMPLE = 1MSPS
50Ω
1kΩ
10kΩ
50kΩ
fSAMPLE = 1MSPS
–80
–85
R
MATCHED ON Vx+ AND Vx–
R
MATCHED ON Vx+ AND Vx–
SOURCE
SOURCE
–85
–90
–90
–95
–95
–100
–105
–110
–100
–105
–110
0Ω
50Ω
1kΩ
10kΩ
50kΩ
0.01
0.1
1
10
40
0.01
0.1
1
10
40
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 33. THD vs. Input Frequency for Various Source Impedances (RSOURCE),
20 V Differential Range, Low Bandwidth Mode
Figure 36. THD vs. Input Frequency for Various Source Impedances,
20 V Differential Range, High Bandwidth Mode
–75
–75
±10V SINGLE-ENDED RANGE
±10V SINGLE-ENDED RANGE
LOW BW MODE
HIGH BW MODE
fSAMPLE = 1MSPS
SOURCE
fSAMPLE = 1MSPS
SOURCE
–80
–80
–85
R
MATCHED ON Vx+ AND Vx–
R
MATCHED ON Vx+ AND Vx–
–85
–90
–90
–95
–95
–100
–105
–110
–100
–105
–110
0Ω
0Ω
50Ω
1kΩ
10kΩ
50kΩ
50Ω
1kΩ
10kΩ
50kΩ
0.01
0.1
1
10
40
0.01
0.1
1
10
40
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 34. THD vs. Input Frequency for Various Source Impedances,
10 V Single-Ended Range, Low Bandwidth Mode
Figure 37. THD vs. Input Frequency for Various Source Impedances,
10 V Single-Ended Range, High Bandwidth Mode
–75
–75
0V TO 10V SINGLE-ENDED RANGE
HIGH BW MODE
0V TO 10V SINGLE-ENDED RANGE
LOW BW MODE
fSAMPLE = 1MSPS
SOURCE
fSAMPLE = 1MSPS
SOURCE
–80
–85
–80
R
MATCHED ON Vx+ AND Vx–
R
MATCHED ON Vx+ AND Vx–
–85
–90
0Ω
50Ω
1kΩ
10kΩ
50kΩ
–90
–95
–95
–100
–105
–110
–100
–105
–110
0Ω
50Ω
1kΩ
10kΩ
50kΩ
0.01
0.1
1
10
40
0.01
0.1
1
10
40
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 35. THD vs. Input Frequency for Various Source Impedances,
0 V to 10 V Single-Ended Range, Low Bandwidth Mode
Figure 38. THD vs. Input Frequency for Various Source Impedances,
0 V to 10 V Single-Ended Range, High Bandwidth Mode
Rev. 0 | Page 20 of 75
Data Sheet
AD7606C-18
1.0
0.9
0.8
1.0
0.9
0.8
±10V SINGLE-ENDED RANGE
LOW BW MODE
INTERNAL REFERENCE
±10V SINGLE-ENDED RANGE
HIGH BW MODE
INTERNAL REFERENCE
0.7
0.7
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
0
65536
131072
CODE
196608
262144
262144
125
0
65536
131072
CODE
196608
262144
262144
125
Figure 39. Typical DNL, Low Bandwidth Mode
Figure 42. Typical DNL, High Bandwidth Mode
4.0
3.5
4.0
3.5
±10V SINGLE-ENDED RANGE
LOW BW MODE
INTERNAL REFERENCE
±10V SINGLE-ENDED RANGE
HIGH BW MODE
INTERNAL REFERENCE
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
0
65536
131072
CODE
196608
0
65536
131072
CODE
196608
Figure 40. Typical INL, Low Bandwidth Mode
Figure 43. Typical INL, High Bandwidth Mode
94
92
90
88
86
84
82
80
94
92
90
88
86
84
82
80
AV
= 5V, V
= 3.3V
CC
DRIVE
fSAMPLE = 1MSPS
HIGH BW MODE
AV
= 5V, V
= 3.3V
CC
DRIVE
fSAMPLE = 1MSPS
LOW BW MODE
±20V DIFFERENTIAL RANGE
±10V SINGLE-ENDED RANGE
0V TO 10V SINGLE-ENDED RANGE
±20V DIFFERENTIAL RANGE
±10V SINGLE-ENDED RANGE
0V TO 10V SINGLE-ENDED RANGE
–40
–20
0
20
45
65
85
105
–40
–20
0
20
45
65
85
105
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 41. SNR vs. Temperature, Low Bandwidth Mode
Figure 44. SNR vs. Temperature, High Bandwidth Mode
Rev. 0 | Page 21 of 75
AD7606C-18
Data Sheet
50
50
45
40
35
30
25
20
15
10
5
fSAMPLE = 1MSPS
PFS
NFS
LOW BW MODE
40
30
±20V DIFFERENTIAL RANGE
20
PFS
NFS
10
0
–10
–20
–30
–40
–50
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
0
–1.0
–40
–20
0
20
40
60
80
100
120
–0.5
0
0.5
1.0
1.5
2.0
PFS AND NFS DRIFT (PPM/°C)
TEMPERATURE (°C)
Figure 48. PFS and NFS Drift Histogram, 10 V Single-Ended Range
Figure 45. Positive Full-Scale (PFS) and Negative Full-Scale (NFS) Error vs.
Temperature, 20 V Differential Range
50
45
40
35
30
25
20
15
10
5
50
fSAMPLE = 1MSPS
LOW BW MODE
40
±10V SINGLE-ENDED RANGE
30
20
10
PFS
0
NFS
–10
–20
–30
–40
–50
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
CH 8
0
–1.0
–40
–20
0
20
40
60
80
100
120
–0.5
0
0.5
1.0
1.5
2.0
BZC DRIFT (PPM/°C)
TEMPERATURE (°C)
Figure 49. Bipolar Zero Code (BZC) Drift Histogram, 10 V Single-Ended Range
Figure 46. PFS and NFS Error vs. Temperature, 10 V Single-Ended Range
50
50
fSAMPLE = 1MSPS
FS
LOW BW MODE
45
40
ZS
0V TO 10V SINGLE-ENDED RANGE
30
40
35
30
25
20
15
10
5
20
10
0
–10
–20
–30
–40
–50
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
CH 8
0
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–40
–20
0
20
40
60
80
100
120
FS AND ZS DRIFT (PPM/°C)
TEMPERATURE (°C)
Figure 50. FS and Zero-Scale (ZS) Drift Histogram, 0 V to 10 V Single-Ended Range
Figure 47. FS Error vs. Temperature, 0 V to 10 V Single-Ended Range
Rev. 0 | Page 22 of 75
Data Sheet
AD7606C-18
50
900
800
700
600
500
400
300
200
fSAMPLE = 1MSPS
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
LOW BW MODE
40
30
±20V DIFFERENTIAL RANGE
20
10
0
–10
–20
–30
–40
–50
Vx+ AND Vx– SHORTED TO AGND
= 25°C
T
A
4096 SAMPLES
AVERAGE = –15.8679
PEAK TO PEAK = 14
100
0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
CH 8
–40
–20
0
20
40
60
80
100
120
–50 –40 –30 –20 –10
0
10
20
30
40
50
50
50
ADC CODE
TEMPERATURE (°C)
Figure 54. Histogram of Codes, 20 V Differential Range
Figure 51. Bipolar Zero Code Error vs. Temperature, 20 V Differential Range
800
700
600
500
400
300
200
50
fSAMPLE = 1MSPS
CH1
LOW BW MODE
40
CH2
CH3
CH4
CH5
CH6
CH7
CH8
±10V SINGLE-ENDED RANGE
30
20
10
0
–10
–20
–30
Vx+ AND Vx– SHORTED TO AGND
= 25°C
4096 SAMPLES
AVERAGE = –13.5076
PEAK TO PEAK = 16
T
A
100
0
–40
–50
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
CH 8
–40
–20
0
20
40
60
80
100
120
–50 –40 –30 –20 –10
0
10
20
30
40
ADC CODE
TEMPERATURE (°C)
Figure 55. Histogram of Codes, 10 V Single-Ended Range
Figure 52. Bipolar Zero Code Error vs. Temperature, 10 V Single-Ended Range
900
800
700
600
500
400
300
200
100
0
50
V
T
= 1mV
= 25°C
fSAMPLE = 1MSPS
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
IN
LOW BW MODE
A
40
4096 SAMPLES
PEAK TO PEAK = 20
0V TO 10V SINGLE-ENDED RANGE
30
20
10
0
–10
–20
–30
–40
–50
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
CH 8
0
10
20
30
40
–40
–20
0
20
40
60
80
100
120
ADC CODE
TEMPERATURE (°C)
Figure 56. Histogram of Codes, 0 V to 10 V Single-Ended Range
Figure 53. ZS Error vs. Temperature, 0 V to 10 V Single-Ended Range
Rev. 0 | Page 23 of 75
AD7606C-18
Data Sheet
50
50
45
40
35
30
25
20
15
10
5
AV
= 5V, V
= 3.3V
CC
DRIVE
NORMAL MODE
AUTOSTANDBY MODE
INTERNAL REFERENCE
LOW BW MODE
45
40
35
30
25
20
15
10
5
AV
= 5V, V
= 3.3V
CC
DRIVE
T
T
T
= –40°C
= +25°C
= +125°C
INTERNAL REFERENCE
LOW BW MODE
A
A
A
T
= 25°C
A
0
0
0
200
400
600
800
1000
0
100 200 300 400 500 600 700 800 900 1000
THROUGHPUT RATE (kSPS)
THROUGHPUT RATE (kSPS)
Figure 57. AVCC Supply Current vs. Throughput Rate for Various Temperatures
Figure 60. AVCC Supply Current vs. Throughput Rate, Normal Mode and
Autostandby Mode
20
2.505
AV = 5V, V
CC DRIVE
fSAMPLE = 1MSPS
= 3.3V
AV
= 5V, V = 3.3V
DRIVE
CC
fSAMPLE = 1MSPS
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
15
10
T
= 25°C
A
Vx–
5
±20V
±12.5V
±10V
±5V
0
–5
Vx+
–10
–15
–20
–20
–15
–10
–5
0
5
10
15
20
–40
–20
0
20
40
60
80
100
120
INPUT VOLTAGE, [Vx+] – [Vx–] (V)
TEMPERATURE (°C)
Figure 58. Analog Input Current vs. Input Voltage for Various Differential Ranges
Figure 61. Reference Drift
20
10
9
AV
= 5V, V
= 3.3V
AV
= 5V, V
= 3.3V
±12.5V
±10V
±6.25V
±5V
CC
DRIVE
0V TO 12.5V
0V TO 10V
0V TO 5V
CC
DRIVE
fSAMPLE = 1MSPS
fSAMPLE = 1MSPS
T = 25°C
A
Vx– TIED TO AGND
15
10
T
= 25°C
A
8
Vx– TIED TO AGND
7
±2.5V
6
5
5
Vx–
0
4
3
–5
Vx–
2
Vx+
–10
–15
–20
1
0
Vx+
–1
–2
–12.5 –10 –7.5 –5 –2.5
0
2.5
5
7.5
10 12.5
0
2
4
6
8
10
12
INPUT VOLTAGE, [Vx+] – [Vx–] (V)
INPUT VOLTAGE, [Vx+] – [Vx–] (V)
Figure 59. Analog Input Current vs. Input Voltage for Various Bipolar Single-
Ended Ranges
Figure 62. Analog Input Current vs. Input Voltage for Various Unipolar
Single-Ended Ranges
Rev. 0 | Page 24 of 75
Data Sheet
AD7606C-18
131072
104858
78643
5000
4000
3000
2000
1000
0
±20V DIFFERENTIAL RANGE
1kHz SQUARE WAVE
±20V DIFFERENTIAL RANGE
1kHz SQUARE WAVE
52429
26214
0
LOW BW RISING
HIGH BW RISING
LOW BW FALLING
HIGH BW FALLING
–26214
–52429
–78643
–104858
–131072
–1000
–2000
–3000
–4000
–5000
LOW BW RISING
HIGH BW RISING
LOW BW FALLING
HIGH BW FALLING
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
TIME (µs)
TIME (µs)
Figure 63. Step Response, 20 V Differential Range
Figure 66. Step Response, 20 V Differential Range, Fine Settling
131072
104858
78643
5000
4000
±10V SINGLE-ENDED RANGE
1kHz SQUARE WAVE
±10V SINGLE-ENDED RANGE
1kHz SQUARE WAVE
3000
52429
2000
1000
0
26214
0
–26214
–52429
–78643
–104858
–131072
–1000
LOW BW RISING
–2000
HIGH BW RISING
LOW BW FALLING
HIGH BW FALLING
LOW BW RISING
HIGH BW RISING
LOW BW FALLING
HIGH BW FALLING
–3000
–4000
–5000
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
TIME (µs)
TIME (µs)
Figure 64 Step Response, 10 V Single-Ended Range
Figure 67. Step Response, 10 V Single-Ended Range, Fine Settling
262144
235930
209715
183501
157286
131072
104858
78643
52429
26214
0
5000
4000
0V TO 10V SINGLE-ENDED RANGE
1kHz SQUARE WAVE
0V TO 10V SINGLE-ENDED RANGE
1kHz SQUARE WAVE
3000
2000
1000
0
LOW BW RISING
HIGH BW RISING
LOW BW FALLING
HIGH BW FALLING
LOW BW RISING
HIGH BW RISING
LOW BW FALLING
HIGH BW FALLING
–1000
–2000
–3000
–4000
–5000
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
80
90
100
TIME (µs)
TIME (µs)
Figure 65. Step Response, 0 V to 10 V Single-Ended Range
Figure 68. Step Response, 0 V to 10 V Single-Ended Range, Fine Settling
Rev. 0 | Page 25 of 75
AD7606C-18
Data Sheet
–70
–70
–80
INTERNAL REFERENCE
LOW BW MODE
INTERFERER IN ALL UNSELECTED CHANNELS
INTERNAL REFERENCE
HIGH BW MODE
INTERFERER IN ALL UNSELECTED CHANNELS
–80
–90
±20V DIFFERENTIAL RANGE
±10V SINGLE-ENDED RANGE
0V TO 10V SINGLE-ENDED RANGE
±20V DIFFERENTIAL RANGE
±10V SINGLE-ENDED RANGE
0V TO 10V SINGLE-ENDED RANGE
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
0.01
0.1
1
10
100
300
0.01
0.1
1
10
100
300
NOISE FREQUENCY (kHz)
NOISE FREQUENCY (kHz)
Figure 69. Channel to Channel Isolation vs. Noise Frequency,
Low Bandwidth Mode
Figure 72. Channel to Channel Isolation vs. Noise Frequency,
High Bandwidth Mode
–50
–50
–55
–60
–65
–70
–75
–80
–85
–90
–55
–60
–65
–70
–75
–80
–85
–90
±20V DIFFERENTIAL RANGE
±10V SINGLE-ENDED RANGE
0V TO 10V SINGLE-ENDED RANGE
±20V DIFFERENTIAL RANGE
±10V SINGLE-ENDED RANGE
0V TO 10V SINGLE-ENDED RANGE
RECOMMENDED DECOUPLING USED
fSAMPLE = 1MSPS
HIGH BW MODE
RECOMMENDED DECOUPLING USED
fSAMPLE = 1MSPS
LOW BW MODE
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 70. AC Power Supply Rejection Ratio (PSRR) vs. Frequency,
Low Bandwidth Mode
Figure 73. AC PSRR vs. Frequency, High Bandwidth Mode
1.176
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
1.175
1.174
1.173
1.172
1.171
1.170
1.169
1.168
1.167
1.166
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 71. Input Impedance vs. Temperature
Rev. 0 | Page 26 of 75
Data Sheet
AD7606C-18
TERMINOLOGY
Integral Nonlinearity (INL)
Total Unadjusted Error (TUE)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale at ½ LSB below
the first code transition and full scale at ½ LSB above the last code
transition.
TUE is the maximum deviation of the output code from the
ideal. TUE includes INL errors, bipolar zero code and positive
and negative full-scale errors, and reference errors.
Signal-to-Noise-and-Distortion (SINAD) Ratio
SINAD ratio is the measured ratio of signal-to-noise-and-
distortion at the output of the ADC. The signal is the rms
amplitude of the fundamental. Noise is the sum of all
nonfundamental signals up to half of the sampling frequency
(fS/2, excluding dc).
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Bipolar Zero Code Error
Bipolar zero code error is the deviation of the midscale transition
(all 1s to all 0s) from the ideal, which is 0 V − ½ LSB.
The ratio depends on the number of quantization levels in
the digitization process: the more levels, the smaller the
quantization noise.
Bipolar Zero Code Error Matching
Bipolar zero code error matching is the absolute difference in
bipolar zero code error between any two input channels.
The theoretical SINAD for an ideal N-bit converter with a sine
wave input is given by
Open Circuit Code Error
SINAD = (6.02N + 1.76) dB
Open circuit code error is the ADC output code when there is
an open circuit on the analog input and a pull-down resistor
(RPD) connected between the analog input pair of pins. See
Figure 94 for more details.
Thus, for a 16-bit converter, the SINAD is 98 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the harmonics to the
fundamental. For the AD7606C-18, it is defined as
Positive Full-Scale (PFS) Error
THD (dB) =
In bipolar ranges, PFS error is the deviation of the actual last code
transition from the ideal last code transition (for example, 10 V −
1½ LSB (9.99988), 5 V − 1½ LSB (4.99994), or 2.5 V − 1½ LSB
(2.49997)) after the bipolar zero code error is adjusted out. The
PFS error includes the contribution from the reference buffer.
V 2 + V 2 + V42 + V 2 + V 2 + V 2 + V 2 + V 2
2
3
5
6
7
8
9
20log
where:
V
1
V2 to V9 are the rms amplitudes of the second through ninth
harmonics.
V1 is the rms amplitude of the fundamental.
Positive Full-Scale (PFS) Error Matching
PFS error matching is the absolute difference in positive full-scale
error between any two input channels.
Peak Harmonic or Spurious Noise
Negative Full-Scale (NFS) Error
Peak harmonic or spurious noise is the ratio of the rms value of
the next largest component in the ADC output spectrum (up to
fS/2, excluding dc) to the rms value of the fundamental. Normally,
the value of this specification is determined by the largest
harmonic in the spectrum, but for ADCs where the harmonics are
buried in the noise floor, the value is determined by a noise
peak.
In bipolar ranges, NFS error is the deviation of the first code
transition from the ideal first code transition (for example, −10 V +
½ LSB (−9.99996), −5 V + ½ LSB (−4.99998), or −2.5 V + ½ LSB
(−2.49999)) after the bipolar zero code error is adjusted out.
The NFS error includes the contribution from the reference
buffer.
Negative Full-Scale (NFS) Error Matching
NFS error matching is the absolute difference in negative full-scale
error between any two input channels.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. The power supply rejection (PSR)
is the maximum change in full-scale transition point due to a
change in power supply voltage from the nominal value. The
PSRR is defined as the ratio of the 100 mV p-p sine wave
applied to the AVCC supplies of the ADC frequency, fS, to the
power of the ADC output at that frequency, fS.
Full-Scale (FS) Error
In unipolar ranges, FS error is the deviation of the actual last code
transition from the ideal last code transition (for example, 10 V −
1½ LSB (9.99954), or 5 V − 1½ LSB (4.99977)) after the zero scale
error is adjusted out. The FS error includes the contribution
from the reference buffer
PSRR (dB) = 20 log (0.1/PfS)
Zero Scale (ZS) Error
where:
In unipolar ranges, ZS error is the deviation of the first code
transition from the ideal first code transition, which is
0 V − ½ LSB.
PfS is equal to the power at frequency, fS, coupled onto the AVCC
supply.
Rev. 0 | Page 27 of 75
AD7606C-18
Data Sheet
Channel to Channel Isolation
Box Method
The box method is represented by the following equation:
Channel to channel isolation is a measure of the level of
crosstalk between all input channels. It is measured by applying
a full-scale sine wave signal, up to 200 kHz, to all unselected
input channels and then determining the degree to which the
signal attenuates in the selected channel with a 1 kHz sine wave
signal applied (see Figure 58).
TCVOUT
=
max{VOUT (T ,T2 ,T3 )}−min{VOUT (T ,T2 ,T3)}
1
1
×106
V
OUT (T2 ) × (T3 − T )
1
Phase Delay
where:
TCVOUT is expressed in ppm/°C.
VOUT(TX) is the output voltage at temperature TX.
T1 = −40°C.
T2 = +25°C.
T3 = +125°C.
Phase delay is a measure of the absolute time delay between
when an input is sampled by the converter and when the result
associated with that sample is available to be read back from the
ADC, including delay induced by the analog front end of the
device.
Phase Delay Drift
Phase delay drift is the change in phase delay per unit temperature
across the entire operating temperature of the device.
This box method ensures that TCVOUT accurately portrays the
maximum difference between any of the three temperatures at
which the output voltage of the device is measured.
Phase Delay Matching
Phase delay matching is the maximum phase delay seen between
any simultaneously sampled pair.
Rev. 0 | Page 28 of 75
Data Sheet
AD7606C-18
THEORY OF OPERATION
Figure 75 shows the input clamp current vs. the source voltage
characteristic of the clamp circuit. For input voltages of up to
21 V, no current flows in the clamp circuit. For input voltages
that are above 21 V, the AD7606C-18 clamp circuitry turns on.
15
ANALOG FRONT-END
The AD7606C-18 is an 18-bit, simultaneous sampling, analog-
to-digital DAS with eight channels. Each channel contains
analog input clamp protection, a PGA, an LPF, and an 18-bit
SAR ADC.
T
T
T
= –40°C
= +25°C
= +125°C
A
A
A
Analog Input Ranges
10
5
The AD7606C-18 can handle true bipolar differential, bipolar
single-ended, and unipolar single-ended input voltages. In
software mode, it is possible to configure an individual analog
input range per channel, from Address 0x03 through
Address 0x06. The logic level on the RANGE pin is ignored in
software mode.
0
–5
–10
–15
In hardware mode, the logic level on the RANGE pin determines
either 10 V or 5 V single-ended as the analog input range of
all analog input channels, as shown in Table 10.
–30
–20
–10
0
10
20
30
A logic change on the RANGE pin has an immediate effect on
the analog input range. However, there is typically a settling
time of approximately 80 µs in addition to the normal acquisition
time requirement. Changing the RANGE pin during a conversion
is not recommended for fast throughput rate applications.
SOURCE VOLTAGE (V)
Figure 75. Input Protection Clamp Profile
It is recommended to place a series resistor on the analog input
channels to limit the current to 10 mA for input voltages
greater than 21 V. In an application where there is a series
resistance (R) on an analog input channel, Vx+, it is recommended
to match the resistance (R) with the resistance on Vx− to
eliminate any offset introduced into the system, as shown in
Figure 76. However, in software mode, there is a per channel
system offset calibration that removes the offset of the full
system (see the System Offset Calibration section).
Table 10. Analog Input Range Selection
Range (V)
Hardware Mode1
Software Mode2
10 Single-Ended RANGE pin high
Address 0x03 through
Address 0x06
5 Single-Ended
RANGE pin low
Address 0x03 through
Address 0x06
Any Other Range Not applicable
Address 0x03 through
Address 0x06
During normal operation, it is not recommended to leave the
AD7606C-18 in a condition where the analog input is greater
than the input range for extended periods of time because this
can degrade the bipolar zero code error performance. In shutdown
or standby mode, there is no such concern.
1 The same analog input range, 10 V or 5 V, applies to all eight channels.
2 The analog input range is selected on a per channel basis using the memory
map.
Analog Input Impedance
AD7606C-18
The analog input impedance of the AD7606C-18 is 1 MΩ
minimum. This is a fixed input impedance that does not vary
with the AD7606C-18 sampling frequency. This high analog
input impedance eliminates the need for a driver amplifier in
front of the AD7606C-18, allowing direct connection to the
source or sensor. Therefore, bipolar supplies can be removed
from the signal chain.
1MΩ
R
R
Vx+
Vx–
CLAMP
C
1MΩ
CLAMP
Figure 76. Input Resistance Matching on the Analog Input of the AD7606C-18 for
Single-Ended Ranges (Vx− Tied to Ground)
Analog Input Clamp Protection
Figure 74 shows the analog input circuitry of the AD7606C-18.
Each analog input of the AD7606C-18 contains clamp protection
circuitry. Despite single, 5 V supply operation, the analog input
clamp protection allows an input overvoltage of up to 21 V.
1MΩ
Vx+
Vx–
CLAMP
CLAMP
18-BIT
SAR ADC
1MΩ
LPF
Figure 74. Analog Input Circuitry for Each Channel
Rev. 0 | Page 29 of 75
AD7606C-18
Data Sheet
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
PGA
A PGA is provided at each input channel. The gain is configured
depending on the analog input range selected (see Table 10) to
scale the analog input signal, either bipolar differential or
bipolar or unipolar single-ended, to the ADC fully differential
input range.
±12.5V SINGLE-ENDED
±10V SINGLE-ENDED
±6.25V SINGLE-ENDED
±5V SINGLE-ENDED
±2.5V SINGLE-ENDED
0V to 12.5V SINGLE-ENDED
0V to 10V SINGLE-ENDED
0V to 5V SINGLE-ENDED
±20V DIFFERENTIAL
±12.5V DIFFERENTIAL
±10V DIFFERENTIAL
±5V DIFFERENTIAL
Input impedance on each input of the PGA is accurately
trimmed to keep overall gain error. This trimmed value is then
used when the gain calibration is enabled to compensate for the
gain error introduced by an external series resistor. See the
System Gain Calibration section for more information on the
PGA feature.
fSAMPLE = 1MSPS
A
HIGH BW MODE
T
= 25°C
0.1
1
10
FREQUENCY (kHz)
100 300
Analog Input Antialiasing Filter
Figure 79. Analog Antialiasing Filter Frequency Response, High Bandwidth Mode
An analog antialiasing filter is provided on the AD7606C-18.
Figure 77 and Figure 78 show the frequency response and phase
response, respectively, of the analog antialiasing filter. The
−3 dB frequency is typically 25 kHz.
5
fSAMPLE = 1MSPS
A
T
= 25°C
HIGH BW MODE
4
3
2
1
0
0
fSAMPLE = 1MSPS
A
T
= 25°C
LOW BW MODE
–1
–2
–3
–4
±20V DIFFERENTIAL
±12.5V DIFFERENTIAL
±10V DIFFERENTIAL
±5V DIFFERENTIAL
±12.5V SINGLE-ENDED
±10V SINGLE-ENDED
±6.25V SINGLE-ENDED
±5V SINGLE-ENDED
±2.5V SINGLE-ENDED
0V to 12.5V SINGLE-ENDED
0V to 10V SINGLE-ENDED
0V to 5V SINGLE-ENDED
±5V DIFFERENTIAL
±6.25V SINGLE-ENDED
±10V SINGLE-ENDED
±12.5V SINGLE-ENDED
0V TO 5V SINGLE-ENDED
0V TO 10V SINGLE-ENDED
0V TO 12.5V SINGLE-ENDED
±10V DIFFERENTIAL
±12.5V DIFFERENTIAL
±20V DIFFERENTIAL
±2.5V SINGLE-ENDED
±5V SINGLE-ENDED
0.1
1
10
FREQUENCY (kHz)
100
300
Figure 80. Analog Antialiasing Filter Phase Response, High Bandwidth Mode
0.1
1
10
FREQUENCY (kHz)
100
300
SAR ADC
The AD7606C-18 allows the ADC to accurately acquire an
input signal of full-scale amplitude to 18-bit resolution. All
eight SAR ADCs sample their respective inputs simultaneously
on the rising edge of the CONVST signal.
Figure 77. Analog Antialiasing Filter Frequency Response, Low Bandwidth Mode
10
fSAMPLE = 1MSPS
A
T
= 25°C
9
8
6
5
4
3
1
0
LOW BW MODE
The BUSY signal indicates when conversions are in progress.
Therefore, when the rising edge of the CONVST signal is applied,
the BUSY pin goes logic high and transitions low at the end of
the entire conversion process. The end of the conversion process
across all eight channels is indicated by the falling edge of the
BUSY signal. When the BUSY signal edge falls, the acquisition
time for the next set of conversions begins. The rising edge of the
CONVST signal has no effect while the BUSY signal is high.
±5V DIFFERENTIAL
±10V DIFFERENTIAL
±12.5V DIFFERENTIAL
±20V DIFFERENTIAL
±2.5V SINGLE-ENDED
±5V SINGLE-ENDED
±6.25V SINGLE-ENDED
±10V SINGLE-ENDED
±12.5V SINGLE-ENDED
0V TO 5V SINGLE-ENDED
0V TO 10V SINGLE-ENDED
0V TO 12.5V SINGLE-ENDED
New data can be read from the output register via the parallel or
serial interface after the BUSY output goes low. Alternatively, data
from the previous conversion can be read while the BUSY pin is
high, as explained in the Reading During Conversion section.
0.1
1
10
FREQUENCY (kHz)
100
300
Figure 78. Analog Antialiasing Filter Phase Response, Low Bandwidth Mode
In addition, the AD7606C-18 allows the ADC to enable the high
bandwidth mode, on a per channel basis, that moves the −3 dB
frequency up to 220 kHz, as shown in Figure 79 and Figure 80.
This mode is dedicated for fast analog input settling applications,
as shown in Figure 63 to Figure 68.
Rev. 0 | Page 30 of 75
Data Sheet
AD7606C-18
(Vx+ – Vx–)
PFS (V)
The AD7606C-18 contains an on-chip oscillator that performs
the conversions. The conversion time for all ADC channels is
CODE =
× 131,072
011...111
011...110
tCONV (see Table 3). In software mode, there is an option to
apply an external clock through the CONVST pin. Providing a
low jitter external clock improves SNR performance for large
oversampling ratios. See the Digital Filter section and Figure 15
to Figure 18 for further information.
000...001
000...000
111...111
PFS – (NFS)
LSB =
N
2
100...010
100...001
100...000
Connect all unused analog input channels to AGND. The
results for any unused channels are still included in the data
read because all channels are always converted.
NFS + 1/2LSB 0V – 1/2LSB PFS – 3/2LSB
ANALOG INPUT
Figure 81. AD7606C-18 Ideal Transfer Characteristics, Bipolar Analog Input
Ranges (Twos Complement Output Coding)
ADC Transfer Function
The output coding of the AD7606C-18 is twos complement for
the bipolar analog input ranges, either single-ended or differential.
In unipolar ranges, the output coding is straight binary.
(Vx+ – Vx–)
CODE =
× 262,144
FS (V)
The designed code transitions occur midway between
successive integer LSB values, that is, 1/2 LSB and 3/2 LSB. The
LSB size is FSR/262,144 for the AD7606C-18. Figure 81 shows
the ideal transfer characteristics for the AD7606C-18. The LSB
size is dependent on the analog input range selected, as shown
in Table 11 and Table 12.
111...111
111...110
100...001
100...000
011...111
FS – ZS
N
2
LSB =
000...010
000...001
000...000
ZS + 1/2LSB FS/2 – 1/2LSB
FS – 3/2LSB
ANALOG INPUT
Figure 82. AD7606C-18 Ideal Transfer Characteristics, Unipolar Analog Input
Ranges (Straight Binary Output Coding)
Table 11. Bipolar Input Voltage Ranges
Range
PFS (V)
Midscale (V)
NFS (V)
LSB (μV)
Differential, Bipolar
20 V
12.5 V
10 V
5 V
+20
+12.5
+10
+5
0
0
0
0
−20
−12.5
−10
−5
152.58
95.36
76.3
38.1
Single-Ended, Bipolar
12.5 V
10 V
6.25 V
5 V
+12.5
+10
+6.25
+5
0
0
0
0
0
−12.5
−10
−6.25
−5
95.36
76.3
47.7
38.1
19
2.5 V
+2.5
−2.5
Table 12. Unipolar Input Voltage Ranges
Range
FS (V)
Midscale (V)
ZS (V)
LSB (μV)
Single-Ended, Unipolar
0 V to 12.5 V
0 V to 10 V
12.5
10
5
6.25
5
2.5
0
0
0
47.7
38.1
19
0 V to 5 V
Rev. 0 | Page 31 of 75
AD7606C-18
Data Sheet
REFERENCE
AD7606C-18
REF SELECT
AD7606C-18
REF SELECT
AD7606C-18
REF SELECT
The AD7606C-18 contains an on-chip, 2.5 V, band gap reference.
The REFIN/REFOUT pin allows either of the following:
REFIN/REFOUT
REFIN/REFOUT
REFIN/REFOUT
•
Access to the internal 2.5 V reference if the
REF SELECT pin is tied to logic high
100nF
100nF
100nF
•
Application of an external reference of 2.5 V if the REF
SELECT pin is tied to logic low
REF
1µF
Table 13. Reference Configuration
REF SELECT Pin Reference Selected
Figure 84. Single External Reference Driving Multiple AD7606C-18
REFIN/REFOUT Pins
Logic High
Logic Low
Internal reference enabled
Internal Reference Mode
Internal reference disabled, an external 2.5 V
reference voltage must be applied to the
REFIN/REFOUT pin
One AD7606C-18 device, configured to operate in the internal
reference mode, can drive the remaining AD7606C-18 devices,
which are configured to operate in external reference mode (see
Figure 85). Decouple the REFIN/REFOUT pin of the
The AD7606C-18 contains a reference buffer configured to gain
the reference voltage up to approximately 4.4 V, as shown in
Figure 83. The 4.4 V buffered reference is the reference used by the
SAR ADC, as shown in Figure 83. After a reset, the AD7606C-18
operates in the reference mode selected by the REF SELECT pin.
The REFCAPA and REFCAPB pins must be shorted together
externally, and a ceramic capacitor of 10 μF must be applied to
the REFGND pin to ensure that the reference buffer is in closed-
loop operation. A 0.1 µF ceramic capacitor is required on the
REFIN/REFOUT pin.
AD7606C-18, configured in internal reference mode, using a 10 µF
ceramic decoupling capacitor. The other AD7606C-18 devices,
configured in external reference mode, must use at least a 100 nF
decoupling capacitor on their REFIN/REFOUT pins.
V
DRIVE
AD7606C-18
REF SELECT
AD7606C-18
REF SELECT
AD7606C-18
REF SELECT
REFIN/REFOUT
REFIN/REFOUT
REFIN/REFOUT
When the AD7606C-18 is configured in external reference mode,
the REFIN/REFOUT pin is a high input impedance pin.
REFIN/REFOUT
+
10µF
100nF
100nF
Figure 85. Internal Reference Driving Multiple AD7606C-18 REFIN/REFOUT Pins
SAR
OPERATION MODES
REFCAPA
BUF
The AD7606C-18 can be operated in hardware or software mode
by controlling the OSx pins, as described in Table 14.
10µF
REFCAPB
In hardware mode, the AD7606C-18 is configured depending on
2.5V
REF
the logic level on the RANGE, OSx, or
pins. The AD7606C-
STBY
18 is backwards compatible to the AD7606, AD7606B, AD7608,
and AD7609.
Figure 83. Reference Circuitry
In software mode, when all three OSx pins are connected to logic
high level, the AD7606C-18 is configured by the corresponding
registers accessed via the serial or parallel interface. Additional
features are available, as described in Table 15. The reference
and the data interface is selected through the REFSELECT and
Using Multiple AD7606C-18 Devices
For applications using multiple AD7606C-18 devices, the
configurations in the External Reference Mode section and the
Internal Reference Mode section are recommended, depending
on the application requirements.
/SER SEL pins in both hardware and software modes.
PAR
External Reference Mode
Table 14. Oversample Pin Decoding
One external reference can drive the REFIN/REFOUT pins of
all AD7606C-18 devices (see Figure 84). In this configuration,
decouple each REFIN/REFOUT pin of the AD7606C-18 with at
least a 100 nF decoupling capacitor.
OS2
0
OS1
0
OS0
0
AD7606C-18
No oversampling
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
Enters software mode
Rev. 0 | Page 32 of 75
Data Sheet
AD7606C-18
Table 15. Functionality Matrix
Parameter
Analog Input Range1
Hardware Mode
10 V or 5 V2
Software Mode
Single-ended, bipolar: 12.5 V, 10 V, 6.25 V, 5 V, and 2.5 V3
Single-ended, unipolar: 0 V to 12.5 V, 0 V to 10 V, 0 V to 5 V3
Differential, bipolar: 20 V, 12.5 V, 10 V, and 5 V3
Available3
System Gain, Phase, and Offset Calibration Not accessible
OSR
From no oversampling to
From no oversampling to OSR = 256
OSR = 64
Not accessible
2
Not accessible
Standby and shutdown
Analog Input Open Circuit Detection
Serial Data Output Lines
Diagnostics
Available3
Selectable: 1, 2, 4, or 8
Available
Power-Down Modes
Standby, shutdown, and autostandby
1 See Table 10 for the analog input range selection.
2 Same input range configured in all input channels.
3 On a per channel basis
Power-Down Modes
Reset Functionality
In hardware mode, two power-down modes are available on the
The AD7606C-18 has two reset modes: full or partial. The reset
mode selected is dependent on the length of the reset high pulse. A
partial reset requires the RESET pin to be held high between
55 ns and 2 μs. After 50 ns from the release of the RESET pin
(tDEVICE_SETUP, partial reset), the device is fully functional and a
conversion can be initiated. A full reset requires the RESET pin to
STBY
AD7606C-18: standby mode and shutdown mode. The
controls whether the AD7606C-18 is in normal mode or in one of
STBY
pin
the two power-down modes, as shown in Table 16. If the
pin
is low, the power-down mode is selected by the state of the
RANGE pin.
be held high for a minimum of 3.2 µs. After 274 μs (tDEVICE_SETUP
full reset) from the release of the RESET pin, the device is
completely reconfigured and a conversion can be initiated.
,
Table 16. Power-Down Mode Selection, Hardware Mode
STBY Pin
Power Mode
Normal
Standby
RANGE Pin
X1
1
0
1
0
0
A partial reset reinitializes the following modules:
•
•
•
•
Digital filter
SPI and parallel, resetting to ADC mode
SAR ADCs
CRC logic
Shutdown
1 X = don’t care.
In software mode, the power-down mode is selected through
the OPERATION_MODE bits on the CONFIG register
(Address 0x02, Bits[1:0]), within the memory map. There is an
extra power-down mode available in software mode called
autostandby mode.
After the partial reset, the RESET_DETECT bit on the status
register asserts (Address 0x01, Bit 7). The current conversion
result is discarded after the completion of a partial reset. The
partial reset does not affect the register values programmed in
software mode or the latches that store the user configuration
in both hardware and software modes.
Table 17. Power-Down Mode Selection, Software Mode,
Through CONFIG Register (Address 0x02)
Operation Mode Address 0x02, Bit 1 Address 0x02, Bit 0
A full reset returns the device to its default power-on state, the
RESET_DETECT bit on the status register asserts (Address 0x01,
Bit 7), and the current conversion result is discarded. The
following features, in addition to those listed above, are
configured when the AD7606C-18 is released from full reset:
Normal
Standby
Autostandby
Shutdown
0
0
1
1
0
1
0
1
When the AD7606C-18 is placed in shutdown mode, all circuitry
is powered down and the current consumption reduces to
4.5 µA maximum. The power-up time is approximately 10 ms.
When the AD7606C-18 is powered up from shutdown mode, a
full reset must be applied to the AD7606C-18 after the required
power-up time elapses.
•
•
Hardware mode or software mode
Interface type, serial or parallel
Rev. 0 | Page 33 of 75
AD7606C-18
Data Sheet
CONVST
BUSY
When the AD7606C-18 is placed in standby mode, all of the PGAs
and all of the SAR ADCs enter a low power mode, such that the
overall current consumption reduces to 6.5 mA maximum. No
reset is required after exiting standby mode.
STANDBY
NORMAL
tWAKE_UP
STANDBY
POWER MODE
When the AD7606C-18 is placed in autostandby mode, which is
available only in software mode, the device automatically enters
standby mode on the BUSY signal falling edge. The AD7606C-18
exits standby mode automatically on the CONVST signal rising
edge. Therefore, the CONVST signal low pulse time is longer
than tWAKE_UP (standby mode) = 1 μs (see Figure 86).
Figure 86. Autostandby Mode Operation
Rev. 0 | Page 34 of 75
Data Sheet
AD7606C-18
DIGITAL FILTER
The AD7606C-18 contains an optional digital averaging filter
that can be enabled in slower throughput rate applications that
require higher SNR or dynamic range.
For example, if oversampling by eight is configured, eight
samples are taken, averaged, and the result is provided on the
output. A CONVST signal rising edge triggers the first sample,
and the remaining seven samples are taken with an internally
generated sampling signal (OS_CLOCK). Consequently,
turning on the averaging of multiple samples leads to an
improvement in SNR performance at the expense of reducing the
maximum throughput rate. When the oversampling function is
turned on, the BUSY signal high time (tCONV) extends, as shown in
Table 3.
In hardware mode, the oversampling ratio of the digital filter is
controlled using the oversampling pins, OSx, as shown in Table 14.
The OSx pins are latched on either the falling edge of the BUSY
signal or upon a full reset.
In software mode, if all OSx pins are tied to logic high, the
oversampling ratio is selected through the oversampling register
(Address 0x08). Two additional oversampling ratios
(oversampling by 128 and oversampling by 256) are available in
software mode.
Table 18 and Table 19 show the trade off in SNR vs. bandwidth
and throughput for the 10 V single-ended range, 20 V
differential range, and 0 V to 10 V single-ended range.
In oversampling mode, the ADC takes the first sample for each
channel on the rising edge of the CONVST signal. After
converting the first sample, the subsequent samples are taken
by the internally generated sampling signal, as shown in Figure 87.
Alternatively, this sampling signal can be applied externally as
described in the External Oversampling Clock section.
Figure 87 shows that the conversion time (tCONV) extends when
oversampling is turned on. The throughput rate (1/tCYCLE) must
be reduced to accommodate the longer conversion time and to
allow the read operation to occur. To achieve the fastest
throughput rate possible when oversampling is turned on, the
read can be performed during the BUSY signal high time, as
explained in the Reading During Conversion section.
tCYCLE
CONVST
OS_CLOCK
BUSY
tCONV
CS
RD
DB0 TO
DB17
Figure 87. AD7606C-18 Oversampling by 8 Example, Read After Conversion, Parallel Interface, OS_CLOCK Is the Internally Generated Sampling Signal
Table 18. Oversampling Performance, Low Bandwidth Mode
10 V Single-Ended
Range
20 V Differential
Range
0 V to 10 V Single-
Ended Range
−3 dB
Bandwidth
SNR (dB) (kHz)
−3 dB
Bandwidth SNR
SNR (dB) (kHz)
−3 dB
Maximum
Oversampling
Ratio
Input
Frequency (Hz)
Bandwidth Throughput
(kHz)
(dB)
(kSPS)
1000
500
250
125
62.5
31.25
15.6
7.8
No oversampling 1000
2
4
8
16
32
64
128
256
92.5
94.5
96.5
98
98.5
102
102.5
104.5
105
25
24.6
24
22.3
17.8
11.6
6.5
93
95
25
90
25
24.6
24
22.3
17.8
11.6
6.4
1000
1000
1000
1000
160
160
50
24.4
23.7
22.2
17.6
11.5
6.4
91.5
92.3
93.3
94.3
96
97.5
99
100
97.2
98.5
99.1
102
102.5
104.4
104.7
3.3
1.7
3.4
1.7
3.3
1.7
50
3.9
Rev. 0 | Page 35 of 75
AD7606C-18
Data Sheet
Table 19. Oversampling Performance, High Bandwidth Mode
10 V Single-Ended
Range
20 V Differential
Range
0 V to 10 V Single-
Ended Range
−3 dB
Bandwidth
SNR (dB) (kHz)
−3 dB
Bandwidth
SNR (dB) (kHz)
−3 dB
Maximum
Oversampling
Ratio
Input
Frequency (Hz)
Bandwidth Throughput
SNR (dB) (kHz)
(kSPS)
1000
500
250
125
62.5
31.25
15.6
7.8
No oversampling 1000
2
4
8
16
32
64
128
256
87
89
92
95
96.5
99.8
101.5
104
104.5
220
154
97.5
53
27.5
13.8
7
89
220
154
97.5
53
27.5
13.7
7
82
84.5
87
89.5
91.5
94
95.5
97
220
155
97.5
53.5
27.5
13.8
7
1000
1000
1000
1000
160
160
50
91.5
94.5
96.5
98
100.5
101.5
105
3.5
1.7
3.5
1.7
3.5
1.7
50
105.2
97.7
3.9
Rev. 0 | Page 36 of 75
Data Sheet
AD7606C-18
That is, the sampling signal is provided externally through the
CONVST pin, and after every OSR number of clocks, an output
is averaged and provided, as shown in Figure 90. This feature is
available using either the parallel interface or serial interface.
PADDING OVERSAMPLING
As shown in Figure 87, an internally generated clock triggers
the samples to be averaged, and then the ADC remains idle
until the following CONVST signal rising edge. In software
mode, through the oversampling register (Address 0x08), the
internal clock (OS_CLOCK) frequency can be changed such that
idle time is minimized and sampling instants are equally spaced,
as shown in Figure 88. As a result, the actual oversampling clock
frequency depends on the OS_PAD bits configuration, as per
the following equation:
Simultaneous Sampling of Several AD7606C-18 Devices
In general, synchronizing several SAR ADCs is achieved by
using a common CONVST signal. However, when oversampling is
enabled, an internal clock is used to trigger the subsequent
samples by default. Any deviation between these internal clocks
may impede device to device synchronization. This deviation
can be minimized by using external oversampling, as the
CONVST signal of all the samples is managed externally.
1
OS_CLOCK(kHz) =
OS_PAD
1000 ×(1+
)
16
A partial reset (tRESET < 2 µs) interrupts the oversampling
process and empties the data register. Therefore, if by any
reason the different AD7606C-18 devices are not synchronized,
issuing a partial reset resynchronizes the devices, as shown in
Figure 89.
tCYCLE
CONVST
OS_CLOCK
BUSY
tCONV
RESET
Figure 88. Oversampling by 8 Example, Oversampling Padding Enabled
EXTERNAL OVERSAMPLING CLOCK
AD7606C-18
BUSY1
AD7606C-18
BUSY2
AD7606C-18
BUSY3
In software mode, there is an option to apply an external clock
through the CONVST pin when oversampling mode is enabled.
Providing a low jitter external clock helps improve SNR
performance for large oversampling ratios. By applying an
external clock, the input is sampled at regular time intervals,
which is optimum for antialiasing performance.
CONVST
CONVST
RESET
BUSY1
BUSY2
BUSY3
To enable the external oversampling clock, Bit 5 in the CONFIG
register (Address 0x02, Bit 5) must be set. Then, the throughput
rate is
Figure 89. Synchronizing Several AD7606C-18 Devices When External
Oversampling Clock Is Enabled
1
Throughput =
t
CYCLE × OSR
tCYCLE
CONVST
BUSY
CS
RD
DB0 TO
DB17
Figure 90. External Oversampling Clock Applied on the CONVST Pin (OSR = 4), Parallel Interface
Rev. 0 | Page 37 of 75
AD7606C-18
Data Sheet
SYSTEM CALIBRATION FEATURES
The following system calibration features are available in
software mode by writing to corresponding registers in the
memory map:
Note that system gain calibration is only available on bipolar
analog input ranges, both single-ended and differential. System
gain calibration is not available in unipolar single-ended ranges.
AD7606C-18
•
•
•
•
Phase calibration
Gain calibration
Offset calibration
Analog input open circuit detection
ANALOG
INPUT
SIGNAL
R
1MΩ
1MΩ
FILTER
Vx+
Vx–
C
R
FILTER
SYSTEM PHASE CALIBRATION
Figure 92. System Gain Error
When using an external filter, as shown in Figure 92, any
mismatch on the discrete components or in the sensor used can
cause phase mismatch between channels. This phase mismatch
can be compensated for in software mode, on a per channel basis,
by delaying the sampling instant on individual channels.
For example, if a 27 kΩ resistor is placed in series to the analog
input of Channel 5, the resistor generates about −2% positive
full-scale error on the system (at 10 V range), as seen in Figure 93.
In software mode, this error is eliminated by writing 27 decimal
to the CH5_GAIN register (Address 0x0D).
The sampling instant on any particular channel can be delayed
with regards to the CONVST signal rising edge, with a
resolution of 1 μs, and up to 255 μs, by writing to the
corresponding CHx_PHASE register (Address 0x19 through
Address 0x20).
0.1
0
–0.1
–1000
–0.5
–2000
For example, if the CH4_PHASE register (Address 0x1C) is
written with 10 decimal, Channel 4 is effectively sampled 10 μs
after the CONVST signal rising edge, as shown in Figure 91.
–1
–3000
–4000
–5000
INPUT V1
INPUT V4
–2
ON-CHIP CALIBRATION ENABLE
ON-CHIP CALIBRATION DISABLED
–6000
CONVST
0
10
20
30
40
50
60
INTERNAL
CONVST CH1
n
R
(kΩ)
FILTER
INTERNAL
CONVST CH4
Figure 93. System Gain Calibration, with and Without Calibration,
10 V Single-Ended Range
tCONV = n+1
BUSY
SYSTEM OFFSET CALIBRATION
V1 CODE
V4 CODE
A potential offset on the sensor, or any offset caused by a mismatch
between the RFILTER pair placed on a particular channel (as
described in the Analog Front-End section), can be compensated
in software mode on a per channel basis. The CHx_OFFSET
registers (Address 0x11 through Address 0x18) allow the ability
to add or subtract up to 512 LSBs to the ADC code automatically
with a resolution of 4 LSB, as shown in Table 20.
Figure 91. System Phase Calibration Functionality
Note that delaying any channel extends the BUSY signal high
time, and tCONV extends until tCONV = n + 1 μs, with n as the
CHx_PHASE register content of the most delayed channel. In
the previously explained example, if only the CH4_PHASE
register is programmed, tCONV is 11 μs. Therefore, this scenario
must be considered when running at higher throughput rates.
For example, if the signal connected to Channel 3 has a 9 mV
offset, and the analog input range is set to 10 V range (where
LSB size = 76.3 μV) to compensate for this offset, program
−30 LSB to the corresponding register (that is, 9 mV/76.3 μV/4).
Writing 128 decimal – 30 decimal = 0x80 − 0x1E = 0x62 into
the CH3_OFFSET register (Address 0x13) removes such offset.
SYSTEM GAIN CALIBRATION
Using an external RFILTER, which is a resistor placed in a series to
the analog input front-end, see Figure 92, generates a system
gain error. This gain error can be compensated for in software
mode, on a per channel basis, by writing the series resistor
value used on the corresponding register, Address 0x09
through Address 0x10. These registers can compensate up to
65 kΩ series resistors with a resolution of 1024 Ω.
Rev. 0 | Page 38 of 75
Data Sheet
AD7606C-18
Table 20. CHx_OFFSET Register Bit Decoding
Manual Mode
CHx_OFFSET Register Code
Offset Calibration (LSB)
Manual mode is enabled by writing 0x01 to the OPEN_DETECT_
QUEUE register (Address 0x2C). In manual mode, each PGA
common-mode voltage is controlled by the corresponding
CHx_OPEN_DETECT_EN bit on the OPEN_DETECT_ENABLE
register (Address 0x23). Setting this bit high shifts up the PGA
common-mode voltage. If there is an open circuit on the analog
input, the ADC output changes proportionally to the RPD, as
shown in Figure 95. If there is not an open circuit, any change on
the PGA common-mode voltage has no effect on the ADC output.
0x00
0x45
0x80 (Default)
0x83
0xFF
−512
−236
0
+12
+508
ANALOG INPUT OPEN CIRCUIT DETECTION
The AD7606C-18 has an analog input open circuit detection
feature available in software mode. To use this feature, an RPD
must be placed as shown in Figure 94. If the analog input is
disconnected, for example, if a switch opens in Figure 94, the
source impedance changes from the burden resistor (RS) to RPD
as long as RS < RPD. It is recommended to use RPD = 20 kΩ so
that the AD7606C-18 can detect changes in the source
impedance by internally switching the PGA common-mode
voltage. Analog input open circuit detection operates in manual
mode or in automatic mode.
1600
±2.5V SINGLE-ENDED
±5V SINGLE-ENDED
±6.25V SINGLE-ENDED
±10V SINGLE-ENDED
1400
,
1200
±12.5V SINGLE-ENDED
±5V DIFFERENTIAL
1000
±10V DIFFERENTIAL
±12.5V DIFFERENTIAL
±20V DIFFERENTIAL
800
600
400
200
0
AD7606C-18
R
FILTER
1MΩ
Vx+
C
SAR
ADC
FILTER
Vx–
R
R
S
PD
R
0
10
20
30
40
50
(kΩ)
60
70
80
90
100
FILTER
1MΩ
R
PD
Figure 95. Open Circuit Code Error increment, Dependent of RPD
Figure 94. Analog Front End with RPD
Note that analog input open circuit detection is only available
on bipolar analog input ranges, both single-ended and
differential. Analog input open circuit detection is not available
in unipolar single-ended ranges.
Rev. 0 | Page 39 of 75
AD7606C-18
Data Sheet
If no oversampling is used, the recommended minimum number
of conversions to be programmed for the AD7606C-18 to
automatically detect an open circuit on the analog input is
Automatic Mode
Automatic mode is enabled by writing any value greater than
0x01 to the OPEN_DETECT_QUEUE register (Address 0x2C),
as shown in Table 21. If the AD7606C-18 detects that the ADC
reported a number (specified in the OPEN_DETECT_QUEUE
register) of consecutive unchanged conversions, the analog input
open circuit detection algorithm is performed internally and
automatically. The analog input open circuit detection algorithm
automatically changes the PGA common-mode voltage, checks
the ADC output, and returns to the initial common-mode voltage,
as shown in Figure 96. If the ADC code changes in any channel
with the PGA common-mode change, this implies there is
no input signal connected to that analog input, and the
corresponding flag asserts within the OPEN_DETECTED
register (Address 0x24). Each channel can be individually
enabled or disabled through the OPEN_DETECT_ENABLE
register (Address 0x23).
OPEN _DETECT_QUEUE =
10 × fSAMPLE
R
+ 2 × RFILTER × (C
+10 pF)
FILTER
PD
However, when oversampling mode is enabled, the
recommended minimum number of conversions to use is
OPEN _DETECT_QUEUE =
1 + f
× 2 R + 2 × RFILTER × (C
+10 pF) × OSR
FILTER
(
)
SAMPLE
PD
START
CONVERSION
NO
0 < ADC CODE < 1400 LSB
i = 0
YES
N = NUMBER OF
NO
CONSECUTIVE REPEATED
i = N?
(WITHIN 10 LSB)
i = i + 1
ADC OUTPUT CODE
YES, SET
COMMON-MODE HIGH
NO
ΔADC CODE > 20 LSB
i = 0
YES, SET
COMMON-MODE LOW
NO
ADC CODE BACK
TO ORIGINAL?
i = 0
YES
ERROR FLAG
Figure 96. Automatic Analog Input Open Circuit Detect Flowchart
Table 21. Analog Input Open-Circuit Detect Mode Selection and Register Functionality
OPEN_DETECT_QUEUE
(Address 0x2C)
0x00 (Default)
0x01
Open Detect Mode
Disabled.
Manual.
OPEN_DETECT_ENABLE (Address 0x23)
Not applicable.
Sets common-mode voltage high or low on a
per channel basis.
Enables or disables automatic analog input
open circuit detection on a per channel basis.
0x021 to 0xFF
Automatic. OPEN_DETECT_QUEUE is the number of
consecutive conversions before asserting any CHx_OPENED flag.
1 It is recommended to write to OPEN_DETECT_QUEUE a value greater than 5.
Rev. 0 | Page 40 of 75
Data Sheet
AD7606C-18
DIGITAL INTERFACE
The AD7606C-18 provides two interface options: a parallel
interface and a high speed serial interface. The required
See the Reading Conversion Results (Parallel ADC Mode) section
and the Reading Conversion Results (Serial ADC Mode) section
for more details on how the ADC mode operates.
PAR
interface mode is selected via the
/SER SEL pin.
Software Mode
Table 22. Interface Mode Selection
In software mode, which is active only when all three OSx pins are
tied high, both ADC mode and register mode are available. ADC
data can be read from the AD7606C-18, and registers can also
be read from and written to the AD7606C-18 via the parallel
PAR/SER SEL Setting
Interface Mode
0
1
Parallel interface
Serial interface
Operation of the interface modes is discussed in the Hardware
Mode section and the Software Mode section.
CS RD
WR
data bus with standard
,
, and
signals or via the serial
CS
interface with standard , SCLK, SDI, and DOUTA lines.
Hardware Mode
See the Parallel Register Mode (Writing Register Data) section
and the Parallel Register Mode (Reading Register Data) section
for more details on how register mode operates.
In hardware mode, only ADC mode is available. ADC data can
be read from the AD7606C-18 via the parallel data bus with
CS
RD
standard
and
signals or via the serial interface with
Pin functions differ depending on the interface selected
(parallel or serial) and the operation mode (hardware or
software), as shown in Table 23.
CS
standard , SCLK, and two DOUTx signals.
Table 23. Data Interface Pin Function per Mode of Operation
Parallel Interface
Serial Interface
Software Mode
Software Mode
Hardware Mode ADC Mode Register Mode
Pin Mnemonic Pin No.
Hardware Mode
ADC Mode
Register Mode
N/A
DB2 to DB4
16 to 18
19
DB2 to DB4
DB5
Register data
Register data
Register data
Register data
Register data
N/A1
N/A
N/A
N/A
N/A
DB5/DOUT
DB6/DOUT
DB7/DOUT
DB8/DOUT
DB9/DOUT
E
DOUTE2
DOUTF2
DOUTG2
DOUTH2
Unused
Unused
Unused
Unused
F
20
DB6
G
H
A
21
DB7
22
DB8
24
DB9
Register data (MSB) DOUT
A
B
DOUT
A
DOUTA
DB10/DOUT
DB11/DOUT
DB12/DOUT
DB13/SDI
B
C
D
25
DB10
ADD0
ADD1
ADD2
ADD3
ADD4
ADD5
ADD6
DOUT
N/A
N/A
N/A
N/A
N/A
N/A
N/A
DOUTB3
DOUTC4
DOUTD4
Unused
Unused
Unused
Unused
SDI
27
DB11
28
DB12
29
DB13
DB14 to DB16
DB15
30
DB14
N/A
31
DB15
N/A
DB16/DB0
DB17/DB1
32
DB16/DB05
DB17/DB15
N/A
33
W
R/
N/A
1 N/A means not applicable. Tie all N/A pins to AGND.
2 Only used if 8 DOUTx mode is selected on the CONFIG register, otherwise leave unconnected.
3 Only used if 2 DOUTx, 4 DOUTx, or 8 DOUTx mode is selected on the CONFIG register, otherwise leave unconnected.
4 Only used if 4 DOUTx or 8 DOUTx mode is selected on the CONFIG register, otherwise leave unconnected.
5 Pin functionality depends on whether it is the first or second read frame during an ADC read operation, see Figure 99.
Rev. 0 | Page 41 of 75
AD7606C-18
Data Sheet
The parallel interface consists of 16 parallel lines on Pin 16 to
Pin 22 and Pin 24 to Pin 33. Because the ADC data is 18 bit,
two parallel frames are required as follows:
PARALLEL INTERFACE
To read ADC data, or to read and write the register content
over the parallel interface, tie the
PAR
/SER SEL pin low.
•
•
1st frame clocks out ADC data from Bit 2 to Bit 17 (MSB)
2nd frame clocks out ADC data from Bit 1 and Bit 0 (LSB)
CS
CS
CS
The rising edge of the
the falling edge of the
high impedance state.
input signal three-states the bus, and
input signal takes the bus out of the
is the control signal that enables the
CS
RD
signal
The
signal can be permanently tied low, and the
data lines and it is the function that allows multiple AD7606C-18
devices to share the same parallel data bus.
can access the conversion results, as shown in Figure 3. A read
operation of new data can take place after the BUSY signal goes
low (see Figure 2). Alternatively, a read operation of data from
the previous conversion process can take place while the
BUSY pin is high.
AD7606C-18
INTERRUPT
BUSY 14
13
12
CS
When there is only one AD7606C-18 in a system and it does
not share the parallel bus, data can be read using one control
RD/SCLK
DIGITAL
HOST
CS
RD
signal from the digital host. The
together, as shown in Figure 4. In this case, the falling edge of
CS RD
signals brings the data bus out of three-state and
and
signals can be tied
WR 10
24 TO 33
16 TO 22
DB17 TO DB0
the
and
clocks out the data.
Figure 97. AD7606C-18 Interface Diagram—One AD7606C-18 Using the
CS RD
Parallel Bus with and
Shorted Together
The FRSTDATA output signal indicates when the first channel,
CS
V1, is being read back, as shown in Figure 4. When the
input is high, the FRSTDATA output pin is in three-state. The
CS
Reading Conversion Results (Parallel ADC Mode)
RD
The falling edge of the
conversion results register. Applying a sequence of
RD
pin reads data from the output
falling edge of
takes the FRSTDATA pin out of three-state.
RD
RD
pulses
pin clocks the conversion results out from each
The falling edge of the
signal corresponding to the result of
to the
V1 sets the FRSTDATA pin high, indicating that the result
from V1 is available on the output data bus. The FRSTDATA
pin returns to a logic low following the next falling edge of
channel onto the parallel bus, DB17 to DB0, in ascending order,
from V1 to V8, as shown in Figure 98.
RD
.
CONVST
BUSY
CS
RD
V7[1]
V7[0]
V8[1]
V8[0]
V1[17]
V1[1]
V1[0]
V2[17]
V2[1]
V2[0]
V7[17]
V8[17]
DB17/DB1
V1[16]
V1[15]
V1[14]
V1[13]
V1[12]
V1[11]
V1[10]
V2[16]
V2[15]
V2[14]
V2[13]
V2[12]
V2[11]
V2[10]
V7[16]
V7[15]
V7[14]
V7[13]
V7[12]
V7[11]
V7[10]
V8[16]
V8[15]
V8[14]
V8[13]
V8[12]
V8[11]
V8[10]
DB16/DB0
DB15
DB14
DB13
DB12
DB11
DB10
STATUS7[7]
STATUS7[6]
STATUS7[5]
STATUS7[4]
STATUS7[3]
STATUS7[2]
STATUS7[1]
STATUS7[0]
STATUS8[7]
STATUS8[6]
STATUS8[5]
STATUS8[4]
STATUS8[3]
STATUS8[2]
STATUS8[1]
STATUS8[0]
V1[9]
V1[8]
V1[7]
V1[6]
V1[5]
V1[4]
V1[3]
V1[2]
STATUS1[7]
STATUS1[6]
STATUS1[5]
STATUS1[4]
STATUS1[3]
STATUS1[2]
STATUS1[1]
STATUS1[0]
V2[9]
V2[8]
V2[7]
V2[6]
V2[5]
V2[4]
V2[3]
V2[2]
STATUS2[7]
STATUS2[6]
STATUS2[5]
STATUS2[4]
STATUS2[3]
STATUS2[2]
STATUS2[1]
STATUS2[0]
V7[9]
V7[8]
V7[7]
V7[6]
V7[5]
V7[4]
V7[3]
V7[2]
V8[9]
V8[8]
V8[7]
V8[6]
V8[5]
V8[4]
V8[3]
V8[2]
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
Figure 98. Parallel Interface, ADC Mode with Status Header Enabled
Rev. 0 | Page 42 of 75
Data Sheet
AD7606C-18
Reading During Conversion
Parallel ADC Mode with Status Enabled
Data read operations from the AD7606C-18, as shown in
Figure 99, can occur in the following three scenarios:
In software mode, the 8-bit status header is enabled (see Table 25)
by setting Bit 6 in the CONFIG register (Address 0x02, Bit 6),
and each channel then takes the following two frames of data:
•
•
•
After a conversion while the BUSY line is low
During a conversion while the BUSY line is high
Starting while the BUSY line is low and ending while the
following conversion is in progress, see Figure 2
•
The first frame clocks the ADC data out normally through
DB17 to DB2 from the MSB to Bit 2.
•
The second frame clocks out the status header of the channel
on DB9 to DB2, DB9 being the MSB and DB2 being the
LSB of the status header, while DB1 to DB0 clock out the
two LSBs of the conversion result and the DB15 to DB10
pins clock out zeros.
Reading during conversions has little effect on the performance
of the converter, and it allows a faster throughput rate to be
achieved. Data can be read from the AD7606C-18 at any time
other than on the falling edge of the BUSY signal because this is
when the output data registers are updated with the new
conversion data. Any data read while the BUSY signal is high
must be completed before the falling edge of the BUSY signal.
This sequence is shown in Figure 98. Table 25 explains the
status header content and describes each bit.
Table 24. CH.ID Bits Decoding in Status Header
Parallel ADC Mode with CRC Enabled
CH.ID2
CH.ID1
CH.ID0
Channel Number
Channel 1 (V1)
Channel 2 (V2)
Channel 3 (V3)
Channel 4 (V4)
Channel 5 (V5)
Channel 6 (V6)
Channel 7 (V7)
Channel 8 (V8)
In software mode, the parallel interface supports reading the
ADC data with the CRC appended, when enabled through the
INT_CRC_ERR_EN bit (Address 0x21, Bit 2). The CRC is
16 bits, and it is clocked out after reading all eight channel
conversions, as shown in Figure 100. The CRC calculation
includes all data on the DBx pins: data, status (when appended),
and zeros. See the Diagnostics section for more details on CRC.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 25. Status Header, Parallel Interface
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Content
RESET_DETECT DIGITAL_ERROR OPEN_DETECTED
RESERVED
CH. ID 2 CH. ID 1 CH. ID 0
Channel ID (see Table 24)
Meaning1 Reset detected
Error flag on
Address 0x22
The analog input of
this channel is open
1 See the Diagnostics section for more information.
CONVST
tACQ_C
tACQ_B
BUSY
tCONV_A
tCONV_B
D
x
DBx
OUT
ADC_DATA
ADC_DATA
B
A
Figure 99. ADC Data Read Can Happen After Conversion and/or During the Following Conversion
CONVST
BUSY
CS
RD
DBx
CRC
V1[17:2]
V1[1:0]
V2[17:2]
V2[1:0]
V7[17:2]
V7[1:0]
V8[17:2]
V8[1:0]
Figure 100. Parallel Interface, ADC Mode with CRC Enabled
Rev. 0 | Page 43 of 75
AD7606C-18
Data Sheet
Parallel Register Mode (Reading Register Data)
WR
To revert to ADC mode, keep all DBx pins low during one
cycle, as shown in the Parallel Register Mode (Writing Register
Data) section. No ADC data can be read while the device is in
register mode.
In software mode, all of the registers in Table 31 can be read over
the parallel interface. Bits[DB17:DB2] leave a high impedance
CS
RD
state when both the
signal and
signal are logic low for
CS WR
reading register content, or when both the
signal and
Parallel Register Mode (Writing Register Data)
signal are logic low for writing register address and/or register
content.
In software mode, all of the R/W registers in Table 31 can be
written to over the parallel interface. To write a sequence of
registers, exit ADC mode (default mode) by reading any register
on the memory map. A register write command is performed by
A register read is performed through two frames: first, a read
command is sent to the AD7606C-18 and second, the
AD7606C-18 clocks out the register content. The format for a
register read command is shown in Figure 101. On the first
frame, perform the following:
CS
a single frame, via the parallel bus (Bits[DB17:DB2]),
signal,
signal. The format for a write command, as shown in
Figure 101, is structured as follows:
WR
and
•
Bit DB17 must be set to 1 to select a read command. The
read command puts the AD7606C-18 into register mode.
Bits[DB16:DB10] must contain the register address.
The subsequent eight bits, Bits[DB9:DB2], are ignored.
•
•
•
Bit DB17 must be set to 0 to select a write command.
Bits[DB16:DB10] contain the register address.
The subsequent eight bits, Bits[DB9:DB2], contain the data
to be written to the selected register.
•
•
The register address is latched on the AD7606C-18 on the
WR
WR
Data is latched onto the device on the rising edge of the
pin.
rising edge of the
signal. The register content can then be
To revert back to ADC mode, keep all DBx pins low during one
WR
RD
read from the latched register by bringing the
the following frame, as follows:
line low on
cycle. No ADC data can be read while the device is in
register mode.
•
•
•
Bit DB17 is pulled to 0 by the AD7606C-18.
Bits[DB16: DB10] provide the register address being read.
The subsequent eight bits, Bits[DB9: DB2], provide the
register content.
CS
RD
WR
DB17
R/W = 1
R/W = 0
R/W = 0
R/W = 0
DB10 TO
DB16
REG. ADDRESS
REG. ADDRESS
REG. ADDRESS
ADDRESS = 0x00
DB2 TO
DB9
DON’T CARE
REGISTER DATA
REGISTER DATA
DON’T CARE
MODE
ADC MODE
REGISTER MODE
ADC MODE
Figure 101. Parallel Interface Register Read Operation Followed by a Write Operation
Rev. 0 | Page 44 of 75
Data Sheet
AD7606C-18
CS
SERIAL INTERFACE
To read ADC data or to read and write the register content over
SCLK
PAR
the serial interface, tie the
/SER SEL pin high.
D
D
A
B
V1
V3
V2
OUT
AD7606C-18
V4
OUT
INTERRUPT
BUSY 14
D
D
C
D
V5
V7
V6
V8
OUT
13
12
CS
OUT
RD/SCLK
Figure 104. Serial Interface ADC Reading, Four DOUTx Lines
DB13/SDI 29
24
CS
DIGITAL
HOST
DB9/D
DB10/D
DB11/D
DB12/D
A
B
C
D
OUT
OUT
OUT
OUT
25
27
28
19
20
21
22
SCLK
D
D
A
B
V1
V2
OUT
OUT
DB5/D
DB6/D
E
OUT
F
OUT
D
D
C
D
E
V5
V3
V4
OUT
OUT
DB7/D
DB8/D
G
H
OUT
OUT
D
OUT
Figure 102. AD7606C-18 Interface Diagram—One AD7606C-18 Using the
Serial Interface with Eight DOUTx Lines
D
D
F
V5
V6
V7
OUT
G
H
Reading Conversion Results (Serial ADC Mode)
OUT
The AD7606C-18 has eight serial data output pins, DOUTA to
D
OUT
D
OUTH. In software mode, data can be read back from the
Figure 105. Serial Interface ADC Reading, Eight DOUTx Lines
AD7606C-18 using either one (see Figure 106), two (see
Figure 103), four (see Figure 104), or eight (see Figure 105)
Table 26. DOUTx Format Selection Using the CONFIG
Register (Address 0x02)
DOUTx lines depending on the configuration set through the
CONFIG register.
DOUTx Format
Address 0x02, Bit 4
Address 0x02, Bit 3
CONVST
1 DOUT
2 DOUT
4 DOUT
8 DOUT
x
x
x
x
0
0
1
1
0
1
0
1
CS
SCLK
In hardware mode, only the 2 DOUTx lines option is available.
However, all channels can be read from DOUTA by providing
eight 18-bit SPI frames between two CONVST pulses.
D
D
D
D
A
B
C
D
V1
V5
V2
V6
V3
V7
V4
V8
OUT
OUT
OUT
OUT
Figure 103. Serial Interface ADC Reading, Two DOUTx Lines
CS
FRSTDATA
SCLK
D
D
D
D
A
B
C
D
V1
V2
V3
V4
V5
V6
V7
V8
OUT
OUT
OUT
OUT
Figure 106. Serial Interface ADC Reading, One DOUTx Line
Rev. 0 | Page 45 of 75
AD7606C-18
Data Sheet
CS
1
9
18
SCLK
MSB
LSB
D
x
OUT
Figure 107. Serial Interface Data Read Back (One Channel)
CS
1
2
3
4
5
6
7
8
9
18
26
SCLK
D
x
ADC DATA
STATUS HEADER
OUT
Figure 108. Serial Interface, ADC Mode, Status On
The FRSTDATA output signal indicates when the first channel,
CS
The falling edge takes the data output lines, DOUTx, out of
three-state and clocks out the MSB of the conversion result, as
shown in Figure 107.
CS
V1, is being read back. When the input is high, the FRSTDATA
output pin is in three-state. In serial mode, the falling edge of the
CS
signal takes the FRSTDATA pin out of three-state and sets
CS
CS
In 3-wire mode ( tied low), instead of clocking out the MSB,
the falling edge of the BUSY signal clocks out the MSB. The rising
edge of the SCLK signal clocks all the subsequent data bits on the
serial data outputs, DOUTx, as shown in Figure 6. The
can be held low for the entire serial read operation, or it can be
pulsed to frame each channel read of 24 SCLK cycles (see
Figure 103). However, if
conversion result transmission, the channel that was interrupted
retransmits on the next frame, completely starting from the MSB.
the FRSTDATA pin high if the BUSY line is already deasserted,
indicating that the result from V1 is available on the DOUTA
output data line. The FRSTDATA output returns to a logic low
CS
input
th
CS
following the 18 SCLK falling edge. If the
pin is tied
permanently low (3-wire mode), the falling edge of the BUSY
line sets the FRSTDATA pin high when the result from V1 is
available on DOUTA.
CS
is pulsed during a channel
If the SDI is tied low or high, nothing is clocked to the
AD7606C-18. Therefore, the device remains reading
conversion results. When using the AD7606C-18 in 3-wire
mode, keep the SDI at high level. While in ADC mode, single
write operations can be performed, as shown in Figure 108. For
writing a sequence of registers, switch to register mode, as
described in the Serial Register Mode (Writing Register Data)
section.
Data can also be clocked out using only the DOUTA pin, as
shown in Figure 106. For the AD7606C-18 to access all eight
conversion results on one DOUTx line, a total of 144 SCLK cycles
is required. In hardware mode, these 144 SCLK cycles must be
CS
framed on groups of 18 SCLK cycles by the
signal. The
disadvantage of using just one DOUTx line is that the throughput
rate is reduced if reading occurs after conversion. Leave the
unused DOUTx lines disconnected in serial mode.
Reading During Conversion
Data read operations from the AD7606C-18, as shown in
Figure 99, can occur in the following three scenarios:
Figure 104 shows a read of eight simultaneous conversion
results using four DOUTx lines on the AD7606C-18, available in
software mode. In this case, a 36 SCLK transfer accesses data
•
•
•
After a conversion while the BUSY line is low
During a conversion while the BUSY line is high
Starting while the BUSY line is low and ending while the
following conversion is in progress, see Figure 2
CS
from the AD7606C-18, and
is either held low to frame the
entire 36 SCLK cycles or is pulsed between two 18-bit frames.
This mode is only available in software mode, and it is
configured through the CONFIG register (Address 0x02).
Reading during conversions has little effect on the performance
of the converter, and it allows a faster throughput rate to be
achieved. Data can be read from the AD7606C-18 at any time
other than on the falling edge of the BUSY signal because this is
when the output data registers are updated with the new
conversion data. Any data read while the BUSY signal is high
must be completed before the falling edge of the BUSY signal.
Figure 6 shows the timing diagram for reading one channel of
data, framed by the
mode. The SCLK input signal provides the clock source for the
serial read operation. The
from the AD7606C-18.
CS
signal, from the AD7606C-18 in serial
CS
signal goes low to access the data
Rev. 0 | Page 46 of 75
Data Sheet
AD7606C-18
Serial ADC Mode with CRC Enabled
•
•
•
The second bit clocked in SDI must be set to 1 to select a
read command.
Bits[3:8] clocked in SDI contain the register address to be
clocked out on DOUTA on the following frame.
The subsequent eight bits, Bits[9:16], clocked in SDI are
ignored.
In software mode, the CRC can be enabled by writing to the
register map. In this case, the CRC is appended on each DOUTx
line after the last channel is clocked out, as shown in Figure 114.
See the Interface CRC section for more information on how the
CRC is calculated.
Serial ADC Mode with Status Enabled
If the AD7606C-18 is in ADC mode, the DOUTx lines keep
clocking ADC data on Bits[9:16], and then the AD7606C-18
switches to register mode.
In software mode, the 8-bit status header (see Table 27) can be
turned on when using the serial interface so that it is appended
after each 18-bit data conversion, extending the frame size to
26 bits per channel, as shown in Figure 108.
If the AD7606C-18 is in register mode, the DOUTx lines read
back the content from the previous addressed register, no
matter if the previous frame was a read or a write command. To
exit register mode, keep the SDI line low for 16 SCLK cycles, as
shown in Figure 110.
Serial Register Mode (Reading Register Data)
All the registers in Table 31 can be read over the serial interface.
The format for a read command is shown in Figure 109. It
consists of two 16-bit frames. On the first frame, perform the
following:
•
The first bit clocked in SDI must be set to 0 to enable
writing the address.
CS
SCLK
SDI
1
8
16
WEN R/W
READ OR WRITE COMMAND
D
A
OUT
ADC DATA (8LSB) OR PREVIOUS
REGISTER READ/WRITTEN
ADC DATA (8LSB) OR XX
REGISTER [ADD5:ADD0] CONTENT
Figure 109. Serial Interface Read Command, First Frame Provides the Address, Second Frame Provides the Register Content
CS
SCLK
READ COMMAND
R/W COMMAND
R/W COMMAND
WRITE COMMAND
SDI
D
x
ADC DATA
ADC DATA
ADC DATA
ADC MODE
OUT
MODE
ADC MODE
REGISTER MODE
Figure 110. AD7606C-18 Register Mode
Table 27. Status Header, Serial Interface
Bit 7 (MSB) Bit 6
RESET_DETECT DIGITAL_ERROR OPEN_DETECTED
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Content
RESERVED
CH.ID 2 CH.ID 1 CH. ID 0
Channel ID (see Table 24)
Meaning1 Reset detected
Error flag on
Address 0x22
The analog input
of this channel is
open
1 See the Diagnostics section for more information.
Rev. 0 | Page 47 of 75
AD7606C-18
Data Sheet
When writing continuously to the device, the data that appears
on DOUTA is from the register address that was written to on the
previous frame, as shown in Figure 111. The DOUTB, DOUTC, and
Serial Register Mode (Writing Register Data)
In software mode, all the read and write registers in Table 31
can be written to over the serial interface. To write a sequence
of registers, exit ADC mode (default mode) by reading any
register on the memory map. A register write command is
performed by a single 16-bit SPI access. The format for a write
command, as shown in Figure 111, is structured as follows:
D
OUTD pins are kept low during the transmission.
While in register mode, no ADC data is clocked out because the
OUTx lines are used to clock out register content. After writing
D
all required registers, keeping the SDI line low for 16 SCLK cycles
returns the AD7606C-18 to ADC mode, where the ADC data is
again clocked out on the DOUTx lines, as shown in Figure 110.
•
•
•
•
The first bit clocked in SDI must be set to 0 to enable a
write command.
In software mode, when the CRC is turned on, eight additional
bits are clocked in and out on each frame. Therefore, 24-bit
frames are required.
W
The second bit clocked in SDI, the R/ bit, must be
cleared to 0.
Bit ADD5 to Bit ADD0 clocked in SDI contain the register
address to be written.
The subsequent eight bits (Bits[DIN7:DIN0]) clocked in
SDI contain the data to be written to the selected register.
Data is clocked in from SDI on the falling edge of SCLK,
while data is clocked out on DOUTA on the rising edge of
SCLK.
CS
1
2
3
4
17
18
19
26
SCLK
A TO D
D
H
OUT
DB17 DB16 DB15 DB14
WEN R/W ADD5 ADD4
DB1 DB0 CRC7
CRC7 CRC6 CRC5
CRC0
OUT
SDI
Figure 111. AD7606C-18 Serial Interface, Single Write Command, SDI Clocks in the Address Bit ADD5 to Bit ADD0 and the Register Content Bit DIN7 to Bit DIN0 During
the Same Frame, DOUTA Provides Register Content Requested on the Previous Frame
Rev. 0 | Page 48 of 75
Data Sheet
AD7606C-18
With the CRC enabled, the SPI frames extend to 24 bits in length,
as shown in Figure 112.
Serial Register Mode with CRC
Registers can be written to and read from the AD7606C-18
with CRC enabled, in software mode, by asserting the
INT_CRC_ERR_EN bit (Address 0x21, Bit 2).
When writing a register, the controller must clock the data
(register address plus register content) in the AD7606C-18
followed by an 8-bit CRC word, calculated from the previous
16 bits using the above polynomial. The AD7606C-18 reads the
register address and the register content, calculates the
corresponding 8-bit CRC word, and asserts the INT_CRC_ERR bit
(Address 0x22, Bit 2) if the calculated CRC word does not match
the CRC word received between the 17th and 24th bit through the
SDI, as shown in Figure 113.
When reading a register, the AD7606C-18 provides eight
additional bits on the DOUTA pin with the CRC resultant of the
data shifted out previously on the same frame. The controller
can then check whether the data received is correct by applying
the following polynomial:
x8 + x2 + x + 1
CS
1
8
9
16
24
SCLK
SDI
ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
WEN
R/W
MSB
LSB
8-BIT CRC
D
A
OUT
Figure 112. Reading Registers Through the SPI with CRC Enabled
CS
1
8
9
16
24
SCLK
SDI
ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
WEN
MSB
LSB
8-BIT CRC
R/W
Figure 113. Writing Registers Through the SPI with CRC Enabled
Rev. 0 | Page 49 of 75
AD7606C-18
Data Sheet
DIAGNOSTICS
Diagnostic features are available in software mode to verify the
correct operation of the AD7606C-18. The list of diagnostic
monitors includes reset detection, overvoltage detection,
undervoltage detection, analog input open circuit detection,
and digital error detection.
If the calculated and stored CRC values do not match, the error
checking and correction (ECC) block can detect up to 3 bit errors
(hamming distance of 4). Otherwise, the ROM_CRC_ERR
(Address 0x22, Bit 0) asserts. When ROM_CRC_ERR asserts
after power-up, it is recommended to issue a full reset to reload
all factory settings.
If an error is detected, a flag asserts on the status header, if
enabled, as described in the Digital Interface section. This flag
points to the registers on which the error is located, as explained
in the following sections.
This ROM CRC monitoring feature is enabled by default but
can be disabled by clearing the ROM_CRC_ERR_EN bit
(Address 0x21, Bit 0).
In addition, a diagnostic multiplexer can dedicate any channel
to verify a series of internal nodes, as explained in the
Diagnostics Multiplexer section.
Memory Map CRC
The memory map CRC is disabled by default. After the
AD7606C-18 is configured in software mode through writing
the required registers, the memory map CRC can be enabled
through the MM_CRC_ERR_EN bit (Address 0x21, Bit 1).
When enabled, the CRC calculation is performed on the entire
memory map and stored. Every 4 μs, the CRC on the memory
map is recalculated and compared to the stored CRC value.
RESET DETECTION
The RESET_DETECT bit on the status register (Address 0x01,
Bit 7) asserts if either a partial reset or full reset pulse is applied
to the AD7606C-18. On power-up, a full reset is required. This
reset asserts the RESET_DETECT bit, indicating that the
power-on reset (POR) initialized properly on the device.
The AD7606C-18 uses the following 16-bit CRC polynomial to
calculate the CRC checksum value on the memory map:
The POR monitors the REGCAP voltage and issues a full reset
if the voltage drops under a certain threshold.
x16 + x14 + x13 + x12 + x10 + x8 +x6 + x4 + x3 + x + 1
(0xBAAD)
The RESET_DETECT bit can be used to detect an unexpected
device reset or a large glitch on the RESET pin, or a voltage
drop on the supplies.
If the calculated and the stored CRC values do not match, the
ECC block can detect up to 3 bit errors (hamming distance of 4).
Otherwise, the memory map is corrupted and the MM_CRC_ERR
bit (Address 0x22, Bit 1) asserts. Every time the memory map is
written, the CRC is recalculated and the new value stored.
The RESET_DETECT bit is only cleared by reading the status
register.
DIGITAL ERROR
If the MM_CRC_ERR bit asserts, it is recommended to write
the memory map to recalculate the CRC. If the MM_CRC_ERR
bit persists, it is recommended to issue a full reset to restore the
default contents of the memory map.
Both the status register and status header contain a
DIGITAL_ERROR bit. This bit asserts when any of the
following monitors trigger:
•
Memory map CRC, read only memory (ROM) CRC, and
digital interface CRC.
SPI invalid read or write.
Interface CRC Checksum
The AD7606C-18 has a CRC checksum mode to improve
interface robustness by detecting errors in data transmission.
The CRC feature is available in both ADC modes (serial and
parallel) and register mode (serial only).
•
•
BUSY stuck high.
To find out which monitor triggered the DIGITAL_ERROR bit,
the DIGITAL_DIAG_ERR register (Address 0x22) has a bit
dedicated for each of them, as explained in the ROM CRC,
Memory Map CRC, Interface CRC Checksum, Interface Check,
SPI Invalid Read and Write, and BUSY Stuck High sections.
The AD7606C-18 uses the following 16-bit CRC polynomial to
calculate the CRC checksum value:
x16 + x14 + x13 + x12 + x10 + x8 +x6 + x4 + x3 + x + 1
(0xBAAD)
ROM CRC
To replicate the polynomial division in the controller, the data
shifts left by 16 bits to create a number ending in 16 Logic 0s.
The polynomial is aligned so that the MSB is adjacent to the
leftmost Logic 1 of the data. An exclusive OR (XOR) function is
applied to the data to produce a new, shorter number. The
polynomial is again aligned so that the MSB is adjacent to the
leftmost Logic 1 of the new result, and the procedure repeats.
This process repeats until the original data is reduced to a value
less than the polynomial, which results in the 16-bit checksum.
The ROM stores the factory trimming settings for the
AD7606C-18. After power-up, the ROM content is loaded to
registers during device initialization. After the load, a CRC is
calculated on the loaded data and verified if the result matches
the CRC stored in the ROM.
The AD7606C-18 uses the following 16-bit CRC polynomial to
calculate the CRC checksum value on the memory map:
x16 + x14 + x13 + x12 + x10 + x8 +x6 + x4 + x3 + x + 1
(0xBAAD)
Rev. 0 | Page 50 of 75
Data Sheet
AD7606C-18
An example of the CRC calculation for the 16-bit data is shown
in Table 28. The CRC corresponding to the data 0x064E, using
the previously described polynomial, is 0x2137.
use after reading all the channels. An example using four DOUT
lines is shown in Figure 114.
x
If using two DOUTx lines (DOUTA and DOUTB), each 16-bit CRC
word is calculated using data from four channels (72 bits), as
shown in Figure 115. If using only one DOUTx line, all eight
channels are clocked out through DOUTA, followed by the 16-bit
The serial interface supports the CRC when enabled via the
INT_CRC_ERR_EN bit (Address 0x21, Bit 2). The CRC is a
16-bit word that is appended to the end of each DOUTx line in
CRC word calculated using data from the eight channels (144 bits).
Table 28. Example CRC Calculation for 16-Bit Data1, 2
Data
0
0
0
0
0
1
1
1
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
0
1
1
0
1
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
1
X
0
0
0
1
1
0
1
1
0
0
0
X
0
1
1
0
1
1
0
1
1
1
0
X
0
1
1
1
0
0
0
0
0
1
1
X
0
0
0
1
1
1
0
1
1
1
0
X
0
1
1
0
1
1
0
0
0
0
0
X
0
1
1
1
0
0
0
1
1
1
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
Process Data
Polynomial
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
0
0
1
1
0
1
0
0
0
1
1
0
1
1
1
0
0
1
1
0
1
0
1
1
0
1
1
CRC
1 This table represents the division of the data. Blank cells are for formatting purposes.
2 X = don’t care.
CONVST
CS
SCLK
D
D
D
D
A
B
C
D
V1
V3
V5
V7
V2
V4
V6
V8
CRC(V1,V2)
CRC(V3,V4)
CRC(V5,V6)
CRC(V7,V8)
OUT
OUT
OUT
OUT
Figure 114. Serial Interface ADC Reading with CRC On, Four DOUTx Lines
CONVST
CS
SCLK
D
D
D
D
A
B
C
D
V1
V5
V2
V6
V3
V7
V4
V8
CRC(V1,V4)
CRC(V5,V8)
OUT
OUT
OUT
OUT
Figure 115. Serial Interface ADC Reading with CRC On, Two DOUTx Lines
Rev. 0 | Page 51 of 75
AD7606C-18
Data Sheet
When the AD7606C-18 is in register mode and registers are being
read or written, the CRC polynomial used is x8 + x2 + x + 1 (0x83).
When reading a register, and CRC is enabled, each SPI frame is
26 bits long and the CRC 8-bit word is clocked out from the
17th to 24th SCLK cycle. Similarly, when writing a register, a CRC
word can be appended on the SDI line, as shown in Figure 116.
The AD7606C-18 checks and triggers an error, INT_CRC_ERR
(Address 0x22, Bit 2), if the CRC word given and the CRC word
internally calculated do not match.
SPI Invalid Read and Write
When attempting to read back an invalid register address, the
SPI_READ_ERR bit (Address 0x22, Bit 4) is set. The invalid
readback address detection can be enabled by setting the
SPI_READ_ERR_EN bit (Address 0x21, Bit 4). If an SPI read
error is triggered, it is cleared by overwriting that bit or disabling
the checker.
When attempting to write to an invalid register address or a
read only register, the SPI_WRITE_ERR bit (Address 0x22, Bit 3)
is set. The invalid write address detection can be enabled by
setting the SPI_WRITE _ERR_EN bit (Address 0x21, Bit 3). If
an SPI write error is triggered, it is cleared by overwriting that
bit or disabling the checker.
The parallel interface also supports CRC in ADC mode only,
and it is clocked out through DB17 to DB2 after Channel 8, as
shown in Figure 100. The 16-bit CRC word is calculated using
data from the eight channels (128 bits).
Interface Check
BUSY Stuck High
The integrity of the digital interface can be checked by setting
the INTERFACE_CHECK_EN bit (Address 0x21, Bit 7).
Selecting the interface check forces the conversion result
registers to a known value, as shown in Table 29.
BUSY stuck high monitoring is enabled by setting the
BUSY_STUCK_HIGH_ERR_EN bit (Address 0x21, Bit 5).
After this bit is enabled, the conversion time (tCONV in Table 3)
is monitored internally with an independent clock. If tCONV exceeds
4 μs, the AD7606C-18 automatically issues a partial reset and
asserts the BUSY_STUCK_HIGH_ERR bit (Address 0x22, Bit 5).
To clear this error flag, the BUSY_STUCK_HIGH_ERR bit must
be overwritten with a 1.
Verifying that the controller receives the data in Table 29
ensures that the interface between the AD7606C-18 and the
controller operates properly. If the interface CRC is enabled
because the data transmitted is known, this mode verifies that
the controller performs the CRC calculation properly.
When oversampling mode is enabled, the individual conversion
time for each internal conversion is monitored.
Table 29. Interface Check Conversion Results
Channel Number
Conversion Result Forced (Hex)
V1
V2
V3
V4
V5
V6
V7
V8
0x2ACCA
0x15CC5
0x2A33A
0x15335
0x0CAAC
0x0C55C
0x33AA3
0x33553
CS
1
2
3
4
17
18
19
26
SCLK
A TO D
D
H
OUT
DB17 DB16 DB15 DB14
WEN R/W ADD5 ADD4
DB1 DB0 CRC7
CRC7 CRC6 CRC5
CRC0
OUT
SDI
Figure 116. Register Write with CRC On
Rev. 0 | Page 52 of 75
Data Sheet
AD7606C-18
Temperature Sensor
DIAGNOSTICS MULTIPLEXER
The temperature sensor can be selected through the diagnostic
multiplexer and converted with the ADC, as shown in Figure 117.
The temperature sensor voltage is measured and is proportional to
the die temperature as per the following equation with an
accuracy of 2°C:
All eight input channels contain a diagnostics multiplexer in
front of the PGA that monitors the internal nodes described in
Table 30 to ensure the correct operation of the AD7606C-18. For
accurate measurements, it is recommended to use Channel 8,
where the offset and gain for diagnostic channels have been
trimmed in production.
ADCOUT V − 2.76272 V
(
)
( )
Temperature °C =
+ 25 °C
(
)
(
)
Table 30 shows the bit decoding for the diagnostic mux register on
Channel 1 as an example. When an internal node is selected,
the input voltage at the input pins is deselected from the PGA,
as shown in Figure 117.
0.077312 V / °C
(
)
Reference Voltage
The reference voltage can be selected through the diagnostic
multiplexer and converted with the ADC, as shown in Figure 118.
The internal or external reference is selected as an input to the
diagnostic multiplexer based on the REF SELECT pin. Ideally,
the ADC output follows the voltage reference level ratiometrically.
Therefore, if the ADC output goes beyond the expected 2.5 V,
either the reference buffer or the PGA is malfunctioning.
Each diagnostic multiplexer configuration is accessed in software
mode through the corresponding register (Address 0x28 to
Address 0x2B). To use the multiplexer on one channel, the
10 V range must be selected on that channel.
Table 30. Channel 1 Diagnostic Mux Register Bit Decoding
Address 0x18
AD7606C-18
Bit 2
Bit 1
Bit 0
Signal on Channel 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V1
Temperature sensor
VREF
INT REF
4.4V
ALDO
DLDO
VDRIVE
AGND
AVCC
EXT REF
2.5V
MUX
R
R
FB
1MΩ
1MΩ
Vx+
Vx–
ADC
FB
TEMPERATURE
SENSOR
AD7606C-18
V
REF
Figure 118. Reference Voltage Signal Path Through the Diagnostic Multiplexer
ALDO
DLDO
MUX
Internal LDOs
V
DRIVE
AGND
AV
CC
1MΩ
The analog and digital LDO (REGCAP pins) can be selected
through the diagnostic multiplexer and converted with the
ADC, as shown in Figure 117. The ADC output is four times
the voltage on the REGCAP pins. This measurement verifies
that each LDO is at the correct operating voltage so that the
internal circuitry is biased correctly.
R
FB
Vx+
Vx–
1MΩ
R
FB
Supply Voltages
AVCC, VDRIVE, and AGND can be selected through the diagnostic
multiplexer and converted with the ADC, as shown in Figure 117.
This setup ensures the voltage and grounds are correctly applied to
the device to ensure correct operation.
Figure 117. Diagnostic Multiplexer (Channel 1 Shown as an Example)
(RFB = Feedback Resistor)
Rev. 0 | Page 53 of 75
AD7606C-18
Data Sheet
TYPICAL CONNECTION DIAGRAM
There are four AVCC supply pins on the AD7606C-18 and it is
recommended that each of the four pins are decoupled using a
100 nF capacitor at each supply pin and a 10 µF capacitor at the
supply source. The AD7606C-18 can operate with the internal
reference or an externally applied reference. When using a
single AD7606C-18 device on the PCB, decouple the
PAR
/SER SEL pin is tied
uses the parallel interface because the
to AGND. The analog input range for all eight channels is 10 V,
provided the RANGE pin is tied to a high level and the
oversampling ratio is controlled through the OSx pins by the
controller.
In Figure 120, the AD7606C-18 is configured in software mode
because the OSx pins are at logic level high. The oversampling
ratio, as well as each channel range, are configured by accessing
REFIN/REFOUT pin with a 100 nF capacitor. Refer to the
Reference section when using an application with multiple
AD7606C-18 devices. The REFCAPA and REFCAPB pins are
shorted together and decoupled with a 10 µF ceramic capacitor.
PAR
the memory map. In this example, the
/SER SEL pin is at
logic level high. Therefore, the serial interface is used for both
reading the ADC data and reading and writing the memory
map. The REF SELECT pin is tied to AGND. Therefore, the
internal reference is disabled and an external reference is
connected externally to the REFIN/REFOUT pin and decoupled
through a 100 nF capacitor.
The VDRIVE supply is connected to the same supply as the
processor. The VDRIVE voltage controls the voltage value of the
output logic signals. For more information on layout, decoupling,
and grounding, see the Layout Guidelines section.
After supplies are applied to the AD7606C-18, apply a full reset
to the AD7606C-18 to ensure that it is configured for the correct
mode of operation.
Figure 119 and Figure 120 are examples of typical connection
diagrams. Other combinations of the reference, data interface,
and operation mode are also possible, depending on the logic
levels applied to each configuration pin.
In Figure 119, the AD7606C-18 is configured in hardware mode
and is operating with the internal reference because the REF
SELECT pin is set to logic high. In this example, the device also
ANALOG SUPPLY
DIGITAL SUPPLY
VOLTAGE 1.71V TO 5.25V
1
VOLTAGE 5V
+
100nF
100nF
1µF
100nF
2
REFIN/REFOUT
REGCAP
AV
V
CC
DRIVE
REFCAPA
PARALLEL
INTERFACE
DB0 TO DB17
+
REFCAPB
REFGND
10µF
CONVST
CS
V1+
V1–
V2+
V2–
V3+
V3–
V4+
V4–
V5+
V5–
V6+
V6–
V7+
V7–
V8+
V8–
RD
BUSY
RESET
OS2
AD7606C-18
OS1
OVERSAMPLING
EIGHT ANALOG
INPUTS V1 TO V8
OS0
REF SELECT
PAR/SER SEL
RANGE
STBY
V
DRIVE
V
DRIVE
AGND
1
2
DECOUPLING SHOWN ON THE AV PIN APPLIES TO EACH AV PIN (PIN 1, PIN 37, PIN 38, PIN 48).
CC
CC
DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV
PIN 37 AND PIN 38.
CC
DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).
Figure 119. Typical Connection Diagram, Hardware Mode
Rev. 0 | Page 54 of 75
Data Sheet
AD7606C-18
ANALOG SUPPLY
DIGITAL SUPPLY
VOLTAGE 1.71V to 5.25V
1
VOLTAGE 5V
REF
+
100nF
1µF
100nF
100nF
2
REFIN/REFOUT
REFCAPA
REGCAP
AV
V
DRIVE
CC
DB0 TO DB17
+
REFCAPB
REFGND
10µF
CONVST
CS
V1+
V1–
V2+
V2–
V3+
V3–
V4+
V4–
V5+
V5–
V6+
V6–
V7+
V7–
V8+
V8–
SDI
D
x
OUT
SCLK
RESET
AD7606C-18
OS2
OS1
OVERSAMPLING =
111b
EIGHT ANALOG
INPUTS V1 TO V8
OS0
REF SELECT
PAR/SER SEL
RANGE
V
DRIVE
STBY
AGND
1
2
DECOUPLING SHOWN ON THE AV
DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV PIN 37 AND PIN 38.
DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).
PIN APPLIES TO EACHAV PIN (PIN 1, PIN 37, PIN 38, PIN 48).
CC
CC
CC
Figure 120. Typical Connection Diagram, Software Mode
Rev. 0 | Page 55 of 75
AD7606C-18
Data Sheet
APPLICATIONS INFORMATION
Figure 121 shows the recommended decoupling on the top
LAYOUT GUIDELINES
layer of the AD7606C-18 PCB. Figure 122 shows bottom layer
decoupling, which is used for the four AVCC pins and the VDRIVE pin
decoupling. Where the ceramic 100 nF capacitors for the AVCC
pins are placed close to their respective device pins, a single
100 nF capacitor can be shared between Pin 37 and Pin 38.
The following layout guidelines are recommended to be followed
when designing the PCB that houses the AD7606C-18:
•
•
If the AD7606C-18 is in a system where multiple devices
require analog-to-digital ground connections, use a solid
ground plane (without splitting between analog and digital
grounds).
Make stable connections to the ground plane. Avoid
sharing one connection for multiple ground pins. Use
individual vias or multiple vias to the ground plane for
each ground pin.
•
•
Avoid running digital lines under the devices because doing
so couples noise on the die. Allow the analog ground plane
to run under the AD7606C-18 to avoid noise coupling.
Shield fast switching signals like CONVST or clocks with
digital ground to avoid radiating noise to other sections of
the board and ensure that they do not run near analog
signal paths.
•
•
Avoid crossover of digital and analog signals.
Ensure traces on layers in close proximity on the board
run at right angles to each other to reduce the effect of
feedthrough through the board.
Figure 121. Top Layer Decoupling REFIN/REFOUT,
REFCAPA, REFCAPB, and REGCAP Pins
•
Ensure power supply lines to the AVCC and VDRIVE pins on
the AD7606C-18 use as large a trace as possible to provide
low impedance paths and reduce the effect of glitches on
the power supply lines. Where possible, use supply planes
and make stable connections between the AD7606C-18
supply pins and the power tracks on the board. Use a
single via or multiple vias for each supply pin.
Place the decoupling capacitors close to (ideally, directly
against) the supply pins and their corresponding ground
pins. Place the decoupling capacitors for the
•
REFIN/REFOUT pin and the REFCAPA pin and
REFCAPB pin as close as possible to their respective
AD7606C-18 pins. Where possible, place the pins on the
same side of the board as the AD7606C-18 device.
Figure 122. Bottom Layer Decoupling
To ensure stable device to device performance matching in a
system that contains multiple AD7606C-18 devices, a symmetrical
layout between the AD7606C-18 devices is important.
Rev. 0 | Page 56 of 75
Data Sheet
AD7606C-18
Figure 123 shows a layout with two AD7606C-18 devices. The
AVCC supply plane runs to the right of both devices, and the
AVCC
VDRIVE supply track runs to the left of the two devices. The
reference chip is positioned between the two devices, and the
reference voltage track runs north to Pin 42 of U1 and south
to Pin 42 of U2. A solid ground plane is used.
U2
These symmetrical layout principles can also be applied to a
system that contains more than two AD7606C-18 devices. The
AD7606C-18 devices can be placed in a north to south direction,
with the reference voltage located midway between the devices
and the reference track running in the north to south direction,
similar to Figure 123.
U1
Figure 123. Layout for Multiple AD7606C-18 Devices—Top Layer and
Supply Plane Layer
Rev. 0 | Page 57 of 75
AD7606C-18
Data Sheet
REGISTER SUMMARY
Table 31. AD7606C-18 Register Summary
Addr
0x01
0x02
0x03
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RESERVED
RESERVED
CH1_RANGE
Bit 1
Bit 0
Reset
0x00
0x08
0x33
R/W
R
STATUS
CONFIG
RESET_DETECT
RESERVED
DIGITAL_ERROR
STATUS_HEADER
OPEN_DETECTED
EXT_OS_CLOCK
DOUT_FORMAT
OPERATION_MODE
R/W
R/W
RANGE_CH1_
CH2
CH2_RANGE
0x04
0x05
0x06
RANGE_CH3_
CH4
CH4_RANGE
CH6_RANGE
CH8_RANGE
CH3_RANGE
CH5_RANGE
CH7_RANGE
0x33
0x33
0x33
R/W
R/W
R/W
RANGE_CH5_
CH6
RANGE_CH7_
CH8
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
BANDWIDTH
OVERSAMPLING
CH1_GAIN
CH8_BW
CH7_BW
OS_PAD
CH6_BW
CH5_BW
CH4_BW
CH1_GAIN
CH3_BW
CH2_BW
CH1_BW
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OS_RATIO
RESERVED
CH2_GAIN
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CH2_GAIN
CH3_GAIN
CH4_GAIN
CH5_GAIN
CH6_GAIN
CH7_GAIN
CH8_GAIN
CH3_GAIN
CH4_GAIN
CH5_GAIN
CH6_GAIN
CH7_GAIN
CH8_GAIN
CH1_OFFSET
CH2_OFFSET
CH3_OFFSET
CH4_OFFSET
CH5_OFFSET
CH6_OFFSET
CH7_OFFSET
CH8_OFFSET
CH1_PHASE
CH2_PHASE
CH3_PHASE
CH4_PHASE
CH5_PHASE
CH6_PHASE
CH7_PHASE
CH8_PHASE
CH1_OFFSET
CH2_OFFSET
CH3_OFFSET
CH4_OFFSET
CH5_OFFSET
CH6_OFFSET
CH7_OFFSET
CH8_OFFSET
CH1_PHASE
CH2_PHASE
CH3_PHASE
CH4_PHASE
CH5_PHASE
CH6_PHASE
CH7_PHASE
CH8_PHASE
DIGITAL_
DIAG_
ENABLE
INTERFACE_
CHECK_EN
CLK_FS_OS_
COUNTER_EN
BUSY_STUCK_
HIGH_ERR_EN
SPI_READ
_ERR_EN
SPI_
WRITE_
ERR_EN
INT_CRC_
ERR_EN
MM_CRC_
ERR_EN
ROM_
CRC_
ERR_EN
0x22
0x23
DIGITAL_
DIAG_ERR
RESERVED
BUSY_STUCK_
HIGH_ERR
SPI_
READ_
ERR
SPI_
WRITE_
ERR
INT_CRC_
ERR
MM_CRC_
ERR
ROM_
CRC_
ERR
0x00
0x00
R/W
R/W
OPEN_
DETECT_
ENABLE
CH8_OPEN_
DETECT_EN
CH7_OPEN_
DETECT_EN
CH6_OPEN_
DETECT_EN
CH5_
CH4_
CH3_OPEN_
DETECT_EN
CH2_OPEN_
DETECT_EN
CH1_
OPEN_
DETECT_
EN
OPEN_
DETECT_
EN
OPEN_
DETECT_
EN
0x24
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
OPEN_
DETECTED
CH8_OPEN
CH7_OPEN
CH6_OPEN
CH5_
OPEN
CH4_
OPEN
CH3_OPEN
CH2_OPEN
CH1_
OPEN
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x31
R/W
R/W
R/W
R/W
R/W
R/W
R
DIAGNOSTIC_
MUX_CH1_2
RESERVED
CH2_DIAG_MUX_CTRL
CH4_DIAG_MUX_CTRL
CH6_DIAG_MUX_CTRL
CH8_DIAG_MUX_CTRL
CH1_DIAG_MUX_CTRL
CH3_DIAG_MUX_CTRL
CH5_DIAG_MUX_CTRL
CH7_DIAG_MUX_CTRL
DIAGNOSTIC_
MUX_CH3_4
RESERVED
RESERVED
RESERVED
DIAGNOSTIC_
MUX_CH5_6
DIAGNOSTIC_
MUX_CH7_8
OPEN_DETECT_
QUEUE
OPEN_DETECT_QUEUE
CLK_FS_COUNTER
CLK_OS_COUNTER
FS_CLK_
COUNTER
OS_CLK_
COUNTER
R
ID
DEVICE_ID
SILICON_REVISION
R
Rev. 0 | Page 58 of 75
Data Sheet
AD7606C-18
REGISTER DETAILS
Address: 0x01, Reset: 0x00, Name: STATUS
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] RESET_DETECT (R)
[4:0] RESERVED
Reset Detected. Either a full, partial, or power-on
[5] OPEN_DETECTED (R)
reset has been detected on the internal LDO.
Open Circuit Detected. Check the OPEN_DETECTED
register (Address 0x24) to determine which
channel is affected.
[6] DIGITAL_ERROR (R)
Digital Error Present. Read the DIGITAL_DIAG_ERR
register (Address 0x22) to determine the
type of digital error.
Table 32. Bit Descriptions for STATUS
Bits Bit Name Description
Reset Access
7
6
5
RESET_DETECT
Reset Detected. Either a full, partial, or power-on reset has been detected on the internal
LDO.
Digital Error Present. Read the DIGITAL_DIAG_ERR register (Address 0x22) to determine the
type of digital error.
0x0
0x0
0x0
0x0
R
R
R
R
DIGITAL_ERROR
OPEN_DETECTED Open Circuit Detected. Check the OPEN_DETECTED register (Address 0x24) to determine
which channel is affected.
[4:0] RESERVED
Reserved.
Address: 0x02, Reset: 0x08, Name: CONFIG
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
[7] RESERVED
[1:0] OPERATION_MODE (R/W)
Operation Mode
00: normal mode.
01: standby mode.
10: autostandby mode.
11: shutdown mode.
[6] STATUS_HEADER (R/W)
Enables STATUS Header to be Appended
to ADC Data in Both Serial and Parallel Interface
Modes
[5] EXT_OS_CLOCK (R/W)
[2] RESERVED
External Oversampling Clock. In oversampling
mode, enables external oversampling clock.
Oversampling conversions are triggered
through a clock signal applied to CONVST
pin and not managed by the internal oversampling
clock
[4:3] DOUT_FORMAT (R/W)
Number of DOUTX Lines Used in Serial Mode
when Reading Conversions
00: 1 DOUTx.
01: 2 DOUTx.
10: 4 DOUTx.
11: 8 DOUTx.
Table 33. Bit Descriptions for CONFIG
Bits Bit Name
Description
Reset Access
7
6
RESERVED
STATUS_HEADER
Reserved.
0x0
0x0
R
R/W
Enables STATUS Header to be Appended to ADC Data in Both Serial and Parallel Interface
Modes.
5
EXT_OS_CLOCK
External Oversampling Clock. In oversampling mode, enables external oversampling
clock. Oversampling conversions are triggered through a clock signal applied to CONVST
pin and not managed by the internal oversampling clock.
0x0
0x1
R/W
R/W
[4:3] DOUT_FORMAT
Number of DOUTx Lines Used in Serial Mode when Reading Conversions.
00: 1 DOUTx.
01: 2 DOUTx.
10: 4 DOUTx.
11: 8 DOUTx.
Reserved.
2
RESERVED
0x0
0x0
R
R/W
[1:0] OPERATION_MODE Operation Mode.
00: normal mode.
01: standby mode.
10: autostandby mode.
11: shutdown mode.
Rev. 0 | Page 59 of 75
AD7606C-18
Data Sheet
Address: 0x03, Reset: 0x33, Name: RANGE_CH1_CH2
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
1
[7:4] CH2_RANGE (R/W)
Range Options for Channel 2
0000: ±2.5 V single-ended range.
0001: ± 5V single-ended range.
0010: ±6.25 V single-ended range.
...
[3:0] CH1_RANGE (R/W)
Range Options for Channel 1
0000: ±2.5V single-ended range.
0001: ±5 V single-ended range.
0010: ±6.25 V single-ended range.
...
1001: ±10 V differential range.
1010: ±12.5 V differential range.
1011: ±20 V differential range.
1001: ±10 V differential range.
1010: ±12.5 V differential range.
1011: ±20 V differential range.
Table 34. Bit Descriptions for RANGE_CH1_CH2
Bits
Bit Name
Description
Reset
Access
[7:4]
CH2_RANGE
Range Options for Channel 2.
0x3
R/W
0000: 2.5 V single-ended range.
0001: 5 V single-ended range.
0010: 6.25 V single-ended range.
0011: 10 V single-ended range.
0100: 12.5 V single-ended range.
0101: 0 V to 5 V single-ended range.
0110: 0 V to 10 V single-ended range.
0111: 0 V to 12.5 V single-ended range.
1000: 5 V differential range.
1001: 10 V differential range.
1010: 12.5 V differential range.
1011: 20 V differential range.
Range Options for Channel 1.
[3:0]
CH1_RANGE
0x3
R/W
0000: 2.5 V single-ended range.
0001: 5 V single-ended range.
0010: 6.25 V single-ended range.
0011: 10 V single-ended range.
0100: 12.5 V single-ended range.
0101: 0 V to 5 V single-ended range.
0110: 0 V to 10 V single-ended range.
0111: 0 V to 12.5 V single-ended range.
1000: 5 V differential range.
1001: 10 V differential range.
1010: 12.5 V differential range.
1011: 20 V differential range.
Address: 0x04, Reset: 0x33, Name: RANGE_CH3_CH4
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
1
[7:4] CH4_RANGE (R/W)
Range Options for Channel 4
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±6.25 V single-ended range.
...
[3:0] CH3_RANGE (R/W)
Range Options for Channel 3
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±6.25 V single-ended range.
...
1001: ±10 V differential range.
1010: ±12.5 V differential range.
1011: ±20 V differential range.
1001: ±10 V differential range.
1010: ±12.5 V differential range.
1011: ±20 V differential range.
Table 35. Bit Descriptions for RANGE_CH3_CH4
Bits
Bit Name
Description
Reset
Access
[7:4]
CH4_RANGE
Range Options for Channel 4.
0x3
R/W
0000: 2.5 V single-ended range.
0001: 5 V single-ended range.
0010: 6.25 V single-ended range.
Rev. 0 | Page 60 of 75
Data Sheet
AD7606C-18
Bits
Bit Name
Description
Reset
Access
0011: 10 V single-ended range.
0100: 12.5 V single-ended range.
0101: 0 V to 5 V single-ended range.
0110: 0 V to 10 V single-ended range.
0111: 0 V to 12.5 V single-ended range.
1000: 5 V differential range.
1001: 10 V differential range.
1010: 12.5 V differential range.
1011: 20 V differential range.
Range Options for Channel 3.
0000: 2.5 V single-ended range.
0001: 5 V single-ended range.
0010: 6.25 V single-ended range.
0011: 10 V single-ended range.
0100: 12.5 V single-ended range.
0101: 0 V to 5 V single-ended range.
0110: 0 V to 10 V single-ended range.
0111: 0 V to 12.5 V single-ended range.
1000: 5 V differential range.
[3:0]
CH3_RANGE
0x3
R/W
1001: 10 V differential range.
1010: 12.5 V differential range.
1011: 20 V differential range.
Address: 0x05, Reset: 0x33, Name: RANGE_CH5_CH6
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
1
[7:4] CH6_RANGE (R/W)
Range Options for Channel 6
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±6.25 V single-ended range.
...
[3:0] CH5_RANGE (R/W)
Range Options for Channel 5
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±6.25 V single-ended range.
...
1001: ±10 V differential range.
1010: ±12.5 V differential range.
1011: ±20 V differential range.
1001: ±10 V differential range.
1010: ±12.5 V differential range.
1011: ±20 V differential range.
Table 36. Bit Descriptions for RANGE_CH5_CH6
Bits
Bit Name
Description
Reset
Access
[7:4]
CH6_RANGE
Range Options for Channel 6.
0x3
R/W
0000: 2.5 V single-ended range.
0001: 5 V single-ended range.
0010: 6.25 V single-ended range.
0011: 10 V single-ended range.
0100: 12.5 V single-ended range.
0101: 0 V to 5 V single-ended range.
0110: 0 V to 10 V single-ended range.
0111: 0 V to 12.5 V single-ended range.
1000: 5 V differential range.
1001: 10 V differential range.
1010: 12.5 V differential range.
1011: 20 V differential range.
Range Options for Channel 5.
0000: 2.5 V single-ended range.
0001: 5 V single-ended range.
0010: 6.25 V single-ended range.
0011: 10 V single-ended range.
[3:0]
CH5_RANGE
0x3
R/W
Rev. 0 | Page 61 of 75
AD7606C-18
Data Sheet
Bits
Bit Name
Description
Reset
Access
0100: 12.5 V single-ended range.
0101: 0 V to 5 V single-ended range.
0110: 0 V to 10 V single-ended range.
0111: 0 V to 12.5 V single-ended range.
1000: 5 V differential range.
1001: 10 V differential range.
1010: 12.5 V differential range.
1011: 20 V differential range.
Address: 0x06, Reset: 0x33, Name: RANGE_CH7_CH8
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
1
[7:4] CH8_RANGE (R/W)
Range Options for Channel 8
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±6.25 V single-ended range.
...
[3:0] CH7_RANGE (R/W)
Range Options for Channel 7
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±6.25 V single-ended range.
...
1001: ±10 V differential range.
1010: ±12.5 V differential range.
1011: ±20 V differential range.
1001: ±10 V differential range.
1010: ±12.5 V differential range.
1011: ±20 V differential range.
Table 37. Bit Descriptions for RANGE_CH7_CH8
Bits
Bit Name
Description
Reset
Access
[7:4]
CH8_RANGE
Range Options for Channel 8.
0x3
R/W
0000: 2.5 V single-ended range.
0001: 5 V single-ended range.
0010: 6.25 V single-ended range.
0011: 10 V single-ended range.
0100: 12.5 V single-ended range.
0101: 0 V to 5 V single-ended range.
0110: 0 V to 10 V single-ended range.
0111: 0 V to 12.5 V single-ended range.
1000: 5 V differential range.
1001: 10 V differential range.
1010: 12.5 V differential range.
1011: 20 V differential range.
Range Options for Channel 7.
[3:0]
CH7_RANGE
0x3
R/W
0000: 2.5 V single-ended range.
0001: 5 V single-ended range.
0010: 6.25 V single-ended range.
0011: 10 V single-ended range.
0100: 12.5 V single-ended range.
0101: 0 V to 5 V single-ended range.
0110: 0 V to 10 V single-ended range.
0111: 0 V to 12.5 V single-ended range.
1000: 5 V differential range.
1001: 10 V differential range.
1010: 12.5 V differential range.
1011: 20 V differential range.
Rev. 0 | Page 62 of 75
Data Sheet
AD7606C-18
Address: 0x07, Reset: 0x00, Name: BANDWIDTH
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] CH8_BW (R/W)
Enables high bandwidth mode on Channel 8
[0] CH1_BW (R/W)
Enables high bandwidth mode on Channel 1
[6] CH7_BW (R/W)
Enables high bandwidth mode on Channel 7
[1] CH2_BW (R/W)
Enables high bandwidth mode on Channel 2
[5] CH6_BW (R/W)
Enables high bandwidth mode on Channel 6
[2] CH3_BW (R/W)
Enables high bandwidth mode on Channel 3
[4] CH5_BW (R/W)
Enables high bandwidth mode on Channel 5
[3] CH4_BW (R/W)
Enables high bandwidth mode on Channel 4
Table 38. Bit Descriptions for BANDWIDTH
Bits Bit Name Description
Reset Access
7
6
5
4
3
2
1
0
CH8_BW
CH7_BW
CH6_BW
CH5_BW
CH4_BW
CH3_BW
CH2_BW
CH1_BW
Enables high bandwidth mode on Channel 8.
Enables high bandwidth mode on Channel 7.
Enables high bandwidth mode on Channel 6.
Enables high bandwidth mode on Channel 5.
Enables high bandwidth mode on Channel 4.
Enables high bandwidth mode on Channel 3.
Enables high bandwidth mode on Channel 2.
Enables high bandwidth mode on Channel 1.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address: 0x08, Reset: 0x00, Name: OVERSAMPLING
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] OS_PAD (R/W)
[3:0] OS_RATIO (R/W)
Oversampling Ratio
0: oversampling off.
1: oversampling by 2.
10: oversampling by 4.
...
Oversampling Padding. Extends the internal
oversampling period allowing evenly spaced
sampling between CONVST rising edges.
110: oversampling by 64.
111: oversampling by 128.
1000: oversampling by 256.
Table 39. Bit Descriptions for OVERSAMPLING
Bits Bit Name
Description
Reset Access
[7:4] OS_PAD
Oversampling Padding. Extends the internal oversampling period allowing evenly spaced sampling 0x0
between CONVST rising edges.
R/W
[3:0] OS_RATIO Oversampling Ratio.
0000: oversampling off.
0x0
R/W
0001: oversampling by 2.
0010: oversampling by 4.
0011: oversampling by 8.
0100: oversampling by 16.
0101: oversampling by 32.
0110: oversampling by 64.
0111: oversampling by 128.
1000: oversampling by 256.
Rev. 0 | Page 63 of 75
AD7606C-18
Data Sheet
Address: 0x09, Reset: 0x00, Name: CH1_GAIN
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:0] CH1_GAIN (R/W)
Gain Register to Remove Gain Error Caused
by External RFILTER. Resolution: 1024 Ω.
Range: 0 Ω to 65,536 Ω
Table 40. Bit Descriptions for CH1_GAIN
Bits Bit Name
Description
Reset Access
[7:6] RESERVED Reserved.
[5:0] CH1_GAIN Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to
65,536 Ω.
0x0
0x0
R
R/W
Address: 0x0A, Reset: 0x00, Name: CH2_GAIN
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:0] CH2_GAIN (R/W)
Gain Register to Remove Gain Error Caused
by External RFILTER. Resolution: 1024 Ω.
Range: 0 Ω to 65,536 Ω
Table 41. Bit Descriptions for CH2_GAIN
Bits Bit Name Description
[7:6] RESERVED Reserved.
[5:0] CH2_GAIN Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to
65,536 Ω.
Reset Access
0x0
0x0
R
R/W
Address: 0x0B, Reset: 0x00, Name: CH3_GAIN
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:0] CH3_GAIN (R/W)
Gain Register to Remove Gain Error Caused
by External RFILTER. Resolution: 1024 Ω.
Range: 0 Ω to 65,536 Ω
Table 42. Bit Descriptions for CH3_GAIN
Bits Bit Name Description
[7:6] RESERVED Reserved.
[5:0] CH3_GAIN Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to
65,536 Ω.
Reset Access
0x0
0x0
R
R/W
Address: 0x0C, Reset: 0x00, Name: CH4_GAIN
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:0] CH4_GAIN (R/W)
Gain Register to Remove Gain Error Caused
by External RFILTER. Resolution: 1024 Ω.
Range: 0 Ω to 65,536 Ω
Table 43. Bit Descriptions for CH4_GAIN
Bits Bit Name Description
[7:6] RESERVED Reserved.
[5:0] CH4_GAIN Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to
65,536 Ω.
Reset Access
0x0
0x0
R
R/W
Rev. 0 | Page 64 of 75
Data Sheet
AD7606C-18
Address: 0x0D, Reset: 0x00, Name: CH5_GAIN
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:0] CH5_GAIN (R/W)
Gain Register to Remove Gain Error Caused
by External RFILTER. Resolution: 1024 Ω.
Range: 0 Ω to 65,536 Ω
Table 44. Bit Descriptions for CH5_GAIN
Bits Bit Name
Description
Reset Access
[7:6] RESERVED Reserved.
[5:0] CH5_GAIN Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to
65,536 Ω.
0x0
0x0
R
R/W
Address: 0x0E, Reset: 0x00, Name: CH6_GAIN
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:0] CH6_GAIN (R/W)
Gain Register to Remove Gain Error Caused
by External RFILTER. Resolution: 1024 Ω.
Range: 0 Ω to 65,536 Ω
Table 45. Bit Descriptions for CH6_GAIN
Bits Bit Name Description
[7:6] RESERVED Reserved.
[5:0] CH6_GAIN Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to
65,536 Ω.
Reset Access
0x0
0x0
R
R/W
Address: 0x0F, Reset: 0x00, Name: CH7_GAIN
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:0] CH7_GAIN (R/W)
Gain Register to Remove Gain Error Caused
by External RFILTER. Resolution: 1024 Ω.
Range: 0 Ω to 65,536 Ω
Table 46. Bit Descriptions for CH7_GAIN
Bits Bit Name Description
[7:6] RESERVED Reserved.
[5:0] CH7_GAIN Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to
65,536 Ω.
Reset Access
0x0
0x0
R
R/W
Address: 0x10, Reset: 0x00, Name: CH8_GAIN
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:0] CH8_GAIN (R/W)
Gain Register to Remove Gain Error Caused
by External RFILTER. Resolution: 1024 Ω.
Range: 0 Ω to 65,536 Ω
Table 47. Bit Descriptions for CH8_GAIN
Bits Bit Name Description
[7:6] RESERVED Reserved.
[5:0] CH8_GAIN Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to
65,536 Ω.
Reset Access
0x0
0x0
R
R/W
Rev. 0 | Page 65 of 75
AD7606C-18
Data Sheet
Address: 0x11, Reset: 0x80, Name: CH1_OFFSET
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7:0] CH1_OFFSET (R/W)
Offset Register to Remove External System
Offset Errors. Range from –512 LSB to +511
LSB.
Table 48. Bit Descriptions for CH1_OFFSET
Bits Bit Name Description
Reset Access
[7:0] CH1_OFFSET Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB.
0x80
R/W
Address: 0x12, Reset: 0x80, Name: CH2_OFFSET
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7:0] CH2_OFFSET (R/W)
Offset Register to Remove External System
Offset Errors. Range from –512 LSB to +511
LSB.
Table 49. Bit Descriptions for CH2_OFFSET
Bits Bit Name Description
[7:0] CH2_OFFSET Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB.
Reset Access
0x80 R/W
Address: 0x13, Reset: 0x80, Name: CH3_OFFSET
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7:0] CH3_OFFSET (R/W)
Offset Register to Remove External System
Offset Errors. Range from –512 LSB to +511
LSB.
Table 50. Bit Descriptions for CH3_OFFSET
Bits Bit Name Description
[7:0] CH3_OFFSET Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB.
Reset Access
0x80 R/W
Address: 0x14, Reset: 0x80, Name: CH4_OFFSET
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7:0] CH4_OFFSET (R/W)
Offset Register to Remove External System
Offset Errors. Range from –512 LSB to +511
LSB.
Table 51. Bit Descriptions for CH4_OFFSET
Bits Bit Name Description
[7:0] CH4_OFFSET Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB.
Reset Access
0x80 R/W
Address: 0x15, Reset: 0x80, Name: CH5_OFFSET
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7:0] CH5_OFFSET (R/W)
Offset Register to Remove External System
Offset Errors. Range from –512 LSB to +511
LSB.
Table 52. Bit Descriptions for CH5_OFFSET
Bits Bit Name Description
[7:0] CH5_OFFSET Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB.
Reset Access
0x80 R/W
Rev. 0 | Page 66 of 75
Data Sheet
AD7606C-18
Address: 0x16, Reset: 0x80, Name: CH6_OFFSET
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7:0] CH6_OFFSET (R/W)
Offset Register to Remove External System
Offset Errors. Range from –512 LSB to +511
LSB.
Table 53. Bit Descriptions for CH6_OFFSET
Bits Bit Name Description
Reset Access
[7:0] CH6_OFFSET Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB.
0x80
R/W
Address: 0x17, Reset: 0x80, Name: CH7_OFFSET
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7:0] CH7_OFFSET (R/W)
Offset Register to Remove External System
Offset Errors. Range from –512 LSB to +511
LSB.
Table 54. Bit Descriptions for CH7_OFFSET
Bits Bit Name Description
[7:0] CH7_OFFSET Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB.
Reset Access
0x80 R/W
Address: 0x18, Reset: 0x80, Name: CH8_OFFSET
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7:0] CH8_OFFSET (R/W)
Offset Register to Remove External System
Offset Errors. Range from –512 LSB to +511
LSB.
Table 55. Bit Descriptions for CH8_OFFSET
Bits Bit Name Description
[7:0] CH8_OFFSET Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB.
Reset Access
0x80 R/W
Address: 0x19, Reset: 0x00, Name: CH1_PHASE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CH1_PHASE (R/W)
Phase Register to Remove External System
Phase Errors Between Channels. Phase
delay from 0 µs to 255 µs in steps of 1 µs.
Table 56. Bit Descriptions for CH1_PHASE
Bits Bit Name Description
Reset Access
[7:0] CH1_PHASE Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs 0x0
to 255 µs in steps of 1 µs.
R/W
Address: 0x1A, Reset: 0x00, Name: CH2_PHASE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CH2_PHASE (R/W)
Phase Register to Remove External System
Phase Errors Between Channels. Phase
delay from 0 µs to 255 µs in steps of 1 µs.
Table 57. Bit Descriptions for CH2_PHASE
Bits Bit Name Description
Reset Access
[7:0] CH2_PHASE Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs 0x0
to 255 µs in steps of 1 µs.
R/W
Rev. 0 | Page 67 of 75
AD7606C-18
Data Sheet
Address: 0x1B, Reset: 0x00, Name: CH3_PHASE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CH3_PHASE (R/W)
Phase Register to Remove External System
Phase Errors Between Channels. Phase
delay from 0 µs to 255 µs in steps of 1 µs.
Table 58. Bit Descriptions for CH3_PHASE
Bits Bit Name
Description
Reset Access
[7:0] CH3_PHASE Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs 0x0
to 255 µs in steps of 1 µs.
R/W
Address: 0x1C, Reset: 0x00, Name: CH4_PHASE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CH4_PHASE (R/W)
Phase Register to Remove External System
Phase Errors Between Channels. Phase
delay from 0 µs to 255 µs in steps of 1 µs.
Table 59. Bit Descriptions for CH4_PHASE
Bits Bit Name Description
Reset Access
[7:0] CH4_PHASE Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs 0x0
to 255 µs in steps of 1 µs.
R/W
Address: 0x1D, Reset: 0x00, Name: CH5_PHASE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CH5_PHASE (R/W)
Phase Register to Remove External System
Phase Errors Between Channels. Phase
delay from 0 µs to 255 µs in steps of 1 µs.
Table 60. Bit Descriptions for CH5_PHASE
Bits Bit Name Description
Reset Access
[7:0] CH5_PHASE Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs 0x0
to 255 µs in steps of 1 µs.
R/W
Address: 0x1E, Reset: 0x00, Name: CH6_PHASE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CH6_PHASE (R/W)
Phase Register to Remove External System
Phase Errors Between Channels. Phase
delay from 0 µs to 255 µs in steps of 1 µs.
Table 61. Bit Descriptions for CH6_PHASE
Bits Bit Name Description
Reset Access
[7:0] CH6_PHASE Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs 0x0
to 255 µs in steps of 1 µs.
R/W
Rev. 0 | Page 68 of 75
Data Sheet
AD7606C-18
Address: 0x1F, Reset: 0x00, Name: CH7_PHASE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CH7_PHASE (R/W)
Phase Register to Remove External System
Phase Errors Between Channels. Phase
delay from 0 µs to 255 µs in steps of 1 µs.
Table 62. Bit Descriptions for CH7_PHASE
Bits Bit Name
Description
Reset Access
[7:0] CH7_PHASE Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs 0x0
to 255 µs in steps of 1 µs.
R/W
Address: 0x20, Reset: 0x00, Name: CH8_PHASE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CH8_PHASE (R/W)
Phase Register to Remove External System
Phase Errors Between Channels.. Phase
delay from 0 µs to 255 µs in steps of 1 µs.
Table 63. Bit Descriptions for CH8_PHASE
Bits Bit Name Description
Reset Access
[7:0] CH8_PHASE Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs 0x0
to 255 µs in steps of 1 µs.
R/W
Address: 0x21, Reset: 0x01, Name: DIGITAL_DIAG_ENABLE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7] INTERFACE_CHECK_EN (R/W)
Enables interface check. Provides a fixed
data on each channel when reading ADC
data.
[0] ROM_CRC_ERR_EN (R/W)
Enables ROM CRC check.
[1] MM_CRC_ERR_EN (R/W)
Enables memory map CRC check.
[6] CLK_FS_OS_COUNTER_EN (R/W)
Enables FS_CLOCK and OS_CLOCK counter.
[2] INT_CRC_ERR_EN (R/W)
Enables interface CRC check.
[5] BUSY_STUCK_HIGH_ERR_EN (R/W)
Enables busy line stuck high which is a monitor
of the conversion time to ensure ADC operation.
[3] SPI_WRITE_ERR_EN (R/W)
Enables checking if attempting to write to
an invalid address.
[4] SPI_READ_ERR_EN (R/W)
Enables checking if attempting to read from
an invalid address.
Table 64. Bit Descriptions for DIGITAL_DIAG_ENABLE
Bits Bit Name
Description
Reset Access
7
INTERFACE_CHECK_EN
Enables interface check. Provides a fixed data on each channel when reading
ADC data.
0x0
R/W
6
5
CLK_FS_OS_COUNTER_EN
Enables FS_CLOCK and OS_CLOCK counter.
0x0
0x0
R/W
R/W
BUSY_STUCK_HIGH_ERR_EN Enables busy line stuck high which is a monitor of the conversion time to ensure
ADC operation.
4
3
2
1
0
SPI_READ_ERR_EN
SPI_WRITE_ERR_EN
INT_CRC_ERR_EN
MM_CRC_ERR_EN
ROM_CRC_ERR_EN
Enables checking if attempting to read from an invalid address.
Enables checking if attempting to write to an invalid address.
Enables interface CRC check.
Enables memory map CRC check.
Enables ROM CRC check.
0x0
0x0
0x0
0x0
0x1
R/W
R/W
R/W
R/W
R/W
Rev. 0 | Page 69 of 75
AD7606C-18
Data Sheet
Address: 0x22, Reset: 0x00, Name: DIGITAL_DIAG_ERR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[0] ROM_CRC_ERR (R/W1C)
ROM CRC Error.
[5] BUSY_STUCK_HIGH_ERR (R/W1C)
Busy Stuck High Error. Busy pin has been
at a high logic level for longer than 4 µs.
[1] MM_CRC_ERR (R/W1C)
Memory Map CRC Error.
[4] SPI_READ_ERR (R/W1C)
SPI Invalid Read Address.
[2] INT_CRC_ERR (R/W1C)
Interface CRC Error.
[3] SPI_WRITE_ERR (R/W1C)
SPI Invalid Write Address.
Table 65. Bit Descriptions for DIGITAL_DIAG_ERR
Bits Bit Name
Description
Reset Access
[7:6] RESERVED
Reserved.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R
5
4
3
2
1
0
BUSY_STUCK_HIGH_ERR Busy Stuck High Error. Busy pin has been at high logic level for longer than 4 μs.
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
SPI_READ_ERR
SPI_WRITE_ERR
INT_CRC_ERR
MM_CRC_ERR
ROM_CRC_ERR
SPI Invalid Read Address.
SPI Invalid Write Address.
Interface CRC Error.
Memory Map CRC Error.
ROM CRC Error.
Address: 0x23, Reset: 0x00, Name: OPEN_DETECT_ENABLE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] CH8_OPEN_DETECT_EN (R/W)
In automatic mode, enables analog input
open circuit detection for Channel 8. In manual
mode, sets the PGA common mode to high.
[0] CH1_OPEN_DETECT_EN (R/W)
In automatic mode, enables analog input
open circuit detection for Channel 1. In manual
mode, sets the PGA common mode to high.
[6] CH7_OPEN_DETECT_EN (R/W)
[1] CH2_OPEN_DETECT_EN (R/W)
In automatic mode, enables analog input
open circuit detection for Channel 7. In manual
mode, sets the PGA common mode to high.
In automatic mode, enables analog input
open circuit detection for Channel 2. In manual
mode, sets the PGA common mode to high.
[5] CH6_OPEN_DETECT_EN (R/W)
[2] CH3_OPEN_DETECT_EN (R/W)
In automatic mode, enables analog input
open circuit detection for Channel 6. In manual
mode, sets the PGA common mode to high.
In automatic mode, enables analog input
open circuit detection for Channel 3. In manual
mode, sets the PGA common mode to high.
[4] CH5_OPEN_DETECT_EN (R/W)
[3] CH4_OPEN_DETECT_EN (R/W)
In automatic mode, enables analog input
open circuit detection for Channel 5. In manual
mode, sets the PGA common mode to high.
In automatic mode, enables analog input
open circuit detection for Channel 4. In manual
mode, sets the PGA common mode to high.
Table 66. Bit Descriptions for OPEN_DETECT_ENABLE
Bits Bit Name
Description
Reset Access
7
6
5
4
3
2
1
0
CH8_OPEN_DETECT_EN In automatic mode, enables analog input open circuit detection for Channel 8. In
manual mode, sets the PGA common mode to high.
CH7_OPEN_DETECT_EN In automatic mode, enables analog input open circuit detection for Channel 7. In
manual mode, sets the PGA common mode to high.
CH6_OPEN_DETECT_EN In automatic mode, enables analog input open circuit detection for Channel 6. In
manual mode, sets the PGA common mode to high.
CH5_OPEN_DETECT_EN In automatic mode, enables analog input open circuit detection for Channel 5. In
manual mode, sets the PGA common mode to high.
CH4_OPEN_DETECT_EN In automatic mode, enables analog input open circuit detection for Channel 4. In
manual mode, sets the PGA common mode to high.
CH3_OPEN_DETECT_EN In automatic mode, enables analog input open circuit detection for Channel 3. In
manual mode, sets the PGA common mode to high.
CH2_OPEN_DETECT_EN In automatic mode, enables analog input open circuit detection for Channel 2. In
manual mode, sets the PGA common mode to high.
CH1_OPEN_DETECT_EN In automatic mode, enables analog input open circuit detection for Channel 1. In
manual mode, sets the PGA common mode to high.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 0 | Page 70 of 75
Data Sheet
AD7606C-18
Address: 0x24, Reset: 0x00, Name: OPEN_DETECTED
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] CH8_OPEN (R/W1C)
Analog Input 8 Open Circuit Detected
[0] CH1_OPEN (R/W1C)
Analog Input 1 Open Circuit Detected
[6] CH7_OPEN (R/W1C)
Analog Input 7 Open Circuit Detected
[1] CH2_OPEN (R/W1C)
Analog Input 2 Open Circuit Detected
[5] CH6_OPEN (R/W1C)
Analog Input 6 Open Circuit Detected
[2] CH3_OPEN (R/W1C)
Analog Input 3 Open Circuit Detected
[4] CH5_OPEN (R/W1C)
Analog Input 5 Open Circuit Detected
[3] CH4_OPEN (R/W1C)
Analog Input 4 Open Circuit Detected
Table 67. Bit Descriptions for OPEN_DETECTED
Bits
7
6
5
Bit Name
Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
CH8_OPEN
CH7_OPEN
CH6_OPEN
CH5_OPEN
CH4_OPEN
CH3_OPEN
CH2_OPEN
CH1_OPEN
Analog Input 8 Open Circuit Detected.
Analog Input 7 Open Circuit Detected.
Analog Input 6 Open Circuit Detected.
Analog Input 5 Open Circuit Detected.
Analog Input 4 Open Circuit Detected.
Analog Input 3 Open Circuit Detected.
Analog Input 2 Open Circuit Detected.
Analog Input 1 Open Circuit Detected.
4
3
2
1
0
Address: 0x28, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH1_2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:3] CH2_DIAG_MUX_CTRL (R/W)
Channel 2 Diagnostic Mux Control. Select
±10 V range.
000: Analog Input pin.
001: Temperature sensor.
010: 2.5 V reference.
011: ALDO 1.8 V.
[2:0] CH1_DIAG_MUX_CTRL (R/W)
Channel 1 Diagnostic Mux Control. Select
±10 V range.
000: Analog Input pin.
001: Temperature sensor.
010: 2.5 V reference.
011: ALDO 1.8 V.
100: DLDO 1.8 V.
101: VDRIVE
110: AGND.
111: AVCC
.
100: DLDO 1.8 V.
101: VDRIVE
110: AGND.
111: AVCC
.
.
.
Table 68. Bit Descriptions for DIAGNOSTIC_MUX_CH1_2
Bits Bit Name
Description
Reset Access
[7:6] RESERVED
Reserved.
0x0
0x0
R
R/W
[5:3] CH2_DIAG_MUX_CTRL Channel 2 Diagnostic Mux Control. Select 10 V range.
000: Analog input pin.
001: Temperature sensor.
010: 2.5 V reference.
011: ALDO 1.8 V.
100: DLDO 1.8 V.
101: VDRIVE
.
110: AGND.
111: AVCC.
[2:0] CH1_DIAG_MUX_CTRL Channel 1 Diagnostic Mux Control. Select 10 V range.
0x0
R/W
000: Analog input pin.
001: Temperature sensor.
010: 2.5 V reference.
011: ALDO 1.8 V.
100: DLDO 1.8 V.
101: VDRIVE
.
110: AGND.
111: AVCC.
Rev. 0 | Page 71 of 75
AD7606C-18
Data Sheet
Address: 0x29, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH3_4
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:3] CH4_DIAG_MUX_CTRL (R/W)
Channel 4 Diagnostic Mux Control. Select
±10 V range.
000: Analog Input pin.
001: Temperature sensor.
010: 2.5 V Reference.
011: ALDO 1.8 V.
[2:0] CH3_DIAG_MUX_CTRL (R/W)
Channel 3 Diagnostic Mux Control. Select
±10 V range.
000: Analog Input pin.
001: Temperature sensor.
010: 2.5 V Reference.
011: ALDO 1.8 V.
100: DLDO 1.8 V.
101: VDRIVE
110: AGND.
111: AVCC
.
100: DLDO 1.8 V.
101: VDRIVE
110: AGND.
111: AVCC
.
.
.
Table 69. Bit Descriptions for DIAGNOSTIC_MUX_CH3_4
Bits
[7:6]
[5:3]
Bit Name
RESERVED
CH4_DIAG_MUX_CTRL
Description
Reserved.
Reset
0x0
0x0
Access
R
R/W
Channel 4 Diagnostic Mux Control. Select 10 V range.
000: Analog input pin.
001: Temperature sensor.
010: 2.5 V reference.
011: ALDO 1.8 V.
100: DLDO 1.8 V.
101: VDRIVE
.
110: AGND.
111: AVCC.
[2:0]
CH3_DIAG_MUX_CTRL
Channel 3 Diagnostic Mux Control. Select 10 V range.
000: Analog input pin.
001: Temperature sensor.
010: 2.5 V reference.
011: ALDO 1.8 V.
0x0
R/W
100: DLDO 1.8 V.
101: VDRIVE
.
110: AGND.
111: AVCC.
Address: 0x2A, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH5_6
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:3] CH6_DIAG_MUX_CTRL (R/W)
Channel 6 Diagnostic Mux Control. Select
±10 V range.
000: Analog Input pin.
001: Temperature sensor.
010: 2.5 V Reference.
011: ALDO 1.8 V.
[2:0] CH5_DIAG_MUX_CTRL (R/W)
Channel 5 Diagnostic Mux Control. Select
±10 V range.
000: Analog Input pin.
001: Temperature sensor.
010: 2.5 V Reference.
011: ALDO 1.8 V.
100: DLDO 1.8 V.
101: VDRIVE
110: AGND.
111: AVCC
.
100: DLDO 1.8 V.
101: VDRIVE
110: AGND.
111: AVCC
.
.
.
Table 70. Bit Descriptions for DIAGNOSTIC_MUX_CH5_6
Bits
[7:6]
[5:3]
Bit Name
RESERVED
CH6_DIAG_MUX_CTRL
Description
Reserved.
Reset
0x0
0x0
Access
R
R/W
Channel 6 Diagnostic Mux Control. Select 10 V range.
000: Analog input pin.
001: Temperature sensor.
010: 2.5 V reference.
011: ALDO 1.8 V.
100: DLDO 1.8 V.
Rev. 0 | Page 72 of 75
Data Sheet
AD7606C-18
Bits
Bit Name
Description
101: VDRIVE
Reset
Access
.
110: AGND.
111: AVCC.
[2:0]
CH5_DIAG_MUX_CTRL
Channel 5 Diagnostic Mux Control. Select 10 V range.
000: Analog input pin.
001: Temperature sensor.
010: 2.5 V reference.
011: ALDO 1.8 V.
0x0
R/W
100: DLDO 1.8 V.
101: VDRIVE
.
110: AGND.
111: AVCC.
Address: 0x2B, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH7_8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:3] CH8_DIAG_MUX_CTRL (R/W)
Channel 8 Diagnostic Mux Control. Select
±10 V range.
000: Analog Input pin.
001: Temperature sensor.
010: 2.5 V Reference.
011: ALDO 1.8 V.
[2:0] CH7_DIAG_MUX_CTRL (R/W)
Channel 7 Diagnostic Mux Control. Select
±10 V range.
000: Analog Input pin.
001: Temperature sensor.
010: 2.5 V Reference.
011: ALDO 1.8 V.
100: DLDO 1.8 V.
101: VDRIVE
110: AGND.
111: AVCC
.
100: DLDO 1.8 V.
101: VDRIVE
110: AGND.
111: AVCC
.
.
.
Table 71. Bit Descriptions for DIAGNOSTIC_MUX_CH7_8
Bits
[7:6]
[5:3]
Bit Name
RESERVED
CH8_DIAG_MUX_CTRL
Description
Reserved.
Reset
0x0
0x0
Access
R
R/W
Channel 8 Diagnostic Mux Control. Select 10 V range.
000: Analog input pin.
001: Temperature sensor.
010: 2.5 V reference.
011: ALDO 1.8 V.
100: DLDO 1.8 V.
101: VDRIVE
.
110: AGND.
111: AVCC.
[2:0]
CH7_DIAG_MUX_CTRL
Channel 7 Diagnostic Mux Control. Select 10 V range.
000: Analog input pin.
001: Temperature sensor.
010: 2.5 V reference.
011: ALDO 1.8 V.
0x0
R/W
100: DLDO 1.8 V.
101: VDRIVE
.
110: AGND.
111: AVCC.
Rev. 0 | Page 73 of 75
AD7606C-18
Data Sheet
Address: 0x2C, Reset: 0x00, Name: OPEN_DETECT_QUEUE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] OPEN_DETECT_QUEUE (R/W)
Open Detect Queue. When set to 1, open
detect is configured in manual mode. When
set to >1, open detect operates in automatic
mode and the value set in this register specifies
the number of conversions when there is
no change in output code before the PGA
common mode is switched.
Table 72. Bit Descriptions for OPEN_DETECT_QUEUE
Bits Bit Name Description
Reset Access
[7:0] OPEN_DETECT_QUEUE Open Detect Queue. When set to 1, open detect is configured in manual mode. When
set to >1, open detect operates in automatic mode and the value set in this register
specifies the number of conversions when there is no change in output code before
the PGA common mode is switched.
0x0
R/W
Address: 0x2D, Reset: 0x00, Name: FS_CLK_COUNTER
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CLK_FS_COUNTER (R)
A counter that is incremented at a frequency
of 16 Meg/64. Reading this register verifies
the operation and frequency of the FS_CLOCK.
Table 73. Bit Descriptions for FS_CLK_COUNTER
Bits Bit Name Description
[7:0] CLK_FS_COUNTER A counter that is incremented at a frequency of 16 Meg/64. Reading this register verifies
the operation and frequency of the FS_CLOCK.
Reset Access
0x0
R
Address: 0x2E, Reset: 0x00, Name: OS_CLK_COUNTER
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CLK_OS_COUNTER (R)
A counter that is incremented at a frequency
of 12.5 Meg/64. Reading this register verifies
the operation and frequency of the oversampling
clock.
Table 74. Bit Descriptions for OS_CLK_COUNTER
Bits Bit Name Description
Reset Access
[7:0] CLK_OS_COUNTER A counter that is incremented at a frequency of 12.5 Meg/64. Reading this register verifies
the operation and frequency of the oversampling clock.
0x0
R
Address: 0x2F, Reset: 0x31, Name: ID
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
1
[7:4] DEVICE_ID (R)
Generic
[3:0] SILICON_REVISION (R)
Silicon Revision.
0001: AD7606B generic.
0011: AD7606C-18 generic.
Table 75. Bit Descriptions for ID
Bits
Bit Name
Description
Reset
Access
[7:4]
DEVICE_ID
Generic.
0x3
R
0001: AD7606B generic.
0011: AD7606C-18 generic.
Silicon Revision.
[3:0]
SILICON_REVISION
0x1
R
Rev. 0 | Page 74 of 75
Data Sheet
AD7606C-18
OUTLINE DIMENSIONS
12.20
12.00 SQ
11.80
0.75
0.60
0.45
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
16
33
0.15
0.05
SEATING
17
32
PLANE
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 124. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD7606C-18BSTZ
AD7606C-18BSTZ-RL
EVAL-AD7606C18FMCZ
EVAL-SDP-CH1Z
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
ST-64-2
ST-64-2
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board for the AD7606C-18
Evaluation Controller Board
1 Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D24593-10/20(0)
Rev. 0 | Page 75 of 75
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