AD7674ASTRL
更新时间：2024-09-18 19:09:38
品牌：ADI
描述：IC 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48, LQFP-48, Analog to Digital Converter
概述
数据手册
替代型号AD7674ASTRL 概述
IC 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48, LQFP-48, Analog to Digital Converter
AD7674ASTRL 数据手册
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PDF下载PRELIMINARY TECHNICAL DATA
a
PreliminaryTechnicalData
18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC
AD7674
FEATURES
FUNCTIONAL BLOCK DIAGRAM
18 Bits Resolution with No Missing Codes
No Pipeline Delay ( SAR architecture )
Differential Input Range: ꢀVREF (VREF up to 5V)
Throughput:
800 kSPS (Warp Mode)
666 kSPS (Normal Mode)
PDBUF
REF
REFGND
DVDD DGND
AGND
AVDD
OVDD
OGND
AD7674
SERIAL
PORT
REFBUFIN
18
IN+
IN-
570 kSPS (Impulse Mode)
SWITCHED
CAP DAC
D[17:0]
BUSY
INL: ꢀ2.5 LSB Max (ꢀ9.5 ppm of Full-Scale)
Dynamic Range : 103 dB Typ ( VREF = 5V )
S/(N+D): 100 dB Typ @ 2 kHz ( VREF = 5V )
THD: –115 dB Typ @ 2 kHz
Parallel (18,16 or 8bits bus) and Serial 5V/3V Interface
SPI/QSPI/MICROWIRE/DSP Compatible
On-board Reference Buffer
PARALLEL
INTERFACE
RD
CS
CLOCK
PD
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
MODE0
MODE1
RESET
Single 5 V Supply Operation
CNVST
IMPULSE
WARP
Power Dissipation: 98 mW Typ @ 800 kSPS
68 mW @ 500 kSPS (Impulse)
PulSAR Selection
100 - 250 500 - 570
136 ꢁW @ 1 kSPS (Impulse)
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flat Pack (LQFP)
48-Lead Frame Chip Scale Package (LFCSP)
Pin-to-Pin Compatible Upgrade of the AD7676/AD7678/
AD7679
Type / kSPS
Pseudo
Differential
800 - 1000
AD7651
AD7660/61
AD7650/52
AD7664/66
AD7653
AD7667
True Bipolar
AD7663
AD7675
AD7665
AD7676
AD7671
AD7677
True
Differential
APPLICATIONS
CT Scanners
High Dynamic Data Acquisition
Geophone and hydrophone sensor
Sigma-Delta replacement (low power, multichannel)
Instrumentation
18 Bit
AD7678
AD7679
AD7674
Multichannel/
Simultaneous
AD7654
AD7655
Spectrum Analysis
Medical Instruments
PRODUCT HIGHLIGHTS
1. High resolution and Fast Throughput
GENERAL DESCRIPTION
The AD7674 is a 800 kSPS, charge redistribution,
The AD7674 is a 18-bit, 800 kSPS, charge redistribu-
tion SAR, fully differential analog-to-digital converter
that operates from a single 5 V power supply. The part
contains a high-speed 18-bit sampling ADC, an internal
conversion clock, an internal reference buffer, error
correction circuits, and both serial and parallel system
interface ports.
18-bit SAR ADC ( no latency ).
2. Excellent accuracy
The AD7674 has a maximum integral nonlinearity of 2.5
LSB with no missing 18-bit code.
3. Single-Supply Operation
The AD7674 operates from a single 5 V supply and
typically dissipates only 98 mW. In impulse mode, its
power dissipation decreases with the throughput as
68mW at 500kSPS. It consumes 7 W maximum when
in power-down.
It features a very high sampling rate mode (Warp) and,
for asynchronous conversion rate applications, a fast
mode (Normal) and, for low power applications, a re-
duced power mode (Impulse) where the power is scaled
with the throughput.
5. Serial or Parallel Interface
Versatile parallel (18, 16 or 8 bits bus) or 2-wire serial
interface arrangement compatible with both 3 V or 5 V
logic.
It is available in a 48-lead LQFP or a 48-lead LFCSP
with operation specified from –40°C to +85°C.
REV. PrC
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
(–40ꢂC to +85ꢂC, VREF = 4.096V, AVDD = DVDD= 5 V, OVDD = 2.7 V to 5.25 V, unless
otherwise noted.)
AD7674–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
R E S O L U T I O N
1 8
Bits
ANALOG INPUT
Voltage Range
Operating Input Voltage
Analog Input CMRR
Input Current
VIN+ – VIN-
IN+, VIN- to AGND
IN = TBD kHz
-VREF
–0.1
+VREF
AVDD
V
V
dB
µA
V
f
TBD
TBD
TBD kSPS Throughput
Input Impedance
See Analog Input Section
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
Time Between Conversions
Complete Cycle
Throughput Rate
In Warp Mode
In Warp Mode
In Warp Mode
In Normal Mode
In Normal Mode
In Impulse Mode
In Impulse Mode
1.25
800
1
µs
kSPS
ms
µs
kSPS
µs
1
1.5
0
0
666
1.75
570
Complete Cycle
Throughput Rate
kSPS
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise
Gain Error, TMIN to TMAX
Gain Error Temperature Drift
Zero Error, TMIN to TMAX
Zero Error Temperature Drift
Power Supply Sensitivity
–2.5
– 1
1 8
+2.5
+1.5
LSB1
L S B
Bits
L S B
% of FSR
ppm/°C
LSB
ppm/°C
LSB
V
REF=5V
0.7
2
TBD
TBD
TBD
TBD
TBD
TBD
2
AVDD = 5 V 5%
AC ACCURACY
Signal-to-Noise
fIN = 2 kHz, VREF=5V
101
9 9
T B D
T B D
103
dB3
d B
d B
d B
d B
d B
d B
d B
d B
d B
d B
d B
d B
M H z
VREF=4.096V 9 8
fIN = 10 kHz
fIN = 100 kHz
VIN+=VIN-=VREF/2=2.5V 101
fIN = 2 kHz
fIN = 10 kHz
fIN = 100 kHz
fIN = 2 kHz
fIN = 10 kHz
fIN = 100 kHz
fIN = 2 kHz,
Dynamic range
Spurious Free Dynamic Range
115
T B D
T B D
–115
T B D
T B D
100
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
–3 dB Input Bandwidth
fIN = 2 kHz,–60 dB Input
4 0
T B D
SAMPLING
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage recovery
DYNAMICS
2
ns
ps rms
ns
TBD
Full-Scale Step
250
250
ns
R E F E R E N C E
External Reference Voltage Range
REF Voltage with reference buffer
Reference Buffer Input Voltage Range
REFBUFIN Input Current
REF Current Drain
REF
2.5
4.05
1.5
–1
4.096
4.096
2.5
AVDD
4.15
TBD
+1
V
V
V
µA
µA
REFBUFIN = 2.5V
REFBUFIN
800 kSPS Throughput
TBD
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+2.0
–1
+0.8
DVDD + 0.3
+1
+1
V
V
µA
µA
IIH
–1
DIGITAL
Data Format
OUTPUTS
Parallel or Serial 18-Bits
Pipeline Delay
Conversion Results Available Immediately
After Completed Conversion
VOL
VOH
ISINK = 1.6 mA
ISOURCE = –500 µA
0.4
V
V
OVDD – 0.6
–2–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7674
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES
Specified Performance
AVDD
4.75
4.75
2.7
5
5
5.25
V
V
V
DVDD
5.25
OVDD
DVDD+0.34
Operating Current5
AVDD
800 kSPS Throughput
15
4.5
130
mA
mA
µA
DVDD6
OVDD6
Power Dissipation6
PDBUF low @500 kSPS7
PDBUF high @500 kSPS7
PDBUF high @1 kSPS7
PDBUF high @800 kSPS5
PDBUF low @800 kSPS5
In Power-Down Mode8
73
68
136
98
103
TBD
mW
mW
µW
mW
mW
µW
TBD
7
TEMPERATURE RANGE9
Specified Performance
TMIN to TMAX
–40
+85
°C
N O T E S
1LSB means Least Significant Bit. With the 4.096
V input range, one LSB is 31.25 µV.
2See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4The max should be the minimum of 5.25V and DVDD+0.3V.
5In warp mode.
6Tested in parallel reading mode.
7In impulse mode.
8With all digital inputs forced to DVDD or DGND respectively.
9Contact factory for extended temperature range.
Specifications subject to change without notice.
(–40ꢂC to +85ꢂC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
REFER TO FIGURES 12 AND 13
Convert Pulsewidth
Time Between Conversions
t1
t2
5
ns
µs
1.25/1.5/1.75
Note 1
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in Master Serial Read After
t3
t4
30
ns
µs
1/1.25/1.5
Convert
Aperture Delay
(Warp Mode/Normal Mode/Impulse Mode)
t5
t6
t7
t8
t9
2
ns
ns
µs
ns
ns
End of Conversion to BUSY LOW Delay
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
10
1/1.25/1.5
1/1.25/1.5
250
10
RESET Pulsewidth
REFER TO FIGURES 14, 15, AND 16 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
Data Valid to BUSY LOW Delay
Bus Access Request to Data Valid
Bus Relinquish Time
t10
µs
t11
t12
t13
45
5
ns
ns
ns
40
15
REV. PrC
–3–
PRELIMINARY TECHNICAL DATA
AD7674
TIMING SPECIFICATIONS (continued)
Symbol
Min
Typ
Max
Unit
REFER TO FIGURES 18 AND 19 (Master Serial Interface Modes)2
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
t14
t15
t16
t17
10
10
10
ns
ns
ns
ns
CNVST LOW to SYNC Delay
25/275/525
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay3
Internal SCLK Period3
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
3
ns
ns
ns
ns
ns
ns
25
12
7
4
2
40
Internal SCLK HIGH3
Internal SCLK LOW3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SCLK Last Edge to SYNC Delay3
CS HIGH to SYNC HI-Z
3
10
10
10
ns
ns
ns
µs
µs
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert3
CNVST LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
See Table I
1/1.25/1.5
t30
25
ns
REFER TO FIGURES 20 AND 22 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
t31
t32
t33
t34
t35
t36
t37
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
18
External SCLK HIGH
External SCLK LOW
NOTES
1Inwarpmodeonly,themaximumtimebetweenconversionsis1ms;otherwise,thereisnorequiredmaximumtime.
2Inserialinterfacemodes,theSYNC,SCLK,andSDOUTtimingsaredefinedwithamaximumloadCLof10pF;otherwise,theloadis60pFmaximum.
3Inserialmasterreadduringconvertmode.SeeTableIforserialmasterreadafterconvertmode.
Specificationssubjecttochangewithoutnotice.
Table I. Serial clock timings in Master Read after Convert
DIVSCLK[1]
0
0
1
1
unit
DIVSCLK[0]
0
1
0
1
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum (Warp)
Busy High Width Maximum (Normal)
Busy High Width Maximum (Impulse)
t18
t19
t19
t20
t21
t22
t23
t24
t28
t28
t28
3
17
50
70
22
21
18
4
60
2.25
2.5
2.75
17
17
200
280
100
99
18
89
300
5.5
5.8
6
ns
ns
ns
ns
ns
ns
ns
ns
µ s
µ s
µ s
25
40
12
7
4
2
100
140
50
49
18
30
3
140
3.25
3.5
3.75
1.75
2
2.25
–4–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7674
ABSOLUTE MAXIMUM RATINGS1
1.6mA
I
OL
Analog Inputs
IN+2, IN-2, REF, REFBUFIN, REFGND to AGND
. . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
TO OUTPUT
PIN
1.4V
C
60pF*
L
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . 0.3 V
Supply Voltages
I
500ꢁA
OH
AVDD, DVDD, OVDD . . . . . . . . . . . . . -0.3V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . 7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . -0.3V to +7 V
Digital Inputs . . . . . . . . . . . . –0.3 V to DVDD + 0.3V
Internal Power Dissipation3 . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . . 2.5W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . –65°C to +150°C
Lead Temperature Range
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
*
C
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
L
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
2V
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
0.8V
tDELAY
tDELAY
N O T E S
1Stresses above those listed under Absolute Maximum Ratings may
2V
2V
cause permanent damage to the device. This is
a stress rating only;
0.8V
0.8V
functional operation of the device at these or any other conditions above
those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
Figure 2. Voltage Reference Levels for Timing
2See Analog Input section.
3Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θJC
30°C/W.
=
4Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD7674AST
AD7674ASTRL
AD7674ACP
AD7674ACPRL
EVAL-AD7674CB1
EVAL-CONTROL BRD22
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Quad Flatpack (LQFP)
Quad Flatpack (LQFP)
Chip Scale (LFCSP)
Chip Scale (LFCSP)
Evaluation Board
ST-48
ST-48
CP-48
CP-48
Controller Board
NOTES
1This board can be used as
purposes.
a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration
2This board allows
a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7674 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARN-
ING!
ESD SENSITIVE
DEVICE
REV. PrC
–5–
PRELIMINARY TECHNICAL DATA
AD7674
PIN CONFIGURATION
48-Lead LQFP and 48-Lead LFCSP
(ST-48 and CP-48)
48
47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
AGND
AVDD
36 AGND
PIN 1
IDENTIFIER
35 CNVST
MODE0
MODE1
D0/OB/2C
WARP
34
33
32
31
30
29
PD
RESET
CS
AD7674
TOP VIEW
(Not to Scale)
RD
IMPULSE
DGND
BUSY
D17
D1/A0
8
9
D2/A1
D3
28
27
26
25
10
11
12
D16
D4/DIVSCLK[0]
D5/DIVSCLK[1]
D15
D14
13 14 15 16 17 18
21 22 23 24
19 20
NC = NO CONNECT
–6–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7674
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Type
Description
1, 44
2, 47
40–42,45 NC
AGND
AVDD
P
P
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 5 V.
No Connect.
3
4
MODE0
MODE1
DI
DI
Data Output Interface mode Selection.
Data Output Interface mode Selection:
Interface MODE #
MODE0
MODE1
Description
0
1
2
3
0
0
1
1
0
1
0
1
18-bit Interface
16-bit Interface
Byte Interface
Serial Interface
5
D0/OB/2C
DI/O When MODE=0 (18 bit interface mode), this pin is Bit 0 of the parallel port data
output bus and the data coding is straight binary. In all other modes, this pin allows
choice of Straight Binary/Binary Two’s Complement.When OB/2C is HIGH, the
digital output is straight binary; when LOW, the MSB is inverted resulting in a two’s
complement output from its internal shift register.
6
7
WARP
DI
Conversion mode selection. When HIGH and IMPULSE LOW, this input selects
the fastest mode, the maximum throughput is achievable, and a minimum conversion
rate must be applied in order to guarantee full specified accuracy. When LOW, full
accuracy is maintained independent of the minimum conversion rate.
Conversion mode selection. When HIGH and WARP LOW, this input selects a
reduced power mode. In this mode, the power dissipation is approximately
proportional to the sampling rate.
IMPULSE
DI
8
9
D1/A0
D2/A1
DI/O
DI/O
When MODE=0 (18-bit interface mode), this pin is Bit 1 of the parallel port data
output bus. In all other modes, this input pin controls the form in which data is
output as shown in Table II.
When MODE=0 or MODE=1 (18-bit or 16-bit interface mode), this pin is Bit 2 of
the parallel port data output bus. In all other modes, this input pin controls the form
in which data is output as shown in Table II.
10
D3
D O
In all modes except MODE=3, this output is used as Bit 3 of the Parallel Port
Data Output Bus. This pin is always an output regard less of the interface mode.
In all modes except MODE=3, these pins are Bit 4 and Bit 5 of the Parallel
Port Data Output Bus.
In MODE=3 (serial mode), when EXT/INT is LOW, and RDC/SDIN is LOW,
which is serial master read after convert, these inputs, part of the serial port, are used
to slow down if desired the internal serial clock which clocks the data output. In other
serial modes, these pins are not used.
11,12
D[4:5]or
DIVSCLK[0:1]
DI/O
13
14
D6
DI/O
DI/O
In all modes except MODE=3, this output is used as Bit 6 of the Parallel Port
Data Output Bus.
When MODE=3 (serial mode), this input, part of the serial port, is used as a digital
select input for choosing the internal or an external data clock. With EXT/INT tied
LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic
HIGH, output data is synchronized to an external clock signal connected to the
SCLK input.
or EXT/INT
D7
In all modes except MODE=3, this output is used as Bit 7 of the Parallel Port
Data Output Bus.
or INVSYNC
When MODE=3 (serial mode), this input, part of the serial port, is used to select the
active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.
15
16
D8
DI/O
DI/O
In all modes except MODE=3, this output is used as Bit 8 of the Parallel Port
Data Output Bus.
When MODE=3 (serial mode), this input, part of the serial port, is used to invert the
SCLK signal. It is active in both master and slave mode.
In all modes except MODE=3, this output is used as Bit 9 of the Parallel Port
Data Output Bus.
or INVSCLK
D9
or RDC/SDIN
When MODE=3 (serial mode), this input, part of the serial port, is used as either an
REV. PrC
–7–
PRELIMINARY TECHNICAL DATA
AD7674
Pin No.
Mnemonic
Type
Description
external data input or a read mode selection input depending on the state of
EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain
the conversion results from two or more ADCs onto a single SDOUT line. The
digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods
after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When
RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When
RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is
complete.
17
18
OGND
OVDD
P
P
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply than the supply
of the host interface (5 V or 3 V). Should not exceed DVDD by more than 0.3V.
Digital Power. Nominally at 5 V.
Digital Power Ground.
In all modes except MODE=3, this output is used as Bit 10 of the Parallel Port
19
20
21
DVDD
DGND
D10
P
P
D O
Data Output Bus.
or SDOUT
When MODE=3 (serial mode), this output, part of the serial port, is used as a serial
data output synchronized to SCLK. Conversion results are stored in an on-chip
register. The AD7674 provides the conversion result, MSB first, from its internal
shift register. The data format is determined by the logic level of OB/2C.
In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK.
In serial mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the
next falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the
next rising edge.
In all modes except MODE=3, this output is used as the Bit 11 of the Parallel
Port Data Output Bus.
When MODE=3 (serial mode), this pin, part of the serial port, is used as a serial
data clock input or output, dependent upon the logic state of the EXT/INT pin. The
active edge where the data SDOUT is updated depends upon the logic state of the
INVSCLK pin.
In all modes except MODE=3, this output is used as the Bit 12 of the Parallel
Port Data Output Bus.
22
23
D11
DI/O
D O
or SCLK
D12
or SYNC
When MODE=3 (serial mode), this output, part of the serial port, is used as a digital
output frame synchronization for use with the internal data clock (EXT/INT = Logic
LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven
HIGH and remains HIGH while SDOUT output is valid. When a read sequence is
initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while
SDOUT output is valid.
24
D13
D O
In all modes except MODE=3, this output is used as the Bit 11 of the Parallel
Port Data Output Bus.
or RDERROR
In MODE=3 (serial mode) and when EXT/INT is HIGH, this output, part of the
serial port, is used as a incomplete read error flag. In slave mode, when a data
read is started and not complete when the following conversion is complete, the
current data is lost and RDERROR is pulsed high.
25–28
D[14:17]
BUSY
D O
D O
Bit 14 to Bit 17 of the Parallel Port Data output bus. These pins are always outputs
regard less of the interface mode.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH
until the conversion is complete and the data is latched into the on-chip shift register.
The falling edge of BUSY could be used as a data ready clock signal.
Must be tied to digital ground.
29
30
31
DGND
RD
P
DI
Read Data. When CS and RD are both LOW, the interface parallel or serial output
bus is enabled.
32
33
CS
DI
DI
Chip Select. When CS and RD are both LOW, the interface parallel or serial output
bus is enabled. CS is also used to gate the external clock.
Reset Input. When set to a logic HIGH, reset the AD7674. Current conversion if any
is aborted. If not used, this pin could be tied to DGND.
RESET
–8–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7674
Pin No.
Mnemonic
Type
Description
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and
conversions are inhibited after the current one is completed.
Start Conversion. A falling edge on CNVST puts the internal sample/hold into the
hold state and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP
LOW), if CNVST is held LOW when the acquisition phase (t8) is complete, the
internal sample/hold is put into the hold state and a conversion is immediately
started.
35
CNVST
DI
36
37
AGND
REF
P
AI
Must be tied to analog ground.
Reference Input Voltage and Internal Reference Buffer Output. Apply an external
reference on this pin if the internal reference buffer is not used. Should be decoupled
effectively with or without the internal buffer.
38
39
43
46
REFGND
IN-
IN+
AI
AI
AI
Reference Input Analog Ground.
Differential Negative Analog Input.
Differential Negative Analog Input.
Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It
outputs 4.096V typically when 2.5V is applied on this pin.
Allows choice of buffering reference. When LOW, the buffer is selected. When
HIGH, the buffer is switched off.
REFBUFIN AI
48
PDBUF DI
NOTES
AI = Analog Input
AI/O = Bidirectional Analog
AO = Analog Output
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
Table II. Data Bus Interface Definition
MODE MODE0 MODE1 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] DESCRIPTION
0
1
1
2
2
2
2
3
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
1
R[0]
OB/2C A0:0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-Bit High Word
OB/2C A0:1 R[0] R[1] All Zeros 16-Bit Low Word
R[10:11] R[12:15] R[16:17] 8-Bit HIGH Byte
R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-Bit Parallel
OB/2C A0:0 A1:0
OB/2C A0:0 A1:1
OB/2C A0:1 A1:0
OB/2C A0:1 A1:1
All Hi-Z
All Hi-Z
All Hi-Z
All Hi-Z
R[2:3]
R[0:1]
R[4:7]
All Zeros
R[0:1]
R[8:9]
8-Bit MID Byte
8-Bit LOW Byte
8-Bit LOW Byte
Serial Interface
All Zeros
Serial Interface
OB/2C
All Hi-Z
R[0:17] is the 18-bit ADC value stored in its output register.
REV. PrC
–9–
PRELIMINARY TECHNICAL DATA
AD7674
DEFINITION OF SPECIFICATIONS
Effective number of bits (ENOB)
ENOB is a measurement of the resolution with a sine
wave input. It is related to S/(N+D) by the following for-
mula:
Integral nonlinearity error (INL)
Linearity error refers to the deviation of each individual
code from a line drawn from “negative full scale” through
“positive full scale”. The point used as “negative full
scale” occurs 1/2 LSB before the first code transition.
“Positive full scale” is defined as a level 1 1/2 LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line.
ENOB = (S/[N+D]dB – 1.76)/6.02)
and is expressed in bits.
Total harmonic distortion (THD)
THD is the ratio of the rms sum of the first five har-
monic components to the rms value of a full-scale input
signal and is expressed in decibels.
Differential nonlinearity error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differ-
ential nonlinearity is the maximum deviation from this
ideal value. It is often specified in terms of resolution for
which no missing codes are guaranteed.
Dynamic range
Dynamic range is the ratio of the rms value of the full
scale to the rms noise measured with the inputs shorted
together. The value for dynamic range is expressed in
decibels.
Gain error
The first transition (from 000 . . . 00 to 000 . . . 01)
should occur for an analog voltage 1/2 LSB above the
nominal –full scale (-4.095991 V for the 4.096V range).
The last transition (from 111 . . . 10 to 111 . . . 11)
should occur for an analog voltage 1 1/2 LSB below the
nominal full scale (4.095977 V for the 4.096V range).
The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of
the first transition from the difference between the ideal
levels.
Signal-to-noise ratio (SNR)
SNR is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding harmonics and dc. The
value for SNR is expressed in decibels.
Signal to (noise + distortion) ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input
signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but
excluding dc. The value for S/(N+D) is expressed in deci-
bels.
Zero error
The zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
Aperture delay
Aperture delay is a measure of the acquisition performance
and is measured from the falling edge of the CNVST
input to when the input signal is held for a conversion.
Spurious free dynamic range (SFDR)
The difference, in decibels (dB), between the rms ampli-
tude of the input signal and the peak spurious signal.
Transient response
The time required for the AD7674 to achieve its rated
accuracy after a full-scale step function is applied to its
input.
–10–
REV. PrC
PRELIMINARY TECHNICAL DATA
Typical Performance Characteristics- AD7674
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
0.0
-0.5
-1.0
0
65536
131072
Code
196608
262144
0
65536
131072
Code
196608
262144
TPC 4. Differential Nonlinearity vs. Code
TPC 1. Integral Nonlinearity vs. Code
To Be Supplied
To Be Supplied
TPC 5. Histogram of 131,072 Conversions of a DC Input
at the Code Center
TPC 2. Histogram of 131,072 Conversions of a DC Input
at the Code Transition
To Be Supplied
To Be Supplied
TPC 6. Typical Negative INL Distribution (TBD Units)
TPC 3. Typical Positive INL Distribution (TBD Units)
REV. PrC
–11–
PRELIMINARY TECHNICAL DATA
AD7674
To Be Supplied
To Be Supplied
TPC 7. Typical INL and DNL vs Temperature
TPC 10. Typical INL and DNL vs Sampling rate
To Be Supplied
To Be Supplied
TPC 8. FFT
TPC 11. SNR, S/(N+D) and ENOB vs. Frequency
To Be Supplied
To Be Supplied
TPC 9. FFT after digital filtering
TPC 12. THD, SFDR and Harmonics vs. Frequency
–12–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7674
To Be Supplied
To Be Supplied
TPC 16.Operating Current vs. Sampling Rate
TPC 13. SNR, S/(N+D) and THD vs. Input Level
To Be Supplied
To Be Supplied
TPC 17. Power-Down Operating Currents vs. Temperature
TPC 14. SNR, S/(N+D) and ENOB vs Temperature
To Be Supplied
To Be Supplied
TPC 18. Positive and Negative Full Scale, Offset and Refer-
ence Buffer Gain vs. Temperature
TPC 15. THD, SFDR and Harmonics vs Temperature
REV. PrC
–13–
PRELIMINARY TECHNICAL DATA
AD7674
To Be Supplied
TPC 19.Positive and Negative Full Scale, Offset and
Reference Buffer Gain vs. Supply .
To Be Supplied
TPC 20.Typical Delay vs. Load Capacitance CL
–14–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7674
IN+
SWITCHES CONTROL
SW
+
MSB
LSB
262,144C 131,072C
4C
2C
2C
C
C
BUSY
CONTROL
LOGIC
REF
COMP
OUTPUT CODE
REFGND
262,144C 131,072C
MSB
4C
C
C
SW
-
LSB
CNVST
IN -
Figure 3. ADC Simplified Schematic
CIRCUIT INFORMATION
nected from the inputs and connected to the REFGND
input. Therefore, the differential voltage between the in-
puts IN+ and IN- captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each
element of the capacitor array between REFGND or REF,
the comparator input varies by binary weighted voltage
steps (VREF/2, VREF/4 . . . VREF/262144). The control logic
toggles these switches, starting with the MSB first, in
order to bring the comparator back into a balanced condi-
tion. After the completion of this process, the control
logic generates the ADC output code and brings BUSY
output low.
The AD7674 is a very fast, low-power, single-supply,
precise 18-bit analog-to-digital converter (ADC) using
successive approximation architecture.
The AD7674 linearity and dynamic range are similar or
better than many sigma-delta ADCs. With the advantages
of its succesive architecture which ease multiplexing and
reduce power with throughput, it can be used advanta-
geously in applications usually using sigma-delta ADCs.
The AD7674 features different modes to optimize perfor-
mances according to the applications.
In Warp mode, the AD7674 is capable of converting
800,000 samples per second (800 kSPS).
Modes of Operation
The AD7674 features three modes of operations, Warp,
Normal, and Impulse. Each of these modes is more suit-
able for specific applications.
The AD7674 provides the user with an on-chip
track/hold, successive approximation ADC that does not
exhibit any pipeline or latency, making it ideal for mul-
tiple multiplexed channel applications.
The Warp mode allows the fastest conversion rate up to
800 kSPS. However, in this mode, and this mode only, the
full specified accuracy is guaranteed only when the time
between conversion does not exceed 1 ms. If the time be-
tween two consecutive conversions is longer than 1 ms, for
instance, after power-up, the first conversion result should
be ignored. This mode makes the AD7674 ideal for appli-
cations where fast sample rate are required.
The AD7674 can be operated from a single 5 V supply
and be interfaced to either 5 V or 3 V digital logic. It is
housed in a 48-lead LQFP or a tiny LFCSP packages that
combines space savings and allows flexible configurations
as either serial or parallel interface. The AD7674 is a pin-
to-pin-compatible upgrade of the AD7676, AD7678,
AD7679.
The normal mode is the fastest mode (666 kSPS) without
any limitation about the time between conversions. This
mode makes the AD7674 ideal for asynchronous appli-
cations such as data acquisition systems, where both high
accuracy and fast sample rate are required.
CONVERTER OPERATION
The AD7674 is a successive approximation analog-to-
digital converter based on a charge redistribution DAC.
Figure 3 shows the simplified schematic of the ADC.
The capacitive DAC consists of two identical arrays of 18
binary weighted capacitors which are connected to the two
comparator inputs.
The impulse mode, the lowest power dissipation mode,
allows power saving between conversions. The maximum
throughput in this mode is 570 kSPS. When operating at
100 SPS, for example, it typically consumes only 15 µW.
This feature makes the AD7674 ideal for battery-powered
applications.
During the acquisition phase, terminals of the array tied to
the comparator’s input are connected to AGND via SW+
and SW-. All independent switches are connected to the
analog inputs. Thus, the capacitor arrays are used as sam-
pling capacitors and acquire the analog signal on IN+ and
IN- inputs. When the acquisition phase is complete and
the CNVST input goes low, a conversion phase is initi-
ated. When the conversion phase begins, SW+ and SW- are
opened first. The two capacitor arrays are then discon-
Transfer Functions
Except in 18 Bit interface mode, using the OB/2C digital
input, the AD7674 offers two output codings: straight
binary and two’s complement. The ideal transfer charac-
teristic for the AD7674 is shown in Figure 4 and Table
III.
REV. PrC
–15–
PRELIMINARY TECHNICAL DATA
AD7674
Table I. Output Codes and Ideal Input Voltages
Digital Output Code
Hexa
111...111
111...110
111...101
Analog
Straight Two’s
D
escription
Input
VREF = 4.096V
Binary
Comple-
ment
FSR –1 LSB
FSR – 2 LSB
Midscale + 1 LSB 31.25µV
Midscale 0 V
Midscale – 1 LSB -31.25µV
4.095962 V
4.095924 V
3FFFF1 1FFFF1
3 F F F E
20001
1 F F E
00001
00000
3 F F F F
20001
200002
20000
000...010
000...001
000...000
1 F F F F
–FSR + 1 LSB
–FSR
-4.095962 V 00001
-4.096 V
000002
-FS
-FS+1 LSB
+FS-1 LSB
+FS-1.5 LSB
ANALOG INPUT
-FS+0.5 LSB
N O T E S
1This is also the code for overrange analog input (VIN+ – VIN- above
VREF
– VREFGND).
Figure 4. ADC Ideal Transfer Function
2This is also the code for underrange analog input (VIN+ – VIN- below
-VREF
+ VREFGND).
DVDD
ANALOG
SUPPLY
(5V)
20ꢃ
DIGITAL SUPPLY
(3.3V OR 5V)
note 6
100nF
100nF
100nF
10ꢁF
10ꢁF
10ꢁF
ADR421
AVDD AGND
DGND
DVDD
OVDD
OGND
SERIAL
PORT
REFBUFIN
2.5V REF
note 1
SCLK
100 nF
1Mꢃ
50kꢃ
100nF
SDOUT
note 3
REF
BUSY
CREF
ꢁC/ꢁP/DSP
AD7674
50ꢃ
10ꢁF
D
CNVST
note 2
REFGND
IN+
MODE0
MODE1
OB/2C
note 7
15ꢃ
U1
note 4
DVDD
ANALOG INPUT+
2.7nF
note 5
AD8021
C
C
PDBUF
CS
CLOCK
RD
15ꢃ
U2
IN-
RESET
PD
note 4
ANALOG INPUT-
2.7nF
AD8021
C
C
note
5
NOTES :
Note 1 : See Voltage Reference Input Section.
Note 2 : C is 10ꢁF ceramic capacitor or low esr tantalum. Ceramic size 1206 Panasonic ECJ-3xB0J106 is recommended. See Voltage Reference Input Section.
REF
Note 3 : Optional circuitry for hardware gain calibration.
Note 4 : The AD8021 is recommended. See Driver Amplifier Choice Section.
Note 5 : See Analog Inputs Section.
Note 6 : Option. See Power Supply Section.
Note 7 : Optional Low jitter CNVST. See Conversion Control Section.
Figure 5. Typical Connection Diagram ( internal reference buffer, serial interface ).
–16–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7674
TYPICAL CONNECTION DIAGRAM
During the acquisition phase, for AC signals, the AD7674
behaves like a one pole RC filter consisted of the equiva-
lent resistance R+ , R- and CS. The resistors R+ and R-
are typically 87 ⍀ and are lumped component made up of
some serial resistor and the on resistance of the switches.
The capacitor CS is typically 60 pF and is mainly the ADC
sampling capacitor. This one pole filter with a typical -3dB
cutoff frequency of 30 MHz reduces undesirable aliasing
effect and limits the noise coming from the inputs.
Figure 5 shows a typical connection diagram for the
AD7674. Different circuitry shown on this diagram are
optional and are discussed below.
Analog Inputs
Figure 6 shows a simplified analog input section of the
AD7674.
AVDD
Because the input impedance of the AD7674 is very high,
the AD7674 can be driven directly by a low impedance
source without gain error. That allows to put, as shown in
Figure 5, an external one-pole RC filter between the out-
put of the amplifier output and the ADC analog inputs to
even further improve the noise filtering done by the
AD7674 analog input circuit. However, the source imped-
ance has to be kept low because it affects the ac
R
= 87ꢃ
+
IN+
IN-
C
s
C
s
R
= 87ꢃ
-
performances, especially the total harmonic distortion.
The maximum source impedance depends on the amount
of total harmonic distortion (THD) that can be tolerated.
The THD degrades as a function of the source impedance
and the maximum input frequency as shown in Figure 8.
AGND
Figure 6. AD7674 simplified Analog Input.
The diodes shown in Figure 6 provide ESD protection for
the inputs. Care must be taken to ensure that the analog
input signal never exceeds the absolute ratings on these
inputs. This will cause these diodes to become forward-
biased and start conducting current. These diodes can
handle a forward-biased current of 120 mA maximum.
This condition could eventually occur when the input
buffer's (U1) or (U2) supplies are different from AVDD.
In such case, an input buffer with a short-circuit current
limitation can be used to protect the part.
To Be Supplied
This analog input structure is a true differential structure.
By using these differential inputs, signals common to both
inputs are rejected as shown in Figure 7 which represents
the typical CMRR over frequency.
Figure 8. THD Vs. Analog Input Frequency and
Source Resistance.
Driver Amplifier Choice
Although the AD7674 is easy to drive, the driver amplifier
needs to meet at least the following requirements:
To Be Supplied
•
The driver amplifier and the AD7674 analog input
circuit have to be able together to settle for a full-scale
step the capacitor array at a 18-bit level (0.0004%). In
the amplifier’s datasheet, the settling at 0.1% or 0.01%
is more commonly specified. It could significantly dif-
fer from the settling time at 18 bit level and, therefore,
it should be verified prior to the driver selection. The
tiny op-amp AD8021 which combines ultra low noise
and a high gain bandwidth meets this settling time
requirement.
Figure 7. Analog Input CMRR vs. Frequency
•
The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR
REV. PrC
–17–
PRELIMINARY TECHNICAL DATA
AD7674
and transition noise performance of the AD7674. The
noise coming from the driver is filtered by the AD7674
analog input circuit one-pole low-pass filter made by
R+, R- and CS. The SNR degradation due to the ampli-
fier is :
U1
ANALOG INPUT
(UNIPOLAR 0 to 4.096V)
AD8021
10pF
IN+
IN-
15ꢃ
15ꢃ
590ꢃ
2.7nF
2.7nF
AD7674
590ꢃ
25
U2
1.82kꢃ
8.25kꢃ
REF
REFBUFIN
SNRLOSS = 20LOG
AD8021
10pF
,
2
)
100nF
10ꢁF
625 + ꢄf -3dB Ne
N
(
2.5V
where :
Figure 9. Single Ended to Differential Driver Circuit (
internal reference buffer used )
f-3dB is the -3dB input bandwidth in MHz of the AD7674
(30 MHz) or the cutoff frequency of the input filter if
any used
Voltage Reference
N is the noise factor of the amplifiers ( 1 if in buffer con-
figuration )
The AD7674 allows the use of an external voltage ref-
erence either with or without the internal reference
buffer.
eN is the equivalent input noise voltage of each op-amp in
nV/(Hz)1/2
It is recommended to use the internal reference buffer
when it is desired to share a common reference voltage
between multiple ADCs.
For instance, a driver with an equivalent input noise of
2nV/ΊHz like the AD8021 and configured as a buffer, thus
with a noise gain of +1, the SNR degrades by only 0.34
dB with the filter in figure 5, and 2 dB without.
However, the advantages to use the external reference
voltage directly are :
•
The driver needs to have a THD performance suitable
to that of the AD7674.
- The power saving of about 5mW typical when the inter-
nal reference buffer is powered down ( PDBUF High )
The AD8021 meets these requirements and is usually
appropriate for almost all applications. The AD8021
needs an external compensation capacitor of 10 pF. This
capacitor should have good linearity as an NPO ceramic
or mica type.
- The SNR and dynamic range improvement of about 1.7
dB resulting of the use of a reference voltage very close to
the supply (5V) instead of a typical 4.096V reference when
the internal buffer is used.
To use the internal reference buffer, PDBUF should be
LOW. A 2.5V reference voltage applied on REFBUFIN
input will result in a 4.096V reference on REF pin.
The AD8022 could also be used where dual version is
needed and gain of 1 is used.
The AD829 is another alternative where high frequency (
above 100 kHz ) performances is not required. In gain of
1, it requires a 82pF compensation capacitor.
In both cases, the voltage reference input REF has a dy-
namic input impedance and requires, therefore, an
efficient decoupling between REF and REFGND inputs.
When the internal reference buffer is used, this decoupling
consists of a 10 µF ceramic capacitor ( e.g. : Panasonic
ECJ-3xB0J106 1206 size ).
When external reference is used, the decoupling con-
sists of a low ESR 47 µF tantalum capacitor connected
to the REF and REFGND inputs with minimum parasitic
inductance.
The AD8610 is also another option where low bias cur-
rent is needed in low frequency applications.
Single to Differential Driver
For applications using unipolar analog signals, a single-
ended to differential driver will allow for a differential
input into the part. The schematic is shown in Figure 9.
This configuration, when provided an input signal of 0 to
VREF , will produce a differential ꢀ VREF with midscale at
VREF/2.
Care should also be taken with the reference temperature
coefficient of the voltage reference which directly affects
the full-scale accuracy if this parameter matters. For in-
stance, a 4 ppm/°C tempco of the reference changes the
full scale by 1 LSB/°C.
If the application can tolerate more noise, the AD8138,
differential driver, can be used.
Power Supply
The AD7674 uses three sets of power supply pins: an analog
5 V supply AVDD, a digital 5 V core supply DVDD, and
a digital input/output interface supply OVDD. The
–18–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7674
OVDD supply allows direct interface with any logic work-
ing between 2.7 V and DVDD + 0.3 V. To reduce the
number of supplies needed, the digital core (DVDD)
can be supplied through a simple RC filter from the ana-
log supply as shown in Figure 5. The AD7674 is
independent of power supply sequencing, once OVDD
does not exceed DVDD by more than 0.3V, and thus free
from supply voltage induced latchup. Additionally, it is very
insensitive to power supply variations over a wide frequency
range as shown in Figure 10.
To Be Supplied
To Be Supplied
Figure 11. Power Dissipation vs. Sample Rate
Figure 10. PSRR vs. Frequency
POWER DISSIPATION Vs. THROUGHPUT
In Impulse mode, the AD7674 automatically reduces its
power consumption at the end of each conversion phase.
During the acquisition phase, the operating currents are
very low which allows a significant power saving when the
conversion rate is reduced as shown in Figure 11. This
feature makes the AD7674 ideal for very low-power bat-
tery applications.
It should be noted that the digital interface remains active
even during the acquisition phase. To reduce the operat-
ing digital supply currents even further, the digital inputs
need to be driven close to the power rails (i.e., DVDD
and DGND) and OVDD should not exceed DVDD by
more than 0.3V.
REV. PrC
–19–
PRELIMINARY TECHNICAL DATA
AD7674
CONVERSION CONTROL
Figure 12 shows the detailed timing diagrams of the con-
version process. The AD7674 is controlled by the signal
CNVST which initiates conversion. Once initiated, it
cannot be restarted or aborted, even by the power-down
input PD, until the conversion is complete. The CNVST
signal operates independently of CS and RD signals.
t
9
RESET
BUSY
t
2
t
1
DATA
BUS
CNVST
BUSY
t
8
CNVST
t
4
t
3
t
6
Figure 13. RESET Timing
t
5
MODE
ACQUIRE
CONVERT
ACQUIRE
CONVERT
t
t
7
8
DIGITAL INTERFACE
The AD7674 has a versatile digital interface; it can be
interfaced with the host system by using either a serial or
parallel interface. The serial interface is multiplexed on
the parallel data bus. The AD7674 digital interface also
accommodates both 3 V or 5 V logic by simply connect-
ing the OVDD supply pin of the AD7674 to the host
system interface digital supply. Finally, except in 18 bit
interface mode, by using the OB/2C input pin, both
two’s complement or straight binary coding can be used.
Figure 12. Basic Conversion Timing
Although CNVST is a digital signal, it should be de-
signed with this special care with fast, clean edges and
levels, with minimum overshoot and undershoot or ring-
ing.
For applications where the SNR is critical, the CNVST
signal should have a very low jitter. Some solutions to
achieve that are to use a dedicated oscillator for CNVST
generation or, at least, to clock it with a high frequency
low jitter clock as shown in Figure 5.
The two signals CS and RD control the interface. When
at least one of these signals is high, the interface outputs
are in high impedance. Usually, CS allows the selection
of each AD7674 in multi-circuits applications and is
held low in a single AD7674 design. RD is generally
used to enable the conversion result on the data bus.
In impulse mode, conversions can be automatically initi-
ated. If CNVST is held low when BUSY is low, the
AD7674 controls the acquisition phase and then automati-
cally initiates a new conversion. By keeping CNVST low,
the AD7674 keeps the conversion process running by itself.
It should be noted that the analog input has to be settled
when BUSY goes low. Also, at power-up, CNVST should
be brought low once to initiate the conversion process. In
this mode, the AD7674 could sometimes run slightly faster
then the guaranteed limits in the impulse mode of 570
kSPS. This feature does not exist in warp or normal modes.
CS = RD = 0
t
1
CNVST
t
10
BUSY
t
4
t
3
t
11
DATA
BUS
PREVIOUS CONVERSION DATA
NEW DATA
Figure 14. Master Parallel Data Timing for Reading
(Continuous Read)
–20–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7674
CS = 0
CNVST, RD
PARALLEL INTERFACE
t1
The AD7674 is configured to use the parallel interface
with either a 18-bit, 16-bit or 8-bit bus width according to
the Table II. The data can be read either after each con-
version, which is during the next acquisition phase, or
during the following conversion as shown, respectively, in
Figure 15 and Figure 16. When the data is read during
the conversion, however, it is recommended that it is read
only during the first half of the conversion phase. That
avoids any potential feedthrough between voltage transients
on the digital interface and the most critical analog con-
version circuitry. Please refer to table II for a detailed
description of the different options available.
BUSY
t4
t3
DATA
BUS
PREVIOUS
CONVERSION
t12
t13
Figure 16. Slave Parallel Data Timing for Reading
(Read During Convert)
CS
RD
CS
RD
BUSY
A0, A1
DATA
BUS
CURRENT
CONVERSION
HI-Z
HI-Z
Pins D[15:8]
Pins D[7:0]
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
t12
t13
t
t
t
12
12
13
HI-Z
HI-Z
Figure 15. Slave Parallel Data Timing for Reading
(Read After Convert)
Figure 17. 8-Bit and 16-Bit Parallel Interface
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
CS, RD
t3
CNVST
t28
BUSY
t30
t29
t25
SYNC
t14
t18
t19
t24
t20
t21
t26
1
2
3
16
17
18
SCLK
t15
t27
SDOUT
D17
D16
t23
D2
D1
D0
X
t16
t22
Figure 18. Master Serial Data Timing for Reading (Read After Convert)
REV. PrC
–21–
PRELIMINARY TECHNICAL DATA
AD7674
SERIAL INTERFACE
SLAVE SERIAL INTERFACE
The AD7674 is configured to use the serial interface when
MODE0 and MODE1 are held high. The AD7674 out-
puts 18 bits of data, MSB first, on the SDOUT pin. This
data is synchronized with the 18 clock pulses provided on
SCLK pin. The output data is valid on both the rising and
falling edge of the data clock.
External Clock
The AD7674 is configured to accept an externally sup-
plied serial data clock on the SCLK pin when the
EXT/INT pin is held high. In this mode, several meth-
ods can be used to read the data. The external serial
clock is gated by CS. When CS and RD are both low,
the data can be read after each conversion or during the
following conversion. The external clock can be either a
continuous or discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 20 and Figure 22 show the detailed timing
diagrams of these methods.
MASTER SERIAL INTERFACE
Internal Clock
The AD7674 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low.
The AD7674 also generates a SYNC signal to indicate to
the host when the serial data is valid. The serial clock
SCLK and the SYNC signal can be inverted if desired.
Depending on RDC/SDIN input, the data can be read
after each conversion or during the following conversion.
Figure 18 and Figure 19 show the detailed timing dia-
grams of these two modes.
While the AD7674 is performing a bit decision, it is impor-
tant that voltage transients not occur on digital
input/output pins or degradation of the conversion result
could occur. This is particularly important during the
second half of the conversion phase because the AD7674
provides error correction circuitry that can correct for an
improper bit decision made during the first half of the
conversion phase. For this reason, it is recommended
that when an external clock is being provided, it is a
discontinuous clock that is toggling only when BUSY is
low or, more importantly, that it does not transition dur-
ing the latter half of BUSY high.
Usually, because the AD7674 is used with a fast through-
put, the mode master, read during conversion is the most
recommended serial mode when it can be used.
In read-during-conversion mode, the serial clock and data
toggle at appropriate instants which minimize potential
feedthrough between digital activity and the critical con-
version decisions.
In read-after-conversion mode, it should be noted that,
unlike in other modes, the signal BUSY returns low after
the 18 data bits are pulsed out and not at the end of the
conversion phase which results in a longer BUSY width.
To accomodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
CS, RD
CNVST
t1
t3
BUSY
SYNC
t17
t25
t14
t19
t20 t21
t24
t26
t15
SCLK
1
2
3
16
17
18
t18
t27
SDOUT
X
D17
D16
t23
D2
D1
D0
t16
t22
Figure 19. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
–22–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7674
External Discontinuous Clock Data Read After Con-
version
Another advantage is to be able to read the data at any
speed up to 40 MHz which accommodates both slow
digital host interface and the fastest serial reading.
Though the maximum throughput cannot be achieved
using this mode, it is the most recommended of the serial
slave modes. Figure 20 shows the detailed timing dia-
grams of this method. After a conversion is complete,
indicated by BUSY returning low, the result of this con-
version can be read while both CS and RD are low. The
data is shifted out, MSB first, with 18 clock pulses and is
valid on both rising and falling edge of the clock.
Finally, in this mode only, the AD7674 provides a
“daisy-chain” feature using the RDC/SDIN input pin for
cascading multiple converters together. This feature is
useful for reducing component count and wiring connec-
tions when desired as, for instance, in isolated
multiconverter applications.
An example of the concatenation of two devices is shown
in Figure 21. Simultaneous sampling is possible by using
a common CNVST signal. It should be noted that the
RDC/SDIN input is latched on the edge of SCLK opposite
to the one used to shift out the data on SDOUT. Hence, the
MSB of the “upstream” converter just follows the LSB of
the “downstream” converter on the next SCLK cycle.
Among the advantages of this method, the conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion
process.
EXT/INT = 1
INVSCLK = 0
= 0
RD
CS
BUSY
t35
t36 t37
SCLK
1
2
3
14
15
16
17
18
t31
t32
X
D17
D16
D15
X15
D1
X17
Y17
X16
Y16
SDOUT
D0
X0
t16
t34
SDIN
X17
X16
X1
t33
Figure 20. Slave Serial Data Timing for Reading (Read After Convert)
RD =0
EXT/INT = 1
INVSCLK = 0
CS
CNVST
BUSY
t3
t35
t36 t37
SCLK
1
2
3
16
17
18
t31
t32
D16
X
D1
SDOUT
D17
D15
D0
t16
Figure 22. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
REV. PrC
–23–
PRELIMINARY TECHNICAL DATA
AD7674
MICROPROCESSOR INTERFACING
The AD7674 is ideally suited for traditional dc measure-
BUSY
OUT
ment applications supporting a microprocessor, and ac
signal processing applications interfacing to a digital sig-
nal processor. The AD7674 is designed to interface either
with a parallel 8-bit or 16-bit wide interface or with a
general purpose serial port or I/O ports on a
microcontroller. A variety of external buffers can be used
with the AD7674 to prevent digital noise from coupling
into the ADC. The following section illustrates the use of
the AD7674 with an SPI equipped DSP, the ADSP-219x.
BUSY
BUSY
AD7674
#2
(UPSTREAM)
AD7674
#1
(DOWNSTREAM)
DATA
OUT
RDC/SDIN
SDOUT
RDC/SDIN
SDOUT
CNVST
CS
CNVST
CS
SCLK
SCLK
SPI Interface (ADSP-219x)
Figure 22 shows an interface diagram between the
AD7674 and an SPI-equipped DSP, ADSP219x. To
accommodate the slower speed of the DSP, the AD7674
acts as a slave device and data must be read after conver-
sion. This mode also allows the “daisy chain” feature.
The convert command could be initiated in response to an
internal timer interrupt. The 18-bit output data are read
with 3 SPI byte access. The reading process could be
initiated in response to the end-of-conversion signal
(BUSY going low) using an interrupt line of the DSP.
The Serial Peripheral Interface (SPI) on the ADSP-219x
is configured for master mode (MSTR) = 1, Clock Polar-
ity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and
SPI interrupt enable (TIMOD) =00 by writing to the SPI
Control Register (SPICLTx). It should be noted that to
meet all timing requirements, the SPI clock should be
limited to 17Mbits/s which allow to read an ADC result
in about 1.1 ꢁs. When higher sampling rate is desired, it
is recomended to use one of the parallel interface mode
with the ADSP-219x.
SCLK IN
CS IN
CNVST IN
Figure 21. Two AD7674s in a “Daisy-Chain” Configuration
External Clock Data Read During Conversion
Figure 22 shows the detailed timing diagrams of this
method. During a conversion, while both CS and RD are
both low, the result of the previous conversion can be
read. The data is shifted out, MSB first, with 18 clock
pulses and is valid on both rising and falling edge of the
clock. The 18 bits have to be read before the current con-
version is complete. If that is not done, RDERROR is
pulsed high and can be used to interrupt the host inter-
face to prevent incomplete data reading. There is no
“daisy chain” feature in this mode and RDC/SDIN
input should always be tied either high or low.
To reduce performance degradation due to digital activity,
a fast discontinuous clock of is recommended to ensure that
all the bits are read during the first half of the conversion
phase. It is also possible to begin to read the data after
conversion and continue to read the last bits even after a new
conversion has been initiated.
DVDD
AD7674*
ADSP-219x*
SER/PAR
EXT/INT
PFx
BUSY
SPIxSEL (PFx)
MISOx
CS
SDOUT
SCLK
SCKx
RD
INVSCLK
CNVST
PFx or TFSx
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. Interfacing the AD7674 to SPI Interface
–24–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7674
APPLICATION HINTS
ing on the configuration. OGND is connected to the
digital system ground.
Layout
The AD7674 has very good immunity to noise on the
power supplies. However, care should still be taken with
regard to grounding layout.
The layout of the decoupling of the reference voltage is
important. The decoupling capacitor should be close to
the ADC and connected with short and large traces to
minimize parasitic inductances.
The printed circuit board that houses the AD7674
should be designed so the analog and digital sections
are separated and confined to certain areas of the board.
This facilitates the use of ground planes that can be
easily separated. Digital and analog ground planes
should be joined in only one place, preferably under-
neath the AD7674, or, at least, as close as possible to the
AD7674. If the AD7674 is in a system where multiple
devices require analog to digital ground connections,
the connection should still be made at one point only, a
star ground point, which should be established as close
as possible to the AD7674.
Evaluating the AD7674 Performance
A recommended layout for the AD7674 is outlined in the
documentation of the EVAL-AD7674-CB, evaluation
board for the AD7674. The evaluation board package
includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board
from a PC via the Eval-Control BRD2.
It is recommended to avoid running digital lines under the
device as these will couple noise onto the die. The analog
ground plane should be allowed to run under the
AD7674 to avoid noise coupling. Fast switching signals
like CNVST or clocks should be shielded with digital
ground to avoid radiating noise to other sections of the
board, and should never run near analog signal paths.
Crossover of digital and analog signals should be
avoided. Traces on different but close layers of the board
should run at right angles to each other. This will reduce
the effect of feedthrough through the board. The power
supply lines to the AD7674 should use as large a trace as
possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decou-
pling is also important to lower the supplies impedance
presented to the AD7674 and reduce the magnitude of
the supply spikes. Decoupling ceramic capacitors, typi-
cally 100 nF, should be placed on each power supplies
pins AVDD, DVDD and OVDD close to, and ideally
right up against these pins and their corresponding
ground pins. Additionally, low ESR 10 µF capacitors
should be located in the vicinity of the ADC to further
reduce low frequency ripple.
The DVDD supply of the AD7674 can be either a
separate supply or come from the analog supply,
AVDD, or from the digital interface supply, OVDD.
When the system digital supply is noisy, or fast switching
digital signals are present, it is recommended if no sepa-
rate supply available, to connect the DVDD digital
supply to the analog supply AVDD through an RC filter
as shown in Figure 5, and connect the system supply to the
interface digital supply OVDD and the remaining digital
circuitry. When DVDD is powered from the system sup-
ply, it is useful to insert a bead to further reduce
high-frequency spikes.
The AD7674 has four different ground pins; REFGND,
AGND, DGND, and OGND. REFGND senses the refer-
ence voltage and should be a low impedance return to
the reference because it carries pulsed currents. AGND
is the ground to which most internal ADC analog sig-
nals are referenced. This ground must be connected with
the least resistance to the analog ground plane. DGND
must be tied to the analog or digital ground plane depend-
REV. PrC
–25–
PRELIMINARY TECHNICAL DATA
AD7674
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Quad Flatpack (LQFP)
(ST-48)
0.063 (1.60)
MAX
0.354 (9.00) BSC SQ
0.030 (0.75)
0.018 (0.45)
37
48
36
1
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
COPLANARITY
0.003 (0.08)
12
25
0ꢂ
MIN
13
24
0.011 (0.27)
0.006 (0.17)
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
0.057 (1.45)
0.053 (1.35)
7ꢂ
0ꢂ
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
48-Lead Frame Chip Scale Package (LFCSP)
(CP-48)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
0.024 (0.60)
0.276 (7.0)
BSC SQ
0.017 (0.42)
0.009 (0.24)
37
48
36
1
PIN 1
INDICATOR
0.215 (5.45)
0.209 (5.30) SQ
0.203 (5.15)
TOP
VIEW
0.266 (6.75)
BSC SQ
BOTTOM
VIEW
12
25
24
0.020 (0.50)
0.016 (0.40)
0.012 (0.30)
13
0.012 (0.30)
0.009 (0.23)
0.031 (0.80) MAX
0.026 (0.65) NOM
128MAX
0.007 (0.18) Paddle connected to AGND
( This connection is not required
to meet electrical performances )
0.002 (0.05)
0.0004 (0.01)
0.0 (0.0)
0.039 (1.00) MAX
0.033 (0.85) NOM
0.020 (0.50)
BSC
0.008 (0.20)
REF
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
–26–
REV. PrC
AD7674ASTRL CAD模型
引脚图
封装焊盘图
AD7674ASTRL 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| AD7679AST | ADI | 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC | 完全替代 |
|
| AD7679ASTZ | ADI | 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC | 功能相似 |
|
| AD7678ASTZ | ADI | 18-Bit,100 kSPS PulSAR® A/D Converter | 功能相似 |
|
AD7674ASTRL 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| AD7674ASTZ | ADI | 18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC | 获取价格 |
|
| AD7674ASTZ1 | ADI | 18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC | 获取价格 |
|
| AD7674ASTZL | ADI | 18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC | 获取价格 |
|
| AD7674ASTZRL | ADI | 18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC | 获取价格 |
|
| AD7674_17 | ADI | 18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC | 获取价格 |
|
| AD7675 | ADI | 16-Bit, 100 kSPS, Differential ADC | 获取价格 |
|
| AD7675ACP | ADI | IC 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48, 7 X 7 MM, MO-220VKKD-2, LFCSP-48, Analog to Digital Converter | 获取价格 |
|
| AD7675ACPRL | ADI | IC 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48, 7 X 7 MM, MO-220VKKD-2, LFCSP-48, Analog to Digital Converter | 获取价格 |
|
| AD7675ACPZ | ADI | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48, 7 X 7 MM, MO-220VKKD-2, LFCSP-48 | 获取价格 |
|
| AD7675ACPZRL | ADI | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48, 7 X 7 MM, MO-220VKKD-2, LFCSP-48 | 获取价格 |
|
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