AD7711ARZ_技术文档

LC²MOS Signal Conditioning ADC

with RTD Excitation Currents

AD7711

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Charge-Balancing ADC

24 Bits, No Missing Codes

REF

AV

DV

DD

V

IN (+)

DD

IN (–)

REF OUT

BIAS

؎0.0015% Nonlinearity

AV

DD

2-Channel Programmable Gain Front End

Gains from 1 to 128

1 Differential Input

2.5V REFERENCE

4.5␮A

CHARGE-BALANCING A/D

CONVERTER

1 Single-Ended Input

AIN1(+)

AIN1(–)

AUTO-ZEROED

DIGITAL

SYNC

Low-Pass Filter with Programmable Filter Cutoffs

Ability to Read/Write Calibration Coefficients

RTD Excitation Current Sources

Bidirectional Microcontroller Serial Interface

Internal/External Reference Option

Single- or Dual-Supply Operation

Low Power (25 mW typ) with Power-Down Mode

(7 mW typ)

M

U

X

⌺-⌬

PGA

A = 1–128

FILTER

MODULATOR

AIN2

MCLK

IN

CLOCK

200␮A

AV

DD

GENERATION

MCLK

OUT

RTD1

RTD2

SERIAL INTERFACE

200␮A

CONTROL

REGISTER

OUTPUT

REGISTER

APPLICATIONS

RTD Transducers

AD7711

Process Control

Smart Transmitters

Portable Industrial Instruments

AGND DGND

V

MODE SDATA SCLK

A0

DRDY

RFS TFS

SS

The AD7711 is ideal for use in smart, microcontroller based

systems. Gain settings, signal polarity, input channel selection,

and RTD current control can be configured in software using

the bidirectional serial port. The AD7711 contains self-

calibration, system calibration, and background calibration

options, and also allows the user to read and write the on-chip

calibration registers.

GENERAL DESCRIPTION

The AD7711 is a complete analog front end for low frequency

measurement applications. The device accepts low level signals

directly from a transducer and outputs a serial digital word. It

employs a ⌺-⌬ conversion technique to realize up to 24 bits of

no missing codes performance. The input signal is applied to a

proprietary programmable gain front end based around an ana-

log modulator. The modulator output is processed by an on-chip

digital filter. The first notch of this digital filter can be pro-

grammed via the on-chip control register, allowing adjustment

of the filter cutoff and settling time.

CMOS construction ensures low power dissipation, and a software

programmable power-down mode reduces the standby power

consumption to only 7 mW typical. The part is available in a

24-lead, 0.3-inch-wide, plastic and hermetic dual-in-line pack-

age (DIP) as well as a 24-lead small outline (SOIC) package.

The part features one differential analog input and one single-

ended analog input as well as a differential reference input.

Normally, one of the input channels will be used as the main

channel with the second channel used as an auxiliary input to

periodically measure a second voltage. It can be operated from a

single supply (by tying the V_SSpin to AGND), provided that the

input signals on the analog inputs are more positive than –30 mV.

By taking the V_SSpin negative, the part can convert signals

down to –V_REFon its inputs. The part provides two current

sources that can be used to provide excitation in 3-wire and 4-wire

RTD configurations. The AD7711 thus performs all signal

conditioning and conversion for a single- or dual-channel system.

PRODUCT HIGHLIGHTS

1. The programmable gain front end allows the AD7711 to

accept input signals directly from an RTD transducer,

removing a considerable amount of signal conditioning.

On-chip current sources provide excitation for 3-wire and

4-wire RTD configurations.

2. No missing codes ensure true, usable, 23-bit dynamic range

coupled with excellent ± 0.0015% accuracy. The effects of

temperature drift are eliminated by on-chip self-calibration,

which removes zero-scale and full-scale errors.

3. The AD7711 is ideal for microcontroller or DSP processor

applications with an on-chip control register that allows

control over filter cutoff, input gain, channel selection, signal

polarity, RTD current control, and calibration modes.

4. The AD7711 allows the user to read and to write the on-chip

calibration registers. This means that the microcontroller has

much greater control over the calibration procedure.

REV. G

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

(AV = +5 V ؎ 5%; DV = +5 V ؎ 5%; V = 0 V or –5 V ؎ 5%; REF IN(+) =

+2.5 V; REF IN(–) = AGND; MCLK IN = 10 MHz unless otherwise stated. All specifications T_MINto T_MAX, unless otherwise noted.)

AD7711–SPECIFICATIONS

DD

SS

Parameter

A, S Versions¹

Unit

Conditions/Comments

STATIC PERFORMANCE

No Missing Codes

24

22

18

15

Bits min

Guaranteed by Design. For Filter Notches £ 60 Hz

For Filter Notch = 100 Hz

For Filter Notch = 250 Hz

For Filter Notch = 500 Hz

For Filter Notch = 1 kHz

12

Output Noise

See Tables I and II

Depends on Filter Cutoffs and Selected Gain

Integral Nonlinearity @ 25∞C

± 0.0015

± 0.003

See Note 4

1

0.3

See Note 4

0.5

0.25

See Note 4

0.5

0.25

% FSR max

Filter Notches £ 60 Hz

T

_MINto T_MAX

Typically ± 0.0003%

Positive Full-Scale Error^{2, 3}

Full-Scale Drift⁵

Excluding Reference

Excluding Reference. For Gains of 1, 2

Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

mV/∞C typ

Unipolar Offset Error²

Unipolar Offset Drift⁵

mV/∞C typ

For Gains of 1, 2

For Gains of 4, 8, 16, 32, 64, 128

Bipolar Zero Error²

Bipolar Zero Drift⁵

mV/∞C typ

ppm/∞C typ

% FSR max

mV/∞C typ

For Gains of 1, 2

For Gains of 4, 8, 16, 32, 64, 128

Gain Drift

2

Bipolar Negative Full-Scale Error²@ 25∞C

T_MINto T_MAX

± 0.003

± 0.006

1

Excluding Reference

Typically ± 0.0006%

Excluding Reference. For Gains of 1, 2

Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

Bipolar Negative Full-Scale Drift⁵

0.3

ANALOG INPUTS/REFERENCE INPUTS

Normal Mode 50 Hz Rejection⁶

100

10

1

20

dB min

pA max

nA max

pF max

For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ± 0.02 ¥ f_NOTCH

For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ± 0.02 ¥ f_NOTCH

Normal Mode 60 Hz Rejection⁶

DC Input Leakage Current @ 25∞C⁶

T

_MINto T_MAX

Sampling Capacitance⁶

AIN1/REF IN

Common-Mode Rejection (CMR)

Common-Mode 50 Hz Rejection⁶

Common-Mode 60 Hz Rejection⁶

Common-Mode Voltage Range⁷

Analog Inputs⁸

100

90

150

dB min

At DC and AV_DD= 5 V

At DC and AV_DD= 10 V

For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ± 0.02 ¥ f_NOTCH

For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ± 0.02 ¥ f_NOTCH

V_SSto AV_DD

V min to V max

Input Voltage Range⁹

For Normal Operation. Depends on Gain Selected

Unipolar Input Range (B/U Bit of Control Register = 1)

Bipolar Input Range (B/U Bit of Control Register = 0)

10

0 to +V_REF

max

± V_REF

See Table III

2.5

Input Sampling Rate, f_S

AIN2 Offset Error

mV max

Removed by System Calibrations but not by Self-Calibration

AIN2 Offset Drift

1.5

mV/∞C typ

Reference Inputs

REF IN(+) – REF IN(–) Voltage¹¹

+2.5 to +5

f_{CLK IN}/256

V min to V max

For Specified Performance. Part Is Functional with

Lower V_REFVoltages

Input Sampling Rate, f_S

REFERENCE OUTPUT

Output Voltage

Initial Tolerance @ 25∞C

Drift

2.5

± 1

20

30

1

1.5

1

V nom

% max

ppm/∞C typ

mV typ

mV/V max

mV/mA max

mA max

Output Noise

Peak-to-Peak Noise. 0.1 Hz to 10 Hz Bandwidth

Maximum Load Current 1 mA

Line Regulation (AV_DD

Load Regulation

)

External Current

NOTES

¹Temperature range is as follows: A Version = – 40∞C to +85∞C; S Version = –55∞C to +125∞C. See also Note 16.

²Applies after calibration at the temperature of interest.

³Positive full-scale error applies to both unipolar and bipolar input ranges.

⁴These errors will be of the order of the output noise of the part, as shown in Table I, after system calibration. These errors will be 20 mV typical after self-calibration

or background calibration.

⁵Recalibration at any temperature or use of the background calibration mode will remove these drift errors.

⁶These numbers are guaranteed by design and/or characterization.

⁷This common-mode voltage range is allowed, provided the input voltage on AIN(+) and AIN(–) does not exceed AV_DD+ 30 mV and V_SS– 30 mV.

⁸The analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source resis-

tance depends on the selected gain (see Tables IV and V).

⁹The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2 input is

with respect to AGND. The absolute voltage on the analog inputs should not go more positive than AV_DD+ 30 mV, or more negative than V_SS– 30 mV.

10

V

= REF IN(+) – REF IN(–).

REF

¹¹The reference input voltage range may be restricted by the input voltage range requirement on the V_BIASinput.

–2–

REV. G

AD7711

Parameter

A, S Versions¹

Unit

Conditions/Comments

V

_BIASINPUT¹²

Input Voltage Range

AV_DD– 0.85 ¥ V_REF

See V_BIASInput Section

Whichever Is Smaller; +5 V/–5 V or +10 V/0 V

Nominal AV_DD/V_SS

Whichever Is Smaller; +5 V/0 V Nominal AV_DD/V_SS

See V_BIASInput Section

or AV_DD– 3.5

V max

V min

or AV_DD– 2.1

V_SS+ 0.85 ¥ V_REF

or V_SS+ 3

Whichever Is Greater; +5 V/–5 V or +10 V/0 V

Nominal AV_DD/V_SS

Whichever Is Greater; +5 V/0 V Nominal AV_DD/V_SS

Increasing with Gain

or V_SS+ 2.1

65 to 85

V min

dB typ

V_BIASRejection

LOGIC INPUTS

Input Current

All Inputs except MCLK IN

± 10

mA max

V

_INL, Input Low Voltage

_INH, Input High Voltage

0.8

2.0

V max

V min

MCLK IN Only

V_INL, Input Low Voltage

V_INH, Input High Voltage

0.8

3.5

V max

V min

LOGIC OUTPUTS

V_OL, Output Low Voltage

0.4

4.0

± 10

9

V max

V min

mA max

pF typ

I_SINK= 1.6 mA

I_SOURCE= 100 mA

V

_OH, Output High Voltage

Floating State Leakage Current

Floating State Output Capacitance¹³

TRANSDUCER BURNOUT

Current

Initial Tolerance @ 25∞C

Drift

4.5

± 10

0.1

mA nom

% typ

%/∞C typ

RTD EXCITATION CURRENTS (RTD1, RTD2)

Output Current

Initial Tolerance @ 25∞C

Drift

200

± 20

20

mA nom

% max

ppm/∞C typ

Initial Matching @ 25∞C

Drift Matching

± 1

% max

Matching between RTD1 and RTD2 Currents

Matching between RTD1 and RTD2 Current Drift

AV_DD= 5 V

3

ppm/∞C typ

nA/V max

V max

Line Regulation (AV_DD

)

200

AV_DD– 2

Load Regulation

Output Compliance

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit¹⁴

Negative Full-Scale Calibration Limit¹⁴

Offset Calibration Limit¹⁵

(1.05 ¥ V_REF)/GAIN

–(1.05 ¥ V_REF)/GAIN

0.8 ¥ V_REF/GAIN

V max

V min

V max

GAIN Is the Selected PGA Gain (between 1 and 128)

Input Span¹⁵

(2.1 ¥ V_REF)/GAIN

NOTES

¹²The AD7711 is tested with the following V_BIASvoltages. With AV_DD= 5 V and V_SS= 0 V, V_BIAS= 2.5 V; with AV_DD= 10 V and V_SS= 0 V, V_BIAS= 5 V, and

with AV_DD= 5 V and V_SS= –5 V, V_BIAS= 0 V.

¹³Guaranteed by design, not production tested.

¹⁴After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s.

¹⁵These calibration and span limits apply, provided the absolute voltage on the analog inputs does not exceed AV_DD+ 30 mV or go more negative than V_SS– 30 mV.

The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

REV. G

–3–

AD7711–SPECIFICATIONS

Parameter

A, S Versions¹

Unit

Conditions/Comments

POWER REQUIREMENTS

Power Supply Voltages

AV_DDVoltage¹⁶

5 to 10

5

10.5

V nom

V max

± 5% for Specified Performance

For Specified Performance

DV_DDVoltage¹⁷

AV_DD– V_SSVoltage

Power Supply Currents

AV_DDCurrent

4

4.5

1.5

mA max

DV_DDCurrent

V_SSCurrent

V_SS= –5 V

Power Supply Rejection¹⁸

Positive Supply (AV_DDand DV_DD

Rejection w.r.t. AGND; Assumes V_BIASIs Fixed

)

See Note 19

90

dB typ

Negative Supply (V_SS

Power Dissipation

Normal Mode

)

45

52.5

15

mW max

AV_DD= DV_DD= +5 V, V_SS= 0 V; Typically 25 mW

AV_DD= DV_DD= +5 V, V_SS= –5 V; Typically 30 mW

AV_DD= DV_DD= +5 V, V_SS= 0 V or –5 V; Typically 7 mW

Standby (Power-Down) Dissipation

NOTES

¹⁶The AD7711 is specified with a 10 MHz clock for AV_DDvoltages of 5 V ± 5%. It is specified with an 8 MHz clock for AV_DDvoltages greater than 5.25 V and less

than 10.5 V. Operating with AV_DDvoltages in the range 5.25 V to 10.5 V is only guaranteed over the 0∞C to 70∞C temperature range.

¹⁷The ± 5% tolerance on the DV_DDinput is allowed provided DV_DDdoes not exceed AV_DDby more than 0.3 V.

¹⁸Measured at dc and applies in the selected pass band. PSRR at 50 Hz will exceed 120 dB with filter notches of 10 Hz, 25 Hz, or 50 Hz. PSRR at 60 Hz will exceed

120 dB with filter notches of 10 Hz, 30 Hz, or 60 Hz.

¹⁹PSRR depends on gain: Gain of 1 = 70 dB typ; Gain of 2: 75 dB typ; Gain of 4 = 80 dB typ; Gains of 8 to 128 = 85 dB typ. These numbers can be improved (to

95 dB typ) by deriving the V_BIASvoltage (via Zener diode or reference) from the AV_DDsupply.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

(T_A= 25∞C, unless otherwise noted.)

REF OUT to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V to AV_DD

Digital Input Voltage to DGND . . . . . –0.3 V to AV_DD+ 0.3 V

Digital Output Voltage to DGND . . . –0.3 V to DV_DD+ 0.3 V

Operating Temperature Range

Commercial (A Version) . . . . . . . . . . . . . . . . –40∞C to +85∞C

Extended (S Version) . . . . . . . . . . . . . . . . . –55∞C to +125∞C

Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300∞C

Power Dissipation (Any Package) to 75∞C . . . . . . . . . . 450 mW

AV_DDto DV_DD. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

AV_DDto V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

AV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

DV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

V_SSto AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of the specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

V

_SSto DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

Analog Input Voltage to AGND

. . . . . . . . . . . . . . . . . . . . . . . . . V_SS– 0.3 V to AV_DD+ 0.3 V

Reference Input Voltage to AGND

. . . . . . . . . . . . . . . . . . . . . . . . . V_SS– 0.3 V to AV_DD+ 0.3 V

ORDERING GUIDE

Temperature Range Package Option*

Model

AD7711AN

AD7711AR

AD7711AR-REEL –40∞C to +85∞C

AD7711AR-REEL7 –40∞C to +85∞C

AD7711AQ

AD7711SQ

–40∞C to +85∞C

N-24

R-24

Q-24

–40∞C to +85∞C

–55∞C to +125∞C

EVAL-AD7711EB Evaluation Board

*N = Plastic DIP, Q = CERDIP, R = SOIC.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD7711 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

–4–

REV. G

AD7711

(DV_DD= +5 V ؎ 5%; AV_DD= +5 V or +10 V³؎ 5%; V_SS= 0 V or –5 V ؎ 10%; AGND = DGND =

0 V; f_{CLK IN}= 10 MHz; Input Logic 0 = 0 V, Logic 1 = DV_DD, unless otherwise noted.)

TIMING CHARACTERISTICS^{1, 2}

Limit at T_MIN, T_MAX

(A, S Versions)

Parameter

Unit

Conditions/Comments

4, 5

f_{CLK IN}

400

kHz min

Master Clock Frequency: Crystal Oscillator or Externally

Supplied for Specified Performance

10

MHz max

ns min

ns max

ns min

2

t_{CLK IN LO}

0.4 × t_{CLK IN}

50

1000

Master Clock Input Low Time; t_{CLK IN}= 1/f_{CLK IN}

Master Clock Input High Time

Digital Output Rise Time. Typically 20 ns

Digital Output Fall Time. Typically 20 ns

SYNC Pulse Width

t_{CLK IN HI}

t_r⁶

t_f⁶

t₁

Self-Clocking Mode

t₂

t₃

t₄

0

ns min

ns max

ns min

ns max

ns nom

ns min

ns max

ns min

DRDY to RFS Setup Time

DRDY to RFS Hold Time

A0 to RFS Setup Time

A0 to RFS Hold Time

RFS Low to SCLK Falling Edge

Data Access Time (RFS Low to Data Valid)

SCLK Falling Edge to Data Valid Delay

2 × t_{CLK IN}

0

4 × t_{CLK IN}+ 20

t_{CLK IN}/2

t₅

t₆₇

t₇₇

t₈

t

_{CLK IN}/2 + 30

t₉

t_{CLK IN}/2

3 × t_{CLK IN}/2

50

SCLK High Pulse Width

SCLK Low Pulse Width

A0 to TFS Setup Time

A0 to TFS Hold Time

TFS to SCLK Falling Edge Delay Time

TFS to SCLK Falling Edge Hold Time

Data Valid to SCLK Setup Time

Data Valid to SCLK Hold Time

t₁₀

t₁₄

t₁₅

t₁₆

t₁₇

t₁₈

t₁₉

0

4 × t_{CLK IN}+ 20

4 × t_{CLK IN}

0

10

NOTES

¹Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

²See Figures 10 to 13.

³The AD7711 is specified with a 10 MHz clock for AV_DDvoltages of 5 V 5%. It is specified with an 8 MHz clock for AV_DDvoltages greater than 5.25 V and less

than 10.5 V.

⁴CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711 is not in STANDBY mode. If no clock is present in this case, the device

can draw higher current than specified and possibly become uncalibrated.

⁵The AD7711 is production tested with f_{CLK IN}at 10 MHz (8 MHz for AV_DD> 5.25 V). It is guaranteed by characterization to operate at 400 kHz.

⁶Specified using 10% and 90% points on waveform of interest.

⁷These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

REV.G

–5–

AD7711

TIMING CHARACTERISTICS

Limit at T_MIN, T_MAX

(A, S Versions)

Parameter

Unit

Conditions/Comments

External Clocking Mode

f_SCLK

t₂₀

t₂₁

t₂₂

f_{CLK IN}/5

0

2 ¥ t_{CLK IN}

0

4 ¥ t_{CLK IN}

10

MHz max

ns min

ns max

ns min

ns max

ns min

ns max

ns min

ns max

ns min

ns max

ns min

Serial Clock Input Frequency

DRDY to RFS Setup Time

DRDY to RFS Hold Time

A0 to RFS Setup Time

A0 to RFS Hold Time

t₂₃

t₂₄

t₂₅

7

Data Access Time (RFS Low to Data Valid)

SCLK Falling Edge to Data Valid Delay

7

2 ¥ t_{CLK IN}+ 20

t₂₆

t₂₇

t₂₈

2 ¥ t_{CLK IN}

SCLK High Pulse Width

SCLK Low Pulse Width

SCLK Falling Edge to DRDY High

SCLK to Data Valid Hold Time

2 ¥ t_{CLK IN}

t_{CLK IN}+ 10

8

t₂₉

10

t_{CLK IN}+ 10

10

5 ¥ t_{CLK IN}/2 + 50

0

t₃₀

t₃₁

RFS/TFS to SCLK Falling Edge Hold Time

RFS to Data Valid Hold Time

A0 to TFS Setup Time

8

t₃₂

t₃₃

t₃₄

t₃₅

t₃₆

0

A0 to TFS Hold Time

4 ¥ t_{CLK IN}

SCLK Falling Edge to TFS Hold Time

Data Valid to SCLK Setup Time

Data Valid to SCLK Hold Time

2 ¥ t_{CLK IN}– SCLK High

30

NOTES

⁸These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then

extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus

relinquish times of the part and, as such, are independent of external bus loading capacitances.

Specifications subject to change without notice.

PIN CONFIGURATION

DIP AND SOIC

1.6mA

1

2

24

23

DGND

DV

SCLK

MCLK IN

MCLK OUT

A0

DD

3

22 SDATA

TO OUTPUT

+2.1V

4

21

DRDY

100pF

5

20

19

18

17

RFS

SYNC

MODE

AIN1(+)

AIN1(–)

RTD1

AD7711

200␮A

6

TFS

TOP VIEW

(Not to Scale)

7

AGND

AIN2

8

Figure 1. Load Circuit for Access Time and Bus

Relinquish Time

9

16 REF OUT

10

11

12

15

14

13

RTD2

REF IN(+)

REF IN(–)

V

SS

AV

DD

V

BIAS

–6–

REV. G

AD7711

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic

Function

1

SCLK

Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the

device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK becomes

active when RFS or TFS goes low, and goes high impedance when either RFS or TFS returns high or when

the device has completed transmission of an output word. When MODE is low, the device is in its external

clocking mode and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all

data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the

information being transmitted to the AD7711 in smaller batches of data.

2

MCLK IN

Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A crystal can

be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a

CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz.

3

4

MCLK OUT

A0

When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.

Address Input. With this input low, reading and writing to the device is to the control register. With this input

high, access is to either the data register or the calibration registers.

5

6

7

SYNC

Logic Input. Allows for synchronization of the digital filters when using a number of AD7711s. It resets

the nodes of the digital filter.

MODE

AIN1(+)

Logic Input. When this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its

external clocking mode.

Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input

is connected to an output current source that can be used to check that an external transducer has burned out

or gone open circuit. This output current source can be turned on/off via the control register.

8

9

AIN1(–)

RTD1

Analog Input Channel 1. Negative input of the programmable gain differential analog input.

Constant Current Output. A nominal 200 mA constant current is provided at this pin; this current can be

used as the excitation current for RTDs. This current can be turned on or off via the control register.

10

11

RTD2

V_SS

Constant Current Output. A nominal 200 mA constant current is provided at this pin; this current can be

used as the excitation current for RTDs. This current can be turned on or off via the control register, and

can be used to eliminate lead resistance errors in 3-wire RTD configurations.

Analog Negative Supply, 0 V to –5 V. Tied to AGND for single-supply operation. The input voltage on AIN1

or AIN2 should not go > 30 mV negative w.r.t. V_SSfor correct operation of the device.

12

13

AV_DD

V_BIAS

Analog Positive Supply Voltage, 5 V to 10 V.

Input Bias Voltage. This input voltage should be set such that V_BIAS+ 0.85 ¥ V_REF< AV_DDand V_BIAS– 0.85

¥ V_REF> V_SSwhere V_REFis REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AV_DD

and V_SS. Thus with AV_DD= 5 V and V_SS= 0 V, it can be tied to REF OUT; with AV_DD= +5 V and

V_SS= –5 V, it can be tied to AGND; with AV_DD= 10 V, it can be tied to 5 V.

14

15

16

REF IN(–)

REF IN(+)

REF OUT

Reference Input. The REF IN(–) can lie anywhere between AV_DDand V_SSprovided REF IN(+) is greater

than REF IN(–).

Reference Input. The reference input is differential provided REF IN(+) is greater than REF IN(–).

REF IN(+) can lie anywhere between AV_DDand V_SS.

Reference Output. The internal 2.5 V reference is provided at this pin. This is a single-ended output

that is referred to AGND. It is a buffered output capable of providing 1 mA to an external load.

17

18

19

AIN2

AGND

TFS

Analog Input Channel 2. Single-ended programmable gain analog input.

Ground Reference Point for Analog Circuitry.

Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial

data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active

after TFS goes low. During a write operation to the AD7711, the SDATA line should not return to high

impedance until after TFS returns high.

REV.G

–7–

AD7711

Pin Mnemonic

Function

20

RFS

Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the

self-clocking mode, the SCLK and SDATA lines both become active after RFS goes low. In the external

clocking mode, the SDATA line becomes active after RFS goes low.

21

DRDY

Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin

will return high upon completion of transmission of a full output word. DRDY is also used to indicate

when the AD7711 has completed its on-chip calibration sequence.

22 SDATA

Serial Data. Input/output with serial data being written to either the control register or the calibration

registers and serial data being accessed from the control register, calibration registers, or the data register.

During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is

low). During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low.

The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.

23 DV_DD

Digital Supply Voltage, 5 V. DV_DDshould not exceed AV_DDby more than 0.3 V in normal operation.

Ground Reference Point for Digital Circuitry.

24 DGND

TERMINOLOGY

Intergral Nonlinearity

Positive Full-Scale Overrange

Positive full-scale overrange is the amount of overhead avail-

This is the maximum deviation of any code from a straight line

passing through the endpoints of the transfer function. The end-

points of the transfer function are zero-scale (not to be confused

with bipolar zero), a point 0.5 LSB below the first code transi-

tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB

above the last code transition (111 . . . 110 to 111 . . . 111). The

error is expressed as a percentage of full scale.

able to handle input voltages on the AIN1(+) input greater

than AIN1(–) + V_REF/GAIN or on the AIN2 input greater

than + V_REF/GAIN (for example, noise peaks or excess

voltages due to system gain errors in system calibration rou-

tines) without introducing errors due to overloading the analog

modulator or to overflowing the digital filter.

Negative Full-Scale Overrange

Positive Full-Scale Error

This is the amount of overhead available to handle voltages on

AIN1(+) below AIN1(–) – V_REF/GAIN or on AIN2 below

–V_REF/GAIN without overloading the analog modulator or over-

flowing the digital filter. Note that the analog input will accept

negative voltage peaks on AIN1(+) even in the unipolar mode

provided that AIN1(+) is greater than AIN1(–) and greater than

V_SS– 30 mV.

Positive full-scale error is the deviation of the last code transi-

tion (111 . . . 110 to 111 . . . 111) from the ideal input full-scale

voltage. For AIN1(+), the ideal full-scale input voltage is

(AIN1(–) + V_REF/GAIN – 3/2 LSBs); for AIN2, the ideal full-

scale input voltage is V_REF/GAIN – 3/2 LSBs. It applies to both

unipolar and bipolar analog input ranges.

Unipolar Offset Error

Offset Calibration Range

Unipolar offset error is the deviation of the first code transition

from the ideal voltage. For AIN1(+), the ideal input voltage is

(AIN1(–) + 0.5 LSB); for AIN2, the ideal input is 0.5 LSB

when operating in the unipolar mode.

In the system calibration modes, the AD7711 calibrates its

offset with respect to the analog input. The offset calibration

range specification defines the range of voltages that the AD7711

can accept and still calibrate offset accurately.

Bipolar Zero Error

Full-Scale Calibration Range

This is the deviation of the midscale transition (0111 . . . 111

to 1000 . . . 000) from the ideal input voltage. For AIN1(+), the

ideal input voltage is (AIN1(–) – 0.5 LSB); for AIN2, the ideal

input is – 0.5 LSB when operating in the bipolar mode.

This is the range of voltages that the AD7711 can accept in the

system calibration mode and still calibrate full-scale correctly.

Input Span

In system calibration schemes, two voltages applied in sequence

to the AD7711’s analog input define the analog input range.

The input span specification defines the minimum and maxi-

mum input voltages from zero- to full-scale that the AD7711

can accept and still calibrate gain accurately.

Bipolar Negative Full-Scale Error

This is the deviation of the first code transition from the ideal

input voltage. For (AIN1(+), the ideal input voltage is (AIN1(–)

– V_REF/GAIN + 0.5 LSB); for AIN2 the ideal input is – V_REF/GAIN

+ 0.5 LSB when operating in the bipolar mode.

–8–

REV. G

AD7711

CONTROL REGISTER (24 BITS)

A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the

contents of the control register. The control register is 24 bits wide; 24 bits of data must be written to the registers or the data will not

be loaded. In other words, it is not possible to write just the first 12-bits of data into the control register. If more than 24 clock pulses

are provided before TFS returns high, then all clock pulses after the 24th clock pulse are ignored. Similarly, a read operation from the

control register should access 24 bits of data.

MSB

2

MD2

FS11

MD1

FS10

MD0

FS9

G2

G1

G0

CH

PD

WL

FS3

RO

BO

B/U

FS8

FS7

FS6

FS5

FS4

FS2

FS1

FS0

LSB

Operating Mode

MD2

MD1

MD0 Operating Mode

0

Normal Mode. This is the normal mode of operation where a read to the device with A0 high accesses

data from the data register. This is the default condition of these bits after the internal power-on reset.

0

1

Activate Self-Calibration. This activates self-calibration on the channel selected by CH. This is a one-step

calibration sequence, and when complete, the part returns to normal mode (with MD2, MD1, MD0 of

the control register returning to 0, 0, 0). The DRDY output indicates when this self-calibration is complete.

For this calibration type, the zero-scale calibration is done internally on shorted (zeroed) inputs, and the

full-scale calibration is done internally on V_REF

.

0

Activate System Calibration. This activates system calibration on the channel selected by CH. This is a

two-step calibration sequence, with the zero-scale calibration done first on the selected input channel and

DRDY indicating when this zero-scale calibration is complete. The part returns to normal mode at the

end of this first step in the two-step sequence.

0

1

0

1

0

Activate System Calibration. This is the second step of the system calibration sequence with full-scale

calibration being performed on the selected input channel. Once again, DRDY indicates when the full-

scale calibration is complete. When this calibration is complete, the part returns to normal mode.

Activate System Offset Calibration. This activates system offset calibration on the channel selected by

CH. This is a one-step calibration sequence and, when complete, the part returns to normal mode with

DRDY indicating when this system offset calibration is complete. For this calibration type, the zero-scale

calibration is done on the selected input channel, and the full-scale calibration is done internally on V_REF

.

1

0

1

Activate Background Calibration. This activates background calibration on the channel selected by CH. If

the background calibration mode is on, the AD7711 provides continuous self-calibration of the

reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence,

extending the conversion time and reducing the word rate by a factor of 6. The major advantage is that

the user does not have to recalibrate the device when there is a change in the ambient temperature. In this

mode, the shorted (zeroed) inputs and V_REF, as well as the analog input voltage, are continuously moni-

tored and the calibration registers of the device are automatically updated.

1

0

1

Read/Write Zero-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents

of the zero-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high

writes data to the zero-scale calibration coefficients of the channel selected by CH. The word length for

reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control

register. Therefore, 24 bits of data must be written to the calibration register or the new data will not be

transferred to the calibration register.

Read/Write Full-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of

the full-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high

writes data to the full-scale calibration coefficients of the channel selected by CH. The word length for

reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control

register. Therefore, 24 bits of data must be written to the calibration register, or the new data will not be

transferred to the calibration register.

REV.G

–9–

AD7711

PGA Gain

G2

Gl

G0

Gain

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

(Default Condition after the Internal Power-On Reset)

CHANNEL SELECTION

CH

0

1

Channel

AIN1

AIN2

(Default Condition after Internal Power-On Reset)

Power-Down

PD

0

1

Normal Operation

Power-Down

Word Length

WL

0

1

Output Word Length

16-bit

24-bit

RTD Excitation Current

IO

0

1

Off

On

Burnout Current

BO

0

1

Off

On

Bipolar/Unipolar Selection (Both Inputs)

B/U

0

1

Bipolar

Unipolar

(Default Condition after Internal Power-On Reset)

FILTER SELECTION (FS11–FS0)

time) for the device is equal to the frequency selected for the

first notch of the filter. For example, if the first notch of the

filter is selected at 50 Hz, a new word is available at a 50 Hz rate

or every 20 ms. If the first notch is at 1 kHz, a new word is avail-

able every 1 ms.

The on-chip digital filter provides a sinc³(or (sinx/x)³) filter

response. The 12 bits of data programmed into these bits deter-

mine the filter cutoff frequency, the position of the first notch of

the filter and the data rate for the part. In association with the

gain selection, it also determines the output noise (and therefore

the effective resolution) of the device.

The settling time of the filter to a full-scale step input change

is worst case 4 ¥ 1/(output data rate). This settling time is to

100% of the final value. For example, with the first filter notch

at 50 Hz, the settling time of the filter to a full-scale step input

change is 80 ms max. If the first notch is at 1 kHz, the settling

time of the filter to a full-scale input step is 4 ms max. This

settling time can be reduced to 3 ¥ 1/(output data rate) by syn-

chronizing the step input change to a reset of the digital filter. In

other words, if the step input takes place with SYNC low, the

settling time is 3 ¥ 1/(output data rate). If a change of channels

takes place, the settling time is 3 ¥ 1/(output data rate) regard-

less of the SYNC input.

The first notch of the filter occurs at a frequency determined by

the relationship: filter first notch frequency = (f_{CLK IN}/512)/code

where code is the decimal equivalent of the code in bits FS0 to

FS11 and is in the range 19 to 2,000. With the nominal f_{CLK IN}

of 10 MHz, this results in a first notch frequency range from

9.76 Hz to 1.028 kHz. To ensure correct operation of the

AD7711, the value of the code loaded to these bits must be

within this range. Failure to do this will result in unspecified

operation of the device.

Changing the filter notch frequency, as well as the selected gain,

impacts resolution. Tables I and II and Figure 2 show the effect

of the filter notch frequency and gain on the effective resolution

of the AD7711. The output data rate (or effective conversion

The –3 dB frequency is determined by the programmed first

notch frequency according to the relationship:

filter –3 dB frequency = 0.262 ¥ first notch frequency.

–10–

REV. G

AD7711

Tables I and II show the output rms noise for some typical

notch and –3 dB frequencies. The numbers given are for the

bipolar input ranges with a V_REFof 2.5 V. These numbers are

typical and are generated with an analog input voltage of 0 V.

The output noise from the part comes from two sources. The

first is the electrical noise in the semiconductor devices used in

the implementation of the modulator (device noise). The second

occurs when the analog input signal is converted into the digital

domain adding quantization noise. The device noise is at a low

level and is largely independent of frequency. The quantization

noise starts at an even lower level but rises rapidly with increas-

ing frequency to become the dominant noise source. Conse-

quently, lower filter notch settings (below 60 Hz approximately)

tend to be device-noise dominated while higher notch settings

are dominated by quantization noise. Changing the filter notch

and cutoff frequency in the quantization-noise dominated region

results in a more dramatic improvement in noise performance

than it does in the device-noise dominated region as shown in

Table I. Furthermore, quantization noise is added after the PGA,

so effective resolution is independent of gain for the higher filter

notch frequencies. Meanwhile, device noise is added in the PGA

and, therefore, effective resolution suffers a little at high gains

for lower notch frequencies.

At the lower filter notch settings (below 60 Hz), the no missing

codes performance of the device is at the 24-bit level. At the higher

settings, more codes will be missed until at the 1 kHz notch setting,

no missing codes performance is guaranteed only to the 12-bit

level. However, since the effective resolution of the part is 10.5 bits

for this filter notch setting, this no missing codes performance

should be more than adequate for all applications.

2

The effective resolution of the device is defined as the ratio of the

output rms noise to the input full scale. This does not remain

constant with increasing gain or with increasing bandwidth.

Table II is the same as Table I except that the output is expressed

in terms of effective resolution (the magnitude of the rms noise

with respect to 2 ¥ V_REF/GAIN, or the input full scale). It is pos-

sible to do post filtering on the device to improve the output data

rate for a given –3 dB frequency and also to further reduce the

output noise (see the Digital Filtering section).

Table I. Output Noise vs. Gain and First Notch Frequency

Typical Output RMS Noise (␮V)

Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

First Notch of

Filter and O/P –3 dB

Data Rate¹

Frequency Gain of 1 Gain of 2

10 Hz²

25 Hz²

30 Hz²

50 Hz²

60 Hz²

100 Hz³

250 Hz³

500 Hz³

1 kHz³

2.62 Hz

6.55 Hz

7.86 Hz

13.1 Hz

15.72 Hz

26.2 Hz

65.5 Hz

131 Hz

262 Hz

1.0

1.8

2.5

4.33

5.28

13

0.78

1.1

1.31

2.06

2.36

6.4

0.48

0.63

0.84

1.2

1.33

3.7

0.33

0.50

0.57

0.64

0.87

1.8

0.25

0.44

0.46

0.54

0.63

1.1

7.5

35

180

0.25

0.41

0.43

0.46

0.62

0.9

4

25

120

0.25

0.38

0.4

0.46

0.6

0.65

2.7

15

0.25

0.38

0.4

0.46

0.56

0.65

1.7

130

75

25

12

0.6 ¥ 10³

3.1 ¥ 10³

0.26 ¥ 10³140

70

8

40

1.6 ¥ 10³

0.7 ¥ 10³

0.29 ¥ 10³

70

NOTES

¹The default condition (after the internal power-on reset) for the first notch of filter is 60 Hz.

²For these filter notch frequencies, the output rms noise is primarily dominated by device noise, and, as a result, is independent of the value of the reference voltage.

Therefore, increasing the reference voltage will give an increase in the effective resolution of the device (that is, the ratio of the rms noise to the input full scale is

increased because the output rms noise remains constant as the input full scale increases).

³For these filter notch frequencies, the output rms noise is dominated by quantization noise, and, as a result, is proportional to the value of the reference voltage.

Table II. Effective Resolution vs. Gain and First Notch Frequency

Effective Resolution (Bits)

First Notch of

Filter and O/P –3 dB

Data Rate

*

Frequency Gain of 1 Gain of 2

Gain of 4

Gain of 8

Gain of 16

Gain of 32 Gain of 64 Gain of 128

10 Hz

25 Hz

30 Hz

50 Hz

60 Hz

100 Hz

250 Hz

500 Hz

1 kHz

2.62 Hz

6.55 Hz

7.86 Hz

13.1 Hz

15.72 Hz

26.2 Hz

65.5 Hz

131 Hz

262 Hz

22.5

21.5

21

20

18.5

15

13

21.5

21

20

18.5

15

13

21.5

21

20.5

20

21

20

19.5

18.5

15.5

13

20.5

19.5

19

18

15.5

13

11

19.5

18.5

18

17.5

15.5

12.5

10.5

18.5

17.5

17

15

17.5

16.5

16

20

18.5

15.5

13

16

14.5

12.5

10

12.5

10

10.5

11

*Effective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 ¥ V_REF/GAIN). The above table applies for

a V_REFof 2.5 V and resolution numbers are rounded to the nearest 0.5 LSB.

REV.G

–11–

AD7711

Figure 2 shows similar information to that outlined in Table I.

In these plots, however, the output rms noise is shown for the

full range of available cutoffs frequencies. The numbers given in

these plots are typical values at 25∞C.

A/D converter (sigma-delta modulator) converts the sampled

signal into a digital pulse train whose duty cycle contains the

digital information. The programmable gain function on the

analog input is also incorporated in this sigma-delta modulator

with the input sampling frequency being modified to give the

higher gains. A sinc³digital low-pass filter processes the out-

put of the sigma-delta modulator and updates the output

register at a rate determined by the first notch frequency of

this filter. The output data can be read from the serial port

randomly or periodically at any rate up to the output register

update rate. The first notch of this digital filter (and therefore

its –3 dB frequency) can be programmed via an on-chip con-

trol register. The programmable range for this first notch

frequency is 9.76 Hz to 1.028 kHz, giving a programmable range

for the –3 dB frequency of 2.58 Hz to 269 Hz.

10000

GAIN OF 1

GAIN OF 2

GAIN OF 4

GAIN OF 8

1000

100

10

The basic connection diagram for the part is shown in Figure 3.

This figure shows the AD7711 in the external clocking mode

with both the AV_DDand DV_DDpins of the AD7711 being driven

from the analog 5 V supply. Some applications have separate

supplies for both AV_DDand DV_DD, and in some cases, the ana-

log supply exceeds the 5 V digital supply (see the Power Sup-

plies and Grounding section).

1

0.1

10

100

1000

10000

NOTCH FREQUENCY – Hz

Figure 2a. Output Noise vs. Gain and Notch

Frequency (Gains of 1 to 8)

ANALOG

+5V SUPPLY

10␮F

0.1␮F

1000

AV

DD

DV

DD

GAIN OF 16

GAIN OF 32

AIN1(+)

AIN1(–)

DATA READY

DRDY

DIFFERENTIAL

ANALOG INPUT

100

10

1

TRANSMIT (WRITE)

RECEIVE (READ)

SERIAL DATA

TFS

RFS

SINGLE-ENDED

ANALOG INPUT

GAIN OF 64

AIN2

AD7711

GAIN OF 128

RTD1

RTD2

SDATA

SCLK

A0

SERIAL CLOCK

ADDRESS INPUT

AGND

ANALOG GROUND

DIGITAL GROUND

V

SS

DGND

MODE

REF OUT

REF IN(+)

+5V

SYNC

MCLK OUT

V

BIAS

REF IN(–)

0.1

MCLK IN

10

100

1000

10000

NOTCH FREQUENCY – Hz

Figure 3. Basic Connection Diagram

Figure 2b. Output Noise vs. Gain and Notch

Frequency (Gains of 16 to 128)

The AD7711 provides a number of calibration options that can

be programmed via the on-chip control register. A calibration

cycle may be initiated at any time by writing to this control

register. The part can perform self-calibration using the on-chip

calibration microcontroller and SRAM to store calibration

parameters. Other system components may also be included in

the calibration loop to remove offset and gain errors in the input

channel using the system calibration mode. Another option is a

background calibration mode where the part continuously

performs self-calibration and updates the calibration coeffi-

cients. Once the part is in this mode, the user does not have to

issue periodic calibration commands to the device or recalibrate

when there is a change in the ambient temperature or power

supply voltage.

CIRCUIT DESCRIPTION

The AD7711 is a sigma-delta A/D converter with on-chip digital

filtering for measuring wide dynamic range, low frequency signals

such as those in RTD applications, industrial control, or process

control applications. It contains a sigma-delta (or charge-bal-

ancing) ADC, a calibration microcontroller with on-chip static

RAM, a clock oscillator, a digital filter, and a bidirectional serial

communications port.

The part contains two analog input channels, a programmable

gain differential analog input, and a programmable gain single-

ended input. The gain range is from 1 to 128 allowing the part

to accept unipolar signals of 0 mV to 20 mV and 0 V to 2.5 V

or bipolar signals in the range ± 20 mV to ± 2.5 V when the

reference input voltage equals 2.5 V. The input signal to the

selected analog input channel is continuously sampled at a

rate determined by the frequency of the master clock, MCLK

IN, and the selected gain (see Table III). A charge-balancing

The AD7711 gives the user access to the on-chip calibration

registers, allowing the microprocessor to read the device calibra-

tion coefficients and also to write its own calibration coefficients

to the part from prestored values in E²PROM. This gives the

–12–

REV. G

AD7711

microprocessor much greater control over the AD7711’s cali-

bration procedure. It also means that the user can verify the

calibration is correct by comparing the coefficients after calibra-

tion with prestored values in E²PROM.

low-pass filter or integrator. It also illustrates the derivation of

the alternative name for these devices, charge-balancing ADCs.

DIFFERENTIAL

AMPLIFIER

INTEGRATOR

COMPARATOR

The AD7711 can be operated in single-supply systems provided

that the analog input voltage does not go more negative than

–30 mV. For larger bipolar signals, a V_SSof –5 V is required by

the part. For battery operation, the AD7711 also offers a pro-

grammable standby mode that reduces idle power consumption

to typically 7 mW.

V

IN

͐

+FS

2

DAC

–FS

THEORY OF OPERATION

Figure 5. Basic Charge-Balancing ADC

The general block diagram of a sigma-delta ADC is shown in

Figure 4. It contains the following elements:

The device consists of a differential amplifier (whose output is

the difference between the analog input and the output of a

1-bit DAC), an integrator, and a comparator. The term charge-

balancing comes from the fact that this system is a negative

feedback loop that tries to keep the net charge on the integrator

capacitor at zero, by balancing charge injected by the input

voltage with charge injected by the 1-bit DAC. When the analog

input is zero, the only contribution to the integrator output

comes from the 1-bit DAC. For the net charge on the integrator

capacitor to be zero, the DAC output must spend half its time at

+FS and half its time at –FS. Assuming ideal components, the

duty cycle of the comparator will be 50%.

∑ A sample-hold amplifier.

∑ A differential amplifier or subtracter.

∑ An analog low-pass filter.

∑ A 1-bit A/D converter (comparator).

∑ A 1-bit DAC.

∑ A digital low-pass filter.

COMPARATOR

S/H AMP

ANALOG

LOW-PASS

FILTER

+

–

DIGITAL

FILTER

When a positive analog input is applied, the output of the 1-bit

DAC must spend a larger proportion of the time at +FS, so the

duty cycle of the comparator increases. When a negative input

voltage is applied, the duty cycle decreases.

DIGITAL

DATA

DAC

Figure 4. General Sigma-Delta ADC

The AD7711 uses a second-order sigma-delta modulator and a

digital filter that provides a rolling average of the sampled out-

put. After power-up, or if there is a step change in the input

voltage, there is a settling time that must elapse before valid

data is obtained.

In operation, the analog signal sample is fed to the subtracter,

along with the output of the 1-bit DAC. The filtered difference

signal is fed to the comparator, which samples the difference

signal at a frequency many times that of the analog signal sampling

frequency (oversampling).

Input Sample Rate

The modulator sample frequency for the device remains at

Oversampling is fundamental to the operation of sigma-delta

ADCs. Using the quantization noise formula for an ADC,

f

_{CLK IN}/512 (19.5 kHz @ f_{CLK IN}= 10 MHz) regardless of the

selected gain. However, gains greater than ¥1 are achieved by a

combination of multiple input samples per modulator cycle and

scaling the ratio of reference capacitor to input capacitor. As a

result of the multiple sampling, the input sample rate of

the device varies with the selected gain (see Table III). The

effective input impedance is 1/C ¥ f_Swhere C is the input sam-

pling capacitance and f_Sis the input sample rate.

SNR = (6.02 ¥ number of bits + 1.76) dB,

a 1-bit ADC or comparator yields an SNR of 7.78 dB.

The AD7711 samples the input signal at a frequency of 39 kHz or

greater (see Table III). As a result, the quantization noise is

spread over a much wider frequency than that of the band of

interest. The noise in the band of interest is reduced still further

by analog filtering in the modulator loop, which shapes the

quantization noise spectrum to move most of the noise energy to

frequencies outside the bandwidth of interest. The noise perfor-

mance is thus improved from this 1-bit level to the performance

outlined in Tables I and II and in Figure 2.

Table III. Input Sampling Frequency vs. Gain

Gain

Input Sampling Frequency (f_S)

1

f_{CLK IN}/256 (39 kHz @ f_{CLK IN}= 10 MHz)

2

4

8

16

32

64

128

2 ¥ f_{CLK IN}/256 (78 kHz @ f_{CLK IN}= 10 MHz)

4 ¥ f_{CLK IN}/256 (156 kHz @ f_{CLK IN}= 10 MHz)

8 ¥ f_{CLK IN}/256 (312 kHz @ f_{CLK IN}= 10 MHz)

The output of the comparator provides the digital input for the

1-bit DAC, so that the system functions as a negative feedback

loop that tries to minimize the difference signal. The digital data

that represents the analog input voltage is contained in the duty

cycle of the pulse train appearing at the output of the compara-

tor. It can be retrieved as a parallel binary data-word using a

digital filter.

Sigma-delta ADCs are generally described by the order of the

analog low-pass filter. A simple example of a first-order sigma-

delta ADC is shown in Figure 5. This contains only a first-order

DIGITAL FILTERING

The AD7711’s digital filter behaves like a similar analog filter,

with a few minor differences.

REV.G

–13–

AD7711

First, since digital filtering occurs after the A-to-D conversion

process, it can remove noise injected during the conversion

process. Analog filtering cannot do this.

notch frequency of the filter. Since the output data rate ex-

ceeds the Nyquist criterion, the output rate for a given band-

width will satisfy most application requirements. However,

there may be some applications that require a higher data rate

for a given bandwidth and noise performance. Applications

that need this higher data rate will require some post filtering

following the digital filter of the AD7711.

On the other hand, analog filtering can remove noise super-

imposed on the analog signal before it reaches the ADC. Digital

filtering cannot do this, and noise peaks riding on signals near

full scale have the potential to saturate the analog modulator

and digital filter, even though the average value of the signal is

within limits. To alleviate this problem, the AD7711 has

overrange headroom built into the sigma-delta modulator and

digital filter, which allows overrange excursions of 5% above the

analog input range. If noise signals are larger than this, consid-

eration should be given to analog input filtering, or to reducing

the input channel voltage so that its full scale is half that of the

analog input channel full scale. This will provide an overrange

capability greater than 100% at the expense of reducing the

dynamic range by 1 bit (50%).

For example, if the required bandwidth is 7.86 Hz but the required

update rate is 100 Hz, the data can be taken from the AD7711

at the 100 Hz rate giving a –3 dB bandwidth of 26.2 Hz. Post

filtering can be applied to this to reduce the bandwidth and

output noise to the 7.86 Hz bandwidth level, while maintaining

an output rate of 100 Hz.

Post filtering can also be used to reduce the output noise from

the device for bandwidths below 2.62 Hz. At a gain of 128, the

output rms noise is 250 nV. This is essentially device noise or

white noise, and since the input is chopped, the noise has a flat

frequency response. By reducing the bandwidth below 2.62 Hz,

the noise in the resultant pass band can be reduced. A reduction

in bandwidth by a factor of 2 results in a ÷2 reduction in the

output rms noise. This additional filtering will result in a longer

settling time.

Filter Characteristics

The cutoff frequency of the digital filter is determined by the

value loaded to Bits FS0 to FS11 in the control register. At the

maximum clock frequency of 10 MHz, the minimum cutoff

frequency of the filter is 2.58 Hz while the maximum program-

mable cutoff frequency is 269 Hz.

Antialias Considerations

Figure 6 shows the filter frequency response for a cutoff fre-

quency of 2.62 Hz, which corresponds to a first filter notch fre-

quency of 10 Hz. This is a (sinx/x)³response (also called sinc³)

that provides >100 dB of 50 Hz and 60 Hz rejection. Program-

ming a different cutoff frequency via FS0–FS11 does not alter

the profile of the filter response; it changes the frequency of the

notches as outlined in the Control Register section.

The digital filter does not provide any rejection at integer mul-

tiples of the modulator sample frequency (n ¥ 19.5 kHz, where

n = 1, 2, 3 . . . ). This means that there are frequency bands,

± f_{3 dB}wide (f_{3 dB}is the cutoff frequency selected by FS0 to FS11),

where noise passes unattenuated to the output. However, due to

the AD7711’s high oversampling ratio, these bands occupy only

a small fraction of the spectrum, and most broadband noise is

filtered. In any case, because of the high oversampling ratio a

simple, RC, single-pole filter is generally sufficient to attenuate

the signals in these bands on the analog input and thus provide

adequate antialiasing filtering.

0

–20

–40

–60

If passive components are placed in front of the AD7711, care

must be taken to ensure that the source impedance is low enough

so as not to introduce gain errors in the system. The dc input

impedance for the AD7711 is over 1 GW. The input appears as

a dynamic load that varies with the clock frequency and with the

selected gain (see Figure 7). The input sample rate, as shown

in Table III, determines the time allowed for the analog input

capacitor, C_IN, to be charged. External impedances result in a

longer charge time for this capacitor, which may result in gain

errors being introduced on the analog inputs. Table IV shows the

allowable external resistance/capacitance values such that no

gain error to the 16-bit level is introduced while Table V shows

the allowable external resistance/capacitance values such that no

gain error to the 20-bit level is introduced. Both inputs of the

differential input channel (AIN1) look into similar input circuitry.

–80

–100

–120

–140

–160

–180

–200

–220

–240

0

10

20

30

40

50

60

FREQUENCY – Hz

Figure 6. Frequency Response of AD7711 Filter

Since the AD7711 contains this on-chip, low-pass filtering,

there is a settling time associated with step function inputs, and

data on the output will be invalid after a step change until the

settling time has elapsed. The settling time depends upon the

notch frequency chosen for the filter. The output data rate

equates to this filter notch frequency and the settling time of the

filter to a full-scale step input is four times the output data

period. In applications using both input channels, the settling

time of the filter must be allowed to elapse before data from

the second channel is accessed.

AD7711

R

INT

7k⍀ TYP

HIGH

IMPEDANCE

>1G⍀

AIN

C

INT

11.5pF TYP

V

BIAS

SWITCHING FREQUENCY DEPENDS

ON f_CLKINAND SELECTED GAIN

Post Filtering

The on-chip modulator provides samples at a 19.5 kHz output

rate. The on-chip digital filter decimates these samples to provide

data at an output rate that corresponds to the programmed first

Figure 7. Analog Input Impedance

–14–

REV. G

AD7711

For 4-wire RTD applications, one of these excitation currents is

used to provide the excitation current for the RTD; the second

current source can be left unconnected. For 3-wire RTD con-

figurations, the second on-chip current source can be used to

eliminate errors due to voltage drops across lead resistances.

Figures 19 to 21 in the Applications section show some RTD

configurations with the AD7711.

Table IV. External Series Resistance That Will Not Introduce

16-Bit Gain Error

External Capacitance (pF)

Gain

0

50

100

500

1000

5000

1

2

4

184 kW 45.3 kW 27.1 kW 7.3 kW 4.1 kW 1.1 kW

88.6 kW 22.1 kW 13.2 kW 3.6 kW 2.0 kW 560 W

The temperature coefficient of the RTD current sources is

typically 20 ppm/∞C with a typical matching between the tem-

perature coefficients of both current sources of 3 ppm/∞C. For

applications where the absolute value of the temperature coeffi-

cient is too large, the following schemes can be used to remove

the drift error.

41.4 kW 10.6 kW 6.3 kW 1.7 kW 970 W

270 W

120 W

2

8–128 17.6 kW 4.8 kW 2.9 kW 790 W 440 W

Table V. External Series Resistance That Will Not Introduce

20-Bit Gain Error

External Capacitance (pF)

The conversion result from the AD7711 is ratiometric to the

V_REFvoltage. Therefore, if the V_REFvoltage varies with the RTD

Gain

0

50

100

500

1000

5000

temperature coefficient, the temperature drift from the current

source will be removed. For 4-wire RTD applications, the refer-

ence voltage can be made ratiometric to RTD current source

by using the second current with a low TC resistor to generate

the reference voltage for the part. In this case, if a 12.5 kW

resistor is used, the 200 mA current source generates 2.5 V across

the resistor. This 2.5 V can be applied to the REF IN(+) input

of the AD7711 and with the REF IN(–) input at ground, it will

supply a V_REFof 2.5 V for the part. For 3-wire RTD configura-

tions, the reference voltage for the part is generated by placing a

low TC resistor (12.5 kW for 2.5 V reference) in series with one

of the constant current sources. The RTD current sources can

be driven to within 2 V of AV_DD. The reference input of the

AD7711 is differential so the REF IN(+) and REF IN(–) of the

AD7711 are driven from either side of the resistor. Both schemes

ensure that the reference voltage for the part tracks the RTD

current sources over temperature and, thereby, remove the

temperature drift error.

1

2

4

145 kW 34.5 kW 20.4 kW 5.2 kW 2.8 kW 700 W

70.5 kW 16.9 kW 10 kW

2.5 kW 1.4 kW 350 W

31.8 kW 8.0 kW 4.8 kW 1.2 kW 670 W

170 W

80 W

8–128 13.4 kW 3.6 kW 2.2 kW 550 W 300 W

The numbers in Tables IV and V assume a full-scale change

on the analog input. In any case, the error introduced due to

longer charging times is a gain error that can be removed using

the system calibration capabilities of the AD7711, provided

the resultant span is within the limits of the system calibration

techniques.

ANALOG INPUT FUNCTIONS

Analog Input Ranges

Both analog inputs are programmable gain input channels that

can handle either unipolar or bipolar input signals. The AIN1

channel is a differential channel with a common-mode range

from V_SSto AV_DD, provided the absolute value of the analog

input voltage lies between V_SS– 30 mV and AV_DD+ 30 mV.

The AIN2 input channel is a single-ended input that is referred

to as AGND.

Bipolar/Unipolar Inputs

The two analog inputs on the AD7711 can accept either unipo-

lar or bipolar input voltage ranges. Bipolar or unipolar options

are chosen by programming the B/U bit of the control register.

This programs both channels for either unipolar or bipolar

operation. Programming the part for either type of operation

does not change any of the input signal conditioning; it simply

changes the data output coding, using binary for unipolar inputs

and offset binary for bipolar inputs.

The dc input leakage current is 10 pA maximum at 25∞C (± 1 nA

over temperature). This results in a dc offset voltage developed

across the source impedance. However, this dc offset effect can

be compensated for by a combination of the differential input

capability of the part and its system calibration mode.

Burnout Current

The AIN1 input channel is differential and, as a result, the

voltage to which the unipolar and bipolar signals are referenced

is the voltage on the AIN1(–) input. For example, if AIN1(–) is

1.25 V and the AD7711 is configured for unipolar operation

with a gain of 1 and a V_REFof 2.5 V, the input voltage range on

the AIN1(+) input is 1.25 V to 3.75 V. If AIN1(–) is 1.25 V,

and the AD7711 is configured for bipolar mode with a gain of

1 and a V_REFof 2.5 V, the analog input range on the AIN1(+)

input is –1.25 V to +3.75 V. For the AIN2 input, the input

signals are referenced to AGND.

The AIN1(+) input of the AD7711 contains a 4.5 mA current

source that can be turned on/off via the control register. This

current source can be used in checking that a transducer has not

burned out or gone open circuit before attempting to take mea-

surements on that channel. If the current is turned on and

allowed to flow into the transducer and a measurement of the

input voltage on the AIN1 input is taken, it can indicate that the

transducer has burned out or gone open circuit. For normal

operation, this burnout current is turned off by writing a 0 to

the BO bit in the control register.

RTD Excitation Current

REFERENCE INPUT/OUTPUT

The AD7711 also contains two matched 200 mA constant cur-

rent sources that are provided at the RTD1 and RTD2 pins of

the device. These currents can be turned on/off via the control

register. Writing a 1 to the RO bit of the control register enables

these excitation currents.

The AD7711 contains a temperature compensated 2.5 V reference

that has an initial tolerance of ± 1%. This reference voltage is

provided at the REF OUT pin, and it can be used as the reference

voltage for the part by connecting the REF OUT pin to the REF

REV.G

–15–

AD7711

IN(+) pin. This REF OUT pin is a single-ended output, refer-

enced to AGND, which is capable of providing up to 1 mA to

an external load. In applications where REF OUT is connected

directly to REF IN(+), REF IN(–) should be tied to AGND to

provide the nominal 2.5 V reference for the AD7711.

For maximum internal headroom, the V_BIASvoltage should be

set halfway between AV_DDand V_SS. The difference between

AV_DDand (V_BIAS+ 0.85 ¥ V_REF) determines the amount of

headroom the circuit has at the upper end, while the difference

between V_SSand (V_BIAS– 0.85 ¥ V_REF) determines the amount

of headroom the circuit has at the lower end. When choosing a

V_BIASvoltage, ensure that it stays within prescribed limits. For

single 5 V operation, the selected V_BIASvoltage must ensure that

V_BIAS± 0.85 ¥ V_REFdoes not exceed AV_DDor V_SSor that the

V_BIASvoltage itself is greater than V_SS+ 2.1 V and less than

AV_DD– 2.1 V. For single 10 V operation or dual ± 5 V opera-

tion, the selected V_BIASvoltage must ensure that V_BIAS¥ 0.85 ¥

V_REFdoes not exceed AV_DDor V_SSor that the V_BIASvoltage

itself is greater than V_SS+ 3 V or less than AV_DD– 3 V. For

example, with AV_DD= 4.75 V, V_SS= 0 V, and V_REF= 2.5 V, the

allowable range for the V_BIASvoltage is 2.125 V to 2.625 V. With

AV_DD= 9.5 V, V_SS= 0 V, and V_REF= 5 V, the range for V_BIAS

is 4.25 V to 5.25 V. With AV_DD= +4.75 V, V_SS= –4.75 V,

and V_REF= +2.5 V, the V_BIASrange is –2.625 V to +2.625 V.

The reference inputs of the AD7711, REF IN(+) and REF IN(–),

provide a differential reference input capability. The common-

mode range for these differential inputs is from V_SSto AV_DD

.

The nominal differential voltage, V_REF(REF IN(+) – REF IN(–)),

is 2.5 V for specified operation, but the reference voltage can go

to 5 V with no degradation in performance if the absolute value

of REF IN(+) and REF IN(–) does not exceed its AV_DDand

V

_SSlimits and the V_BIASinput voltage range limits are obeyed.

The part is also functional with V_REFvoltages down to 1 V but with

degraded performance because the output noise will, in terms

of LSB size, be larger. REF IN(+) must always be greater than

REF IN(–) for correct operation of the AD7711.

Both reference inputs provide a high impedance, dynamic load

similar to the analog inputs. The maximum dc input leakage

current is 10 pA (± 1 nA over temperature), and source resis-

tance may result in gain errors on the part. The reference inputs

look like the analog input (see Figure 7). In this case, R_INTis

5 kW typ and C_INTvaries with gain. The input sample rate is

The V_BIASvoltage does have an effect on the AV_DDpower sup-

ply rejection performance of the AD7711. If the V_BIASvoltage

tracks the AV_DDsupply, it improves the power supply rejection

from the AV_DDsupply line from 80 dB to 95 dB. Using an

external Zener diode connected between the AV_DDline and

f

_{CLK IN}/256 and does not vary with gain. For gains of 1 to 8, C_INT

V

_BIASas the source for the V_BIASvoltage gives the improvement

is 20 pF; for a gain of 16, it is 10 pF; for a gain of 32, it is 5 pF; for

a gain of 64, it is 2.5 pF; and for a gain of 128, it is 1.25 pF.

in AV_DDpower supply rejection performance.

The digital filter of the AD7711 removes noise from the refer-

ence input just as it does with the analog input, and the same

limitations apply regarding lack of noise rejection at integer

multiples of the sampling frequency. The output noise perfor-

mance outlined in Tables I and II assumes a clean reference. If

the reference noise in the bandwidth of interest is excessive, it

can degrade the performance of the AD7711. Using the on-chip

reference as the reference source for the part (connecting

REF OUT to REF IN) results in degraded output noise perfor-

mance from the AD7711 for portions of the noise table that are

dominated by the device noise. The on-chip reference noise

effect is eliminated in ratiometric applications where the refer-

ence is used to provide the excitation voltage for the analog

front end. The connection shown in Figure 8 is recommended

when using the on-chip reference. Recommended reference

voltage sources for the AD7711 include the AD580 and AD680

2.5 V references.

USING THE AD7711

SYSTEM DESIGN CONSIDERATIONS

The AD7711 operates differently from successive approxima-

tion ADCs or integrating ADCs. Because it samples the signal

continuously, like a tracking ADC, there is no need for a start

convert command. The output register is updated at a rate

determined by the first notch of the filter, and the output can

be read at any time, either synchronously or asynchronously.

Clocking

The AD7711 requires a master clock input, which may be an

external TTL/CMOS compatible clock signal applied to the

MCLK IN pin with the MCLK OUT pin left unconnected.

Alternatively, a crystal of the correct frequency can be connected

between MCLK IN and MCLK OUT, in which case the clock

circuit will function as a crystal-controlled oscillator. For lower

clock frequencies, a ceramic resonator may be used instead of

the crystal. For these lower frequency oscillators, external

capacitors may be required on either the ceramic resonator or

on the crystal.

REF OUT

REF IN(+)

REF IN(–)

The input sampling frequency, the modulator sampling frequency,

the –3 dB frequency, the output update rate, and the calibration

time are all directly related to the master clock frequency,

f_{CLK IN.}Reducing the master clock frequency by a factor of 2 will

halve the above frequencies and update rate and will double the

calibration time.

AD7711

Figure 8. REF OUT/REF IN Connection

V_BIASInput

The V_BIASinput determines at what voltage the internal analog

circuitry is biased. It essentially provides the return path for

analog currents flowing in the modulator and, as such, it should

be driven from a low impedance point to minimize errors.

The current drawn from the DV_DDpower supply is also directly

related to f_{CLK IN}. Reducing f_{CLK IN}by a factor of 2 will halve the

DV_DDcurrent but will not affect the current drawn from the

AV_DDpower supply.

System Synchronization

If multiple AD7711s are operated from a common master clock,

they can be synchronized to update their output registers simul-

taneously. A falling edge on the SYNC input resets the filter and

–16–

REV. G

AD7711

going low. If DRDY is low before (or goes low during) the cali-

bration command, it may take up to one modulator cycle before

DRDY goes high to indicate that calibration is in progress.

Therefore, DRDY should be ignored for up to one modulator

cycle after the last bit of the calibration command is written to

the control register.

places the AD7711 into a consistent, known state. A common

signal to the AD7711s’ SYNC inputs will synchronize their

operation. This would typically be done after each AD7711 has

performed its own calibration or has had calibration coefficients

loaded to it.

The SYNC input can also be used to reset the digital filter in

systems where the turn-on time of the digital power supply

(DV_DD) is very long. In such cases, the AD7711 starts operat-

ing internally before the DV_DDline has reached its minimum

operating level, 4.75 V. With a low DV_DDvoltage, the

AD7711’s internal digital filter logic does not operate correctly.

Thus, the AD7711 may have clocked itself into an incorrect

operating condition by the time DV_DDhas reached its correct

level. The digital filter is reset upon issue of a calibration com-

mand (whether it is self-calibration, system calibration, or back-

ground calibration) to the AD7711. This ensures correct

operation of the AD7711. In systems where the power-on de-

fault conditions of the AD7711 are acceptable, and no calibra-

tion is performed after power-on, issuing a SYNC pulse to the

AD7711 resets the AD7711’s digital filter logic. An R, C on the

SYNC line, with R, C time constant longer than the DV_DD

power-on time, performs the SYNC function.

Self-Calibration

In the self-calibration mode with a unipolar input range, the

zero-scale point used in determining the calibration coefficients

is with both inputs shorted (that is, AIN1(+) = AIN1(–) =

V_BIASfor AIN1 and AIN2 = V_BIASfor AIN2), and the full-scale

point is V_REF. The zero-scale coefficient is determined by con-

verting an internal shorted input node. The full-scale coefficient

is determined from the span between this shorted input conver-

sion and a conversion on an internal V_REFnode. The self-

calibration mode is invoked by writing the appropriate values

(0, 0, 1) to the MD2, MD1, and MD0 bits of the control regis-

ter. In this calibration mode, the shorted input node is switched

into the modulator first and a conversion is performed; the V_REF

node is then switched in and another conversion is performed.

When the calibration sequence is complete, the calibration coeffi-

cients updated, and the filter resettled to the analog input voltage,

the DRDY output goes low. The self-calibration procedure takes

into account the selected gain on the PGA.

2

Accuracy

Sigma-delta ADCs, like VFCs and other integrating ADCs, do

not contain any source of nonmonotonicity and inherently offer

no missing codes performance. The AD7711 achieves excellent

linearity by the use of high quality, on-chip silicon dioxide capaci-

tors, which have a very low capacitance/voltage coefficient. The

device also achieves low input drift through the use of chopper

stabilized techniques in its input stage. To ensure excellent

performance over time and temperature, the AD7711 uses digital

calibration techniques that minimize offset and gain error.

For bipolar input ranges in the self-calibrating mode, the sequence

is very similar to that just outlined. In this case, the two points

that the AD7711 calibrates are midscale (bipolar zero) and

positive full scale.

System Calibration

System calibration allows the AD7711 to compensate for system

gain and offset errors as well as its own internal errors. System

calibration performs the same slope factor calculations as self-

calibration but uses voltage values presented by the system to

the AIN inputs for the zero- and full-scale points. System

calibration is a two-step process. The zero-scale point must

be presented to the converter first. It must be applied to the

converter before the calibration step is initiated and must

remain stable until the step is complete. System calibration is

initiated by writing the appropriate values (0, 1, 0) to the MD2,

MD1, and MD0 bits of the control register. The DRDY output

from the device signals when the step is complete by going low.

After the zero-scale point is calibrated, the full-scale point is

applied and the second step of the calibration process is initiated

by again writing the appropriate values (0, 1, 1) to MD2, MD1,

and MD0. Again the full-scale voltage must be set up before the

calibration is initiated, and it must remain stable throughout the

calibration step. DRDY goes low at the end of this second step to

indicate that the system calibration is complete. In the unipolar

mode, the system calibration is performed between the two end-

points of the transfer function; in the bipolar mode, it is performed

between midscale and positive full scale.

Autocalibration

Autocalibration on the AD7711 removes offset and gain errors

from the device. A calibration routine should be initiated on the

device whenever there is a change in the ambient operating

temperature or supply voltage. It should also be initiated if there

is a change in the selected gain, filter notch, or bipolar/unipolar

input range. However, if the AD7711 is in background calibra-

tion mode, these changes are taken care of automatically (after

the settling time of the filter has been allowed for).

The AD7711 offers self-calibration, system calibration, and

background calibration facilities. For calibration to occur on

the selected channel, the on-chip microcontroller must record

the modulator output for two different input conditions. These

are zero-scale and full-scale points. With these readings, the

microcontroller can calculate the gain slope for the input-to-

output transfer function of the converter. Internally, the part

works with a resolution of 33 bits to determine its conversion

result of either 16 bits or 24 bits.

The AD7711 also provides the facility to write to the on-chip

calibration registers, and in this manner, the span and offset for

the part can be adjusted by the user. The offset calibration regis-

ter contains a value that is subtracted from all conversion

results, while the full-scale calibration register contains a value

that is multiplied by all conversion results. The offset calibration

coefficient is subtracted from the result prior to the multiplica-

tion by the full-scale coefficient. In the first three modes outlined

here, the DRDY line indicates that calibration is complete by

This two-step system calibration mode offers another feature.

After the sequence has been completed, additional offset or gain

calibrations can be performed by themselves to adjust the zero

reference point or the system gain. This is achieved by perform-

ing the first step of the system calibration sequence (by writing

0, 1, 0 to MD2, MD1, MD0). This adjusts the zero-scale or

offset point but does not change the slope factor from that set

during a full system calibration sequence.

REV.G

–17–

AD7711

Span and Offset Limits

System calibration can also be used to remove any errors from

an antialiasing filter on the analog input. A simple R, C anti-

aliasing filter on the front end may introduce a gain error on the

analog input voltage, but the system calibration can be used to

remove this error.

Whenever a system calibration mode is used, there are limits on

the amount of offset and span that can be accommodated. The

range of input span in both the unipolar and bipolar modes has a

minimum value of 0.8 ¥ V_REF/GAIN and a maximum value of

2.1 ¥ V_REF/GAIN.

System Offset Calibration

The amount of offset that can be accommodated depends on

whether the unipolar or bipolar mode is being used. This offset

range is limited by the requirement that the positive full-scale

calibration limit is £ 1.05 ¥ V_REF/GAIN. Therefore, the offset

range plus the span range cannot exceed 1.05 ¥ V_REF/GAIN. If

the span is at its minimum (0.8 ¥ V_REF/GAIN), the maximum

the offset can be is (0.25 ¥ V_REF/GAIN).

System offset calibration is a variation of both the system cali-

bration and self-calibration. In this case, the zero-scale point

for the system is presented to the AIN input of the converter.

System offset calibration is initiated by writing 1, 0, 0 to MD2,

MD1, MD0. The system zero-scale coefficient is determined by

converting the voltage applied to the AIN input, while the full-

scale coefficient is determined from the span between this AIN

conversion and a conversion on V_REF. The zero-scale point

should be applied to the AIN input for the duration of the cali-

bration sequence. This is a one-step calibration sequence with

DRDY going low when the sequence is completed. In unipolar

mode, the system offset calibration is performed between the

two endpoints of the transfer function; in bipolar mode, it is

performed between midscale and positive full scale.

In bipolar mode, the system offset calibration range is again

restricted by the span range. The span range of the converter in

bipolar mode is equidistant around the voltage used for the zero-

scale point; thus the offset range plus half the span range cannot

exceed (1.05¥ V_REF/GAIN). If the span is set to 2 ¥ V_REF/GAIN,

the offset span cannot move more than ± (0.05 ¥ V_REF/GAIN)

before the endpoints of the transfer function exceed the input

overrange limits ± (1.05 ¥ V_REF/GAIN). If the span range is set to

the minimum ± (0.4 ¥ V_REF/GAIN), the maximum allowable

offset range is ± (0.65 ¥ V_REF/GAIN).

Background Calibration

The AD7711 also offers a background calibration mode where

the part interleaves its calibration procedure with its normal

conversion sequence. In the background calibration mode, the

same voltages are used as the calibration points that are used in

the self-calibration mode, that is, shorted inputs and V_REF. The

background calibration mode is invoked by writing 1, 0, 1 to

MD2, MD1, MD0 of the control register. When invoked, the

background calibration mode reduces the output data rate of the

AD7711 by a factor of 6 while the –3 dB bandwidth remains

unchanged. The advantage is that the part is continually per-

forming calibration and automatically updating its calibration

coefficients. As a result, the effects of temperature drift, sup-

ply sensitivity, and time drift on zero- and full-scale errors are

automatically removed. When the background calibration mode

is turned on, the part will remain in this mode until Bits MD2,

MD1, and MD0 of the control register are changed. With back-

ground calibration mode on, the first result from the AD7711

will be incorrect because the full-scale calibration will not have

been performed. For a step change on the input, the second

output update will have settled to 100% of the final value.

POWER-UP AND CALIBRATION

On power-up, the AD7711 performs an internal reset that sets

the contents of the control register to a known state. However, to

ensure correct calibration for the device, a calibration routine

should be performed after power-up.

The power dissipation and temperature drift of the AD7711

are low, and no warm-up time is required before the initial

calibration is performed. However, if an external reference is

being used, this reference must have stabilized before calibra-

tion is initiated.

Drift Considerations

The AD7711 uses chopper stabilization techniques to minimize

input offset drift. Charge injection in the analog switches and dc

leakage currents at the sampling node are the primary sources of

offset voltage drift in the converter. The dc input leakage current is

essentially independent of the selected gain. Gain drift within the

converter depends primarily upon the temperature tracking of the

internal capacitors. It is not affected by leakage currents.

Table VI summarizes the calibration modes and the calibration

points associated with them. It also gives the duration from

when the calibration is invoked to when valid data is available

to the user.

Table VI. Calibration Truth Table

Cal Type

MD2, MD1, MD0

Zero-Scale Cal

Shorted Inputs

AIN

Full-Scale Cal

V_REF

Sequence

Duration

Self-Cal

System Cal

System Offset Cal

Background Cal

0, 0, 1

0, 1, 0

0, 1, 1

1, 0, 0

1, 0, 1

One-Step

Two-Step

One-Step

9 ¥ 1/Output Rate

4 ¥ 1/Output Rate

9 ¥ 1/Output Rate

6 ¥ 1/Output Rate

AIN

V_REF

AIN

Shorted Inputs

–18–

REV. G

AD7711

Measurement errors due to offset drift or gain drift can be elimi-

nated at any time by recalibrating the converter or by operating

the part in the background calibration mode. Using the system

calibration mode can also minimize offset and gain errors in the

signal conditioning circuitry. Integral and differential linearity

errors are not significantly affected by temperature changes.

It is also important that power is applied to the AD7711 before

signals at REF IN, AIN, or the logic input pins in order to avoid

latch-up. If separate supplies are used for the AD7711 and the

system digital circuitry, the AD7711 should be powered up first.

If it is not possible to guarantee this, current limiting resistors

should be placed in series with the logic inputs.

ANALOG

SUPPLY

DIGITAL 5V

SUPPLY

POWER SUPPLIES AND GROUNDING

2

Because the analog inputs and reference input are differential,

most of the voltages in the analog modulator are common-mode

voltages. V_BIASprovides the return path for most of the analog

currents flowing in the analog modulator. As a result, the V_BIAS

input should be driven from a low impedance to minimize errors

due to charging/discharging impedances on this line. When the

internal reference is used as the reference source for the part,

AGND is the ground return for this reference voltage.

0.1␮F

10␮F

0.1␮F

AV

DD

DV

DD

AD7711

Figure 9. Recommended Decoupling Scheme

The analog and digital supplies to the AD7711 are independent

and separately pinned out to minimize coupling between the

analog and digital sections of the device. The digital filter will

provide rejection of broadband noise on the power supplies,

except at integer multiples of the modulator sampling frequency.

The digital supply (DV_DD) must not exceed the analog positive

supply (AV_DD) by more than 0.3 V in normal operation. If separate

analog and digital supplies are used, the recommended decoupling

scheme is shown in Figure 9. In systems where AV_DD= 5 V and

DV_DD= 5 V, it is recommended that AV_DDand DV_DDare

driven from the same 5 V supply, although each supply should be

decoupled separately as shown in Figure 9. It is preferable that

the common supply is the system’s analog 5 V supply.

DIGITAL INTERFACE

The AD7711’s serial communications port provides a flexible

arrangement to allow easy interfacing to industry-standard

microprocessors, microcontrollers, and digital signal processors.

A serial read to the AD7711 can access data from the output

register, the control register, or the calibration registers. A serial

write to the AD7711 can write data to the control register or the

calibration registers.

Two different modes of operation are available, optimized for

different types of interfaces where the AD7711 can act either as

master in the system (it provides the serial clock) or as slave (an

external serial clock can be provided to the AD7711). These

two modes, labelled self-clocking mode and external clocking

mode, are discussed in detail in the following sections.

REV.G

–19–

AD7711

Self-Clocking Mode

Data can be accessed from the output data register only when

DRDY is low. If RFS goes low with DRDY high, no data trans-

fer takes place. DRDY does not have any effect on reading data

from the control register or from the calibration registers.

The AD7711 is configured for its self-clocking mode by tying

the MODE pin high. In this mode, the AD7711 provides the

serial clock signal used for the transfer of data to and from the

AD7711. This self-clocking mode can be used with processors

that allow an external device to clock their serial port, including

most digital signal processors and microcontrollers such as the

68HC11 and 68HC05. It also allows easy interfacing to serial-

parallel conversion circuits in systems with parallel data commu-

nication, allowing interfacing to 74XX299 universal shift

registers without any additional decoding. In the case of shift

registers, the serial clock line should have a pull-down resistor

instead of the pull-up resistor shown in Figures 10 and 11.

Figure 10 shows a timing diagram for reading from the AD7711

in the self-clocking mode. The read operation shows a read from

the AD7711’s output data register. A read from the control

register or calibration registers is similar, but, in these cases, the

DRDY line is not related to the read function. Depending on

the output update rate, it can go low at any stage in the control/

calibration register read cycle without affecting the read, and its

status should be ignored. A read operation from either the con-

trol or calibration registers must always read 24 bits of data

from the respective register.

Read Operation

Data can be read from either the output register, the control

register, or the calibration registers. A0 determines whether the

data read accesses data from the control register or from the

output/calibration registers. This A0 signal must remain valid

for the duration of the serial read operation. With A0 high, data

is accessed from either the output register or the calibration

registers. With A0 low, data is accessed from the control register.

Figure 10 shows a read operation from the AD7711. For the

timing diagram shown, it is assumed that there is a pull-up

resistor on the SCLK output. With DRDY low, the RFS

input is brought low. RFS going low enables the serial clock of

the AD7711 and also places the MSB of the word on the serial

data line. All subsequent data bits are clocked out on a high to

low transition of the serial clock and are valid prior to the follow-

ing rising edge of this clock. The final active falling edge of

SCLK clocks out the LSB, and this LSB is valid prior to the final

active rising edge of SCLK. Coincident with the next falling

edge of SCLK, DRDY is reset high. DRDY going high turns off

the SCLK and the SDATA outputs, which means the data hold

time for the LSB is slightly shorter than for all other bits.

The function of the DRDY line is dependent only on the output

update rate of the device and the reading of the output data

register. DRDY goes low when a new data-word is available in

the output data register. It is reset high when the last bit of data

(either 16th bit or 24th bit) is read from the output register. If

data is not read from the output register, the DRDY line re-

mains low. The output register continues to be updated at the

output update rate but DRDY will not indicate this. A read

from the device in this circumstance accesses the most recent

word in the output register. If a new data-word becomes available

to the output register while data is being read from the output

register, DRDY will not indicate this and the new data-word

will be lost to the user. DRDY is not affected by reading from

the control register or the calibration registers.

DRDY (O)

t₃

t₂

A0 (I)

t₅

t₄

RFS (I)

t₉

t₆

SCLK (O)

t₇

t₈

MSB

t₁₀

THREE-STATE

LSB

SDATA (O)

Figure 10. Self-Clocking Mode, Output Data Read Operation

–20–

REV. G

AD7711

Write Operation

Read Operation

Data can be written to either the control register or the calibra-

tion registers. In either case, the write operation is not affected

by the DRDY line and does not have any effect on the status of

DRDY. A write operation to the control register or the calibra-

tion register must always write 24 bits.

As with self-clocking mode, data can be read from either the

output register, the control register, or the calibration registers.

A0 determines whether the data read accesses data from the

control register or from the output/calibration registers. This A0

signal must remain valid for the duration of the serial read

operation. With A0 high, data is accessed from either the output

register or from the calibration registers. With A0 low, data is

accessed from the control register.

Figure 11 shows a write operation to the AD7711. A0 deter-

mines whether a write operation transfers data to the control

register or to the calibration registers. This A0 signal must

remain valid for the duration of the serial write operation. The

falling edge of TFS enables the internally generated SCLK

output. The serial data to be loaded to the AD7711 must be

valid on the rising edge of this SCLK signal. Data is clocked

into the AD7711 on the rising edge of the SCLK signal with the

MSB transferred first. On the last active high time of SCLK, the

LSB is loaded to the AD7711. Subsequent to the next falling

edge of SCLK, the SCLK output is turned off. (The timing dia-

gram in Figure 11 assumes a pull-up resistor on the SCLK line.)

2

The function of the DRDY line is dependent only on the output

update rate of the device and the reading of the output data

register. DRDY goes low when a new data-word is available in

the output data register. It is reset high when the last bit of data

(either the 16th bit or 24th bit) is read from the output register.

If data is not read from the output register, the DRDY line

remains low. The output register continues to be updated at the

output update rate, but DRDY will not indicate this. A read

from the device in this circumstance accesses the most recent

word in the output register. If a new data-word becomes avail-

able to the output register while data is being read from the

output register, DRDY will not indicate this and the new data-

word will be lost to the user. DRDY is not affected by reading

from the control register or the calibration register.

External Clocking Mode

The AD7711 is configured for external clocking mode by tying

the MODE pin low. In this mode, SCLK of the AD7711 is config-

ured as an input, and an external serial clock must be provided to

this SCLK pin. This external clocking mode is designed for direct

interface to systems that provide a serial clock output that is syn-

chronized to the serial data output, including microcontrollers

such as the 80C51, 87C51, 68HC11, 68HC05, and most digital

signal processors.

Data can be accessed from the output data register only when

DRDY is low. If RFS goes low while DRDY is high, no data

transfer will take place. DRDY does not have any effect on reading

data from the control register or from the calibration registers.

A0 (I)

t₁₄

t₁₅

TFS (I)

t₁₇

t₁₆

t₉

SCLK (O)

t₁₉

t₁₀

t₁₈

SDATA (I)

MSB

LSB

Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation

REV.G

–21–

AD7711

resets the DRDY line high. This rising edge of DRDY turns off

the serial data output.

Figures 12a and 12b show timing diagrams for reading from the

AD7711 in external clocking mode. In Figure 12a, all the data is

read from the AD7711 in one operation. In Figure 12b, the data

is read from the AD7711 over a number of read operations. Both

read operations show a read from the AD7711’s output data

register. A read from the control register or calibration registers is

similar, but, in these cases, the DRDY line is not related to the

read function. Depending on the output update rate, it can go

low at any stage in the control/calibration register read cycle

without affecting the read, and its status should be ignored. A

read operation from either the control or calibration registers

must always read 24 bits of data.

Figure 12b shows a timing diagram for a read operation where

RFS returns high during the transmission of the word and

returns low again to access the rest of the data-word. Timing

parameters and functions are very similar to that outlined for

Figure 12a, but Figure 12b has a number of additional times to

show timing relationships when RFS returns high in the middle

of transferring a word.

RFS should return high during a low time of SCLK. On the

rising edge of RFS, the SDATA output is turned off. DRDY

remains low and will remain low until all bits of the data-word

are read from the AD7711, regardless of the number of times

RFS changes state during the read operation. Depending on the

time between the falling edge of SCLK and the rising edge of

RFS, the next bit (BIT N+1) may appear on the data bus before

RFS goes high. When RFS returns low again, it activates the

SDATA output. When the entire word is transmitted, the

DRDY line will go high, turning off the SDATA output as shown

in Figure 12a.

Figure 12a shows a read operation from the AD7711 where

RFS remains low for the duration of the data-word transmission.

With DRDY low, the RFS input is brought low. The input

SCLK signal should be low between read and write operations.

RFS going low places the MSB of the word to be read on the

serial data line. All subsequent data bits are clocked out on a

high to low transition of the serial clock and are valid prior to

the following rising edge of this clock. The penultimate falling

edge of SCLK clocks out the LSB and the final falling edge

DRDY (O)

t₂₁

t₂₀

A0 (I)

t₂₂

t₂₃

RFS (I)

t₂₆

t₂₈

SCLK (I)

t₂₄

t₂₇

t₂₅

t₂₉

THREE-STATE

SDATA (O)

MSB

LSB

Figure 12a. External Clocking Mode, Output Data Read Operation

DRDY (O)

t₂₀

A0 (I)

t₂₂

RFS (I)

t₂₆

t₃₀

SCLK (I)

t₂₄

t₂₇

t₃₁

THREE-STATE

t₂₅

BIT N+1

SDATA (O)

MSB

BIT N

Figure 12b. External Clocking Mode, Output Data Read Operation (RFS Returns High during Read Operation)

–22–

REV. G

AD7711

Write Operation

MSB transferred first. On the last active high time of SCLK, the

LSB is loaded to the AD7711.

Data can be written to either the control register or calibration

registers. In either case, the write operation is not affected by

the DRDY line and does not have any effect on the status of

DRDY. A write operation to the control register or the calibra-

tion register must always write 24 bits.

Figure 13b shows a timing diagram for a write operation to the

AD7711 with TFS returning high during the operation and

returning low again to write the rest of the data-word. Timing

parameters and functions are very similar to that outlined for

Figure 13a, but Figure 13b has a number of additional times to

show timing relationships when TFS returns high in the middle

of transferring a word.

Figure 13a shows a write operation to the AD7711 with TFS

remaining low for the duration of the operation. A0 determines

whether a write operation transfers data to the control register

or to the calibration registers. This A0 signal must remain valid

for the duration of the serial write operation. As before, the serial

clock line should be low between read and write operations. The

serial data to be loaded to the AD7711 must be valid on the

high level of the externally applied SCLK signal. Data is clocked

into the AD7711 on the high level of this SCLK signal with the

2

Data to be loaded to the AD7711 must be valid prior to the

rising edge of the SCLK signal. TFS should return high during

the low time of SCLK. After TFS returns low again, the next bit

of the data-word to be loaded to the AD7711 is clocked in on

next high level of the SCLK input. On the last active high time

of the SCLK input, the LSB is loaded to the AD7711.

A0 (I)

t₃₂

t₃₃

TFS (I)

t₂₆

t₃₄

SCLK (I)

t₂₇

t₃₆

t₃₅

SDATA (I)

MSB

LSB

Figure 13a. External Clocking Mode, Control/Calibration Register Write Operation

A0 (I)

t₃₂

TFS (I)

t₂₆

t₃₀

SCLK (I)

t₂₇

t₃₅

t₃₆

t₃₅

BIT N+1

MSB

BIT N

SDATA (I)

Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation

(TFS Returns High during Write Operation)

REV.G

–23–

AD7711

SIMPLIFYING THE EXTERNAL CLOCKING MODE

INTERFACE

START

In many applications, the user may not need to write to the

on-chip calibration registers. In this case, the serial interface to

the AD7711 in external clocking mode can be simplified by

connecting the TFS line to the A0 input of the AD7711 (see

Figure 14). This means that any write to the device will load

data to the control register (because A0 is low while TFS is

low), and any read to the device will access data from the output

data register or from the calibration registers (because A0 is high

while RFS is low). Note that in this arrangement, the user does

not have the capability of reading from the control register.

CONFIGURE AND

INITIALIZE ␮C/␮P

SERIAL PORT

BRING

RFS, TFS HIGH

POLL DRDY

RFS

FOUR

INTERFACE

LINES

SDATA

SCLK

AD7711

DRDY

LOW?

TFS

NO

A0

YES

Figure 14. Simplified Interface with TFS Connected to A0

BRING

RFS LOW

Another method of simplifying the interface is to generate the

TFS signal from an inverted RFS signal. However, generating

the signals the opposite way around (RFS from an inverted

TFS) will cause writing errors.

؋

3

READ

SERIAL BUFFER

MICROCOMPUTER/MICROPROCESSOR INTERFACING

The AD7711’s flexible serial interface allows easy interface to

most microcomputers and microprocessors. Figure 15 shows a

flowchart for a typical programming sequence for reading data

from the AD7711 to a microcomputer, while Figure 16 shows a

flowchart for writing data to the AD7711. Figures 17, 18, and

19 show some typical interface circuits.

BRING

RFS HIGH

REVERSE

Figure 15 shows continuous read operations from the AD7711

output register where the DRDY line is continuously polled.

Depending on the microprocessor configuration, the DRDY line

may come to an interrupt input, in which case DRDY will auto-

matically generate an interrupt without being polled. The read-

ing of the serial buffer could be anything from one read

operation up to three read operations (where 24 bits of data

are read into an 8-bit serial register). A read operation to the

control/calibration registers is similar, but, in this case, the status

of DRDY can be ignored. The A0 line is brought low when the

RFS line is brought low during a read from the control register.

ORDER OF BITS

Figure 15. Flowchart for Continuous Read Operations

to the AD7711

Figure 16 shows a single 24-bit write operation to the AD7711

control or calibration registers. This shows data being transferred

from data memory to the accumulator before being written to

the serial buffer. Some microprocessor systems allow data to be

written directly to the serial buffer from data memory. Writing

data to the serial buffer from the accumulator generally consists

of either two or three write operations, depending on the size of

the serial buffer.

The flowchart also shows the bits being reversed after they have

been read in from the serial port. This depends on whether the

microprocessor expects the MSB of the word first or the LSB of

the word first. The AD7711 outputs the MSB first.

Figure 16 also shows the option of the bits being reversed before

being written to the serial buffer, which depends on whether the

first bit transmitted by the microprocessor is the MSB or the

LSB. The AD7711 expects the MSB as the first bit in the data

stream. In cases where the data is being read or being written in

bytes and the data has to be reversed, the bits have to be reversed

for every byte.

–24–

REV. G

AD7711

Table VII shows some typical 8XC51 code used for a single 24-bit

read from the output register of the AD7711. Table VIII shows

some typical code for a single write operation to the control

register of the AD7711. The 8XC51 outputs the LSB first in a

write operation, while the AD7711 expects the MSB first so the

data to be transmitted has to be rearranged before being written

to the output serial register. Similarly, the AD7711 outputs the

MSB first during a read operation that the 8XC51 expects the

LSB first. Therefore, the data that is read into the serial buffer

needs to be rearranged before the correct data-word from the

AD7711 is available in the accumulator.

START

CONFIGURE AND

INITIALIZE ␮C/␮P

SERIAL PORT

BRING

RFS, TFS AND

A0 HIGH

2

LOAD DATA FROM

ADDRESS TO

Table VII. 8XC51 Code for Reading from the AD7711

ACCUMULATOR

MOV SCON,#00010001B; Configure 8051 for MODE 0

MOV IE,#00010000B;

SETB 90H;

SETB 91H;

SETB 93H;

MOV R1,#003H;

Disable All Interrupts

Set P1.0, Used as RFS

Set P1.1, Used as TFS

Set P1.3, Used as A0

Sets Number of Bytes to Be Read in

Read Operation

REVERSE

ORDER OF

BITS

BRING

MOV R0,#030H;

Start Address for where Bytes Will

Be Loaded

TFS AND A0 LOW

MOV R6,#004H;

WAIT:

NOP;

MOV A,P1;

ANL A,R6;

JZ READ;

SJMP WAIT;

READ:

Use P1.2 as DRDY

؋

3

WRITE DATA FROM

ACCUMULATOR TO

SERIAL BUFFER

Read Port 1

Mask Out All Bits Except DRDY

If Zero Read

Otherwise Keep Polling

BRING

TFS AND A0 HIGH

CLR 90H;

CLR 98H;

POLL:

Bring RFS Low

Clear Receive Flag

END

JB 98H, READ1

SJMP POLL

READ 1:

MOV A,SBUF;

RLC A;

Tests Receive Interrupt Flag

Figure 16. Flowchart for Single Write Operation

to the AD7711

Read Buffer

Rearrange Data

Reverse Order of Bits

AD7711 to 8051 Interface

Figure 17 shows an interface between the AD7711 and the 8XC51

microcontroller. The AD7711 is configured for external clocking

mode, while the 8XC51 is configured in its Mode 0 serial interface

mode. The DRDY line from the AD7711 is connected to the Port

P1.2 input of the 8XC51, so the DRDY line is polled by the

8XC51. The DRDY line can be connected to the INT1 input of

the 8XC51 if an interrupt driven system is preferred.

MOV B.0,C;

RLC A; MOV B.1,C; RLC A; MOV B.2,C;

RLC A; MOV B.3,C; RLC A; MOV B.4,C;

RLC A; MOV B.5,C; RLC A; MOV B.6,C;

RLC A; MOV B.7,C;

MOV A,B;

MOV @R0,A;

INC R0;

Write Data to Memory

Increment Memory Location

Decrement Byte Counter

DV

DD

DEC R1

MOV A,R1

JZ END

JMP WAIT

END:

SETB 90H

FIN:

SYNC

Jump if Zero

Fetch Next Byte

P1.0

P1.1

P1.2

P1.3

RFS

TFS

DRDY

8XC51

Bring RFS High

AD7711

A0

P3.0

P3.1

SDATA

SCLK

SJMP FIN

MODE

Figure 17. AD7711 to 8XC51 Interface

REV.G

–25–

AD7711

Table VIII. 8XC51 Code for Writing to the AD7711

DV

DD

SYNC

MOV SCON,#00000000B; Configure 8051 for MODE 0

and Enable Serial Reception

SS

PC0

RFS

MOV IE,#10010000B;

MOV IP,#00010000B;

SETB 91H;

SETB 90H;

MOV R1,#003H;

Enable Transmit Interrupt

Prioritize the Transmit Interrupt

Bring TFS High

Bring RFS High

Sets Number of Bytes to Be Written

in a Write Operation

Start Address in RAM for Bytes

Clear Accumulator

Initialize the Serial Port

PC1

PC2

TFS

DRDY

68HC11

AD7711

PC3

SCK

A0

SCLK

MISO

MOSI

SDATA

MODE

MOV R0,#030H;

MOV A,#00H;

MOV SBUF,A;

WAIT:

JMP WAIT;

INT ROUTINE:

NOP;

MOV A,R1;

JZ FIN;

DEC R1;

Figure 18. AD7711 to 68HC11 Interface

Wait for Interrupt

APPLICATIONS

4-Wire RTD Configurations

Interrupt Subroutine

Load R1 to Accumulator

If Zero Jump to FIN

Decrement R1 Byte Counter

Move Byte into the Accumulator

Increment Address

Rearrange Data from LSB First

to MSB First

Figure 19 shows a 4-wire RTD application where the RTD

transducer is interfaced directly to the AD7711. In the 4-wire

configuration, there are no errors associated with lead resistances

because no current flows in the measurement leads connected to

AIN1(+) and AIN1(–). One of the RTD current sources is used

to provide the excitation current for the RTD. A common nominal

resistance value for the RTD is 100 W and, therefore, the RTD

will generate a 20 mV signal that can be handled directly by the

analog input of the AD7711. In the circuit shown, the second

RTD excitation current is used to generate the reference voltage

for the AD7711. This reference voltage is developed across R_REF

and applied to the differential reference inputs. For the nominal

reference voltage of 2.5 V, R_REFis 12.5 kW. This scheme ensures

that the analog input voltage span remains ratiometric to the

reference voltage. Any errors in the analog input voltage due to

the temperature drift of the RTD current source is compensated

for by the variation in the reference voltage. The typical matching

between the RTD current sources is less than 3 ppm/∞C.

MOV A,@R;

INC R0;

RLC A;

MOV B.0,C; RLC A; MOV B.1,C; RLC A;

MOV B.2,C; RLC A; MOV B.3,C; RLC A;

MOV B.4,C; RLC A; MOV B.5,C; RLC A;

MOV B.6,C; RLC A; MOV B.7,C; MOV A,B;

CLR 93H;

CLR 91H;

MOV SBUF,A;

RETI;

Bring A0 Low

Bring TFS Low

Write to Serial Port

Return from Subroutine

FIN:

SETB 91H;

SETB 93H;

RETI;

Set TFS High

Set A0 High

Return from Interrupt Subroutine

5V

AD7711 to 68HC11 Interface

AV

DV

DD

Figure 18 shows an interface between the AD7711 and the

68HC11 microcontroller. The AD7711 is configured for its

external clocking mode, while the SPI port is used on the

68HC11 is in single-chip mode. The DRDY line from the

AD7711 is connected to the Port PC2 input of the 68HC11, so

the DRDY line is polled by the 68HC11. The DRDY line can

be connected to the IRQ input of the 68HC11 if an interrupt

driven system is preferred. The 68HC11 MOSI and MISO lines

should be configured for wire-OR operation. Depending on the

interface configuration, it may be necessary to provide bidirec-

tional buffers between the 68HC11 MOSI and MISO lines.

200␮A

RTD2

REF IN(+)

INTERNAL

CIRCUITRY

R

REF

REF IN(–)

200␮A

RTD1

AIN1(+)

RTD

PGA

A = 1–128

AIN1(–)

AGND

The 68HC11 is configured in the master mode with its CPOL

Logic 0 bit set to a Logic 0 and its CPHA bit set to a Logic 1.

With a 10 MHz master clock on the AD7711, the interface will

operate with all four serial clock rates of the 68HC11.

AD7711

V

DGND

SS

Figure 19. 4-Wire RTD Application with the AD7711

–26–

REV. G

AD7711

3-Wire RTD Configurations

The circuit in Figure 21 shows an alternate 3-wire configura-

tion. In this case, the circuit has the same benefits in terms of

eliminating lead resistance errors as outlined in Figure 20, but it

has the additional benefit that the reference voltage is derived

from one of the current sources. This gives all the benefits of

eliminating RTD tempco errors as outlined in Figure 19. The

voltage on either RTD input can go to within 2 V of the AV_DD

supply. The circuit is shown for a 2.5 V reference.

One possible 3-wire configuration using the AD7711 is outlined

in Figure 20. In the 3-wire configuration, the lead resistances

will result in errors if only one current source is used because

the 200 mA will flow through R_L1, developing a voltage error

between AIN1(+) and AIN1(–). In the scheme outlined below,

the second RTD current source is used to compensate for the

error introduced by the 200 mA flowing through R_L1. The second

RTD current flows through R_L2. Assuming R_L1and R_L2are

equal (the leads would normally be of the same material and of

equal length) and RTD1 and RTD2 match, then the error voltage

across R_L2equals the error voltage across R_L1and no error voltage

is developed between AIN1(+) and AIN1(–). Twice the voltage

is developed across R_L3but because this is a common-mode

voltage, it will not introduce any errors. The circuit in Figure 20

shows the reference voltage for the AD7711 derived from the

part’s own internal reference.

2

AV

DV

DD

REF IN(–)

REF IN(+)

RTD1

12.5k⍀

INTERNAL

CIRCUITRY

200␮A

R

L1

AIN1(+)

AIN1(–)

PGA

RTD

A = 1–128

ANALOG 5V SUPPLY

R

L2

L3

AV

DV

DD

REF IN(+)

REF OUT

DD

RTD2

AD7711

200␮A

REF IN(–)

R

2.5V

REFERENCE

AGND

200␮A

RTD1

V

DGND

SS

R

L1

AIN1(+)

Figure 21. Alternate 3-Wire Configuration

INTERNAL

CIRCUITRY

PGA

RTD

AIN1(–)

A = 1–128

R

L2

L3

RTD2

200␮A

R

AD7711

AGND

V

DGND

SS

Figure 20. 3-Wire RTD Application with the AD7711

OUTLINE DIMENSIONS

24-Lead Plastic Dual In-Line Package [PDIP]

(N-24)

Dimensions shown in inches and (millimeters)

1.185 (30.01)

1.165 (29.59)

1.145 (29.08)

0.295 (7.49)

0.285 (7.24)

0.275 (6.99)

24

1

13

12

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.180

(4.57)

MAX

0.015 (0.38) MIN

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

0.100

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.060 (1.52) SEATING

0.050 (1.27)

0.045 (1.14)

(2.54)

BSC

PLANE

COMPLIANT TO JEDEC STANDARDS MO-095AG

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

REV.G

–27–

AD7711

OUTLINE DIMENSIONS

24-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-24)

Dimensions shown in inches and (millimeters)

0.098 (2.49)

MAX

0.005 (0.13)

MIN

0.310 (7.87)

0.220 (5.59)

24

13

12

PIN 1

1

0.060 (1.52)

0.015 (0.38)

0.320 (8.13)

0.290 (7.37)

0.200 (5.08)

MAX

1.280 (32.51) MAX

0.150 (3.81)

MIN

0.015 (0.38)

0.008 (0.20)

0.200 (5.08)

0.125 (3.18)

15

0

SEATING

PLANE

0.100

(2.54)

BSC

0.070 (1.78)

0.030 (0.76)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

24-Lead Standard Small Outline Package [SOIC]

Wide Body

(R-24)

Dimensions shown in millimeters and (inches)

15.60 (0.6142)

15.20 (0.5984)

24

1

13

12

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

0.75 (0.0295)

0.25 (0.0098)

؋

45؇

0.30 (0.0118)

0.10 (0.0039)

8؇

0؇

0.51 (0.0201) SEATING

1.27 (0.0500)

BSC

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COPLANARITY

0.10

PLANE

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013AD

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Revision History

Location

Page

3/04—Data Sheet changed from REV. F to REV. G.

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Deleted AD7711 to ADSP-2105 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Changes to AD7711 to 68HC11 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

–28–

REV. G


型号：	AD7711ARZ
厂家：	ADI
描述：	LC2MOS Signal Conditioning ADC with RTD Excitation Currents LC2MOS信号调理ADC与RTD激励电流转换器光电二极管
文件：	总28页 (文件大小：301K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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