AD7809BSTZ-REEL_技术文档

a

+3.3 V to +5 V Quad/Octal 10-Bit DACs

AD7804/AD7805/AD7808/AD7809*

FUNCTIONAL BLOCK DIAGRAMS

FEATURES

Four 10-Bit DACs in One Package

Serial and Parallel Loading Facilities Available

AD7804 Quad 10-Bit Serial Loading

AD7805 Quad 10-Bit Parallel Loading

AD7808 Octal 10-Bit Serial Loading

AD7809 Octal 10-Bit Parallel Loading

+3.3 V to +5 V Operation

AV

DD

DV

DD

AGND DGND

V

F*

OUT

POWER ON

RESET

REFOUT

REFIN

1.23V REF

AD7804/

AD7808

V

E*

AV

DD

V

BIAS

DIVIDER

V

D

C

B

MUX

DAC D

OUT

COMP

CHANNEL D

CONTROL REG

DATA

REGISTER

DAC

REGISTER

Power-Down Mode

Power-On Reset

V

BIAS

MUX

DAC C

Standby Mode (All DACs/Individual DACs)

Low Power All CMOS Construction

10-Bit Resolution

Double Buffered DAC Registers

Dual External Reference Capability

DATA

REGISTER

CHANNEL C

CONTROL REG

DAC

REGISTER

V

BIAS

MUX

DAC B

CHANNEL B

CONTROL REG

DATA

REGISTER

DAC

REGISTER

APPLICATIONS

Optical Disk Drives

Instrumentation and Communication Systems

Process Control and Voltage Setpoint Control

Trim Potentiometer Replacement

Automatic Calibration

V

BIAS

V

A

MUX

DAC A

OUT

PD**

DATA

REGISTER

DAC

REGISTER

CHANNEL A

CONTROL REG

H*

G*

SYSTEM

CONTROL REG

OUT

V

OUT

FSIN

CLKIN

SDIN

INPUT SHIFT

REGISTER &

CONTROL LOGIC

GENERAL DESCRIPTION

The AD7804/AD7808 are quad/octal 10-bit digital-to-analog

converters, with serial load capabilities, while the AD7805/AD7809

are quad/octal 10-bit digital-to-analog converters with parallel

load capabilities. These parts operate from a +3.3 V to +5 V

(±10%) power supply and incorporates an on-chip reference.

**ONLY AD7804 SHOWN FOR CLARITY

**SHOWS ADDITIONAL CHANNELS ON THE AD7808

**PIN ON THE AD7808 ONLY

CLR LDAC

AV

DD

DV

DD

AGND DGND

V

OUT

F*

E*

POWER ON

RESET

REFOUT

REFIN

1.23V REF

AD7805/

AD7809

These DACs provide output signals in the form of V_BIAS± V_SWING

V_SWINGis derived internally from V_BIAS. On-chip control registers

include a system control register and channel control registers.

The system control register has control over all DACs in the

package. The channel control registers allow individual control

of DACs. The complete transfer function of each individual

DAC can be shifted around the V_BIASpoint using an on-chip

Sub DAC. All DACs contain double buffered data inputs,

which allow all analog outputs to be simultaneously updated

using the asynchronous LDAC input.

.

V

OUT

AV

DD

V

BIAS

DIVIDER

V

D

MUX

DAC D

OUT

COMP

CHANNEL D

CONTROL REG

DATA

REGISTER

DAC

REGISTER

V

BIAS

V

C

MUX

OUT

DAC C

DAC

REGISTER

CHANNEL C

CONTROL REG

DATA

REGISTER

V

BIAS

B

A

MUX

DAC B

Control Features

Channels Controlled

Main DAC

Sub DAC

DATA

REGISTER

DAC

REGISTER

CHANNEL B

CONTROL REG

Hardware Clear

System Control

Power Down¹

System Standby²

System Clear

Input Coding

Channel Control

Channel Standby²

Channel Clear

V_BIAS

All

͙

V

BIAS

All

͙

V

MUX

DAC A

DATA

REGISTER

DAC

REGISTER

CHANNEL A

CONTROL REG

͙

PD**

SYSTEM

CONTROL REG

V

H*

G*

OUT

Selective

͙

INPUT

REGISTER

CS

WR

CONTROL

LOGIC

V

OUT

MODE A0 A1

DB9 DB2 DB1 DB0

A2**

CLR LDAC

NOTES

**ONLY AD7805 SHOWN FOR CLARITY

**SHOWS ADDITIONAL CHANNELS ON THE AD7809

**PIN ON THE AD7809 ONLY

¹Power-down function powers down all internal circuitry including the reference.

²Standby functions power down all circuitry except for the reference.

*Patent pending.

Index on Page 26.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

AD7804/AD7805/AD7808/AD7809

AD7804/AD7805–SPECIFICATIONS _{(AV and DV}

_DD= 3.3 V ؎ 10% to 5 V ؎ 10%; AGND = DGND = 0 V;

Reference = Internal Reference; C_L= 100 pF; R_L= 2 k⍀ to GND. Sub DAC at Midscale. All specifications T_MINto T_MAXunless otherwise noted.)

DD

Parameter

B Grade¹

C Grade¹

Units

Comments

STATIC PERFORMANCE

MAIN DAC

Resolution

10

Bits

Relative Accuracy

Gain Error

±3

–80/+40

–V

±3

–80/+40

–V

LSB max

% FSR max

mV max

Bias Offset Error²

Zero-Scale Error³

DAC Code = 0.5 Full Scale

DAC Code = 000H for Offset Binary

BIAS

/ +40

16

Monotonicity

Minimum Load Resistance

SUB DAC

Resolution

Differential Nonlinearity

9

2

10

2

Bits

kΩ min

and 200H for Twos Complement Coding

Refers to an LSB of the Main DAC

8

Bits

LSB typ

LSB max

±0.125

±0.5

±0.125

±0.5

OUTPUT CHARACTERISTICS

Output Voltage Range³

V

_BIAS± 15/16 × V_BIAS

V

_BIAS± 15/16 × V_BIAS

V

Twos Complement Coding

Offset Binary Coding

Typically 1.5 µs

V_BIAS/16 to 31/16 × V_BIASV_BIAS/16 to 31/16 × V_BIAS

4

Voltage Output Settling Time to 10 Bits

Slew Rate

Digital-to-Analog Glitch Impulse

Digital Feedthrough

Digital Crosstalk

Analog Crosstalk

4

2.5

1

0.5

±0.2

2

µs max

V/µs typ

nV-s typ

LSB typ

Ω typ

2.5

1

0.5

±0.2

2

1 LSB Change Around the Major Carry

DC Output Impedance

Power Supply Rejection Ratio

0.002

%/% typ

∆V_DD± 10%

DAC REFERENCE INPUTS

REF IN Range

1.0 to V_DD/2

V min to V max

REF IN Input Leakage

±1

µA max

Typically ±1 nA

DIGITAL INPUTS

Input High Voltage, V_IH@ V_DD= 5 V

Input High Voltage, V_IH@ V_DD= 3.3 V 2.1

Input Low Voltage, V_IL@ V_DD= 5 V

Input Low Voltage, V_IL@ V_DD= 3.3 V

Input Leakage Current

2.4

2.1

0.8

0.6

V min

V max

0.8

0.6

±10

µA max

Input Capacitance

10

pF max

Input Coding

Twos Comp/Binary

REFERENCE OUTPUT

REF OUT Output Voltage

REF OUT Error

1.23

±8

1.23

±8

V nom

% max

REF OUT Temperature Coefficient

REF OUT Output Impedance

–100

5

–100

5

ppm/°C typ

kΩ nom

POWER REQUIREMENTS

V_DD(AV_DDand DV_DD

)

3/5.5

V min to V max

I_DD(AI_DDPlus DI_DD

Normal Mode

System Standby (SSTBY) Mode

Power-Down (PD) Mode

@ +25°C

)

Excluding Load Currents

V_IH= V_DD, V_IL= DGND

12

250

12

250

mA max

µA

0.8

1.5

0.8

1.5

µA max

V_IH= V_DD, V_IL= DGND

T_MIN–T_MAX

Power Dissipation

Normal Mode

System Standby (SSTBY) Mode

Power-Down (PD) Mode

@ +25°C

Excluding Power Dissipated in Load

66

1.38

66

1.38

mW max

4.4

8.25

4.4

8.25

µW max

T_MIN–T_MAX

NOTES

¹Temperature range is –40°C to +85°C.

²Can be minimized using the Sub DAC.

³V_BIASis the center of the output voltage swing and can be V_DD/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register.

Specifications subject to change without notice.

–2–

REV. A

AD7804/AD7805/AD7808/AD7809

AD7808/AD7809–SPECIFICATIONS _{(AV and DV}

_DD= 3.3 V ؎ 10% to 5 V ؎ 10%; AGND = DGND = 0 V;

Reference = Internal Reference; C_L= 100 pF; R_L= 2 k⍀ to GND. Sub DAC at Midscale. All specifications T_MINto T_MAXunless otherwise noted.)

DD

Parameter

B Grade¹

Units

Comments

STATIC PERFORMANCE

MAIN DAC

Resolution

10

±4

±3

±60

±35

9

Bits

Relative Accuracy

Gain Error

LSB max

% FSR max

mV max

Bits

Bias Offset Error²

Zero-Scale Error

Monotonicity

DAC Code = 0.5 Full Scale

DAC Code = 000H for Offset Binary

and 200H for Twos Complement

Coding

Minimum Load Resistance

SUB DAC

2

kΩ min

Resolution

8

Bits

Differential Nonlinearity

±0.125

±0.5

LSB typ

LSB max

Refers to an LSB of the Main DAC

OUTPUT CHARACTERISTICS

Output Voltage Range³

V

_BIAS± 15/16 × V_BIAS

V

Twos Complement Coding

Offset Binary Coding

Typically 1.5 µs

V_BIAS/16 to 31/16 × V_BIAS

4

Voltage Output Settling Time to 10 Bits

Slew Rate

Digital-to-Analog Glitch Impulse

Digital Feedthrough

Digital Crosstalk

Analog Crosstalk

µs max

V/µs typ

nV-s typ

LSB typ

Ω typ

2.5

1

0.5

±0.2

2

1 LSB Change Around the Major Carry

DC Output Impedance

Power Supply Rejection Ratio

0.002

%/% typ

∆V_DD± 10%

DAC REFERENCE INPUTS

REF IN Range

1.0 to V_DD/2

V min to V max

REF IN Input Leakage

±1

µA max

Typically ±1 nA

DIGITAL INPUTS

Input High Voltage, V_IH@ V_DD= 5 V

Input High Voltage, V_IH@ V_DD= 3.3 V

Input Low Voltage, V_IL@ V_DD= 5 V

Input Low Voltage, V_IL@ V_DD= 3.3 V

Input Leakage Current

2.4

2.1

0.8

0.6

±10

8

V min

V max

µA max

pF max

Input Capacitance

Input Coding

Twos Comp/Binary

REFERENCE OUTPUT

REF OUT Output Voltage

REF OUT Error

1.23

±8

V nom

% max

REF OUT Temperature Coefficient

REF OUT Output Impedance

–100

5

ppm/°C typ

kΩ nom

POWER REQUIREMENTS

V_DD(AV_DDand DV_DD

)

3/5.5

V min to V max

I_DD(AI_DDPlus DI_DD

Normal Mode

System Standby (SSTBY) Mode

Power-Down (PD) Mode

@ +25°C

)

Excluding Load Currents

V_IH= V_DD, V_IL= DGND

18

250

mA max

µA max

1

3

µA max

V_IH= V_DD, V_IL= DGND

T_MIN–T_MAX

Power Dissipation

Normal Mode

System Standby (SSTBY) Mode

Power-Down (PD) Mode

@ +25°C

Excluding Power Dissipated in Load

99

1.38

mW max

5.5

16.5

µW max

T_MIN–T_MAX

NOTES

¹Temperature range is –40°C to +85°C.

²Can be minimized using the Sub DAC.

³V_BIASis the center of the output voltage swing and can be V_DD/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register.

Specifications subject to change without notice.

–3–

REV. A

AD7804/AD7805/AD7808/AD7809

1

(V = 3.3 V ؎ 10% to 5 V ؎ 10%; AGND = DGND = 0 V; Reference =

DD

AD7804/AD7808 TIMING CHARACTERISTICS

Internal Reference. All specifications T_MINto T_MAXunless otherwise noted.)

Limit at T_MIN, T_MAX

All Versions

Parameter

Units

Description

t₁

t₂

t₃

t₄

t₅

t₆

t_6A

t₇

100

40

30

5

ns min

ns max

ns min

CLKIN Cycle Time

CLKIN High Time

CLKIN Low Time

FSIN Setup Time

Data Setup Time

Data Hold Time

LDAC Hold Time

FSIN Hold Time

6

90

20

40

100

t₈

t₉

LDAC, CLR Pulsewidth

LDAC Setup Time

NOTES

¹Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and

timed from a voltage of (V_IL+ V_IH)/2.

Specifications subject to change without notice.

t₁

CLKIN(I)

t₂

t₃

t₄

t₇

FSIN(I)

t₅

t₆

DB0

SDIN(I)

DB15

t_6A

t₅

1

LDAC

t₉

2

LDAC

t₈

CLR

1

2

TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.

TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.

Figure 1. Timing Diagram for AD7804 and AD7808

–4–

REV. A

AD7804/AD7805/AD7808/AD7809

AD7805/AD7809 TIMING CHARACTERISTICS¹

(V_DD= 3.3 V ؎ 10% to 5 V ؎ 10%; AGND = DGND = 0 V; Reference

= Internal Reference. All specifications T_MINto T_MAXunless otherwise noted.)

Limit at T_MIN, T_MAX

All Versions

Parameter

Unit

Description

t₁

t₂

t₃

t₄

t₅

t₆

t_6A

t₇

t₈

25

4.5

25

4.5

25

4.5

6

40

0

40

100

40

100

ns min

Mode Valid to Write Setup Time

Mode Valid to Write Hold Time

Address Valid to Write Setup Time

Address Valid to Write Hold Time

Data Setup Time

Data Hold Time

LDAC Valid to Write Hold Time

Chip Select to Write Setup Time

Chip Select to Write Hold Time

Write Pulsewidth

Time Between Successive Writes

LDAC, CLR Pulsewidth

t₉

t₁₀

t₁₁

t₁₂

Write to LDAC Setup Time

NOTE

¹Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and

timed from a voltage of (V_IL+ V_IH)/2.

Specifications subject to change without notice.

t₁

t₂

MODE

t₄

t₃

A0, A1, A2

t₈

t₇

CS

t₁₀

t₉

WR

t₆

t₅

DATA

t_6A

1

LDAC

t₁₁

t₁₂

2

LDAC

t₁₁

CLR

1

2

TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.

TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.

Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write

REV. A

–5–

AD7804/AD7805/AD7808/AD7809

ABSOLUTE MAXIMUM RATINGS¹

(T_A= +25°C unless otherwise noted)

PDIP (N-24) Package, Power Dissipation . . . . . . . . . 670 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

SOIC (R-28) Package, Power Dissipation . . . . . . . . . 875 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 70°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

PDIP (N-28) Package, Power Dissipation . . . . . . . . . 875 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

SSOP (RS-28) Package, Power Dissipation . . . . . . . . 875 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W

Lead Temperature, Soldering

DV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V + 0.3 V

Digital Input Voltage to DGND . . . . .–0.3 V to DV_DD+ 0.3 V

Analog Input Voltage to AGND . . . . . –0.3 V to AV_DD+ 0.3 V

COMP to AGND . . . . . . . . . . . . . . . –0.3 V to AV_DD+ 0.3 V

REF OUT to AGND . . . . . . . . . . . . . . . . . . –0.3 V to + AV_DD

REF IN to AGND . . . . . . . . . . . . . . . –0.3 V to AV_DD+ 0.3 V

V_OUTto AGND². . . . . . . . . . . . . . . . –0.3 V to AV_DD+ 0.3 V

Input Current to Any Pin Except Supplies³. . . . . . . . ±10 mA

Operating Temperature Range

AD7804/AD7805 Commercial Plastic

(B, C Versions) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

AD7808/AD7809 Commercial Plastic

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

TQFP (ST-44B) Package, Power Dissipation . . . . . . 450 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W

Lead Temperature, Soldering

(B, C Versions) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

SOIC (R-16) Package, Power Dissipation . . . . . . . . . 450 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

PDIP (N-16) Package, Power Dissipation . . . . . . . . . 670 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

SOIC (R-24) Package, Power Dissipation . . . . . . . . . 450 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

²The outputs may be shorted to voltages in this range provided the power dissipation

of the package is not exceeded.

³Transient currents of up to 100 mA will not cause SCR latch-up.

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

ORDERING GUIDE

Supply

Voltage

Temperature

Range

Relative

Accuracy

Package

Options

Model

Package Descriptions

AD7804BN

AD7804BR

3.3 V to 5 V

–40°C to +85°C

±3 LSB

16-Lead Plastic DIP

16-Lead Small Outline IC

N-16

R-16

AD7805BN

AD7805BR

AD7805BRS

AD7805CR

3.3 V to 5 V

–40°C to +85°C

±3 LSB

28-Lead Plastic DIP

N-28

R-28

RS-28

R-28

28 Lead Small Outline IC

28-Lead Shrink Small Outline Package

28-Lead Small Outline IC

AD7808BN

AD7808BR

AD7809BST

3.3 V to 5 V

–40°C to +85°C

±4 LSB

24-Lead Plastic DIP

24 Lead Small Outline IC

44-Lead Thin Plastic Quad Flatpack (TQFP)

N-24

R-24

ST-44B

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although these devices feature proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–6–

REV. A

AD7804/AD7805/AD7808/AD7809

AD7804/AD7808 PIN FUNCTION DESCRIPTION

AD7804

Pin No.

AD7808

Pin No. Mnemonic

Description

1

2, 3

4

1, 6

2, 3

4

AGND

_OUTB, V_OUT

REFOUT

Ground reference point for analog circuitry.

Analog output voltage from the DACs.

Reference Output. This is a bandgap reference and is typically 1.23 V.

V

A

5

PD

Active low input used to put the part into low power mode reducing current consumption

to 1 µA.

7, 8

9

V

FSIN

_OUTF, V_OUT

E

Analog output voltages from the DACs.

5

6

Level-triggered control input (active low). This is the frame synchronization signal for the

input data. When FSIN goes low, it enables the input shift register and data is transferred

on the falling edges of CLKIN.

LDAC Input. When this digital input is taken low, all DAC registers are simultaneously

updated with the contents of the data registers. If LDAC is tied permanently low, or is

low on the sixteenth falling clock edge with timing similar to that of SDIN, an automatic

update will take place.

10

LDAC

7

11

SDIN

Serial Data Input. These devices accept a 16-bit word. Data is clocked into the input shift

register on the falling edge of CLKIN.

8

9

10

12

13

14

DGND

DV_DD

CLKIN

Ground reference point for digital circuitry.

Digital Power Supply.

Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN.

Duty Cycle should be between 40% and 60%.

11

15

CLR

Asynchronous CLR Input. When this input is taken low, all Main DAC outputs are

cleared either to V_BIASor to V_BIAS/16 volts. All Sub DACs are also cleared and thus the

transfer function of the Main DAC will remain centered around the V_BIASpoint.

16

17, 18

20

NC

No Connect. This pin should be left open circuit.

Analog output voltages from the DACs.

This is an external reference input for the DACs. When this reference is selected for a

DAC in the control register, the analog output from the selected DAC swings around this

point.

V_OUTH, V_OUTG

REFIN

12

13

21

COMP

Compensation Pin. This pin provides an output from the internal V_DD/2 divider and is

provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors

to both AV_DDand AGND. This pin can be overdriven with an external reference, thus

giving the facility for two external references on the part.

14, 15

16

22, 23

19, 24

V

AV_DD

_OUTD, V_OUT

C

Analog output voltage from the DACs.

Analog Power Supply. +3.3 V to +5 V.

AD7808 PIN CONFIGURATION

AD7804 PIN CONFIGURATION

1

2

24

23

22

21

20

19

18

17

AGND

AV

V

DD

1

2

3

4

5

6

7

8

16 AV

DD

AGND

C

V

B

A

OUT

V

B

A

15

14

13

12

11

10

9

V

C

OUT

3

V

D

OUT

V

D

OUT

4

COMP

REFIN

REFOUT

AD7804

TOP VIEW

(Not to Scale)

REFOUT

COMP

REFIN

5

PD

AD7808

TOP VIEW

(Not to Scale)

FSIN

LDAC

SDIN

6

AV

DD

AGND

CLR

V

F

E

7

V

G

OUT

CLKIN

8

V

H

OUT

DGND

DV

DD

9

16 NC

15

FSIN

10

11

12

LDAC

SDIN

CLR

14

13

CLKIN

DGND

DV

DD

NC = NO CONNECT

REV. A

–7–

AD7804/AD7805/AD7808/AD7809

AD7805/AD7809 PIN FUNCTION DESCRIPTIONS

AD7805 AD7809

Pin No. Pin No.

Mnemonic

Description

1, 11, 13,

20, 33

NC

No Connect. These pins should be left open circuit.

1

2, 3

4

5–10,

12, 13

19, 20

2, 5, 39, 40

41, 42

43

3, 4, 6, 7, 9, DB9–DB2

10, 15, 23

AGND

Ground reference point for analog circuitry.

Analog output voltages from the DACs.

Reference Output. This is a bandgap reference and is typically 1.23 V.

Data Inputs. DB9 to DB2 are the 8 MSBs of the data word.

V

_OUTB, V_OUT

A

E

REFOUT

24, 26

DB1, DB0

DB1 and DB0 function as the 2 LSBs of the 10-bit word in 10-bit parallel mode but

have other functions when BYTE loading structure is used.

Analog output voltages from the DACs.

LDAC Input. When this digital input is taken low, all DAC registers are simultaneously

updated with the contents of the DAC data registers. If LDAC is permanently tied low, or is

low during the rising edge of WR similar to data inputs, an automatic update will take place.

Ground reference point for digital circuitry.

Digital Power Supply.

Write Input WR is an active low logic input which is used in conjunction with CS and

the address pins to write data to the relevant registers.

8, 12

14

V_OUTF, V_OUT

LDAC

11

14

15

16

17

18

DGND

DV_DD

WR

17

18

21

19

CS

CLR

Chip Select. Active low logic input.

Asynchronous CLR Input. When this input is taken low, all Main DAC outputs are

cleared either to V_BIASor to V_BIAS/16 volts. All Sub DACs are also cleared and thus the

transfer function of the MAIN DAC will remain centered around the V_BIASpoint.

Analog output voltages from the DACs.

22, 25

V_OUTH, V_OUTG

21, 22

27, 29, 30

A2, A1, A0

DAC Address Inputs. These digital inputs are used in conjunction with CS and WR to

determine which DAC channel control register or DAC data register is loaded from the

input register. These address bits are don’t cares when writing to the system control register.

Logic Input. Logic high enables writing to the DAC data registers, a logic low enables

writing to the control registers.

This is an external reference input for the DAC. When this reference is selected for the DAC

in the control register, the analog output from the selected DAC swings around this point.

Compensation Pin. This pin provides an output from the internal V_DD/2 divider and is

provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors

to both AV_DDand AGND. This pin can be overdriven with an external reference, thus

giving the facility for two external references on the part.

23

24

25

31

32

34

MODE

REFIN

COMP

26, 27

28

35, 36

28, 37, 38

44

V_OUTD, V_OUT

AV_DD

PD

C

Analog output voltages from the DACs.

Analog Power Supply.

Active low input used to put the part into low power mode reducing current consump-

tion to 1 µA.

AD7805 PIN CONFIGURATION

AD7809 PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

28

27

26

25

AGND

AV

V

DD

V

B

A

C

OUT

44 43 42 41 40 39 38 37 36 35 34

V

D

OUT

REFOUT

DB9

COMP

1

33

32

31

30

29

28

27

26

25

24

23

NC

PIN 1

IDENTIFIER

2

3

REFIN

MODE

A0

AGND

DB9

24 REFIN

DB8

23

22

21

MODE

A0

AD7805

TOP VIEW

(Not to Scale)

4

DB8

DB7

5

AGND

DB7

A1

AD7809

TOP VIEW

(Not to Scale)

DB6

A1

6

AV

DD

DB5

20 DB0

7

A2

DB6

8

DB0

V

F

DB4 10

11

19

18

17

16

15

DB1

OUT

9

V

G

DB5

DB4

NC

OUT

LDAC

CLR

CS

10

11

DB1

DB2

12

13

14

DB3

DB2

WR

DV

12 13 14 15 16 17 18 19 20 21 22

DGND

DD

NC = NO CONNECT

–8–

REV. A

AD7804/AD7805/AD7808/AD7809

TERMINOLOGY

Relative Accuracy

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the digital inputs change state with the

DAC selected and the LDAC used to update the DAC. It is

normally specified as the area of the glitch in nV-s and is mea-

sured when the digital input code is changed by 1 LSB at the

major carry transition. Regardless of whether offset binary or twos

complement coding is used, the major carry transition occurs at

the analog output voltage change of V_BIASto V_BIAS– 1 LSB

or vice versa.

For the DACs, relative accuracy or endpoint nonlinearity is a

measure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer func-

tion. Figures 32 and 33 show the linearity at 3 V and 5 V

respectively.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of ±1 LSB maxi-

mum ensures monotonicity.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of a DAC from the digital inputs of the same

DAC but is measured when the DAC is not updated. It is speci-

fied in nV secs and is measured with a full-scale code change on

the data bus, i.e., from all 0s to all 1s and vice versa.

Bias Offset Error

If the DACs are ideal, the output voltage of any DAC with

midscale code loaded will be equal to V_BIASwhere V_BIASis se-

lected by MX1 and MX0 in the control register. The DAC bias

offset error is the difference between the actual output voltage

and V_BIAS, expressed in mV.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output

of one converter due to a digital code change to another DAC.

It is specified in nV-s.

Gain Error

The difference between the actual and ideal analog output

range, expressed as a percent of full-scale range. It is the devia-

tion in slope of the DAC transfer characteristic from ideal.

Analog Crosstalk

Analog crosstalk is a change in output of any DAC in response

to a change in the output of one or more of the other DACs. It

is measured in LSBs.

Zero-Scale Error

The zero-scale error is the actual output minus the ideal output

from any DAC when zero code is loaded to the DAC. If offset

binary coding is used, the code loaded is 000Hex, and if twos

complement coding is used, a code of 200HEX is loaded to the

DAC to calculate the zero-scale error. Zero-scale error is ex-

pressed in mV.

Power Supply Rejection Ratio (PSRR)

This specification indicates how the output of the DAC is af-

fected by changes in the power supply voltage. Power-supply

rejection ratio is quoted in terms of % change in output per %

change in V_DDfor full-scale output of the DAC. V_DDis varied

±10%.

AD7804/AD7808 INTERFACE SECTION

sequence for the channel control register write, and Figures 6

and 7 show the sequence for loading data to the Main and Sub

DAC data registers. Figure 3 shows the internal registers associ-

ated with the AD7804/AD7808 serial interface DACs. Only one

DAC structure is shown for clarity.

The AD7804 and AD7808 are serial input devices. Three lines

control the serial interface, FSIN, CLKIN and SDIN. The timing

diagram is shown in Figure 1.

Two mode bits (MD1 and MD0) which are DB13 and DB14 of

the serial word written to the AD7804/AD7808 are used to deter-

mine whether writing is to the DAC data registers or the control

registers of the device. These parts contain a system control

register for controlling the operation of all DACs in the package

as well as a channel control register for controlling the operation of

each individual DAC. Table I shows how to access these registers.

FSIN

CLKIN

SDIN

16-BIT

INPUT SHIFT REGISTER

DECODER

SYSTEM

CONTROL

REGISTER

Table I. Register Selection Table for the AD7804/AD7808

CHANNEL

CONTROL

REGISTER

DATA REGISTER

TO ALL

CHANNELS

MD1

MD0

Function

10

8

DAC REGISTER

0

1

0

1

X

Write enable to system control register.

Write enable to channel control register.

Write enable to DAC data registers.

SINGLE

CHANNEL

10

8

8-BIT DAC

(SUB DAC)

10-BIT DAC

(MAIN DAC)

V

OUT

V

INTERNAL V

BIAS

REF

/2

When the FSIN input goes low, data appearing on the SDIN

line is clocked into the input register on each falling edge of

CLKIN. Data to be transferred to the AD7804/AD7808 is

loaded MSB first. Figure 4 shows the loading sequence for the

AD7804/AD7808 system control register, Figure 5 shows the

V

MUX

DD

REFIN

Figure 3. AD7804/AD7808 Internal Registers

REV. A

–9–

AD7804/AD7805/AD7808/AD7809

MSB

LSB

X

MD0 = 0 MD1 = 0

X

0

BIN/COMP

PD SSTBY SCLR

0

X

X = Don’t Care

Figure 4. AD7804/AD7808 System Control Register Loading Sequence

DB15 (MSB)

DB0 (LSB)

X

MD0 = 1 MD1 = 0 A2* A1

A0

MX1 MX0

X

STBY

CLR

0

X

X = Don’t Care

*Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804.

Figure 5. AD7804/AD7808 Channel Control Register Loading Sequence

DB15 (MSB)

DB0 (LSB)

MAIN/SUB MD0 = X MD1 = 1 A2* A1 A0

DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1 DB0

X = Don’t Care

*Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804.

Figure 6. AD7804/AD7808 Main DAC Data Register Loading Sequence (MAIN/SUB = 0)

DB15 (MSB)

DB0 (LSB)

MAIN/SUB MD0 = X MD1 = 1 A2* A1 A0

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X

X = Don’t Care

*Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804.

Figure 7. AD7804/AD7808 Sub DAC Data Register Loading Sequence (MAIN/SUB = 1)

AD7804/AD7808 SYSTEM CONTROL REGISTER (MD1 = 0,

MD0 = 0)

The bits in this register allow control over all DACs in the

package. The control bits include power down (PD), DAC input

coding select (BIN/COMP), system standby (SSTBY) and a

system clear (SCLR). The function of these bits is as follows:

When the system control register is selected by writing zeros to

the mode bits, MD1 and MD0 the address bits are ignored as

the system control register controls all DACs in the package.

When MD1 = 0 and MD0 = 1, writing is to the channel control

register. Only the DAC selected by the address bits will be af-

fected by writing to this register. Each individual DAC has a

channel control register.

Power Down (PD)

This bit in the control register is used to shut down the complete

device. With a 0 in this position, the reference and all DACs are

put into low power mode. Writing a 1 to this bit puts the part in

the normal operating mode. When in power-down mode, the

contents of all registers are retained and are valid when the

device is put back into normal operation.

The DACs data registers are addressed by writing a one to

MD1 (DB13); the condition of MD0 (DB14) does not matter

when writing to the data registers. DB15 determines whether

writing is to the Main DAC data register or to the Sub DAC

data register. The Main DAC is 10 bits wide and the Sub DAC

is 8 bits wide. Thus when writing to the Sub DAC DB1 and

DB0 become don’t cares. The Sub DAC is used to offset the

complete transfer function of the Main DAC around its V_BIAS

point. The Sub DAC has 1/8 LSB resolution and will enable the

transfer function of the Main DAC to be offset by ± V_BIAS/32.

Coding (BIN/COMP)

This bit in the system control register allows the user to select

one of two input coding schemes. The available schemes are

Twos complement coding and offset binary coding. All DACs

will be configured with the same input coding scheme. Writing

a zero to the control register selects twos complement coding,

while writing a 1 to this bit in the control register selects offset

binary coding.

When the LDAC line goes low, all DAC registers in the device

are simultaneously loaded with the contents of their respective

DAC data registers, and the outputs change accordingly.

Bringing the CLR line low resets the DAC data and DAC regis-

With twos complement coding selected the output voltage from

the Main DAC is of the form :

ters. This hardware clear affects both the Main and Sub DACs.

This operation sets the analog output of the Main DAC to V_BIAS

16 when offset binary coding is selected and the output is set to

V_BIASwhen twos complement coding is used. V_BIASis the output

of the internal multiplexer as shown in Figure 3. The output of

the Sub DAC is used to shift the transfer function of the Main

DAC around the V_BIASpoint and the contribution from the Sub

DAC is zero following an external hardware clear. Software

clears affect the Main DACs only.

/

V_OUT= V_BIAS± V_SWING

where

15

16

V_SWINGis

×V_BIAS

With Offset Binary coding selected the output voltage from the

Main DAC ranges from:

V_BIAS

16

31

16

V

×

BIAS

V_OUT

=

to V_OUT

=

–10–

REV. A

AD7804/AD7805/AD7808/AD7809

V_BIAScan be the internal bandgap reference, the internal V_DD/2

reference or the external REFIN as determined by MX1 and

MX0 in the channel control register. A second external refer-

ence can be used if required by overdriving the V_DD/2 reference

which appears at the COMP pin.

Standby (STBY)

This bit allows the selected DAC in the package to be put into

low power mode. Writing a zero to the STBY bit in the channel

control register puts the selected DAC into standby mode. On

writing a zero to this bit all linear circuitry is switched off and

the DAC output is connected through a high impedance to

ground. The DAC is returned to normal operation by writing a

one to the STBY bit.

System Standby (SSTBY)

This bit allows all the DACs in the package to be put into low

power mode simultaneously but the reference is not affected.

Writing a one to the SSTBY bit in the system control register

puts all DACs into standby mode. On writing a one to this bit

all linear circuitry is switched off and the DAC outputs are

connected through a high impedance to ground. The DACs come

out of standby mode when a 0 is written to the SSTBY bit.

Software Clear Function (CLR)

This function allows the user to clear the contents of the se-

lected DAC’s data in software. Writing a one to the CLR bit in

the control register clears the DAC’s output. A zero in the CLR

bit position puts the DAC in normal operating mode. This

software CLR operation clears only the Main DAC, the con-

tents of the Sub DAC is unaffected by a CLR operation. The

output of the Main DAC can be cleared to one of two places

depending on the input coding used. An LDAC pulse is re-

quired to activate the channel clear function and must be ap-

plied after the bit in the channel control register is set or reset. If

twos complement coding is selected, then issuing a software

clear will reset the output of the Main DAC to midscale (V_BIAS).

If offset binary coding is selected, the Main DAC output will be

reset to V_BIAS/16 following the execution of a software clear.

System Clear Function (SCLR)

This function allows the user to clear the contents of all data

and DAC registers in software. Writing a one to the SCLR bit

in the control register clears the DAC’s outputs. A zero in this

bit position puts the DAC in normal operating mode. The out-

put of the Main DACs are cleared to one of two voltages de-

pending on the input coding used. If twos complement coding

is selected, then issuing a software clear will reset the output of

the Main DAC to midscale (V_BIAS). If offset binary coding is

selected, the Main DAC output will be reset to V_BIAS/16 follow-

ing the execution of a software clear. This system clear function

does not affect the Sub DAC; the Sub DAC data register retains

its value during a system software clear (SCLR).

Multiplexer Selection (MX1, MX0)

These two bits are used to select the reference input for the

selected DAC. Table III shows the options available.

Table III. Multiplexer Output Selection

AD7804/AD7808 CHANNEL CONTROL REGISTER (MD1 = 0,

MD0 = 1)

MX1

MX0

V_BIAS

This register allows the user to have control over individual

DACs in the package. The control bits in this register include

the address bits for the selected DAC, standby (STBY), indi-

vidual DAC clear (CLR) and multiplexer output selection

(MX1 and MX0). The function of these bits follows.

0

1

0

1

0

1

V_DD/2

INTERNAL V_REF

REFIN

Undetermined

DAC Selection (A2, A1, A0)

AD7804/AD7808 SUB DAC DATA REGISTER

Bits A2, A1 and A0 in the input registers are used to address a

specific DAC. Table IIa shows the selection table for the DACs

of the AD7804. Table IIb shows the selection table for the

DACs of the AD7808.

Figure 7 shows the loading sequence for writing to the data

registers of the DACs. DB15 determines whether writing is to

the Main or Sub DAC’s data register. A one in this position

selects the addressed Sub DAC’s data register. The Sub DAC is

8 bits wide and thus DB1 and DB0 of the 16-bit input word are

don’t cares when writing to the Sub DAC. This Sub DAC al-

lows the complete transfer function of each individual DAC to

be offset around the V_BIASpoint. This is achieved by either

adding or subtracting to the output of the Main DAC. This Sub

DAC has a span of ±V_BIAS/32 with 1/8-bit resolution. The

coding scheme for the Sub DAC is the same as that for the

Main DAC. With offset binary coding the transfer function for

the Sub DAC is

Table IIa. DAC Selection Table for the AD7804

A2

A1

A0

Function

X

0

1

0

1

0

1

DAC A Selected

DAC B Selected

DAC C Selected

DAC D Selected

Table IIb. DAC Selection Table for the AD7808

V_BIAS

16

A2

A1

A0

Function

(NB –128)

×

256

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DAC A Selected

DAC B Selected

DAC C Selected

DAC D Selected

DAC E Selected

DAC F Selected

DAC G Selected

DAC H Selected

where NB is the digital code written to the Sub DAC and varies

from 0 to 255.

With twos complement coding the transfer function for the Sub

DAC is

V_BIAS

16

NB

×

(

)

256

where NB is the digital code written to the Sub DAC and varies

from –128 to 127. V_BIAScan be either the internal bandgap

reference, the internal V_DD/2 reference or the external REFIN as

REV. A

–11–

AD7804/AD7805/AD7808/AD7809

determined by MX1 and MX0 in the channel control register as

shown in Table III. The internal V_DD/2 reference is provided at

the COMP pin. This internal reference can be overdriven with

an external reference thus providing the facility for two external

references.

POWER-UP

WRITE TO SYSTEM

CONTROL REGISTER

SYSTEM

CONFIGURATION

WRITE TO CHANNEL

CONTROL REGISTER

CHANNEL

CONFIGURATION

AD7804/AD7808 POWER-UP CONDITIONS

When power is applied to the device, the device will come up in

standby mode where all the linear circuitry excluding the refer-

ence are switched off. Figure 8 shows the relevant default val-

ues for the system control register. Since a write to the system

control register is required to remove the standby condition the

only bits for which default conditions are applicable are PD and

SSTBY. Figure 9 details the relevant default conditions for the

Channel Control Register.

N

ALL CHANNELS

CONFIGURED

Y

WRITE TO SELECTED

MAIN OR SUB DAC

DATA REGISTERS

DATA WRITE

N

DATA LOADING

COMPLETE

PD

SSTBY

1

Y

CHANGE

CHANNEL

Figure 8. Default Conditions for System Control Register

on Power-Up

Y

CONFIGURATION

N

STBY

CLR

MX1

MX0

CHANGE

SYSTEM

CONFIGURATION

1

0

Figure 9. Default Conditions for Channel Control Register

on Power-Up

N

END

After power has been applied to the device the following proce-

dure should be followed to communicate and set up the device.

First, a write to the system control register is required to clear

the SSTBY bit and change the input coding scheme if required.

Figure 10. Flowchart for Controlling the DAC Following

Power-Up

AD7805/AD7809 INTERFACE SECTION

For example, to remove standby and set up offset binary input

coding 0060Hex should be written to the input register, if twos

complement coding is required 0020Hex should be written to

the input register. MD1 and MD0 are decoded in the input

register and this allows the data to be written to the system

control register.

The AD7805 and AD7809 are parallel data input devices and

contain both control registers and data registers. The system

control register has global control over all DACs in the package

while the channel control register allows control over individual

DACs in the package. Two data registers are also available, one

for the 10-bit Main DAC and the second for the 8-bit Sub

DAC. In the parallel mode, CS and WR, in association with the

address pins, control the loading of data. Data is transferred

from the data register to the DAC register under the control of

the LDAC signal. Only data contained in the DAC register deter-

mines the analog output of any DAC. The timing diagram for

10-bit parallel loading is shown in Figure 2. The MODE pin on

the device determines whether writing is to the data registers or

to the control registers. When MODE is at a logic one, writing

is to the data registers. In the next write to the data registers a

bit in the channel control register determines whether the Main

DAC or the Sub DAC is addressed. This means that to address

either the Main or the Sub DAC the Main/Sub bit in the control

register has to be set appropriately before the data register write.

A logic zero on the mode pin enables writing to the control

register. Bit MD0 determines whether writing is to the system

control register or to the addressed channel control register.

Step two requires writing to the channel control register, which

allows individual control over each DAC in the package and

allows the V_BIASfor the DAC to be selected as well as individual

DAC standby and clear functions. For example, if channel A is

to be configured for normal operation with internal reference

selected then 4110Hex should be written to the input register.

In the input register, the MD1 and MD0 bits are decoded in

association with the address bits to give access to the required

channel control register. The third and final step is to write data

to the selected DAC. To write half scale to channel A Main

DAC, 2200Hex should be written to the input register, the

MSB in the sixteen bit stream selects the Main DAC and the

next three bits address the DAC and the final 10 bits contain

the data. To write half scale to channel A Sub DAC, then A200

should be written to the input register. The flowchart in Figure

10 shows in graphic form the steps required in communicating

with the AD7804/AD7808.

Bringing the CLR line low resets the DAC registers to one of

two known conditions depending on the coding scheme se-

lected. The hardware clear affects both the Main and Sub

DAC registers. With offset binary coding a clear sets the output

–12–

REV. A

AD7804/AD7805/AD7808/AD7809

DB9

DB0

X

of the Main DAC to the bottom of the transfer function, V_BIAS/16.

With twos complement coding the output of the DAC is cleared

to midscale which is V_BIAS. A hardware clear always clears the

output of the Sub DAC to midscale thus the output of the Sub

DAC makes zero contribution to the output of the channel.

DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X = Don’t Care

X

Figure 14. AD7805/AD7809 Main DAC Data Register (Top)

and Sub DAC Data Register (Bottom) Configuration

(MODE = 1, 10/8 = 0)

MODE ADDR

D9 D2 D1

D0

CS

WR

LDAC

CONTROL

LOGIC

INPUT REGISTER

Figure 15 shows the bit allocations when 8-bit parallel operation

is selected in the system control register. DB9 to DB2 are re-

tained as data bits. DB1 acts as a high byte or low byte enable.

When DB1 is low, the eight MSBs of the data word are loaded

to the input register. When DB1 is high, the low byte consisting

of the two LSBs are loaded to the input register. DB0 is used to

select either the Main or Sub DAC when in the byte mode.

DECODER

SYSTEM

CONTROL

REGISTER

CHANNEL

CONTROL

REGISTER

DATA REGISTER

TO ALL

CHANNELS

10

8

DAC REGISTER

SINGLE

CHANNEL

DB9

DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1 DB0

DB2 DB1

DB0

MAIN/SUB

10

8

8-BIT DAC

(SUB DAC)

10-BIT DAC

(MAIN DAC)

V

0

1

OUT

V

INTERNAL V

BIAS

REF

/2

X

V

MUX

DD

X = Don’t Care

REFIN

Figure 15. AD7805/AD7809 Main DAC Data Register Con-

figuration (MODE = 1, 10/8 = 1, MAIN/SUB = 0)

Figure 11. AD7805/AD7809 Internal Registers

Figure 16 shows the bit allocations for writing to the Sub DAC.

AD7805/AD7809 CONTROL REGISTERS

Access to the control registers of the AD7805/AD7809 is

achieved by taking the mode pin to a logic low. The control

register of these DACs are configured as in Figures 12 and 13.

There are two control registers associated with the part. System

control register which looks after the input coding, data format,

power down, system clear and system standby. The channel

control register contains bits that affect the operation of the

selected DAC. The external address bits are used to select the

DACs. These registers are eight bits wide and the last two bits

are control bits. The mode pin must be low to have access to the

control registers.

DB9

DB2 DB1

DB0

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X = Don’t Care

X

MAIN/SUB

Figure 16. AD7805/AD7809 Sub DAC Data Register Con-

figuration (MODE = 1, MAIN/SUB = 1)

Each DAC has a separate channel control register. The follow-

ing is a brief discussion on the bits in each of the control registers.

DAC Selection (A2, A1, A0)

The external address pins in conjunction with CS, WR and

MODE are used to address the various DAC data and control

registers. Table IVa shows how these DAC registers can be

addressed on the AD7805. Table IVb shows how these registers

are addressed on the AD7809. Refer to Figures 12 to 16 for infor-

mation on the registers.

DB9

DB2 DB1

DB0

X

10/8 BIN/COMP PD SSTBY SCLR

0

X

MD0 = 0

X = Don’t Care

Figure 12. AD7805/AD7809 System Control Register Con-

figuration, (MODE = 0)

Table IVa. AD7805 DAC Data/Control Register

Selection Table

DB9

DB2

DB1 DB0

X MD0 = 1

MODE

A1

A0

Function Selected

MX1 MX0 MAIN/SUB X

X

STBY CLR

0

X = Don’t Care

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DAC A Control Registers

DAC B Control Registers

DAC C Control Registers

DAC D Control Registers

DAC A Data Registers

DAC B Data Registers

DAC C Data Registers

DAC D Data Registers

Figure 13. AD7805/AD7809 Channel Control Register Con-

figuration (MODE = 0)

The external mode pin must be taken high to allow data to be

written to the DAC data registers. Figure 14 shows the bit allo-

cations when 10-bit parallel operation is selected in the system

control register.

REV. A

–13–

AD7804/AD7805/AD7808/AD7809

Table IVb. AD7809 DAC Data/Control Register

Selection Table

System Clear

SCLR

0

1

Normal operation.

MODE

A2

A1

A0

Function Selected

All DACs in the package are cleared to a known state

depending on the coding scheme selected. The SCLR bit

clears the Main DACs only; the Sub DACs are unaf-

fected by the system clear function. The main DAC is

cleared to different levels depending on the coding

scheme. With offset binary coding the Main DAC output

is cleared to the bottom of the transfer function V_BIAS/16.

With twos complement coding the Main DAC output is

cleared to midscale V_BIAS. The channel output will be the

sum of the Main DAC and Sub DAC contributions.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DAC A Control Register

DAC B Control Register

DAC C Control Register

DAC D Control Register

DAC E Control Register

DAC F Control Register

DAC G Control Register

DAC H Control Register

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DAC A Data Register

DAC B Data Register

DAC C Data Register

DAC D Data Register

DAC E Data Register

DAC F Data Register

DAC G Data Register

DAC H Data Register

AD7805/AD7809 CHANNEL CONTROL REGISTER

This register allows the user to have control over individual

DACs in the package. The control bits in this register include

multiplexer output selection (MX1 and MX0), Main or Sub

DAC selection (MAIN/SUB), standby (STBY) and individual

DAC clear (CLR). The function of these bits is as follows.

Multiplexer Selection (MX1, MX0)

Table V shows the V_BIASselection using MX1 and MX0 bits in

the channel control register.

AD7805/AD7809 SYSTEM OR CHANNEL CONTROL

REGISTER SELECTION

Table V. V_BIASSelection Table

MD0

0

This enables writing to the system control register.

The contents of this are shown in Figure 12. Mode

must be low to access this control register.

MX1

MX0

V_BIAS

0

1

0

1

0

1

V_DD/2 (Default on Power-Up)

INTERNAL VREF

REFIN

1

This enables writing to the channel control register.

The contents of this are shown in Figure 13. Mode

must also be low to access this control register.

Undetermined

Main DAC or Sub DAC Selection

MAIN/SUB

AD7805/AD7809 SYSTEM CONTROL REGISTER

The bits in this register allow control over all DACs in the pack-

age. The control bits include data format (10/8), power down

(PD), DAC input coding select (BIN/COMP), system standby

(SSTBY) and a system clear (SCLR). The function of these bits

is as follows:

0

Writing a 0 to this bit means that the data in the next

data register write is transferred to the selected Main

DAC.

1

Writing a 1 to this bit means that the data in the next

data register write is transferred to the selected Sub DAC.

Data Format

10/8

This applies to the 10-bit parallel load feature. In byte

load mode, (Figure 15) DB0 selects the Main or Sub

DAC data registers.

0

1

10-bit parallel loading structure.

Byte loading structure. (8+2 loading).

Standby

STBY

Input Coding

BIN/COMP

0

Places the selected DAC and its associated linear cir-

cuitry in Standby Mode.

0

1

Twos complement coding.

Offset Binary Coding.

1

Normal operation (default on power-up).

Clear

CLR

Power Down

PD

0

1

Normal operation.

0

1

Complete power-down of device.

Normal operation (default on power-up).

Clears the output of the selected Main DAC to one

of two conditions depending on the input coding se-

lected. With offset binary coding the Main DAC out-

put is cleared to the bottom of the transfer function,

V_BIAS/16 and with twos complement coding the Main

DAC output is cleared to midscale V_BIAS. The Sub

DAC is unaffected by a clear operation. An LDAC

signal has to be applied to the DAC for a channel clear

to be implemented.

System Standby

SSTBY

0

1

Normal operation.

All DACs in the package put in standby mode (default

on power-up).

–14–

REV. A

AD7804/AD7805/AD7808/AD7809

POWER-UP CONDITIONS (POWER-ON RESET)

When power is applied to the AD7805/AD7809 the device

powers up in a known condition. The device powers up in sys-

tem standby (SSTBY) mode where all DACs in the package are

in low power mode, the reference is active and the outputs of

the DACs are connected internally through a high impedance to

ground. Figure 17 show the default conditions for the system

control register. Since a write to the system control register is

required to remove the standby condition, relevant default con-

ditions are only applicable for PD and SSTBY in the system

control register. The following are the bits in the channel con-

trol register for which default conditions are applicable, STBY,

CLR, MX1 and MX0. Figure 18 shows the default conditions

for the channel control register.

START

WRITE TO SYSTEM

CONTROL REGISTER

Y

WRITE TO

MAIN DAC

WRITE TO CHANNEL

CONTROL REGISTER

N

Y

WRITE TO

SUB DAC

WRITE TO MAIN DAC

DATA REGISTER

WRITE TO CHANNEL

CONTROL REGISTER

N

WRITING

COMPLETE

Y

WRITE TO SUB DAC

DATA REGISTER

RECONFIGURE

SYSTEM

Y

N

PD

SSTBY

N

WRITING

COMPLETE

END

1

Y

Figure 17. Default Conditions for the AD7805/AD7809

System Control Register on Power-Up

Figure 19. Flowchart for Controlling the AD7805/AD7809

DACs in 10-Bit Parallel Mode Following Power-Up

STBY

CLR

MX1

MX0

mode as the selection can be made using the hardware bit DB0 and

this will reduce the software overheads when accessing the DACs.

1

0

CLEAR FUNCTIONS

Figure 18. Default Conditions for the AD7805/AD7809

Channel Control Register on Power-Up

There are three methods of clearing the output of the Main

DAC in these devices. The first is the external hardware clear.

An active low logic signal applied to this pin clears all the DACs

in the package. The voltage to which the output is cleared will

depend on the input coding selected. The Main DAC outputs

are cleared to midscale (V_BIAS) in twos complement format and

to the bottom of the transfer function (V_BIAS/16) in offset binary

format. The second way of clearing the main DACs is a software

clear by asserting the SCLR bit in the system control register of

the part. Writing a one to this bit clears all DACs in the pack-

age. The third method of clearing a DAC is to write a one to the

CLR bit in the channel control register. This differs from that of

the system control register in that only the selected DACs out-

put is cleared. The channel clear requires an LDAC pulse to

activate it.

The flowchart in Figure 19 shows the steps necessary to control

the AD7805/AD7809 following power-on. This flowchart de-

tails the necessary steps when using the AD7805/AD7809 in its

10-bit parallel mode. The first step is to write to the system

control register to clear the SSTBY bit and to configure the part

for 10-bit parallel mode and select the required coding scheme.

The next step is to determine whether writing is to the Main or

Sub DAC. This is achieved by writing to the channel control

register. Other bits that need to be configured in the channel

control register are MX1 and MX0 which determine the source

of the V_BIASfor the selected DAC and the channel STBY and

channel CLR bits need to be configured as desired. Once writ-

ing to the channel control register is complete, data can now be

written to the selected Main or Sub DAC.

There is only one way of clearing the output of the Sub DAC

and that is to use the external hardware clear. The output of the

Sub DAC is cleared to midscale (0 V) regardless of the input

coding being used. Figure 20 shows a simplified diagram of the

implementation of the clear functions for a single DAC in the

package.

Parallel data can also be written to the device in 8+2 format to

allow interface to 8-bit processors. Eight-bit mode is invoked by

writing a one to the 10/8 bit in the system control register.

When in the 8-bit mode the two unused data bits (DB1 and

DB0) are used as hardware control bits and have the same tim-

ing characteristics as the address inputs. DB1 is a don’t care bit

when writing to both the system and channel control registers;

DB0 acts as the mode select bit and must be low to enable writ-

ing to the system control register and when high enables access

to the channel control register.

EXT CLR

SYSTEM CLR

CLR

SUB DAC

CHANNEL CLR

LDAC

CLR

When in the 8-bit data write mode, DB1 acts as a low byte and

high byte enable, when low data is written to the 8 MSBs of the

DAC and when high data is written to the two LSBs. DB0 acts

as a bit to select writing to the Main or Sub DAC. When DB0 is

low, writing is to the Main DAC, and when high, writing is to

the Sub DAC data register. In the 8+2 mode the channel con-

trol register does not have to be accessed to switch between

writing to the Main and Sub DACs as in the 10-bit parallel

A2

MAIN DAC

ADDR

A1

DECODER

A0

ALL OTHER CIRCUITRY OMITTED FOR CLARITY

Figure 20. CLR Functions for Main and Sub DACs

REV. A

–15–

AD7804/AD7805/AD7808/AD7809

POWER-DOWN AND STANDBY FUNCTIONS

ANALOG OUTPUTS

There are two distinct low power modes on the device, power-

down mode and standby mode. When in power-down mode all

circuitry including the reference are put into low power mode

and power dissipation from the package is at its minimum.

The AD7804 and AD7805 DACs contain four independent

voltage output Main DACs with 10-bit resolution. The AD7808

and AD7809 contain eight independent voltage output main

DACs with 10-bit resolution. Each Main DAC has an associ-

ated Sub DAC with 8-bit resolution which can be used to offset

the complete transfer function of the Main DAC around the

V_BIASpoint. These DACs produce an output voltage in the form

SYSTEM PD

STANDBY

SYSTEM STBY

INT

REFERENCE

of V_BIAS±V_SWINGwhere V_SWINGis 15/16 of V_BIAS

.

CHANNEL STBY

The digital input code to these DACs can be in twos comple-

ment or offset binary form. All DACs will be configured with

the same input coding scheme which is programmed through

the system control register. The default condition on power-up

is for offset binary coding.

STANDBY

A2

MAIN & SUB

ADDR

A1

A0

DAC

DECODER

ONLY ONE DAC SHOWN FOR CLARITY

Figure 21. Implementation of Power-Down and Standby

Functions

TWOS COMPLEMENT CODING

Table VI shows the twos complement transfer function for the

Main DAC.

The standby functions allow either the selected DAC or all DACs

in the package to be put into low power mode. The reference is

not switched off when any of the standby functions are invoked.

Table VI. Twos Complement Code Table for Main DAC

Digital Input

MSB . . . LSB

Analog Output

The PD bit in the system control register is used to shut down

the complete device. With a 0 in this position the reference and all

DACs are put into low power mode. Writing a 1 to this bit puts the

part in the normal operating mode. When in power-down mode

the contents of all registers are retained and are valid when the

device is taken out of power down. The SSTBY bit which resides

in the system control register can be used to put all DACs and

their associated linear circuitry into standby mode, the SSTBY

function does not power down the reference. The STBY bit in

the channel control register can be used to put a selected DAC

and its associated linear circuitry into standby mode. Figure 18

shows a simplified diagram of how the power-down and standby

functions are implemented for a single DAC in the package.

0111111111

0111111110

V

_BIAS(1+1.875 × 511/1024)

V_BIAS(1+1.875 × 510/1024)

0000000001

0000000000

V_BIAS(1+1.875 × 1/1024)

V_BIAS

1111111111

V_BIAS(1–1.875 × 1/1024)

1000000001

1000000000

V

_BIAS(1–1.875 × 511/1024)

V_BIAS(1–1.875 × 512/1024)

Figure 22 shows the Main DAC transfer function for twos

complement coding. Any Main DAC output voltage can be

expressed as:

LDAC FUNCTION

V

_OUT' = V_BIAS+ 1.875 × V_BIAS× NA/1024

LDAC input is a logic input that allows all DAC registers to be

simultaneously updated with the contents of the DAC data

registers. LDAC input has two operating modes, a synchronous

mode and an asynchronous mode. The LDAC input condition is

sampled on the sixteenth falling edge on the AD7804/AD7808 and

is sampled on the rising edge of write on the AD7805/AD7809. If

LDAC is low on the sixteenth falling clock edge or on the rising

edge of WR, an automatic or synchronous update will take place.

LDAC input can be tied permanently low or have timing similar

to that of the data inputs to operate in the synchronous mode.

where NA is the decimal equivalent of the twos complement

input code. NA ranges from –512 to +511.

31

V

BIAS

16

V

BIAS

If LDAC is high during the sample period, the AD7804/AD7805/

AD7808/AD7809 assumes an asynchronous update. When in

the asynchronous mode, an LDAC setup time has to be allowed

following the sixteenth falling clock edge or the rising edge of

WR before the LDAC can be activated.

V

BIAS

16

200 201

3FF

001

000

1FE 1FF

DAC INPUT CODE

Figure 22. Main DAC Output Voltage vs. DAC Input Codes

(HEX) for Twos Complement Coding

–16–

REV. A

AD7804/AD7805/AD7808/AD7809

Configuring the AD7805/AD7809 for Twos Complement Coding

Figure 24 shows a typical configuration for the AD7805/AD7809.

The circuit can be used for either 3.3 V or 5 V operation and uses

the internal V_DD/2 as the reference for the part and 10-bit paral-

lel interfacing is used. The following are the steps required to

operate the Main DACs in this part.

Table VII shows the twos complement transfer function for the

Sub DAC. Figure 23 shows the Sub DAC transfer function for

twos complement coding. Any Sub DAC output voltage can be

expressed as:

V

_OUT" = V_BIAS/16 × (NB/256)

where NB is the decimal equivalent of the twos complement

input code. NB ranges from –128 to +127.

+3.3V/+5V

Table VII. Twos Complement Code Table for Sub DAC

0.1␮F

10␮F

Digital Input

MSB . . . LSB

Analog Input

0.01␮F

AV

DV

DD

COMP

REFIN

01111111

00000001

00000000

11111111

10000001

10000000

(V_BIAS/16) × (127/256)

(V_BIAS/16) × (126/256)

(V_BIAS/16) × (1/256)

0

(–V_BIAS/16) × (1/256)

(–V_BIAS/16) × (127/256)

(–V_BIAS/16) × (128/256)

REFOUT

A2*

A0

AD7805/

AD7809

V

A

B

OUT

A1

D9

D0

DIGITAL

INTERFACE

V

OUT

MODE

CS

V

C

D

OUT

V

127

256

BIAS

16

WR

؋

V

DV

DD

CLR

OUT

LDAC

AGND

DGND

*USED ON THE

AD7809 ONLY

0

Figure 24. Typical Configuration for AD7805/AD7809

System Control Register Write:

MODE = 0, address inputs (A2, A1, A0) are don’t cares.

V

128

256

BIAS

16

Write 020 Hex Configure part for 10-bit parallel, twos

complement coding, normal operation

؋

Channel Control Register Write:

80

81

FF

01

7F

DAC INPUT CODE

00

7E

MODE = 0, address inputs (A2, A1, A0) select desired channel.

Figure 23. Sub DAC Output Voltage vs. DAC Input Codes

(HEX) for Twos Complement Coding

Write 011 Hex

Internal V_DD/2 selected as V_BIASfor

DAC, and any DAC data writes that

follow are to the Main DAC.

The total output for a single channel when using twos comple-

ment coding is the sum of the voltage from the Main DAC and

the Sub DAC.

DAC Data Register Write:

MODE = 1, address inputs (A2, A1, A0) select desired channel.

V_OUT= V_OUT' + V_OUT

"

= V_BIAS+ 1.875 × V_BIAS× (NA/1024) + V_BIAS/16 × (NB/256)

Write XXX Hex With MODE = 1 all data writes are to

the selected DAC. XXX is the required

= V_BIAS× (1 + 1.875 × NA/1024 + NB/4096)

data. 200 Hex will give zero scale and 1FF

Hex will give full scale from the DAC.

where NA ranges from –512 to +511 and NB ranges from –128 to

+127. Figure 28 shows a pictorial view of the transfer function for

any DAC.

REV. A

–17–

AD7804/AD7805/AD7808/AD7809

Table VI and Figure 22 show the analog outputs available for

the above configuration. The following is the procedure re-

quired if the complete transfer function needs to be offset

around the V_BIASpoint. Table VII and Figure 23 show the ana-

log output variations available from the Sub DAC.

OFFSET BINARY CODING

Table VIII shows the offset binary transfer function for the Main

DAC.

Table VIII. Offset Binary Code Table for Main DAC

Digital Inputs

MSB . . . LSB

Analog Output

System Control Register Write:

MODE = 0, address inputs (A2, A1, A0) are don’t cares.

1111111111

1111111110

1000000001

1000000000

0111111111

0000000001

0000000000

V_BIAS+1.875 × V_BIAS(1023–512)/1024

Write 020 Hex Configure part for 10-bit parallel, twos

complement coding, normal operation

V_BIAS+1.875 × V_BIAS(1022–512)/1024

V_BIAS+1.875 × V_BIAS/1024

V_BIAS

V_BIAS+1.875 × V_BIAS(511–512)/1024

V_BIAS+1.875 × V_BIAS(1–512)/1024

V_BIAS/16

Channel Control Register Write:

MODE = 0, address inputs (A2, A1, A0) select desired channel.

Write 091 Hex

Internal V_DD/2 selected as V_BIASfor

DAC, and any DAC data writes that

follow are to the Sub DAC.

NOTE: The span range is (30/16) × V_BIAS= 1.875 × V_BIAS

DAC Data Register Write:

31

V

BIAS

16

MODE = 1, address inputs (A2, A1, A0) select desired channel.

Write XX Hex

With MODE = 1 all data writes are to

the selected DACs Sub DAC. XX is the

required data. 7F Hex will give zero scale

and 80 Hex will give full scale from the

Sub DAC.

V

BIAS

Channel Control Register Write:

MODE = 0, address inputs (A2, A1, A0) select desired channel.

Write 011 Hex

Internal V_DD/2 selected as V_BIASfor

DAC, and any DAC data writes that

follow are to the Main DAC.

V

BIAS

16

DAC Data Register Write:

000 001

1FF

201

200

3FE 3FF

DAC INPUT CODE

MODE = 1, address inputs (A2, A1, A0) select desired channel.

Figure 25. Main DAC Output Voltage vs. DAC Input Codes

(HEX) for Offset Binary Coding

Write XXX Hex With MODE = 1 all data writes are to

the selected Main DAC. XXX is the

required data. 1FF Hex will give zero

scale and 200 Hex will give full scale

from the DAC.

Figure 25 shows the Main DAC transfer function when offset

binary coding is used. With offset binary coding selected the

output voltage can be calculated as follows:

V

_OUT' = V_BIAS+ 1.875 × V_BIAS× ((NA-512)/1024)

where NA is the decimal equivalent of the offset binary input

code. NA ranges from 0 to 1023.

Table IX shows the offset binary transfer function for the Sub

DAC. Figure 26 shows the Sub DAC transfer function for

offset binary coding. Any Sub DAC output voltage can be

expressed as:

V

_OUT" = V_BIAS/16 × [(NB-128)/256]

where NB is the decimal equivalent of the offset binary input

code. NB ranges from 0 to 255.

–18–

REV. A

AD7804/AD7805/AD7808/AD7809

Table IX. Offset Binary Code Table for Sub DAC

+3.3V/+5V

Digital Input

MSB . . . LSB

Analog Output

0.1␮F

10␮F

6.8k⍀

11111111

11111110

10000001

10000000

01111111

00000001

00000000

V

_BIAS/16 × 127/256

0.01␮F

AV

DV

DD

V_BIAS/16 × 126/256

V_BIAS/16 × 1/256

0

–V_BIAS/16 × 1/256

–V_BIAS/16 × 127/256

–V_BIAS/32

COMP

REFIN

AD589

AD7804/

AD7808

FSIN

REFOUT

SERIAL

INTERFACE

SDIN

CLKIN

V

A

B

OUT

V

OUT

V

C

D

OUT

V

127

128

BIAS

32

؋

V

DV

DD

CLR

OUT

LDAC

DGND

AGND

0

Figure 27. Typical Configuration for AD7804/AD7808

Using an AD589 1.23 V Reference for the AD7804/AD7808

System Control Register Serial Write:

Write 0060 Hex Mode bits select system control register

and configure system for offset binary

V

BIAS

32

coding and normal operation.

Channel Control Register Serial Write:

00

01

7F 80 81

FF

DAC INPUT CODE

FE

Write 4210 Hex Mode bits select channel control register,

channel A is configured for operation with

external reference.

Figure 26. Sub DAC Output Voltage vs. DAC Input Codes

(HEX) for Offset Binary Coding

Configuring the AD7804/AD7808 for Offset Binary Coding

Figure 27 shows a typical configuration for the AD7804/AD7808.

This circuit can be used for both 3.3 V or 5 V operation and

uses an external AD589 as the reference for the part and serial

interfacing with offset binary coding is used. The MX1 and

MX0 bits in the system control register have to be set to enable

selection of the AD589 as the reference. The following are the

steps required to operate the DACs in this part. Figures 4 to 7

show the contents of the registers on the AD7804/AD7808.

Main DAC Data Register Serial Write:

Write 23FF Hex This 16-bit write selects writing to channel

A and writes full scale to the Main DAC.

Sub DAC Data Register Serial Write:

Write A3FF Hex This 16-bit write selects writing to channel

A Sub DAC and writes full scale to the

Sub DAC.

Table VIII and Figure 25 show the analog outputs available for

the above configuration when writing to the Main DAC only

while Table IX and Figure 26 show the contributions from the

Sub DAC to the overall transfer function. The total output for a

single channel when using offset binary coding is the sum of that

from the Main DAC and the Sub DAC.

V_OUT= V_OUT' + V_OUT

"

= V_BIAS+ 1.875 × V_BIAS× ((NA-512)/1024) + V_BIAS/16

= × [(NB-128)/256]

= V_BIAS× (1 + 1.875 × ((NA-512)/1024) + (NB-128)/

4096)

where NA ranges from 0 to +1023 and NB ranges from 0 to

+255. Figure 28 shows a pictorial view of the transfer function

for any DAC channel.

REV. A

–19–

AD7804/AD7805/AD7808/AD7809

MAIN DAC RANGE

32

2

62

V

32

V

32

V

32

BIAS

1

31

63

3

33

61

V

BIAS

V

32

BIAS

32

32 BIAS

32

BIAS

SUB DAC

RANGE

CHANNEL RANGE MIN CODE LOADED TO SUB DAC

CHANNEL RANGE CENTER CODE LOADED TO SUB DAC

CHANNEL RANGE MAX CODE LOADED TO SUB DAC

Figure 28. Pictorial View of Transfer Function for Any DAC Channel

Grounding and Layout Techniques

should be shielded with analog ground. To reduce the noise on

this reference it should be decoupled with a 0.01 µF capacitor to

analog ground, keeping the capacitor as close as possible to the

device. The comp pin which is the output from the internal

V_DD/2 reference is located next to V_OUTD on the DAC and is

sensitive to noise pickup and feedthrough from the DAC output

and thus should be shielded with analog ground to keep this

reference point as quiet as possible. The comp pin should be

decoupled both to AV_DDand AGND with 1–10 nF ceramic

capacitors. The external REFIN pin should also be shielded

with analog ground from the digital pins located next to it.

To obtain optimum performance from the AD7804/AD7805/

AD7808/AD7809 care should be taken with the layout. Causes

for concern would be feedthrough from the interface bus onto

the analog circuitry particularly the reference pins and ground

loops. The board should be designed such that the analog and

digital sections are separated as much as possible. Ground plan-

ing and shielding should be used as much as possible. Digital

and analog ground planes should only be joined in one place to

avoid ground loops. The ideal place to join the ground planes is

at the analog and digital ground pins of the DAC. Alternatively

a star ground should be established on the board to which all

other grounds are returned. Good decoupling is important in

achieving optimum performance. All supplies, analog or digital,

should be decoupled with 10 µF tantalum and 0.1 µF ceramic

capacitors to their respective grounds, and should be as close as

possible to the pins of the device. The main aim of the bypass-

ing element is to maximize the charge stored in the bypass loop

while simultaneously minimizing the inductance of this loop.

Inductance in the loop acts as an impedance to high frequency

transients and results in power supply spiking. By keeping the

decoupling as close as possible to the device, the loop area is kept

to a minimum thus reducing the possibility of power supply spikes.

The same precautions should be taken with the reference pins

on the AD7804/AD7808 to reduce the risk of noise pickup and

feedthrough.

Reference Settling Time

With the REFOUT on the AD7804/AD7805/AD7808/AD7809

decoupled with a 0.01 µF capacitor to AGND it takes the

REFOUT approximately 2 ms to fully settle after taking the

device out of power down. When this capacitor is reduced to

1 nF the settling time reduces to 150 µs. The size of the capaci-

tor required on the REFOUT depends to a large extent on the

layout, if the REFOUT is well shielded with AGND the size of

the capacitor can be reduced thus reducing the settling time for

the reference. The internal V_DD/2 reference provided at the

comp pin when decoupled with a 1 nF capacitor to both AV_DD

and AGND has very fast settling time, typically less than 500 ns.

On the AD7805 the REFOUT pin of the device is located next

to the DB9 of the data bus, to reduce the risk of digital feed-

through and noise being coupled from the digital section onto

the reference, the REFOUT pin and any trace connected to it

–20–

REV. A

Typical Performance Characteristics–AD7804/AD7805/AD7808/AD7809

0.150000

0.125000

0.100000

0.075000

0.050000

0.025000

0.000000

2.0

MAIN DAC = ZERO SCALE

SUB DAC = MID SCALE

AV = DV = 5V

DD

1.5

1.0

V

T

= V /2

DD

BIAS

V

= V /2

BIAS

DD

= +25؇C

A

T

= +25؇C

A

SUB DAC LOADED WITH

1/2 SCALE

V

= 5.5V

0.5

DD

0.0

–0.5

–1.0

–1.5

–2.0

V

= 3V

DD

SINK CURRENT

0.1 0.2 0.3

SOURCE CURRENT

–0.5 –0.4 –0.3 –0.2 –0.1 0.0

0.4 0.5

0

100 200 300 400 500 600 700 800 900 1023

DAC CODE

CURRENT – mA

Figure 29. Sink and Source Current with Zero Scale

Loaded to DAC. V_DD= 5 V and V_DD= 3 V

Figure 32. Integral Linearity with 5 V Operation

5.200000

2.0

V

= 5.5V

DD

AV = DV = 3V

DD

MAIN DAC = FULL SCALE

SUB DAC = MID SCALE

1.5

1.0

V

T

= V /2

DD

BIAS

5.180000

5.160000

5.140000

5.120000

5.100000

= +25؇C

V

= V /2

A

BIAS

DD

SUB DAC LOADED WITH

1/2 SCALE

T

= +25؇C

A

R

=

L

0.5

0.0

R

= 2k⍀

L

–0.5

–1.0

–1.5

–2.0

SOURCE CURRENT SINK CURRENT

–6.0

–4.0

–2.0

0.0

2.0

4.0

6.0

0

100 200 300 400 500 600 700 800 900 1023

DAC CODE

CURRENT – mA

Figure 30. Sink and Source Current at Full Scale with

Figure 33. Integral Linearity with 3 V Operation

V_DD= 5 V

2.850000

2.830000

2.810000

2.790000

2.770000

2.750000

1.225

V

= 3V

DD

V

= 3V

DD

MAIN DAC = FULL SCALE

SUB DAC = MID SCALE

1.224

1.223

1.222

1.221

1.220

1.219

1.218

1.217

1.216

R

= 2k⍀||100pF

L

CODE CHANGE

011111 1111 TO

100000 0000

V

= V /2

BIAS

DD

T

= +25؇C

A

T

= +25؇C

A

R

=

L

R

= 2k⍀

L

SOURCE CURRENT

–4.0 –2.0

SINK CURRENT

2.0

–6.0

0.0

4.0

6.0

0

20

40

60

80 100 120 140 160 180 200

ns

CURRENT – mA

Figure 31. Sink and Source Current at Full Scale with

_DD= 3 V

Figure 34. Digital-to-Analog Glitch Impulse

V

REV. A

–21–

AD7804/AD7805/AD7808/AD7809

MICROPROCESSOR INTERFACING

AD7804*/

AD7808

AD7804/AD7808–ADSP-2101/ADSP-2103 Interface

Figure 35 shows a serial interface between the AD7804/AD7808

and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-

2103 should be set up to operate in the SPORT Transmit Alter-

nate Framing Mode. The ADSP-2101/ADSP-2103 SPORT is

programmed through the SPORT control register and should be

configured as follows: Internal Clock Operation, Active Low

Framing, 16-bit Word Length. Transmission is initiated by

writing a word to the TX register after the SPORT has been

enabled. The data is clocked out on each rising edge of the serial

clock and clocked into the AD7804/AD7808 on the falling edge

of the SCLK.

68HC11/68L11*

PC5

CLR

PC6

LDAC

FSIN

PC7

SCK

CLKIN

SDIN

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 36. AD7804/AD7808–68HC11/68L11 Interface

AD7804/AD7808–80C51/80L51 Interface

Figure 37 shows a serial interface between the AD7804/AD7808

and the 80C51/80L51 microcontroller. The setup for the inter-

face is as follows, TXD of the 80C51/80L51 drives CLKIN of

the AD7804/AD7808 while RXD drives the serial data line of

the part. The FSIN signal is again derived from a bit program-

mable pin on the port in this case port line P3.3 is used. When

data is to be transmitted to the part, P3.3 is taken low. Data on

RXD is valid on the falling edge of TXD. The 80C51/80L51

transmits data in eight bit bytes thus only eight falling clock

edges occur in the transmit cycle. To load data to the DAC,

P3.3 is left low after the first eight bits are transmitted and a

second write cycle is initiated to transmit the second byte of

data, P3.3 is taken high following the completion of this cycle.

The 80C51/80L51 outputs the serial data in a format which has

the LSB first. The AD7804/AD7808 requires its data with the

MSB as the first bit received. The 80C51/80L51 transmit rou-

tine should take this into account. In the diagram shown LDAC

and CLR are also controlled from the bit programmable lines of

the 80C51/80L51 port. The user can bring LDAC low after

every two bytes have been transmitted to update that particular

DAC which has been programmed or alternatively it is possible

to wait until all the input registers have been loaded before

updating takes place.

AD7804*/

AD7808

ADSP-2101/

ADSP-2103*

+5V

CLR

FO

TFS

DT

LDAC

FSIN

SDIN

CLKIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 35. ADSP-2101/ADSP-2103 Interface

AD7804/AD7808–68HC11/68L11 Interface

Figure 36 shows a serial interface between the AD7804/AD7808

and the 68HC11/68L11 microcontroller. SCK of the 68HC11/

68L11 drives the CLKIN of the AD7804/AD7808, while the

MOSI output drives the serial data line of the DAC. The FSIN

signal is derived from a port line (PC7). The setup conditions

for correct operation of this interface are as follows: the

68HC11/68L11 should be configured so that its CPOL bit is a 0

and its CPHA bit is a 1. When data is being transmitted to the

DAC the FSIN line is taken low (PC7). When the 68HC11/

68L11 is configured as above, data appearing on the MOSI

output is valid on the falling edge of SCK. Serial data from the

68HC11/68L11 is transmitted in 8-bit bytes with only eight

falling clock edges occurring in the transmit cycle. Data is trans-

mitted MSB first. In order to load data to the AD7804/AD7808,

PC7 is left low after the first eight bits are transferred and a

second serial write operation is performed to the DAC and then

PC7 is taken high at the end of this procedure. In the diagram

shown LDAC and CLR are also controlled from the bit pro-

grammable lines of the 68HC11/68L11. The user can bring

LDAC low after every two bytes have been transmitted to up-

date that particular DAC which has been programmed or alter-

natively it is possible to wait until all the input registers have

been loaded before updating takes place.

AD7804*/

80C51/80L51*

AD7808

CLR

P3.5

P3.4

P3.3

TXD

LDAC

FSIN

SCLK

SDIN

RXD

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 37. AD7804/AD7808–80C51/80L51 Interface

–22–

REV. A

AD7804/AD7805/AD7808/AD7809

Again fast interface timing allows the AD7805/AD7809 inter-

face directly to the processor. Data is loaded to the AD7805/

AD7809 input latch using the following instruction:

AD7805/AD7809–ADSP-2101 Interface

Figure 38 shows a parallel interface between the AD7805/AD7809

and the ADSP-2101/ADSP-2103 digital signal processor.

OUT DAC, D.

Fast interface timing allows the AD7805/AD7809 interface

directly to the DSP. In this interface an external timer is used to

update the DACs.

DAC = Decoded DAC Address.

D = Data Memory Address.

Certain applications may require that the updating of the DAC

latch be controlled by the microprocessor rather than the exter-

nal timer. One option as shown in the TMS32020 interface is to

decode the LDAC from the address bus so that a write opera-

tion to the DAC latch (at a separate address to the input latch)

updates the output.

TIMER

DMA14

ADDRESS BUS

DMA0

A2**

A0 A1

ADDR

DECODE

LDAC

MODE

DMS

EN

AD7805/AD7809–8051/8088 Interface

CS

Figure 40 shows a parallel interface between the AD7805/

AD7809 and the 8051/8088 processors.

AD7805*/

AD7809

ADSP-2101*/

ADSP-2103*

WR

DB9

DB0

A15

ADDRESS BUS

A8

A0 A1 A2**

ADDR

DMD15

DMD0

DATA BUS

CS

DECODE

MODE

PSEN OR DEN

EN

LDAC

**ADDITIONAL PINS OMITTED FOR CLARITY

**A2 CONTAINED ON THE AD7809 ONLY

WR

Figure 38. AD7805/AD7809–ADSP-2101/ADSP-2103

Interface

AD7805*/

AD7809

8051/8088

ALE

OCTAL

LATCH

DB9

DB0

Data is loaded to the AD7805/AD7809 input register using the

following instruction:

DM(DAC) = MR0,

AD7

AD0

ADDRESS/DATA BUS

MR0 = ADSP-2101 MR0 Register.

DAC = Decoded DAC Address.

**ADDITIONAL PINS OMITTED FOR CLARITY

**A2 CONTAINED ON THE AD7809 ONLY

Figure 40. AD7805/AD7809–8051/8088 Interface

AD7805/AD7809–TMS32020 Interface

Figure 39 shows a parallel interface between the AD7805/AD7809

and the TMS32020 processor.

A15

ADDRESS BUS

A0

A0 A1 A2**

ADDR

CS

DECODE

EN

IS

AD7805*/

AD7809

TMS32020

LDAC

STRB

WR

R/W

DB9

DB0

D15

D0

DATA BUS

**ADDITIONAL PINS OMITTED FOR CLARITY

**A2 CONTAINED ON THE AD7809 ONLY

Figure 39. AD7805/AD7809–TMS32020 Interface

REV. A

–23–

AD7804/AD7805/AD7808/AD7809

APPLICATIONS

AD7808

CLKIN

SDIN

Opto-Isolated Interface for Process Control Applications

The AD7804/AD7808 has a versatile serial three-wire serial

interface making it ideal for generating accurate voltages in

process control and industrial applications. Due to noise, safety

requirements, or distance, it may be necessary to isolate the

AD7804/AD7808 from the controller. This can easily be

achieved by using opto-isolators which will provide isolation in

excess of 3 kV. The serial loading structure of the AD7804/

AD7808 makes it ideally suited for use in opto-isolated appli-

cations. Figure 41 shows an opto-isolated interface to the

AD7804/AD7808 where SDIN, CLKIN and FSIN are driven

from optocouplers. LDAC is hardwired low to reduce the number

of interface lines and this ensures that each DAC is updated follow-

ing the sixteenth serial clock of a write cycle.

FSIN

SDIN

V

CLKIN

DD

LDAC

CC

1Y0

1Y1

1Y2

AD7808

1G

1A

1B

ENABLE

FSIN

SDIN

CODED

ADDRESS

CLKIN

1Y3

74HC139

DGND

AD7808

FSIN

SDIN

CLKIN

+5V

REGULATOR

0.1␮F

10␮F

POWER

AD7808

V

DD

FSIN

AV

DV

DD

10k⍀

SDIN

CLKIN

REFOUT

CLKIN

FSIN

CLKIN

FSIN

LDAC

1 TO 10nF

REFIN

AD7804/

AD7808

DD

10k⍀

V

A

B

OUT

Figure 42. Decoding Multiple AD7808s Using the FSIN Pin

AD7805 As a Digitally Programmable Window Detector

A digitally programmable upper/lower limit detector using two

DACs in the AD7805 is shown in Figure 43. The upper and

lower limits for the test are loaded to DACs A and B that in

turn set the limits on the CMP04. If a signal at the V_INinput is

not within the programmed window an LED will indicate the

fail condition. Only one limit detector is shown below but can

easily be adapted for a dual channel system by using the extra

DACs on the AD7805 and the two unused comparators on the

CMP04.

OUT

V

DD

10k⍀

V

C

D

OUT

SDIN

DATA

CLR

V

1

DD

LDAC

DGND

AGND

Figure 41. AD7804/AD7808 Opto-Isolated Interface

+5V

10␮F

0.1␮F

Decoding Multiple AD7808s

1k⍀

PASS

FAIL

The FSIN pin on the AD7808s can be used in applications to

decode a number of DACs. In this application all DACs in the

system receive the same serial clock and serial data, but only the

FSIN to one of the DACs will be active at any one time allowing

access to eight channels in this thirty-two channel system. The

74HC139 is used as a 2- to 4-line decoder to address any of the

DACs in the system. To prevent timing errors from occurring

the enable input should be brought to its inactive state while the

coded address inputs are changing state. Figure 42 shows a

system decoding multiple AD7808s in a multichannel system.

V

IN

0.01␮F

1/2

CMP04

AV

DV

DD

COMP

V

A

B

OUT

PASS/

FAIL

AD7805

D9

D0

V

MODE

1/6

74HC05

V

C

D

OUT

CS

WR

OUT

DV

DD

CLR

LDAC

DGND

AGND

Figure 43. Digitally Programmable Window Detector

–24–

REV. A

AD7804/AD7805/AD7808/AD7809

Low Cost, Two-Channel Mixer Using AD7805, SSM2164 and

OP275

Dual External Reference Input Capability

It is possible to operate the AD7804/AD7805/AD7808/AD7809

with two externally applied references. Figure 45 shows the

connections for the AD7804. Reference one, the AD589, is

connected to the REFIN pin of the part; the second reference,

the AD780, is used to overdrive the internal VDD/2 reference

which is provided at the COMP pin of the device. With the

circuit shown in Figure 45 it is possible to configure two of the

channels for operation with the AD780 2.5 V reference and the

other two with the AD589 1.23 V reference. The channel con-

trol register allows the user to select the reference for the indi-

vidual channels.

The SSM2164 is a quad voltage controlled amplifier (VCA)

with 120 dB of gain control range. Each VCA in the package is

a current in, current out device with a –33 mV/dB voltage con-

trol input port. Figure 44 shows a basic application circuit

which can be used to implement a low cost stereo, two channel

mixer. A 30 kΩ resistor converts the input voltage to an input

current for the VCA. The 500 Ω resistor and 560 pF capacitor

on the input are added to ensure stable operation of the

SSM2164. The I_OUTpin of the SSM2164 should be maintained

at virtual ground and thus the OP275 is operated in its inverting

mode. Its wide bandwidth, high slew rate and low power make it

ideal for a current to voltage converter. A 30 kΩ feedback resis-

tor is chosen to match the input resistor and thus give unity gain

for a zero volt control voltage input. The 100 pF capacitors

reduce high frequency noise and can be increased to reduce the

low pass cutoff frequency for further noise reduction. The

AD7805 in the circuit is used to control the attenuation of the

VCA, this application circuit only gives attenuation. The voltage

output from the AD7805 provides a low impedance drive to the

SSM2164 so attenuation can be controlled accurately. With a

5 V V_DDand a V_BIASof V_DD/2 the AD7805 has an LSB size of

approximately 4.5 mV. Therefore, the attenuation can be con-

trolled with a resolution of 0.136 dB/bit and thus 750 codes are

required to provide the full 100 dB of attenuation.

+5V

0.1␮F

10␮F

0.1␮F

6.8k⍀

V

AV

DV

DD

IN

DD

V

O

COMP

REFIN

AD780

GND

0.01␮F

AD589

AD7804

REFOUT

FSIN

SERIAL

SDIN

V

A

INTERFACE

OUT

CLKIN

B

C

D

DV

DD

CLR

LDAC

DGND AGND

Figure 45. Two Externally Applied References

+5V

V

1

V

2

IN

10␮F

0.1␮F

30k⍀

100pF

+15V

500⍀

30k⍀

0.01␮F

AV

DV

DD

560pF

+15V

+V

COMP

1/2

OP275

IN

1

AD7805

V 1

C

V

A

OUT

V

A

B

OUT

IN

2

D9

D0

–15V

100pF

V 2

C

V

OUT

IN

3

MODE

CS

V 3

C

30k⍀

+15V

V

C

OUT

WR

IN

4

1/2

OP275

DV

DD

CLR

V 4

C

V

D

OUT

LDAC

SSM2164

V

B

OUT

DGND AGND

–V

500⍀

–15V

560pF

–15V

30k⍀

V

3 V 4

IN

Figure 44. Low Cost, Two-Channel Mixer

REV. A

–25–

AD7804/AD7805/AD7808/AD7809

PAGE INDEX

(AD7804/AD7808 SERIAL INTERFACE PART)

Topic

(AD7805/AD7809 PARALLEL INTERFACE PART)

Topic

Page No.

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3

Timing Information

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3

Timing Information

Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Terminology

Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Terminology

Relative Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bias Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Zero-Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Digital-to-Analog Glitch Impulse . . . . . . . . . . . . . . . . . . . . 9

Digital Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Digital Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Analog Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . 9

Interface Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Channel Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 11

SUB DAC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power-Up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clear Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power-Down and Standby Functions . . . . . . . . . . . . . . . . . 16

LDAC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Transfer Functions

Pictorial View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Twos Complement (Main DAC) . . . . . . . . . . . . . . . . . . . 16

Twos Complement (Sub DAC) . . . . . . . . . . . . . . . . . . . . 17

Complete Channel Transfer Function . . . . . . . . . . . . . . . 17

Offset Binary (Main DAC) . . . . . . . . . . . . . . . . . . . . . . . . 18

Offset Binary (Sub DAC) . . . . . . . . . . . . . . . . . . . . . . . . . 19

Grounding and Layout Techniques . . . . . . . . . . . . . . . . . . . 20

Reference Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 21

Microprocessor Interfacing

Relative Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bias Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Zero-Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Digital-to-Analog Glitch Impulse . . . . . . . . . . . . . . . . . . . 9

Digital Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Digital Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Analog Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . . 9

Interface Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 14

Channel Control Register . . . . . . . . . . . . . . . . . . . . . . . . 14

Power-Up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Clear Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power-Down and Standby Functions . . . . . . . . . . . . . . . . 16

LDAC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Transfer Functions

Pictorial View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Twos Complement (Main DAC) . . . . . . . . . . . . . . . . . . 16

Twos Complement (Sub DAC) . . . . . . . . . . . . . . . . . . . 17

Complete Channel Transfer Function . . . . . . . . . . . . . . 17

Offset Binary (Main DAC) . . . . . . . . . . . . . . . . . . . . . . . 18

Offset Binary (Sub DAC) . . . . . . . . . . . . . . . . . . . . . . . . 19

Grounding and Layout Techniques . . . . . . . . . . . . . . . . . . 20

Reference Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Typical Performance Characteristics . . . . . . . . . . . . . . . . . 21

Microprocessor Interfacing

ADSP-2101/ADSP-2103 . . . . . . . . . . . . . . . . . . . . . . . . 23

TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8051/8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Applications

Programmable Window Detector . . . . . . . . . . . . . . . . . . 24

Low Cost Two-Channel Mixer . . . . . . . . . . . . . . . . . . . 25

Dual External Reference Input Capability . . . . . . . . . . . 25

Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 28

ADSP-2101/ADSP-2103 . . . . . . . . . . . . . . . . . . . . . . . . . 22

68HC11/68L11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

80C51/80L51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Applications

Opto-Isolated Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Decoding Multiple ICs . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 28

–26–

REV. A

AD7804/AD7805/AD7808/AD7809

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Plastic DIP (N-28)

Plastic DIP (N-16)

0.840 (21.33)

0.745 (18.93)

28

1

15

14

0.580 (14.73)

0.485 (12.32)

16

1

9

8

0.280 (7.11)

0.240 (6.10)

PIN 1

0.325 (8.25)

0.300 (7.62)

0.195 (4.95)

0.115 (2.93)

0.060 (1.52)

0.015 (0.38)

1.565 (39.70)

1.380 (35.10)

PIN 1

0.060 (1.52)

0.015 (0.38)

0.250

(6.35)

MAX

0.210 (5.33)

MAX

0.130

(3.30)

MIN

0.150

(3.81)

MIN

0.160 (4.06)

0.115 (2.93)

0.200 (5.05)

0.125 (3.18)

0.015 (0.381)

0.008 (0.204)

0.070 (1.77) SEATING

0.100

(2.54)

BSC

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.100

(2.54)

BSC

0.070 (1.77)

MAX

SEATING

PLANE

0.045 (1.15)

0.625 (15.87)

0.600 (15.24)

0.195 (4.95)

0.125 (3.18)

SOIC (R-16)

0.015 (0.381)

0.008 (0.204)

0.4133 (10.50)

0.3977 (10.00)

SOIC (R-28)

16

9

28

15

1

8

0.2992 (7.60)

0.2914 (7.40)

0.1043 (2.65)

0.0926 (2.35)

0.4193 (10.65)

0.3937 (10.00)

0.0291 (0.74)

PIN 1

x 45°

0.0118 (0.30)

0.0040 (0.10)

0.0098 (0.25)

14

1

0.0500 (1.27)

0.0157 (0.40)

8°

0°

0.1043 (2.65)

0.0500

(1.27)

BSC

0.7125 (18.10)

0.6969 (17.70)

0.0192 (0.49)

0.0926 (2.35)

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

0.0291 (0.74)

0.0098 (0.25)

0.0138 (0.35)

x 45°

0.0500 (1.27)

8°

0°

0.0157 (0.40)

0.0118 (0.30)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0500 (1.27)

BSC

0.0125 (0.32)

0.0091 (0.23)

SSOP (RS-28)

28

15

0.212 (5.38)

0.205 (5.207)

0.311 (7.9)

0.301 (7.64)

PIN 1

1

14

0.07 (1.78)

0.407 (10.34)

0.397 (10.08)

0.066 (1.67)

0.03 (0.762)

8°

0°

0.022 (0.558)

0.008 (0.203)

0.002 (0.050)

0.0256 (0.65)

BSC

0.015 (0.38)

0.010 (0.25)

0.009 (0.229)

0.005 (0.127)

1. LEAD NO. 1 IDENTIFIED BY A DOT.

2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

REV. A

–27–

AD7804/AD7805/AD7808/AD7809

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

TQFP (ST-44B)

Plastic DIP (N-24)

0.047 (1.20)

MAX

0.472 (12.00) SQ

13

24

0.030 (0.75)

0.018 (0.45)

0.280 (7.11)

0.240 (6.10)

PIN 1

33

23

12

1

34

22

SEATING

PLANE

1.275 (32.30)

1.125 (28.60)

0.325 (8.25)

0.300 (7.62)

0.015

(0.38)

MIN

0.210

(5.33)

MAX

0.195 (4.95)

0.115 (2.93)

0.394

(10.0)

SQ

TOP VIEW

(PINS DOWN)

0.130

(3.30)

MIN

0.160 (4.06)

0.115 (2.92)

0.015 (0.381)

0.008 (0.203)

0.022 (0.558)

0.014 (0.356)

0.070 (1.77)

0.045 (1.15)

0.100 (2.54)

BSC

SEATING

PLANE

44

12

1

11

0.006 (0.15)

0.002 (0.05)

0.018 (0.45)

0.012 (0.30)

0.031 (0.80)

BSC

0.04134 (1.05)

0.0374 (0.95)

SOIC (R-24)

0.614 (15.6)

0.598 (15.2)

24

13

0.299 (7.6) 0.419 (10.65)

0.291 (7.4) 0.394 (10.00)

1

12

PIN 1

0.104 (2.65)

0.093 (2.35)

0.03 (0.75)

0.01 (0.25)

8؇

0؇

0.012 (0.3) 0.0500 (1.27)

0.004 (0.1)

0.019 (0.49)

SEATING

PLANE

0.014 (0.35)

0.0500 (1.27)

0.0157 (0.40)

0.013 (0.32)

0.009 (0.25)

BSC

–28–

REV. A


型号：	AD7809BSTZ-REEL
厂家：	ADI
描述：	暂无描述
文件：	总28页 (文件大小：302K)
中文：	中文翻译
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AD7809BSTZ-REEL [ADI]

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