AD7839ASZ [ADI]
Octal 13-Bit, Parallel Input, Voltage-Output DAC; 八通道13位,并行输入,电压输出DAC型号: | AD7839ASZ |
厂家: | ADI |
描述: | Octal 13-Bit, Parallel Input, Voltage-Output DAC |
文件: | 总12页 (文件大小:157K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Octal 13-Bit, Parallel Input,
Voltage-Output DAC
a
AD7839
FEATURES
GENERAL DESCRIPTION
Eight 13-Bit DACs in One Package
Voltage Outputs
Offset Adjust for Each DAC Pair
Reference Range of ؎5 V
Maximum Output Voltage Range of ؎10 V
Clear Function to User-Defined Voltage
44-Lead MQFP Package
The AD7839 contains eight 13-bit DACs on one monolithic
chip. It has output voltages with a full-scale range of ±10 V
from reference voltages of ±5 V.
The AD7839 accepts 13-bit parallel loaded data from the exter-
nal bus into one of the input registers under the control of the
WR, CS and DAC channel address pins, A0–A2.
The DAC outputs are updated on reception of new data into
the DAC registers. All the outputs may be updated simulta-
neously by taking the LDAC input low.
APPLICATIONS
Automatic Test Equipment
Process Control
Each DAC output is buffered with a gain-of-two amplifier into
which an external DAC offset voltage can be inserted via the
DUTGNDx pins.
General Purpose Instrumentation
The AD7839 is available in a 44-lead MQFP package.
FUNCTIONAL BLOCK DIAGRAM
V
(+)
V
(–)
DUTGND
CD
DUTGND
AB
REF
REF
V
V
V
DD
CC
SS
AB
AB
AD7839
R
R
13
13
13
DAC
REG
A
INPUT
REG
A
DAC A
V
V
A
B
OUT
R
R
DB12
DB0
13
13
13
13
13
13
13
13
13
13
13
13
13
13
INPUT
REG
B
DAC 13
REG
B
DAC B
OUT
R
R
R
INPUT
REG
C
DAC 13
REG
C
DAC C
V
V
C
D
OUT
WR
CS
R
13
INPUT
REG
D
DAC
REG
D
DAC D
OUT
A0
A1
INPUT
REG
E
DAC 13
REG
E
DAC E
A2
V
V
E
F
LDAC
OUT
R
R
R
R
INPUT
REG
F
DAC 13
REG
F
DAC F
OUT
INPUT
REG
G
DAC 13
REG
G
DAC G
V
V
G
H
OUT
DAC
REG
H
INPUT
REG
H
13
R
R
R
R
DAC H
OUT
V
REF
(+) V
(–)
GH
V
(+) V
(–)
CDEF CDEF
GND
DUTGND DUTGND
EF GH
CLR
REF
REF
REF
GH
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(VCC = +5 V ؎ 5%; VDD = +15 V ؎ 5%; VSS = –15 V ؎ 5%; GND = DUTGND = 0 V;
1
R = 5 k⍀ and C = 50 pF to GND, T = TMIN to TMAX, unless otherwise noted.)
AD7839–SPECIFICATIONS
L
L
A
Parameter
A Version
Units
Test Conditions/Comments
ACCURACY
Resolution
13
Bits
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
±2
±0.9
±4
±4
±1
0.5
10
120
LSB max
LSB max
LSB max
LSB max
LSB typ
ppm FSR/°C typ
ppm FSR/°C max
µV max
Typically ±0.5 LSB
Guaranteed Monotonic Over Temperature
VREF(+) = +5 V, VREF(–) = –5 V. Typically within ±1 LSB
VREF(+) = +5 V, VREF(–) = –5 V. Typically within ±1 LSB
VREF(+) = +5 V, VREF(–) = –5 V
Gain Temperature Coefficient2
DC Crosstalk2
See Terminology. Typically 75 µV
Per Input. Typically ±0.03 µA
REFERENCE INPUTS2
DC Input Impedance
Input Current
100
±1
MΩ typ
µA max
V
REF(+) Range
0/+5
–5/0
+2/+10
V min/max
V min/max
V min/max
VREF(–) Range
[VREF(+) – VREF(–)]
For Specified Performance. Can Go as Low as 0 V, but
Performance Not Guaranteed
DUTGND INPUTS2
DC Input Impedance
Max Input Current
Input Range
60
±0.3
–2/+2
kΩ typ
mA typ
V min/max
Per Input
OUTPUT CHARACTERISTICS2
Output Voltage Swing
Short Circuit Current
Resistive Load
Capacitive Load
DC Output Impedance
±10
15
5
50
0.5
V min
2 × (VREF(–) + [VREF(+) – VREF(–)] × D) – VDUTGND
mA max
kΩ min
pF max
Ω max
To 0 V
To 0 V
DIGITAL INPUTS2
VINH, Input High Voltage
2.4
0.8
V min
V max
V
INL, Input Low Voltage
I
INH, Input Current
@ +25°C
TMIN to TMAX
Total for All Pins
1
±10
10
µA max
µA max
pF max
CIN, Input Capacitance
POWER REQUIREMENTS3
VCC
VDD
VSS
+4.75/+5.25
+14.25/+15.75 V min/max
–14.25/–15.75 V min/max
V min/max
For Specified Performance
For Specified Performance
For Specified Performance
Power Supply Sensitivity2
∆Full Scale/∆VDD
∆Full Scale/∆VSS
ICC
IDD
ISS
90
90
0.5
10
10
dB typ
dB typ
mA max
mA max
mA max
VINH = VCC, VINL = GND. Dynamic Current
Outputs Unloaded. Typically 8 mA
Outputs Unloaded. Typically 8 mA
NOTES
1Temperature range for A Version: –40°C to +85°C
2Guaranteed by characterization. Not production tested.
3The AD7839 is functional with power supplies of ±12 V ± 10% with reduced output range. At 12 V it is recommended to restrict reference range to ±4 V due to
output amplifier headroom limitations
Specifications subject to change without notice.
–2–
REV. 0
AD7839
(These characteristics are included for Design Guidance and are not subject
to production testing.)
AC PERFORMANCE CHARACTERISTICS
Parameter
A
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
30
40
0.7
µs typ
Full-Scale Change to ±1/2 LSB. DAC Latch Contents Alternately
Loaded with All 0s and All 1s
µs max
V/µs typ
nV-s typ
Slew Rate
Digital-to-Analog Glitch Impulse 230
Measured with VREF(+) = +5 V, VREF(–) = –5 V. DAC Latch
Alternately Loaded with 0FFF Hex and 1000 Hex. Not Dependent
on Load Conditions
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
99
40
0.2
dB typ
nV-s typ
nV-s typ
See Terminology
See Terminology
Feedthrough to DAC Output Under Test Due to Change in Digital
Input Code to Another Converter
Digital Feedthrough
Output Noise Spectral Density
@ 1 kHz
0.1
nV-s typ
Effect of Input Bus Activity on DAC Output Under Test
200
nV/√Hz typ
All 1s Loaded to DAC. VREF(+) = VREF(–) = 0 V
Specifications subject to change without notice.
TIMING SPECIFICATIONS1, 2
(VCC = +5 V ؎ 5%; VDD = +15 V ؎ 5%; VSS = –15 V ؎ 5%; GND = DUTGND = 0 V)
Parameter
Limit at TMIN, TMAX
Units
Description
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
15
0
50
50
0
0
20
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs typ
Address to WR Setup Time
Address to WR Hold Time
CS Pulsewidth Low
WR Pulsewidth Low
CS to WR Setup Time
WR to CS Hold Time
Data Setup Time
Data Hold Time
Settling Time
CLR Pulse Activation Time
LDAC Pulsewidth Low
30
300
50
ns max
ns min
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.
t1
t2
A0, A1, A2
t6
t5
t3
t4
CS
WR
t8
t7
DATA
t9
V
OUT
t10
CLR
V
OUT
t11
LDAC
Figure 1. Timing Diagram
REV. 0
–3–
AD7839
ABSOLUTE MAXIMUM RATINGS1, 2
Lead Temperature, Soldering
(TA = +25°C unless otherwise noted)
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000 V
VCC to GND3 . . . . . . . . . . . . . . .–0.3 V, +7 V or VDD + 0.3 V
(Whichever Is Lower)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V
Digital Inputs to GND . . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V
VREF(+) to VREF(–) . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V
VREF(+) to GND . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
3VCC must not exceed VDD by more than 0.3 V. If it is possible for this to happen
during power supply sequencing, the following diode protection scheme will ensure
protection.
V
REF(–) to GND . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
DUTGND to GND . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
VOUT (A–H) to GND . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
Operating Temperature Range
V
DD
V
CC
IN4148
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . .+150°C
MQFP Package
HP5082-2811
V
DD
V
CC
AD7839
Power Dissipation . . . . . . . . . . . . . . . . . . (TJ max – TA)/θJA
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W
ORDERING GUIDE
Linearity
Error
(LSBs)
Temperature
Range
DNL
(LSBs)
Package
Option*
Model
AD7839AS
–40°C to +85°C
±2
±1
S-44
*S = Plastic Quad Flatpack (MQFP).
PIN CONFIGURATION
44 43 42 41 40 39 38 37 36 35 34
1
33
DUTGND_AB
DUTGND_GH
PIN 1
IDENTIFIER
32
31
30
29
28
27
26
25
24
23
2
3
V
A
V
V
V
V
H
OUT
OUT
V
V
(–)AB
(+)AB
(–)GH
(+)GH
REF
REF
REF
SS
4
5
REF
V
DD
AD7839
TOP VIEW
(Not to Scale)
6
7
CLR
V
SS
LDAC
A2
DB12
DB11
DB10
DB9
8
9
A1
A0 10
11
CS
DB8
12 13 14 15 16 17 18 19 20 21 22
–4–
REV. 0
AD7839
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Description
1
DUTGND_AB
Device Sense Ground for DACs A and B. VOUTA and VOUTB are referenced to the voltage
applied to this pin.
2, 44, 43,
41, 37, 35,
34, 32
V
OUTA . . VOUT
H
DAC Outputs.
4, 3
5
VREF(+)AB, VREF(–)AB
VDD
Reference Inputs for DACs A and B. These reference voltages are referred to GND.
Positive Analog Power Supply; +15 V ± 5%.
6
VSS
Negative Analog Power Supply; –15 V ± 5%.
7
LDAC
Load DAC Logic Input (active low). When this logic input is taken low the contents of the
input registers are transferred to their respective DAC registers. LDAC can be tied perma-
nently low enabling the outputs to be updated on the rising edge of WR.
10, 9, 8
A0, A1, A2
Address inputs. A0, A1 and A2 are decoded to select one of the eight input registers for a
data transfer.
11
12
CS
Level-Triggered Chip Select Input (active low). The device is selected when this input is low.
Level-Triggered Write Input (active low), used in conjunction with CS to write data to the
WR
AD7839 input registers. Data is latched into the selected input register on the rising edge of
WR.
13
VCC
Logic Power Supply; +5 V ± 5%.
14
GND
Ground.
15–27
DB0 . . DB12
Parallel Data Inputs. The AD7839 can accept a straight 13-bit parallel word on DB0 to DB12
where DB12 is the MSB and DB0 is the LSB.
28
CLR
Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog
outputs are switched to the externally set potential on the relevant DUTGND pin. The con-
tents of input registers and DAC registers A to H are not affected when the CLR pin is taken
low. When CLR is brought back high, the DAC outputs revert to their original outputs as
determined by the data in their DAC registers.
30, 31
33
VREF(+)GH, VREF(–)GH Reference Inputs for DACs G and H. These reference voltages are referred to GND.
DUTGND_GH
Device Sense Ground for DACs G and H. VOUTG and VOUTH are referenced to the voltage
applied to this pin.
36
DUTGND_EF
Device Sense Ground for DACs E and F. VOUTE and VOUTF are referenced to the voltage
applied to this pin.
39
40
42
V
V
REF(+)CDEF
REF(–)CDEF
Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND.
DUTGND_CD
Device Sense Ground for DACs C and D. VOUTC and VOUTD are referenced to the voltage
applied to this pin.
REV. 0
–5–
AD7839
TERMINOLOGY
Full-Scale Error
Relative Accuracy
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s loaded
into the DAC latch, should be 2 VREF(+) – 1 LSB.
Relative accuracy or endpoint linearity is a measure of the max-
imum deviation from a straight line passing through the end-
points of the DAC transfer function. It is measured after adjust-
ing for zero error and full-scale error and is normally expressed
in Least Significant Bits.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC latch. Ideally the output voltage,
with all 0s in the DAC latch should be equal to 2 VREF(–). Zero-
scale error is mainly due to offsets in the output amplifier.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Gain Error
Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error).
DC Crosstalk
GENERAL DESCRIPTION
Although the common input reference voltage signals are inter-
nally buffered, small IR drops in the individual DAC reference
inputs across the die can mean that an update to one channel
can produce a dc output change in one or another of the chan-
nel outputs.
DAC Architecture—General
Each channel consists of a straight 13-bit R-2R voltage-mode
DAC. The full-scale output voltage range is equal to twice the
reference span of VREF(+) – VREF(–). The DAC coding is straight
binary; all 0s produces an output of 2 VREF(–); all 1s produces
an output of 2 VREF(+) – 1 LSB.
The eight DAC outputs are buffered by op amps that share
common VDD and VSS power supplies. If the dc load current
changes in one channel (due to an update), this can result in a
further dc change in one or another of the channel outputs. This
effect is most obvious at high load currents and reduces as the
load currents are reduced. With high impedance loads the effect
is virtually unmeasurable.
The analog output voltage of each DAC channel reflects the
contents of its own DAC register. Data is transferred from the
external bus to the input register of each DAC on a per channel
basis.
Bringing the CLR line low switches all the signal outputs, VOUTA
to VOUTH, to the voltage level on the DUTGND pin. When the
CLR signal is brought back high, the output voltages from the
DACs will reflect the data stored in the relevant DAC registers.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Data Loading to the AD7839
Digital-to-Analog Glitch Impulse
Data is loaded into the AD7839 in straight parallel 13-bit wide
words.
This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV-secs. It is measured with VREF(+) = +5 V and
The DAC output voltages, VOUTA – VOUTH are updated to
reflect new data in the DAC registers.
V
REF(–) = –5 V and the digital inputs toggled between 0FFFH and
The actual input register being written to is determined by the
logic levels present on the device’s address lines, as shown in
Table I.
1000H.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input that appears at the out-
put of another DAC. It is expressed in dBs.
Table I. Address Line Truth Table
A2
A1
A0
DAC Selected
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is defined as the glitch impulse that
appears at the output of one converter due to both the digital
change and subsequent analog O/P change at another converter.
It is specified in nV-secs.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
INPUT REG A (DAC A)
INPUT REG B (DAC B)
INPUT REG C (DAC C)
INPUT REG D (DAC D)
INPUT REG E (DAC E)
INPUT REG F (DAC F)
INPUT REG G (DAC G)
INPUT REG H (DAC H)
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the digital crosstalk and is specified in nV-secs.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the VOUT
pins. This noise is digital feedthrough.
DC Output Impedance
This is the effective output source resistance. It is dominated by
package lead resistance.
–6–
REV. 0
Typical Performance Characteristics–AD7839
2.0
1.0
0.75
0.50
0.25
0.50
0.25
V
V
V
V
= +15V
= –15V
DD
SS
V
V
V
V
= +15V
= –15V
DD
SS
1.5
1.0
= +5V
= –5V
REF(+)
REF(–)
= +5V
= –5V
REF(+)
REF(–)
MAX INL
MIN INL
60
T
= +25؇C
A
0.5
0.0
0.0
0.0
–0.5
–0.25
V
V
V
V
= +15V
= –15V
DD
SS
–0.25
–0.50
–0.50
–1.0
–1.5
–2.0
= +5V
= –5V
REF(+)
REF(–)
–0.75
–1.0
T
= +25؇C
A
0
–40 –20
0
20
40
80
100
2048
4096
CODE
6144
8191
0
2048
4096
CODE
6144
8192
TEMPERATURE – ؇C
Figure 2. Typical INL Plot
Figure 3. Typical DNL Plot
Figure 4. Typical INL Error vs.
Temperature
2.0
1.5
1.0
0.5
6
1.0
0.75
0.50
0.25
0
V
V
V
V
= +15V
= –15V
DD
SS
V
V
V
V
= +15V
= –15V
DD
SS
V
V
V
= +5V
= +15V
= –15V
CC
DD
SS
5
4
3
2
1
= +5V
= –5V
REF(+)
REF(–)
= +5V
= –5V
REF(+)
REF(–)
FULL-SCALE ERROR
MAX DNL
DIGITAL INPUTS @
THRESHOLDS
0
–0.5
–1.0
–1.5
–2.0
–0.25
–0.50
MIN DNL
ZERO-SCALE ERROR
DIGITAL INPUTS @ SUPPLIES
0
–0.75
–1.0
–1
–40 –20
0
20
40
60
80
100
–40 –20
0
20
40
60
80
100
–40 –20
0
20
40
60
80
100
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TEMPERATURE – ؇C
Figure 5. Typical DNL Error vs.
Temperature
Figure 7. ICC vs. Temperature
Figure 6. Zero-Scale and Full-Scale
Error vs. Temperature
0.6
10
8
V
V
V
= +15V
= –15V
= +5V
DD
SS
CC
0.5
0.4
0.3
0.2
0.1
0
10.19
10.18
10.17
10.16
I
DD
I
SS
6
؊0.1
؊0.2
4
–40 –20
0
20
40
60
80
100
27
28
29
30
31
32
33
0
50 150 200 250 300 350 400 450 500 550
TEMPERATURE – °C
SETTLING TIME – s
Figure 8. Typical Digital-to-Analog
Glitch Impulse
Figure 9. Settling Time (+)
Figure 10. IDD, ISS vs. Temperature
REV. 0
–7–
AD7839
Unipolar Configuration
When bipolar-zero and full-scale adjustment are not needed, R2
and R3 can be omitted. Pin 12 on the AD588 should be con-
nected to Pin 11 and Pin 5 should be left floating.
Figure 11 shows the AD7839 in the unipolar binary circuit
configuration. The VREF(+) input of the DAC is driven by the
AD586, a +5 V reference. VREF(–) is tied to ground. Table II
gives the code table for unipolar operation of the AD7839.
Other suitable references include the REF02, a precision +5 V
reference, and the REF195, a low dropout, micropower preci-
sion +5 V reference.
+15V
+5V
R1
39k⍀
4
6
2
3
1
V
V
DD
CC
V
7
9
+15V
+5V
V
C1
1F
OUT
OUT
(–10V TO +10V)
V
V
(+)
REF
AD588
AD7839*
14
15
16
5
10
11
2
AD586
4
R2
100k⍀
V
V
DD
(+)
CC
V
DUTGND
6
5
V
(–)
REF
V
V
OUT
OUT
REF
8
(0 TO +10V)
GND
SS
V
AD7839*
R1
10k⍀
12 8 13
C1
1F
R3
100k⍀
SIGNAL
GND
DUTGND
(–)
–15V
REF
GND
V
SS
*ADDITIONAL PINS OMITTED FOR CLARITY
SIGNAL
GND
SIGNAL
GND
Figure 12. Bipolar ±10 V Operation
Table III. Code Table for Bipolar Operation
–15V
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. Unipolar +10 V Operation
Binary Number in DAC
Register
MSB
Offset and gain may be adjusted in Figure 11 as follows: To
adjust offset, disconnect the VREF(–) input from 0 V, load the
DAC with all 0s and adjust the VREF(–) voltage until VOUT = 0 V.
For gain adjustment, the AD7839 should be loaded with all 1s
and R1 adjusted until VOUT = 2 VREF(+) – 1 LSB = 10 V(8191/
8192) = 9.99878 V.
Analog Output
LSB (VOUT)
1
1
1
0
0
0
1111 1111 1111
0000 0000 0001
0000 0000 0000
1111 1111 1111
0000 0000 0001
0000 0000 0000
2[VREF(–) + VREF (8191/8192)] V
2[VREF(–) + VREF (4097/8192)] V
2[VREF(–) + VREF (4096/8192)] V
2[VREF(–) + VREF (4095/8192)] V
2[VREF(–) + VREF (1/8192)] V
2[VREF(–)] V
Many circuits will not require these offset and gain adjustments.
In these circuits R1 can be omitted. Pin 5 of the AD586 may be
left open circuit and Pin 2 (VREF(–)) of the AD7839 tied to 0 V.
NOTES
VREF = (VREF(+) – VREF(–)).
Table II. Code Table for Unipolar Operation
For VREF(+) = +5 V, and VREF(–) = –5 V, VREF = 10 V, 1 LSB = 2 VREF V/213
=
20 V/8192 = 2.44 mV.
Binary Number in DAC Register
Analog Output
(VOUT
MSB
LSB
)
CONTROLLED POWER-ON OF THE OUTPUT STAGE
1
1
0
0
0
1111
0000
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
1111
0001
0000
2 VREF (8191/8192) V
2 VREF (4096/8192) V
2 VREF (4095/8192) V
2 VREF (1/8192) V
0 V
A block diagram of the output stage of the AD7839 is shown in
Figure 13. It is capable of driving a load of 5 kΩ in parallel with
50 pF. G1 to G6 are transmission gates used to control the
power on voltage present at VOUT. On power up G1 and G2 are
also used in conjunction with the CLR input to set VOUT to the
user defined voltage present at the DUTGND pin. When CLR
is taken back high, the DAC outputs reflect the data in the DAC
registers.
NOTES
VREF = VREF(+); VREF(–) = 0 V for unipolar operation.
For VREF(+) = +5 V, 1 LSB = +10 V/213 = +10 V/8192 = 1.22 mV.
Bipolar Configuration
G
1
Figure 12 shows the AD7839 set up for ±10 V operation. The
AD588 provides precision ±5 V tracking outputs that are fed to
the VREF(+) and VREF(–) inputs of the AD7839. The code table
for bipolar operation of the AD7839 is shown in Table III.
G
6
DAC
V
OUT
G
3
G
G
4
2
In Figure 12, full-scale and bipolar zero adjustments are pro-
vided by varying the gain and balance on the AD588. R2 varies
the gain on the AD588 while R3 adjusts the offset of both the
+5 V and –5 V outputs together with respect to ground.
R = 60k⍀
R
G
5
14k⍀
For bipolar-zero adjustment, the DAC is loaded with
1000 . . . 0000 and R3 is adjusted until VOUT = 0 V. Full
scale is adjusted by loading the DAC with all 1s and adjusting
R2 until VOUT = 10(4095/4096) V = 9.997559 V.
DUTGND
Figure 13. Block Diagram of AD7839 Output Stage
–8–
REV. 0
AD7839
G
1
Power-On with CLR Low
G
6
DAC
The output stage of the AD7839 has been designed to allow
output stability during power-on. If CLR is kept low during
power-on, then just after power is applied to the AD7839, the
situation is as depicted in Figure 14. G1, G4 and G6 are open
while G2, G3 and G5 are closed.
V
OUT
G
G
3
5
G
G
4
2
R
R
G
1
14k⍀
G
6
DAC
V
OUT
G
G
3
5
DUTGND
Figure 16. Output Stage After CLR Is Taken High
G
G
4
2
R
Power-On with CLR High
If CLR is high on the application of power to the device, the
output stages of the AD7839 are configured as in Figure 17
while VDD is less than 7 V and VSS is more positive than –3 V.
G1 is closed and G2 is open, thereby connecting the output of the
DAC to the input of its output amplifier. G3 and G5 are closed
while G4 and G6 are open, thus connecting the output amplifier as
a unity gain buffer. VOUT is connected to DUTGND via G5
through a 14 kΩ resistor until VDD exceeds 7 V and VSS is more
negative than –3 V.
R
14k⍀
DUTGND
Figure 14. Output Stage with VDD < 7 V or VSS > –3 V;
CLR Low
VOUT is kept within a few hundred millivolts of DUTGND via
G5 and a 14 kΩ resistor. This thin-film resistor is connected in
parallel with the gain resistors of the output amplifier. The
output amplifier is connected as a unity gain buffer via G3, and
the DUTGND voltage is applied to the buffer input via G2. The
amplifier’s output is thus at the same voltage as the DUTGND
pin. The output stage remains configured as in Figure 14 until
the voltage at VDD exceeds 7 V and VSS is more negative than
–3 V. By now the output amplifier has enough headroom to
handle signals at its input and has also had time to settle. The
internal power-on circuitry opens G3 and G5 and closes G4 and
G6. This situation is shown in Figure 15. Now the output ampli-
fier is configured in its noise gain configuration via G4 and G6.
The DUTGND voltage is still connected to the noninverting
G
1
G
6
DAC
V
OUT
G
G
3
5
G
G
4
2
R
R
14k⍀
DUTGND
Figure 17. Output Stage Powering Up with CLR High
While VDD < 7 V or VSS > –3 V
input via G2 and this voltage appears at VOUT
.
G
1
When the difference between the supply voltages reaches +10 V,
the internal power-on circuitry opens G3 and G5 and closes G4
and G6 configuring the output stage as shown in Figure 18.
G
6
DAC
V
OUT
G
G
3
5
G
1
G
G
4
2
G
6
R
DAC
V
OUT
R
G
G
3
5
14k⍀
G
G
4
2
R
DUTGND
Figure 15. Output Stage with VDD > 7 V and VSS < –3 V;
R
14k⍀
CLR Low
VOUT has been disconnected from the DUTGND pin by the
opening of G5, but will track the voltage present at DUTGND
via the configuration shown in Figure 15.
DUTGND
Figure 18. Output Stage Powering Up with CLR High;
VDD > 7 V and VSS < –3 V
When CLR is taken back high, the output stage is configured as
shown in Figure 16. The internal control logic closes G1 and
opens G2. The output amplifier is connected in a noninverting
gain-of-two configuration. The voltage that appears on the VOUT
pins is determined by the data present in the DAC registers.
REV. 0
–9–
AD7839
DUTGND Voltage Range
APPLICATIONS
During power-on, the VOUT pins of the AD7839 are connected
to the relevant DUTGND pins via G5 and the 14 kΩ thin-film
resistor. The DUTGND potential must obey the max ratings at
all times. Thus, the voltage at DUTGND must always be within
the range VSS – 0.3 V, VDD + 0.3 V. However, in order that the
voltages at the VOUT pins of the AD7839 stay within ±2 V of the
relevant DUTGND potential during power-on, the voltage
applied to DUTGND should also be kept within the range
GND – 2 V, GND + 2 V.
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD7839 is mounted should be designed such that the analog
and digital sections are separated and confined to certain areas
of the board. This facilitates the use of ground planes that can
be easily separated. A minimum etch technique is generally best
for ground planes as it gives the best shielding. Digital and ana-
log ground planes should be joined at only one place. The GND
pin of the AD7839 should be connected to the AGND of the
system. If the AD7839 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only, a star ground point that should be
established as close as possible to the AD7839.
Once the AD7839 has powered on and the on-chip amplifiers
have settled, any voltage that is now applied to the DUTGND
pin is subtracted from the DAC output, which has been gained
up by a factor of two. Thus, for specified operation, the maxi-
mum voltage that can be applied to the DUTGND pin in-
creases to the maximum allowable 2 VREF(+) voltage, and the
minimum voltage that can be applied to DUTGND is the
minimum 2 VREF(–) voltage. After the AD7839 has fully
powered on, the outputs can track any DUTGND voltage within
this minimum/maximum range.
Digital lines running under the device should be avoided as
these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7839 to avoid noise
coupling. The power supply lines of the AD7839 should use as
large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line. Fast
switching signals like clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board and
should never be run near the analog inputs.
Power Supply Sequencing
When operating the AD7839, it is important that ground be
connected at all times to avoid high current states. The recom-
mended power-up sequence is VDD/VSS followed by VCC. If VCC
can exceed VDD on power-up, the diode scheme shown in the
absolute max ratings will ensure protection. The reference in-
puts and digital inputs should be powered up last. Should the
references exceed VDD/VSS on power-up, current limiting resis-
tors should be inserted in series with the reference inputs to
limit the current to 20 mA. Logic inputs should not be applied
before VCC. Current limiting resistors (470 Ω), in series with the
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best but not always possible with a
double sided board. In this technique, the component side of
the board is dedicated to ground plane while signal traces are
placed on the solder side.
logic inputs, should be inserted if these inputs come up before VCC
.
The AD7839 should have ample supply bypassing located as
close to the package as possible, ideally right up against the
device. Figure 20 shows the recommended capacitor values of
10 µF in parallel with 0.1 µF on each of the supplies. The 10 µF
capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low Effective Series Resistance (ESR) and Effective
Series Inductance (ESI), such as the common ceramic types,
which provide a low impedance path to ground at high frequen-
cies to handle transient currents due to internal logic switching.
MICROPROCESSOR INTERFACING
Interfacing the AD7839—16-Bit Interface
The AD7839 can be interfaced to a variety of 16-bit micro-
controllers or DSP processors. Figure 19 shows the AD7839
interfaced to a generic 16-bit microcontroller/DSP processor.
The lower address lines from the processor are connected to A0,
A1 and A2 on the AD7839 as shown. The upper address lines
are decoded to provide a chip select signal or an LDAC signal
for the AD7839. The fast interface timing of the AD7839 allows
direct interface to a wide variety of microcontrollers and DSPs
as shown in Figure 19.
V
V
DD
CC
0.1F
10F
10F
0.1F
AD7839
CONTROLLER/
AD7839
DSP PROCESSOR*
V
SS
10F
D12
0.1F
D12
DATA
BUS
D0
D0
Figure 20. Recommended Decoupling Scheme for AD7839
CS
UPPER BITS OF
ADDRESS BUS
ADDRESS
DECODE
LDAC
A2
A1
A2
A1
A0
WR
A0
R/W
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. AD7839 Parallel Interface
–10–
REV. 0
AD7839
Automated Test Equipment
Programmable Reference Generation for the AD7839 in an
ATE Application
The AD7839 is particularly suited for use in an automated test
environment. Figure 21 shows the AD7839 providing the neces-
sary voltages for the pin driver and the window comparator in a
typical ATE pin electronics configuration. AD588s are used to
provide reference voltages for the AD7839. In the configuration
shown, the AD588s are configured so that the voltage at Pin 1 is
5 V greater than the voltage at Pin 9 and the voltage at Pin 15 is
5 V less than the voltage at Pin 9.
The AD7839 is particularly suited for use in an automated test
environment. The reference input for the AD7839 octal 13-bit
DAC requires three differential references for the eight DACs.
Programmable references may be a requirement in some ATE
applications as the offset and gain errors at the output of a DAC
can be adjusted by varying the voltages on the reference pins of
the DAC. To trim offset errors, the DAC is loaded with the
digital code 000 . . . 000 and the voltage on the VREF(–) pin is
adjusted until the desired negative output voltage is obtained.
To trim out gain errors, first the offset error is trimmed. Then
the DAC is loaded with the code 111 . . . 111 and the voltage
on the VREF(+) pin is adjusted until the desired full-scale voltage
minus one LSB is obtained.
V
+15V –15V
OFFSET
16
2
4
6
8
3
1
+15V
V
V
(+)AB
(–)AB
REF
15
14
9
V
V
A
B
OUT
PIN
DRIVER
AD588
REF
13
10
11
12
OUT
It is not uncommon in ATE design, to have other circuitry at
the output of the AD7839 that can have offset and gain errors of
up to say ±300 mV. These offset and gain errors can be easily
removed by adjusting the reference voltages of the AD7839.
The AD7839 uses nominal reference values of ±5 V to achieve
an output span of ±10 V. Since the AD7839 has a gain of two
from the reference inputs to the DAC output, adjusting the
reference voltages by ±150 mV will adjust the DAC offset and
gain by ±300 mV.
DUTGND AB
0.1F
–15V
7
AD7839*
1F
DUTGND GH
DEVICE
GND
V
+15V –15V
OUT
2
16
V
G
H
4
6
8
3
1
OUT
DEVICE
GND
V
(+)GH
(–)GH
REF
V
15
14
OUT
V
REF
AD588
13
10
11
12
There are a number of suitable 8- and 10-bit DACs available
that would be suitable to drive the reference inputs of the
AD7839, such as the AD7804, a quad 10-bit digital-to-analog
converter with serial load capabilities. The voltage output from
this DAC is in the form of VBIAS ± VSWING and rail-to-rail opera-
tion is achievable. The voltage reference for this DAC can be
internally generated or provided externally. This DAC also
contains an 8-bit SUB DAC which can be used to shift the
complete transfer function of each DAC around the VBIAS point.
This can be used as a fine trim on the output voltage. In this
application two AD7804s are required to provide programmable
reference capability for all eight DACs. One AD7804 is used to
drive the VREF(+) pins and the second package used to drive the
9
GND
DEVICE
GND
WINDOW
COMPARATOR
7
1F
TO TESTER
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. ATE Application
One of the AD588s is used as a reference for DACs A and B.
These DACs are used to provide high and low levels for the pin
driver. The pin driver may have an associated offset. This can
be nulled by applying an offset voltage to Pin 9 of the AD588.
First, the code 1000 . . . 0000 is loaded into the DACA latch
and the pin driver output is set to the DACA output. The
VOFFSET voltage is adjusted until 0 V appears between the pin
driver output and DUT GND. This causes both VREF(+) and
VREF(–) pins.
Another suitable DAC for providing programmable reference
capability is the AD8803. This is an octal 8-bit trimDAC® and
provides independent control of both the top and bottom ends
of the trimDAC. This is helpful in maximizing the resolution of
devices with a limited allowable voltage control range.
V
REF(–) to be offset with respect to GND by an amount equal to
VOFFSET. However, the output of the pin driver will vary from
–10 V to +10 V with respect to DUTGND as the DAC input
code varies from 000 . . . 000 to 111 . . . 111. The VOFFSET
voltage is also applied to the DUTGND pins. When a clear is
performed on the AD7839, the output of the pin driver will be
0 V with respect to DUTGND.
The AD8803 has an output voltage range of GND to VDD (0 V
to +5 V). To trim the VREF(+) input, the appropriate trim range
on the AD8803 DAC can be set using the VREFL and VREFH pins
allowing 8 bits of resolution between the two points. This will
allow the VREF(+) pin to be adjusted to remove gain errors.
The other AD588 is used to provide a reference voltage for
DACs G and H. These provide the reference voltages for the
window comparator shown in the diagram. Note that Pin 9 of
this AD588 is connected to Device GND. This causes VREF(+)GH
and VREF(–)GH to be referenced to Device GND. As DAC G
and DAC H input codes vary from 000 . . . 000 to 111 . . . 111,
To trim the VREF(–) voltage, some method of providing a trim
voltage in the required negative voltage range is required. Nei-
ther the AD7804 or the AD8803 can provide this range in nor-
mal operation as their output range is 0 V to +5 V. There are
two methods of producing this negative voltage. One method is
to provide a positive output voltage and then to level shift that
analog voltage to the required negative range. Alternatively
V
OUTG and VOUTH vary from –10 V to +10 V with respect to
Device GND. Device GND is also connected to DUTGND.
When the AD7839 is cleared, VOUTG and VOUTH are cleared to
0 V with respect to Device GND.
TrimDAC is a registered trademark of Analog Devices, Inc.
REV. 0
–11–
AD7839
these DACs can be operated with supplies of 0 V and –5 V, with
the VDD pin connected to 0 V and the GND pin connected to
–5 V. Now these can be used to provide the negative reference
voltages for the VREF(–) inputs on the AD7839. However, the
digital signals driving the DACs need to be level-shifted from
the 0 V to +5 V range to the –5 V to 0 V range. Figure 22 shows
a typical application circuit to provide programmable reference
capabilities for the AD7839.
ADDR BUS
+5V
ADDR
DECODER
8/10-BIT
DAC
V
DD
FSIN/CS
A0, A1, A2
0V TO +5V
D IN
V
REF
(+)AB
SDATA
SCLK
V A
OUT
V
OUT
A
SCLK
GND
AD7839*
LOGIC LEVEL
SHIFT
CONTROLLER
V
8/10-BIT
DAC
DD
FSIN/CS
D IN
0V TO ؊5V
V
REF
(؊)AB
V B
OUT
SCLK
V
OUT
B
GND
؊5V
DATA BUS
DATA BUS
GND
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Programmable Reference Generation for the AD7839
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead MQFP (S-44)
0.548 (13.925)
0.546 (13.875)
0.398 (10.11)
0.096 (2.44)
MAX
0.390 (9.91)
0.037 (0.94)
8°
0.8°
0.025 (0.64)
33
23
34
22
SEATING
PLANE
TOP VIEW
(PINS DOWN)
12
44
1
11
0.040 (1.02)
0.032 (0.81)
0.040 (1.02)
0.032 (0.81)
0.016 (0.41)
0.012 (0.30)
0.033 (0.84)
0.029 (0.74)
0.083 (2.11)
0.077 (1.96)
–12–
REV. 0
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