AD7908WYRUZ-REEL7_技术文档

8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs

with Sequencer in 20-Lead TSSOP

AD7908/AD7918/AD7928

FUNCTIONAL BLOCK DIAGRAM

FEATURES

AV

DD

Fast throughput rate: 1 MSPS

Specified for AV_DDof 2.7 V to 5.25 V

Low power

6.0 mW max at 1 MSPS with 3 V supply

13.5 mW max at 1 MSPS with 5 V supply

Eight (single-ended) inputs with sequencer

Wide input bandwidth

AD7928, 70 dB min SINAD at 50 kHz input frequency

Flexible power/serial clock speed management

No pipeline delays

REF

V

IN

0

IN

T/H

•

8-/10-/12-BIT

SUCCESSIVE

APPROXIMATION

ADC

I/P

MUX

High speed serial interface SPI®/QSPI™/

MICROWIRE™/DSP compatible

Shutdown mode: 0.5 μA max

V

7

IN

SCLK

DOUT

DIN

CONTROL LOGIC

SEQUENCER

20-lead TSSOP package

CS

Qualified for automotive applications

AD7908/AD7918/AD7928

V

DRIVE

GENERAL DESCRIPTION

GND

The AD7908/AD7918/AD7928 are, respectively, 8-bit, 10-bit, and

12-bit, high speed, low power, 8-channel, successive approximation

ADCs. The parts operate from a single 2.7 V to 5.25 V power

supply and feature throughput rates up to 1 MSPS. The parts

contain a low noise, wide bandwidth track-and-hold amplifier that

can handle input frequencies in excess of 8 MHz.

Figure 1.

PRODUCT HIGHLIGHTS

1. High Throughput with Low Power Consumption. The AD7908/

AD7918/AD7928 offer up to 1 MSPS throughput rates. At the

maximum throughput rate with 3 V supplies, the AD7908/

AD7918/AD7928 dissipate just 6 mW of power maximum.

The conversion process and data acquisition are controlled using

CS

and the serial clock signal, allowing the device to easily interface

with microprocessors or DSPs. The input signal is sampled on the

CS

2. Eight Single-Ended Inputs with a Channel Sequencer.

A sequence of channels can be selected, through which

the ADC cycles and converts on.

falling edge of

and conversion is also initiated at this point.

There are no pipeline delays associated with the part.

3. Single-Supply Operation with V_DRIVEFunction. The AD7908/

AD7918/AD7928 operate from a single 2.7 V to 5.25 V supply.

The V_DRIVEfunction allows the serial interface to connect directly

The AD7908/AD7918/AD7928 use advanced design techniques to

achieve very low power dissipation at maximum throughput rates.

At maximum throughput rates, the AD7908/AD7918/AD7928

consume 2 mA maximum with 3 V supplies; with 5 V supplies, the

current consumption is 2.7 mA maximum.

to either 3 V or 5 V processor systems independent of AV_DD

.

4. Flexible Power/Serial Clock Speed Management. The conversion

rate is determined by the serial clock, allowing the conversion

time to be reduced through the serial clock speed increase. The

parts also feature various shutdown modes to maximize power

efficiency at lower throughput rates. Current consumption is

0.5 μA max when in full shutdown.

Through the configuration of the control register, the analog input

range for the part can be selected as 0 V to REF_INor 0 V to 2 ×

REF_IN, with either straight binary or twos complement output

coding. The AD7908/AD7918/AD7928 each feature eight single-

ended analog inputs with a channel sequencer to allow a

5. No Pipeline Delay. The parts feature a standard successive

approximation ADC with accurate control of the sampling

preprogrammed selection of channels to be converted sequentially.

The conversion time for the AD7908/AD7918/AD7928 is

determined by the SCLK frequency, which is also used as the

master clock to control the conversion.

CS

instant via a input and once off conversion control.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD7908/AD7918/AD7928

TABLE OF CONTENTS

Features .............................................................................................. 1

Control Register.............................................................................. 15

Sequencer Operation ................................................................. 16

SHADOW Register .................................................................... 17

Circuit Information.................................................................... 18

Converter Operation.................................................................. 18

ADC Transfer Function............................................................. 19

Handling Bipolar Input Signals................................................ 19

Typical Connection Diagram ................................................... 19

Modes of Operation................................................................... 21

Power vs. Throughput Rate....................................................... 23

Serial Interface............................................................................ 23

Microprocessor Interfacing....................................................... 24

Application Hints ....................................................................... 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 29

Automotive Products................................................................. 29

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AD7908 Specifications................................................................. 3

AD7918 Specifications................................................................. 5

AD7928 Specifications................................................................. 7

Timing Specifications .................................................................. 9

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Terminology .................................................................................... 12

Typical Performance Characteristics ........................................... 13

Performance Curves................................................................... 13

REVISION HISTORY

12/10—Rev. C to Rev. D

6/06—Rev. A to Rev. B

Changes to Features Section............................................................ 1

Added Automotive SINAD and SNR Parameters (Table 1)........ 3

Added Automotive SINAD and SNR Parameters (Table 2)........ 5

Added Automotive SINAD and SNR Parameters (Table 3)........ 7

Added Automotive Temperature Range (Table 5) ....................... 7

Added Automotive Products Section .......................................... 28

Changes to Ordering Guide .......................................................... 28

Updated Format..................................................................Universal

Changes to Reference Section....................................................... 21

9/03—Rev. 0 to Rev. A

Changes to Figure 3........................................................................ 15

Changes to Reference section ....................................................... 18

11/08—Rev. B to Rev. C

Changes to ESD Parameter, Table 5 ............................................. 10

Rev. D | Page 2 of 32

AD7908/AD7918/AD7928

SPECIFICATIONS

AD7908 SPECIFICATIONS

AV_DD= V_DRIVE= 2.7 V to 5.25 V, REF_IN= 2.5 V, f_SCLK= 20 MHz, T_A= T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

B Version¹

Unit

Test Conditions/Comments

f_IN= 50 kHz sine wave, f_SCLK= 20 MHz

B models

W models

B models

DYNAMIC PERFORMANCE

Signal-to-(Noise + Distortion) (SINAD)²

49

dB min

dB max

48.5

49

Signal-to-Noise Ratio (SNR)²

48.5

−66

−64

W models

Total Harmonic Distortion (THD)²

Peak Harmonic or Spurious Noise (SFDR)²

Intermodulation Distortion (IMD)²

Second-Order Terms

Third-Order Terms

Aperture Delay

fa = 40.1 kHz, fb = 41.5 kHz

−90

10

dB typ

ns typ

Aperture Jitter

50

ps typ

Channel-to-Channel Isolation²

−85

8.2

1.6

dB typ

MHz typ

f_IN= 400 kHz

@ 3 dB

Full Power Bandwidth

@ 0.1 dB

DC ACCURACY²

Resolution

8

Bits

Integral Nonlinearity

Differential Nonlinearity

0 V to REF_INInput Range

Offset Error

Offset Error Match

Gain Error

0.2

LSB max

Guaranteed no missed codes to 8 bits

Straight binary output coding

0.5

0.05

0.2

LSB max

Gain Error Match

0 V to 2 × REF_INInput Range

0.05

−REF_INto +REF_INbiased about REF_INwith

twos complement output coding

Positive Gain Error

Positive Gain Error Match

Zero Code Error

0.2

0.05

0.5

0.1

0.2

LSB max

Zero Code Error Match

Negative Gain Error

Negative Gain Error Match

ANALOG INPUT

0.05

Input Voltage Ranges

0 to REF_IN

0 to 2 × REF_IN

V

RANGE bit set to 1

RANGE bit set to 0, AV_DD/V_DRIVE= 4.75 V to

5.25 V

DC Leakage Current

Input Capacitance

REFERENCE INPUT

REF_INInput Voltage

DC Leakage Current

REF_INInput Impedance

LOGIC INPUTS

1

20

μA max

pF typ

2.5

1

36

V

1ꢀ specified performance

f_SAMPLE= 1 MSPS

μA max

kΩ typ

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

0.7 × V_DRIVE

0.3 × V_DRIVE

1

10

V min

V max

μA max

pF max

Typically 10 nA, V_IN= 0 V or V_DRIVE

3

Input Capacitance, C_IN

Rev. D | Page 3 of 32

AD7908/AD7918/AD7928

Parameter

B Version¹

Unit

Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output Capacitance³

Output Coding

V_DRIVE− 0.2

0.4

1

V min

I_SOURCE= 200 μA, AV_DD= 2.7 V to 5.25 V

I_SINK= 200 μA

V max

μA max

pF max

10

Straight (natural) binary

Twos complement

Coding bit set to 1

Coding bit set to 0

CONVERSION RATE

Conversion Time

Track-and-Hold Acquisition Time

800

300

1

ns max

16 SCLK cycles with SCLK at 20 MHz

Sine wave input

Full-scale step input

Throughput Rate

POWER REQUIREMENTS

AV_DD

MSPS max

See Serial Interface section

2.7/5.25

V min/max

V_DRIVE

4

I_DD

Digital inputs = 0 V or V_DRIVE

AV_DD= 2.7 V to 5.25 V, SCLK On or Off

AV_DD= 4.75 V to 5.25 V, f_SCLK= 20 MHz

AV_DD= 2.7 V to 3.6 V, f_SCLK= 20 MHz

f_SAMPLE= 250 kSPS

Normal Mode (Static)

Normal Mode (Operational)

600

2.7

2

960

0.5

μA typ

mA max

μA typ

μA max

Using Auto Shutdown Mode

(Static)

SCLK on or off (20 nA typ)

Full Shutdown Mode

Power Dissipation⁴

Normal Mode (Operational)

13.5

6

2.5

1.5

2.5

1.5

mW max

μW max

AV_DD= 5 V, f_SCLK= 20 MHz

AV_DD= 3 V, f_SCLK= 20 MHz

AV_DD= 5 V

AV_DD= 3 V

AV_DD= 5 V

Auto Shutdown Mode (Static)

Full Shutdown Mode

AV_DD= 3 V

¹Temperature ranges as follows: B version: −40°C to +85°C.

²See Terminology section.

³Sample tested @ 25°C to ensure compliance.

⁴See Power vs. Throughput Rate section.

Rev. D | Page 4 of 32

AD7908/AD7918/AD7928

AD7918 SPECIFICATIONS

AV_DD= V_DRIVE= 2.7 V to 5.25 V, REF_IN= 2.5 V, f_SCLK= 20 MHz, T_A= T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter

B Version¹

Unit

Test Conditions/Comments

f_IN= 50 kHz sine wave, f_SCLK= 20 MHz

B models

W models

B models

DYNAMIC PERFORMANCE

Signal-to-(Noise + Distortion) (SINAD)²

61

dB min

dB max

60.5

61

Signal-to-Noise Ratio (SNR)²

60.5

−72

−74

W models

Total Harmonic Distortion (THD)²

Peak Harmonic or Spurious Noise (SFDR)²

Intermodulation Distortion (IMD)²

Second-Order Terms

Third-Order Terms

Aperture Delay

fa = 40.1 kHz, fb = 41.5 kHz

−90

10

dB typ

ns typ

Aperture Jitter

50

ps typ

Channel-to-Channel Isolation²

−85

8.2

1.6

dB typ

MHz typ

f_IN= 400 kHz

@ 3 dB

Full Power Bandwidth

@ 0.1 dB

DC ACCURACY²

Resolution

10

Bits

Integral Nonlinearity

Differential Nonlinearity

0 V to REF_INInput Range

Offset Error

Offset Error Match

Gain Error

0.5

LSB max

Guaranteed no missed codes to 10 bits

Straight binary output coding

2

LSB max

0.2

0.5

0.2

Gain Error Match

0 V to 2 × REF_INInput Range

−REF_INto +REF_INbiased about REF_INwith twos

complement output coding

Positive Gain Error

Positive Gain Error Match

Zero Code Error

0.5

0.2

2

0.2

0.5

0.2

LSB max

Zero Code Error Match

Negative Gain Error

Negative Gain Error Match

ANALOG INPUT

Input Voltage Ranges

0 to REF_IN

V

RANGE bit set to 1

0 to 2 × REF_IN

V

RANGE bit set to 0, AV_DD/V_DRIVE= 4.75 V to 5.25 V

DC Leakage Current

Input Capacitance

REFERENCE INPUT

REF_INInput Voltage

DC Leakage Current

REF_INInput Impedance

LOGIC INPUTS

1

20

μA max

pF typ

2.5

1

36

V

1ꢀ specified performance

f_SAMPLE= 1 MSPS

μA max

kΩ typ

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

0.7 × V_DRIVE

0.3 × V_DRIVE

1

10

V min

V max

μA max

pF max

Typically 10 nA, V_IN= 0 V or V_DRIVE

3

Input Capacitance, C_IN

Rev. D | Page 5 of 32

AD7908/AD7918/AD7928

Parameter

B Version¹

Unit

Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output Capacitance³

Output Coding

V_DRIVE− 0.2

0.4

1

V min

I_SOURCE= 200 μA, AV_DD= 2.7 V to 5.25 V

I_SINK= 200 μA

V max

μA max

pF max

10

Straight (natural) binary

Twos complement

Coding bit set to 1

Coding bit set to 0

CONVERSION RATE

Conversion Time

Track-and-Hold Acquisition Time

800

300

1

ns max

MSPS max

16 SCLK cycles with SCLK at 20 MHz

Sine wave input

Full-scale step input

Throughput Rate

POWER REQUIREMENTS

AV_DD

See Serial Interface section

2.7/5.25

V min/max

V_DRIVE

4

I_DD

Digital inputs = 0 V or V_DRIVE

AV_DD= 2.7 V to 5.25 V, SCLK on or off

AV_DD= 4.75 V to 5.25 V, f_SCLK= 20 MHz

AV_DD= 2.7 V to 3.6 V, f_SCLK= 20 MHz

f_SAMPLE= 250 kSPS

Normal Mode (Static)

Normal Mode (Operational)

600

2.7

2

960

0.5

μA typ

mA max

μA typ

μA max

Using Auto Shutdown Mode

(Static)

SCLK on or off (20 nA typ)

Full Shutdown Mode

Power Dissipation⁴

Normal Mode (Operational)

13.5

6

2.5

1.5

2.5

1.5

mW max

μW max

AV_DD= 5 V, f_SCLK= 20 MHz

AV_DD= 3 V, f_SCLK= 20 MHz

AV_DD= 5 V

AV_DD= 3 V

AV_DD= 5 V

Auto Shutdown Mode (Static)

Full Shutdown Mode

AV_DD= 3 V

¹Temperature ranges as follows: B version: –40°C to +85°C.

²See Terminology section.

³Sample tested @ 25°C to ensure compliance.

⁴See Power vs. Throughput Rate section.

Rev. D | Page 6 of 32

AD7908/AD7918/AD7928

AD7928 SPECIFICATIONS

A_VDD= V_DRIVE= 2.7 V to 5.25 V, REF_IN= 2.5 V, f_SCLK= 20 MHz, T_A= T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter

B Version¹

Unit

Test Conditions/Comments

f_IN= 50 kHz sine wave, f_SCLK= 20 MHz

@ 5 V, B models

@ 5 V, W models

@ 3 V typically 70 dB

B models

DYNAMIC PERFORMANCE

Signal-to-(Noise + Distortion) (SINAD)²

70

dB min

dB max

69.5

69

70

Signal-to-Noise Ratio (SNR)²

69.5

−77

−73

−78

−76

W models

Total Harmonic Distortion (THD)²

@ 5 V typically −84 dB

@ 3 V typically −77 dB

@ 5 V typically −86 dB

@ 3 V typically −80 dB

fa = 40.1 kHz, fb = 41.5 kHz

Peak Harmonic or Spurious Noise

(SFDR)²

Intermodulation Distortion (IMD)²

Second-Order Terms

Third-Order Terms

−90

10

dB typ

ns typ

Aperture Delay

Aperture Jitter

50

ps typ

Channel-to-Channel Isolation²

−85

8.2

1.6

dB typ

MHz typ

f_IN= 400 kHz

@ 3 dB

Full Power Bandwidth

@ 0.1 dB

DC ACCURACY²

Resolution

12

Bits

Integral Nonlinearity

Differential Nonlinearity

0 V to REF_INInput Range

Offset Error

Offset Error Match

Gain Error

1

LSB max

−0.9/+1.5

Guaranteed no missed codes to 12 bits

Straight binary output coding

Typically 0.5 LSB

8

LSB max

0.5

1.5

0.5

Gain Error Match

0 V to 2 × REF_INInput Range

−REF_INto +REF_INbiased about REF_INwith twos

complement output coding

Positive Gain Error

Positive Gain Error Match

Zero Code Error

1.5

0.5

8

0.5

1

LSB max

Typically 0.8 LSB

Zero Code Error Match

Negative Gain Error

Negative Gain Error Match

ANALOG INPUT

0.5

Input Voltage Ranges

0 to REF_IN

V

RANGE bit set to 1

0 to 2 × REF_IN

V

RANGE bit set to 0, AV_DD/V_DRIVE= 4.75 V to 5.25 V

DC Leakage Current

Input Capacitance

REFERENCE INPUT

REF_INInput Voltage

DC Leakage Current

REF_INInput Impedance

LOGIC INPUTS

1

20

μA max

pF typ

2.5

1

36

V

1ꢀ specified performance

f_SAMPLE= 1 MSPS

μA max

kΩ typ

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

0.7 × V_DRIVE

0.3 × V_DRIVE

1

10

V min

V max

μA max

pF max

Typically 10 nA, V_IN= 0 V or V_DRIVE

3

Input Capacitance, C_IN

Rev. D | Page 7 of 32

AD7908/AD7918/AD7928

Parameter

B Version¹

Unit

Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output Capacitance³

Output Coding

V_DRIVE− 0.2

0.4

1

V min

I_SOURCE= 200 μA, AV_DD= 2.7 V to 5.25 V

I_SINK= 200 μA

V max

μA max

pF max

10

Straight (natural) binary

Twos complement

Coding bit set to 1

Coding bit set to 0

CONVERSION RATE

Conversion Time

Track-and-Hold Acquisition Time

800

300

1

ns max

MSPS max

16 SCLK cycles with SCLK at 20 MHz

Sine wave input

Full-scale step input

Throughput Rate

POWER REQUIREMENTS

AV_DD

See Serial Interface section

2.7/5.25

V min/max

V_DRIVE

4

I_DD

Digital inputs = 0 V or V_DRIVE

AV_DD= 2.7 V to 5.25 V, SCLK on or off

AV_DD= 4.75 V to 5.25 V, f_SCLK= 20 MHz

AV_DD= 2.7 V to 3.6 V, f_SCLK= 20 MHz

f_SAMPLE= 250 kSPS

Normal Mode (Static)

Normal Mode (Operational)

600

2.7

2

960

0.5

μA typ

mA max

μA typ

μA max

Using Auto Shutdown Mode

(Static)

SCLK on or off (20 nA typ)

Full Shutdown Mode

Power Dissipation⁴

Normal Mode (Operational)

13.5

6

2.5

1.5

2.5

1.5

mW max

μW max

AV_DD= 5 V, f_SCLK= 20 MHz

AV_DD= 3 V, f_SCLK= 20 MHz

AV_DD= 5 V

AV_DD= 3 V

AV_DD= 5 V

Auto Shutdown Mode (Static)

Full Shutdown Mode

AV_DD= 3 V

¹Temperature ranges as follows: B Version: −40°C to +85°C.

²See Terminology section.

³Sample tested @ 25°C to ensure compliance.

⁴See Power vs. Throughput Rate section.

Rev. D | Page 8 of 32

AD7908/AD7918/AD7928

TIMING SPECIFICATIONS

AV_DD= 2.7 V to 5.25 V, V_DRIVE≤ AV_DD, REF_IN= 2.5 V, T_A= T_MINto T_MAX, unless otherwise noted.¹

Table 4.

Limit at T_MIN, T_MAXAD7908/AD7918/AD7928

Parameter

AV_DD= 3 V

AV_DD= 5 V

Unit

Description

2

f_SCLK

10

20

10

20

kHz min

MHz max

t_CONVERT

t_QUIET

16 × t_SCLK

50

16 × t_SCLK

50

ns min

Minimum quiet time required between CS rising edge and start of

next conversion

CS to SCLK setup time

10

ns min

ns max

ns min

ns min/max

ns min

μs max

t₂

3

t₃

Delay from CS until DOUT three-state disabled

Data access time after SCLK falling edge

SCLK low pulse width

SCLK high pulse width

SCLK to DOUT valid hold time

SCLK falling edge to DOUT high impedance

DIN setup time prior to SCLK falling edge

DIN hold time after SCLK falling edge

16^thSCLK falling edge to CS high

35

30

3

t₄

40

0.4 × t_SCLK

10

15/45

10

5

20

1

40

0.4 × t_SCLK

10

15/35

10

5

20

1

t₅

t₆

t₇

t₈

t₉

t₁₀

t₁₁

t₁₂

4

Power-up time from full power-down/auto shutdown mode

¹Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10ꢀ to 90ꢀ of AV_DD) and timed from a voltage level of 1.6 V. See Figure 2.

The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

²Mark/space ratio for the SCLK input is 40/60 to 60/40.

³Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V_DRIVE

.

⁴t₈is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t₈, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

I

200µA

OL

TO

OUTPUT

1.6V

C

L

50pF

I

200µA

OH

Figure 2. Load Circuit for Digital Output Timing Specifications

Rev. D | Page 9 of 32

AD7908/AD7918/AD7928

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 5.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

AV_DDto AGND

−0.3 V to +7 V

V_DRIVEto AGND

−0.3 V to AV_DD+ 0.3 V

−0.3 V to +7 V

−0.3 V to AV_DD+ 0.3 V

10 mA

Analog Input Voltage to AGND

Digital Input Voltage to AGND

Digital Output Voltage to AGND

REF_INto AGND

Input Current to Any Pin Except

Supplies¹

Operating Temperature Range

Commercial (B Version)

Storage Temperature Range

Automotive Temperature Range

Junction Temperature

TSSOP Package, Power Dissipation

θ_JAThermal Impedance

θ_JCThermal Impedance

Lead Temperature, Soldering

Vapor Phase (60 sec)

−40°C to +85°C

−65°C to +150°C

−40°C to +125°C

150°C

450 mW

143°C/W (TSSOP)

45°C/W (TSSOP)

215°C

220°C

1.5 kV

Infrared (15 sec)

ESD

¹Transient currents of up to 100 mA do not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. D | Page 10 of 32

AD7908/AD7918/AD7928

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

DIN

1

2

20

19

18

17

16

15

14

13

12

11

AGND

V

DRIVE

3

CS

DOUT

AGND

AD7908/

AD7918/

AD7928

AGND

4

AV

DD

5

V

0

1

2

3

4

5

IN

AV

DD

6

TOP VIEW

(Not to Scale)

REF

IN

7

8

AGND

V

7

9

IN

10

6

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

SCLK

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also

used as the clock source for the conversion process of the AD7908/AD7918/AD7928.

2

DIN

Data In. Logic input. Data to be written to the control register of the AD7908/AD7918/AD7928 is provided on

this input and is clocked into the register on the falling edge of SCLK (see the Control Register section).

3

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the

AD7908/AD7918/AD7928, and also frames the serial data transfer.

4, 8, 17, 20

AGND

Analog Ground. This is the ground reference point for all analog circuitry on the AD7908/AD7918/AD7928. All

analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins

should be connected together.

5, 6

AV_DD

Analog Power Supply Input. The AV_DDrange for the AD7908/AD7918/AD7928 is from 2.7 V to 5.25 V. For the 0 V

to 2 × REF_INrange, AV_DDshould be from 4.75 V to 5.25 V.

7

REF_IN

Reference Input for the AD7908/AD7918/AD7928. An external reference must be applied to this input. The

voltage range for the external reference is 2.5 V 1ꢀ for specified performance.

16 to 9

V_IN0 to V_IN7

Analog Input 0 through Analog Input 7. These are eight single-ended analog input channels that are

multiplexed into the on-chip track-and-hold. The analog input channel to be converted is selected by using

Address Bit ADD2 through Address Bit ADD0 of the control register. The address bits, in conjunction with the

SEQ and SHADOW bits, allow the sequencer to be programmed. The input range for all input channels can

extend from 0 V to REF_INor 0 V to 2 × REF_INas selected via the RANGE bit in the control register. Any unused

input channels must be connected to AGND to avoid noise pickup.

18

DOUT

Data Out. Logic output. The conversion result from the AD7908/AD7918/AD7928 is provided on this output as

a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the

AD7908 consists of one leading zero, three address bits indicating which channel the conversion result

corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided MSB

first; the data stream from the AD7918 consists of one leading zero, three address bits indicating which

channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two

trailing zeros, also provided MSB first; the data stream from the AD7928 consists of one leading zero, three

address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of

conversion data, provided MSB first. The output coding can be selected as straight binary or twos complement

via the CODING bit in the control register.

19

V_DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of

the AD7908/AD7918/AD7928 operates.

Rev. D | Page 11 of 32

AD7908/AD7918/AD7928

TERMINOLOGY

Integral Nonlinearity

Negative Gain Error Match

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The

endpoints of the transfer function are zero scale, a position 1 LSB

below the first code transition, and full scale, a position 1 LSB

above the last code transition.

This is the difference in negative gain error between any two

channels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of

crosstalk between channels. It is measured by applying a full-

scale 400 kHz sine wave signal to all seven nonselected input

channels and determining how much that signal is attenuated

in the selected channel with a 50 kHz signal. The figure is given

worst case across all eight channels for the AD7908/AD7918/

AD7928.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00 . . . 000) to

(00 . . . 001) from the ideal, that is, AGND + 1 LSB.

Power Supply Rejection (PSR)

Variations in power supply affect the full-scale transition, but

not the converter’s linearity. Power supply rejection is the

maximum change in full-scale transition point due to a change

in power-supply voltage from the nominal value (see the

Performance Curves section).

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is the deviation of the last code transition (111 . . . 110) to

(111 . . . 111) from the ideal (that is, REF_IN– 1 LSB) after the

offset error has been adjusted out.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end

of conversion. Track-and-hold acquisition time is the time

required for the output of the track-and-hold amplifier to reach

its final value, within 1 LSB, after the end of conversion.

Gain Error Match

This is the difference in gain error between any two channels.

Zero Code Error

Signal-to-(Noise + Distortion) Ratio

This applies when using the twos complement output coding

option, in particular to the 2 × REF_INinput range with −REF_IN

to +REF_INbiased about the REF_INpoint. It is the deviation of the

midscale transition (all 0s to all 1s) from the ideal V_INvoltage,

that is, REF_IN− 1 LSB.

This is the measured ratio of signal-to-(noise + distortion) at

the output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the sum of all nonfundamental signals up

to half the sampling frequency (f_S/2), excluding dc. The ratio is

dependent on the number of quantization levels in the

digitization process; the more levels, the smaller the

quantization noise. The theoretical signal-to-(noise +

distortion) ratio for an ideal N-bit converter with a sine wave

input is given by

Zero Code Error Match

This is the difference in zero code error between any two

channels.

Positive Gain Error

Signal-to-(Noise + Distortion) = (6.02N + 1.76)dB

This applies when using the twos complement output coding

option, in particular to the 2 × REF_INinput range with −REF_IN

to +REF_INbiased about the REF_INpoint. It is the deviation of the

last code transition (011. . .110) to (011 . . . 111) from the ideal

(that is, +REF_IN− 1 LSB) after the zero code error has been

adjusted out.

Thus for a 12-bit converter, this is 74 dB; for a 10-bit converter,

this is 62 dB; and for an 8-bit converter, this is 50 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7908/AD7918/

AD7928, it is defined as:

Positive Gain Error Match

This is the difference in positive gain error between any two

channels.

2

V

+V +V + V +V

2

3

4

5

6

THD

(

dB = 20log

)

Negative Gain Error

V

1

This applies when using the twos complement output coding

option, in particular to the 2 × REF_INinput range with −REF_IN

to +REF_INbiased about the REF_INpoint. It is the deviation of the

first code transition (100 . . . 000) to (100 . . . 001) from the ideal

(that is, −REF_IN+ 1 LSB) after the zero code error has been

adjusted out.

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅, and V₆are the rms amplitudes of the second through the

sixth harmonics.

Rev. D | Page 12 of 32

AD7908/AD7918/AD7928

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7 shows a graph of total harmonic distortion vs. analog

input frequency for various supply voltages, and Figure 8 shows a

graph of total harmonic distortion vs. analog input frequency

for various source impedances. See the Analog Input section.

PERFORMANCE CURVES

Figure 4 shows a typical FFT plot for the AD7928 at 1 MSPS

sample rate and 50 kHz input frequency. Figure 5 shows the

signal-to-(noise + distortion) ratio performance vs. input

frequency for various supply voltages while sampling at 1 MSPS

with an SCLK of 20 MHz.

Figure 9 and Figure 10 show typical INL and DNL plots for the

AD7928.

Figure 6 shows the power supply rejection ratio vs. supply ripple

frequency for the AD7928 when no decoupling is used. The

power supply rejection ratio is defined as the ratio of the power

in the ADC output at full-scale frequency f, to the power of a

200 mV p-p sine wave applied to the ADC AV_DDsupply of

frequency f_S

0

AV

= 5V

DD

200mV p-p SINEWAVE ON AV

–10

–20

–30

–40

–50

–60

–70

–80

–90

DD

REF = 2.5V, 1µF CAPACITOR

IN

= 25°C

T

A

PSRR(dB) = 10 log(Pf/Pfs)

Pf is equal to the power at frequency f in ADC output; Pf_Sis

equal to the power at frequency f_Scoupled onto the ADC AV_DD

supply. Here a 200 mV p-p sine wave is coupled onto the AV_DD

supply.

0

100 200 300 400 500 600 700 800 900 1000

SUPPLY RIPPLE FREQUENCY (kHz)

4096 POINT FFT

AV = 5V

–10

DD

f_SAMPLE= 1MSPS

f_IN= 50kHz

Figure 6. AD7928 PSRR vs. Supply Ripple Frequency

–30

SINAD = 71.147dB

THD = –87.229dB

SFDR = –90.744dB

–50

–55

–60

–65

–70

–75

–80

–85

–90

f_SAMPLE= 1MSPS

T

= 25°C

A

RANGE = 0V TO REF

–50

–70

IN

AV

= V = 2.70V

DRIVE

DD

AV

= V

DRIVE

= 3.60V

= 4.75V

DD

–90

–110

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

AV

= V

DRIVE

DD

Figure 4. AD7928 Dynamic Performance at 1 MSPS

AV

= V = 5.25V

DRIVE

DD

75

70

65

60

55

10

100

INPUT FREQUENCY (kHz)

1000

AV

= V

= 5.25V

= 4.75V

DD

DRIVE

Figure 7. AD7928 THD vs. Analog Input Frequency for

Various Supply Voltages at 1 MSPS

DRIVE

AV

= V = 3.60V

DRIVE

DD

f_SAMPLE= 1MSPS

= 25°C

RANGE = 0V TO REF

T

AV

= V = 2.70V

DRIVE

A

DD

IN

10

100

INPUT FREQUENCY (kHz)

1000

Figure 5. AD7928 SINAD vs. Analog Input Frequency for

Various Supply Voltages at 1 MSPS

Rev. D | Page 13 of 32

AD7908/AD7918/AD7928

–50

1.0

0.8

f_SAMPLE= 1MSPS

= 25°C

RANGE = 0V TO REF

R

= 1000Ω

IN

AV

= V

= 5V

DD

DRIVE

T

A

–55

TEMPERATURE = 25°C

IN

AV

= 5.25V

DD

0.6

–60

–65

0.4

0.2

R

= 100Ω

IN

–70

–75

0

R

= 50Ω

IN

–0.2

–0.4

–0.6

–0.8

–1.0

R

= 10Ω

IN

–80

–85

–90

10

100

INPUT FREQUENCY (kHz)

1000

0

512

1024

1536

2048 2560 3072

CODE

3584 4096

Figure 8. AD7928 THD vs. Analog Input Frequency for

Various Source Impedances

Figure 10. AD7928 Typical DNL

1.0

0.8

AV

= V

= 5V

DD

DRIVE

TEMPERATURE = 25°C

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

512

1024

1536 2048

CODE

2560 3072

3584 4096

Figure 9. AD7928 Typical INL

Rev. D | Page 14 of 32

AD7908/AD7918/AD7928

CONTROL REGISTER

The control register on the AD7908/AD7918/AD7928 is a 12-bit, write-only register. Data is loaded from the DIN pin of the

AD7908/AD7918/AD7928 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conversion

result is read from the part. The data transferred on the DIN line corresponds to the AD7908/AD7918/AD7928 configuration for the next

conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after

CS

falling edge) is loaded to the control register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table 7.

MSB

LSB

CODING

WRITE

SEQ

DON’TCARE

ADD2

ADD1

ADD0

PM1

PM0

SHADOW

DON’TCARE

RANGE

Table 7. Control Register Bit Functions

Bit

Mnemonic Comment

11

WRITE

The value written to this bit of the control register determines whether or not the following 11 bits are loaded to the

control register. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, the remaining 11 bits

are not loaded to the control register, and it remains unchanged.

10

9

SEQ

The SEQ bit in the control register is used in conjunction with the SHADOW bit to control the use of the sequencer

function and access the SHADOW register (see the SHADOW register bit map).

DON’TCARE

8 to 6 ADD2 to

ADD0

These three address bits are loaded at the end of the present conversion sequence and select which analog input

channel is to be converted in the next serial transfer, or they can select the final channel in a consecutive sequence as

described in Table 10. The selected input channel is decoded as shown in Table 8. The address bits corresponding to

the conversion result are also output on DOUT prior to the 12 bits of data, see the Serial Interface section. The next

channel to be converted on is selected by the mux on the 14th SCLK falling edge.

5, 4

3

PM1, PM0

SHADOW

Power Management Bits. These two bits decode the mode of operation of the AD7908/AD7918/AD7928 as shown in

Table 9.

The SHADOW bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer

function and access the SHADOW register (see Table 10).

2

1

DON’TCARE

RANGE

This bit selects the analog input range to be used on the AD7908/AD7918/AD7928. If it is set to 0, the analog input

range extends from 0 V to 2 × REF_IN. If it is set to 1, the analog input range extends from 0 V to REF_IN(for the next

conversion). For 0 V to 2 × REF_IN, AV_DD= 4.75 V to 5.25 V.

0

CODING

This bit selects the type of output coding the AD7908/AD7918/AD7928 uses for the conversion result. If this bit is set to

0, the output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight

binary (for the next conversion).

Table 8. Channel Selection

ADD2

ADD1

ADD0

Analog Input Channel

0

1

0

1

0

1

0

1

0

1

0

1

0

1

V_IN0

V_IN1

V_IN2

V_IN3

V_IN4

V_IN5

V_IN6

V_IN7

Rev. D | Page 15 of 32

AD7908/AD7918/AD7928

Table 9. Power Mode Selection

PM1 PM0 Mode

1

Normal Operation. In this mode, the AD7908/AD7918/AD7928 remain in full power mode regardless of the status of any of

the logic inputs. This mode allows the fastest possible throughput rate from the AD7908/AD7918/AD7928.

1

0

Full Shutdown. In this mode, the AD7908/ AD7918/AD7928 is in full shutdown mode with all circuitry powering down. The

AD7908/AD7918/AD7928 retains the information in the control register while in full shutdown. The part remains in full

shutdown until these bits are changed.

0

1

0

Auto Shutdown. In this mode, the AD7908/AD7918/AD7928 automatically enters full shutdown mode at the end of each

conversion when the control register is updated. Wake-up time from full shutdown is 1 μs and the user should ensure that 1 μs

has elapsed before attempting to perform a valid conversion on the part in this mode.

Invalid Selection. This configuration is not allowed.

SEQUENCER OPERATION

The configuration of the SEQ and SHADOW bits in the control register allows the user to select a particular mode of operation of the

sequencer function. Table 10 outlines the four modes of operation of the sequencer.

Table 10. Sequence Selection

SEQ SHADOW Sequence Type

0

This configuration means that the sequence function is not used. The analog input channel selected for each individual

conversion is determined by the contents of the ADD0 through ADD2 channel address bits in each prior write

operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer

function being used, where each write to the AD7908/AD7918/AD7928 selects the next channel for conversion (see

Figure 11).

0

1

This configuration selects the SHADOW register for programming. The following write operation loads the contents of

the SHADOW register. This programs the sequence of channels to be converted on continuously with each successive

valid CS falling edge (see the SHADOW Register section, SHADOW register bit map, and Figure 12). The channels

selected need not be consecutive.

1

0

1

If the SEQ and SHADOW bits are set in this way, then the sequence functions are not interrupted upon completion of

the write operation. This allows other bits in the control register to be altered between conversions while in a sequence,

without terminating the cycle.

This configuration is used in conjunction with the ADD2 to ADD0 channel address bits to program continuous

conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the

channel address bits in the control register (see Figure 13).

Rev. D | Page 16 of 32

AD7908/AD7918/AD7928

SHADOW REGISTER

MSB

LSB

V_IN0

V_IN1

V_IN2

V_IN3

V_IN4

V_IN5

V_IN6

V_IN7

V_IN0

V_IN1

V_IN2

V_IN3

V_IN4

V_IN5

V_IN6

V_IN7

Sequence One

Sequence Two

The SHADOW register on the AD7908/AD7918/AD7928 is a

16-bit, write-only register. Data is loaded from the DIN pin of

POWER-ON

DUMMY CONVERSION

DIN = ALL 1s

the AD7908/AD7918/AD7928 on the falling edge of SCLK. The

data is transferred on the DIN line at the same time that a

conversion result is read from the part. This requires 16 serial

clock falling edges for the data transfer. The information is

clocked into the SHADOW register, provided that the SEQ and

SHADOW bits were set to 0,1, respectively, in the previous

write to the control register. MSB denotes the first bit in the

data stream. Each bit represents an analog input from Channel 0

to Channel 7. Through programming the SHADOW register,

two sequences of channels can be selected, through which the

AD7908/AD7918/AD7928 cycle with each consecutive

conversion after the write to the SHADOW register.

DIN: WRITE TO CONTROL REGISTER,

CS

WRITE BIT = 1, SELECT CODING, RANGE,

AND POWER MODE.

SELECT A2 TO A0 FOR CONVERSION.

SEQ = SHADOW = 0

DOUT: CONVERSION RESULT FROM

PREVIOUSLY SELECTED

CHANNEL A2 TO A0.

CS

WRITE BIT = 1,

SEQ = SHADOW = 0

DIN: WRITE TO CONTROL REGISTER,

WRITE BIT = 1, SELECT CODING, RANGE,

AND POWER MODE.

SELECT A2 TO A0 FOR CONVERSION.

SEQ = SHADOW = 0

Figure 11. SEQ Bit = 0, SHADOW Bit = 0 Flowchart

Sequence One is performed first and then Sequence Two. If the

user does not wish to perform a second sequence option, then

all 0s must be written to the last 8 LSBs of the SHADOW

register. To select a sequence of channels, the associated channel

bit must be set for each analog input. The AD7908/AD7918/

AD7928 continuously cycle through the selected channels in

ascending order beginning with the lowest channel, until a

write operation occurs (that is, the WRITE bit is set to 1) with

the SEQ and SHADOW bits configured in any way except 1, 0,

(see Table 10). The bit functions are outlined in the SHADOW

register bit map.

POWER-ON

DUMMY CONVERSION

DIN = ALL 1s

DIN: WRITE TO CONTROL REGISTER,

WRITE BIT = 1, SELECT CODING, RANGE,

AND POWER MODE.

SELECT CHANNEL A2 TO A0

FOR CONVERSION.

SEQ = 0 SHADOW = 1

CS

DOUT: CONVERSION RESULT FROM

PREVIOUSLY SELECTED CHANNEL A2

TO A0.

Figure 11 reflects the traditional operation of a multichannel

ADC, where each serial transfer selects the next channel for

conversion. In this mode of operation the sequencer function is

not used.

CS

DIN: WRITE TO SHADOW REGISTER,

SELECTING WHICH CHANNELS TO

CONVERT ON; CHANNELS SELECTED

NEED NOT BE CONSECUTIVE

CHANNELS

WRITE BIT = 0

WRITE BIT = 1

Figure 12 shows how to program the AD7908/AD7918/AD7928

to continuously convert on a particular sequence of channels.

To exit this mode of operation and revert back to the traditional

mode of operation of a multichannel ADC (as outlined in

Figure 11), ensure that the WRITE bit = 1 and the SEQ =

SHADOW = 0 on the next serial transfer. Figure 13 shows how

a sequence of consecutive channels can be converted on without

having to program the SHADOW register or write to the part

on each serial transfer. Again, to exit this mode of operation and

revert back to the traditional mode of operation of a multichannel

ADC (as outlined in Figure 11), ensure the WRITE bit = 1 and

the SEQ = SHADOW = 0 on the next serial transfer.

SEQ = 1, SHADOW = 0

CONTINUOUSLY

CONVERTS ON THE

SELECTED SEQUENCE

OF CHANNELS BUT WILL

ALLOW RANGE, CODING,

AND SO ON, TO CHANGE

IN THE CONTROL

REGISTER WITHOUT

INTERRUPTING THE

SEQUENCE, PROVIDED

SEQ = 1 SHADOW = 0

CONTINUOUSLY

CONVERTS ON

THE SELECTED

SEQUENCE OF

CHANNELS

CS

WRITE BIT = 0

WRITE BIT = 1

SEQ = 1, SHADOW = 0

Figure 12. SEQ Bit = 0, SHADOW Bit = 1 Flowchart

Rev. D | Page 17 of 32

AD7908/AD7918/AD7928

POWER-ON

REF_INor 0 V to 2 × REF_IN. Figure 14 and Figure 15 show

simplified schematics of the ADC. The ADC is comprised of

control logic, SAR, and a capacitive DAC, which are used to add

and subtract fixed amounts of charge from the sampling

capacitor to bring the comparator back into a balanced

condition. Figure 14 shows the ADC during its acquisition

phase. SW2 is closed and SW1 is in Position A. The comparator

is held in a balanced condition and the sampling capacitor

acquires the signal on the selected V_INchannel.

DUMMY CONVERSION

DIN = ALL 1s

DIN: WRITE TO CONTROL REGISTER,

WRITE BIT = 1, SELECT CODING, RANGE,

CS

AND POWER MODE.

SELECT CHANNEL A2 TO A0

FOR CONVERSION.

SEQ = 1 SHADOW = 1

DOUT: CONVERSION RESULT FROM

CHANNEL 0.

CAPACITIVE DAC

CONTINUOUSLY CONVERTS ON A

CONSECUTIVE SEQUENCE OF

CHANNELS FROM CHANNEL 0 UP TO,

AND INCLUDING, THE PREVIOUSLY

SELECTED A2 TO A0 IN THE CONTROL

REGISTER.

CS

WRITE BIT = 0

A

4kΩ

V

0

IN

CONTROL

LOGIC

SW1

B

SW2

7

IN

COMPARATOR

AGND

CONTINUOUSLY CONVERTS ON THE

SELECTED SEQUENCE OF CHANNELS

BUT WILL ALLOW RANGE, CODING, AND

SO ON, TO CHANGE IN THE CONTROL

REGISTER WITHOUT INTERRUPTING

THE SEQUENCE, PROVIDED SEQ = 1

SHADOW = 0

Figure 14. ADC Acquisition Phase

CS

WRITE BIT = 1

SEQ = 1, SHADOW = 0

When the ADC starts a conversion (see Figure 15), SW2 opens

and SW1 moves to Position B, causing the comparator to

become unbalanced. The control logic and the capacitive DAC

are used to add and subtract fixed amounts of charge from the

sampling capacitor to bring the comparator back into a

balanced condition. When the comparator is rebalanced, the

conversion is complete. The control logic generates the ADC

output code. Figure 17 and Figure 18 show the ADC transfer

functions.

Figure 13. SEQ Bit = 1, SHADOW Bit = 1 Flowchart

CIRCUIT INFORMATION

The AD7908/AD7918/AD7928 are high speed, 8-channel, 8-bit,

10-bit, and 12-bit, single-supply ADCs, respectively. The parts

can be operated from a 2.7 V to 5.25 V supply. When operated

from either a 5 V or 3 V supply, the AD7908/AD7918/AD7928

are capable of throughput rates of 1 MSPS when provided with

a 20 MHz clock.

CAPACITIVE DAC

A

4kΩ

The AD7908/AD7918/AD7928 provide the user with an on-

chip, track-and-hold ADC, and a serial interface housed in a

20-lead TSSOP package. The AD7908/AD7918/ AD7928 each

have eight single-ended input channels with a channel

V

0

7

IN

CONTROL

LOGIC

SW1

B

SW2

IN

COMPARATOR

AGND

sequencer, allowing the user to select a channel sequence that

Figure 15. ADC Conversion Phase

CS

the ADC can cycle through with each consecutive

falling

edge. The serial clock input accesses data from the part, controls

the transfer of data written to the ADC, and provides the clock

source for the successive approximation ADC. The analog input

range for the AD7908/AD7918/ AD7928 is 0 V to REF_INor 0 V

to 2 × REF_IN, depending on the status of Bit 1 in the control

register. For the 0 to 2 × REF_INrange, the part must be operated

from a 4.75 V to 5.25 V supply.

Analog Input

Figure 16 shows an equivalent circuit of the analog input

structure of the AD7908/AD7918/AD7928. The two diodes (D1

and D2) provide ESD protection for the analog inputs. Care

must be taken to ensure that the analog input signal never

exceeds the supply rails by more than 300 mV. This causes these

diodes to become forward biased and start conducting current

into the substrate. 10 mA is the maximum current these diodes

can conduct without causing irreversible damage to the part.

The Capacitor C1 in Figure 16 is typically about 4 pF and can

primarily be attributed to pin capacitance. The Resistor R1 is a

lumped component made up of the on resistance of the track-

and-hold switch and also includes the on resistance of the input

multiplexer. The total resistance is typically about 400 Ω. The

Capacitor C2 is the ADC sampling capacitor and has a

The AD7908/AD7918/AD7928 provide flexible power

management options to allow the user to achieve the best power

performance for a given throughput rate. These options are

selected by programming the PM1 and PM0 power

management bits in the control register.

CONVERTER OPERATION

The AD7908/AD7918/AD7928 are 8-, 10-, and 12-bit

capacitance of 30 pF typically. For ac applications, removing

high frequency components from the analog input signal is

recommended by use of an RC lowpass filter on the relevant

analog input pin. In applications where harmonic distortion

successive approximation analog-to-digital converters based

around a capacitive DAC, respectively. The AD7908/AD7918/

AD7928 can convert analog input signals in the range 0 V to

Rev. D | Page 18 of 32

AD7908/AD7918/AD7928

and signal-to-noise ratio are critical, the analog input should be

driven from a low impedance source. Large source impedances

significantly affect the ac performance of the ADC. This can

necessitate the use of an input buffer amplifier. The choice of

the op amp is a function of the particular application.

011…111

011…110

•

000…001

000…000

111…111

•

1LSB = 2 × V

/256 AD7908

/1024 AD7918

/4096 AD7928

REF

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance depends on the amount of total harmonic

distortion (THD) that can be tolerated. The THD increases as

the source impedance increases, and performance degrades (see

Figure 8).

100…010

100…001

100…000

–V

+ 1 LSB

+V

– 1 LSB

REF

V

– 1 LSB

REF

ANALOG INPUT

Figure 18. Twos Complement Transfer Characteristic

with REF_INREF_INInput Range

AV

DD

HANDLING BIPOLAR INPUT SIGNALS

C2

30pF

D1

R1

Figure 19 shows how useful the combination of the 2 × REF_IN

input range and the twos complement output coding scheme is

for handling bipolar input signals. If the bipolar input signal is

biased about REF_INand twos complement output coding is

selected, then REF_INbecomes the zero code point, −REF_INis

negative full scale and +REF_INbecomes positive full scale, with

a dynamic range of 2 × REF_IN.

V

IN

C1

4pF

D2

CONVERSION PHASE: SWITCH OPEN

TRACK PHASE: SWITCH CLOSED

Figure 16. Equivalent Analog Input Circuit

ADC TRANSFER FUNCTION

The output coding of the AD7908/AD7918/AD7928 is either

straight binary or twos complement, depending on the status of

the LSB in the control register. The designed code transitions

occur at successive LSB values (that is, 1 LSB, 2 LSBs, and so

on). The LSB size is REF_IN/256 for the AD7908, REF_IN/1024 for

the AD7918, and REF_IN/4096 for the AD7928. The ideal transfer

characteristic for the AD7908/AD7918/AD7928 when straight

binary coding is selected is shown in Figure 17, and the ideal

transfer characteristic for the AD7908/AD7918/AD7928 when

twos complement coding is selected is shown in Figure 18.

TYPICAL CONNECTION DIAGRAM

Figure 20 shows a typical connection diagram for the

AD7908/AD7918/AD7928. In this setup, the AGND pin is

connected to the analog ground plane of the system. In Figure 20,

REF_INis connected to a decoupled 2.5 V supply from a reference

source, the AD780, to provide an analog input range of 0 V to

2.5 V (if RANGE bit is 1) or 0 V to 5 V (if RANGE bit is 0).

Although the AD7908/AD7918/AD7928 is connected to a V_DD

of 5 V, the serial interface is connected to a 3 V microprocessor.

The V_DRIVEpin of the AD7908/AD7918/ AD7928 is connected

to the same 3 V supply of the microprocessor to allow a 3 V

logic interface (see the Digital Inputs section). The conversion

result is output in a 16-bit word. This 16-bit data stream

consists of a leading zero, three address bits indicating which

channel the conversion result corresponds to, followed by the 12

bits of conversion data for the AD7928 (10 bits of data for the

AD7918 and 8 bits of data for the AD7908, each followed by

two and four trailing zeros, respectively). For applications

where power consumption is of concern, the power-down

modes should be used between conversions or bursts of several

conversions to improve power performance (see the Modes of

Operation section).

111…111

111…110

•

111…000

•

011…111

•

1LSB = V

/256 AD7908

/1024 AD7918

/4096 AD7928

REF

000…010

000…001

000…000

1 LSB

+V

– 1 LSB

REF

0V

ANALOG INPUT

NOTE

1. V

IS EITHER REF OR 2 × REF

REF

IN IN.

Figure 17. Straight Binary Transfer Characteristic

Rev. D | Page 19 of 32

AD7908/AD7918/AD7928

V

DD

V

REF

0.1µF

AV

DD

REF

IN

V

DD

V

DRIVE

AD7908/

AD7918/

AD7928

R4

DSP/µP

V

R3

R2

TWOS COMPLEMENT

V

0

DOUT

IN

V

0V

•

011…111

000…000

100…000

+REF

(= 2 × REF

IN)

R1

IN

7

IN

R1 = R2 = R3 = R4

REF

IN

(= 0V)

–REF

IN

Figure 19. Handling Bipolar Signals

during the sequence, then it must be ensured that the SEQ and

SHADOW bits are set to 1, 0 to avoid interrupting the

5V

SUPPLY

SERIAL

INTERFACE

0.1µF

10µF

automatic conversion sequence. This pattern continues until

such time as the AD7908/AD7918/AD7928 is written to and the

SEQ and SHADOW bits are configured with any bit combination

except 1, 0. On completion of the sequence, the AD7908/

AD7918/AD7928 sequencer returns to the first selected channel

in the SHADOW register and commence the sequence again.

AV

0

•

DD

SCLK

DOUT

CS

V

IN

AD7908/

AD7918/

AD7928

0V TO REF

IN

µC/µP

7

IN

DIN

REF

V

DRIVE

AGND

IN

2.5V

0.1µF

Rather than selecting a particular sequence of channels, a

number of consecutive channels beginning with Channel 0 can

also be programmed via the control register alone, without

needing to write to the SHADOW register. This is possible if the

SEQ and SHADOW bits are set to 1,1. The channel address bits

ADD2 through ADD0 then determine the final channel in the

consecutive sequence. The next conversion is on Channel 0,

then Channel 1, and so on until the channel selected via the

address bits ADD2 through ADD0 is reached. The cycle begins

again on the next serial transfer, provided the WRITE bit is set

to low, or if high, that the SEQ and SHADOW bits are set to

1, 0; then the ADC continues its preprogrammed automatic

sequence uninterrupted.

0.1µF

10µF

AD780

3V

SUPPLY

NOTE

1. ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO AGND.

Figure 20. Typical Connection Diagram

Analog Input Selection

Any one of eight analog input channels can be selected for

conversion by programming the multiplexer with the Address

Bit ADD2 to Address Bit ADD0 in the control register. The

channel configurations are shown in Table 8. The AD7908/

AD7918/AD7928 can also be configured to automatically cycle

through a number of channels as selected. The sequencer

feature is accessed via the SEQ and SHADOW bits in the

control register (see Table 10).

Regardless of which channel selection method is used, the 16-bit

word output from the AD7928 during each conversion always

contains a leading zero, three channel address bits that the

conversion result corresponds to, followed by the 12-bit

conversion result. The AD7918 outputs a leading zero, three

channel address bits that the conversion result corresponds to,

followed by the 10-bit conversion result and two trailing zeros;

the AD7908 outputs a leading zero, three channel address bits

that the conversion result corresponds to, followed by the 8-bit

conversion result and four trailing zeros. (See the Serial

Interface section.)

The AD7908/AD7918/AD7928 can be programmed to

continuously convert on a selection of channels in ascending

order. The analog input channels to be converted on are

selected through programming the relevant bits in the

SHADOW register (see the SHADOW Register section). The

next serial transfer then acts on the sequence programmed by

executing a conversion on the lowest channel in the selection.

The next serial transfer results in a conversion on the next

highest channel in the sequence, and so on.

It is not necessary to write to the control register once a

sequencer operation has been initiated. The WRITE bit must be

set to zero or the DIN line tied low to ensure the control register

is not accidentally overwritten, or the sequence operation

interrupted. If the control register is written to at any time

Digital Inputs

The digital inputs applied to the AD7908/AD7918/AD7928 are

not limited by the maximum ratings that limit the analog

Rev. D | Page 20 of 32

AD7908/AD7918/AD7928

inputs. Instead, the digital inputs applied can go to 7 V and are

not restricted by the AV_DD+ 0.3 V limit as on the analog inputs.

CS

and the

The conversion is initiated on the falling edge of

track-and-hold enters hold mode as described in the Serial

Interface section. The data presented to the AD7908/AD7918/

AD7928 on the DIN line during the first 12 clock cycles of the

data transfer are loaded into the control register (provided

WRITE bit is set to 1). If data is to be written to the SHADOW

register (SEQ = 0, SHADOW = 1 on previous write), data

presented on the DIN line during the first 16 SCLK cycles is

loaded into the SHADOW register. The part remains fully

powered up in normal mode at the end of the conversion as

long as PM1 and PM0 are both loaded with 1 on every data

transfer.

CS

Another advantage of SCLK, DIN, and

not being restricted

by the AV_DD+ 0.3 V limit is the fact that power supply

CS

sequencing issues are avoided. If , DIN, or SCLK are applied

before AV_DD, there is no risk of latch-up as there would be on

the analog inputs if a signal greater than 0.3 V was applied prior

to AV_DD

.

V_DRIVE

The AD7908/AD7918/AD7928 also have the V_DRIVEfeature.

V_DRIVEcontrols the voltage at which the serial interface operates.

V_DRIVEallows the ADC to easily interface to both 3 V and 5 V

processors. For example, if the AD7908/AD7918/AD7928 were

operated with an AV_DDof 5 V, the V_DRIVEpin could be powered

from a 3 V supply. The AD7908/AD7918/AD7928 have better

dynamic performance with an AV_DDof 5 V while still being able

to interface to 3 V processors. Care should be taken to ensure

Sixteen serial clock cycles are required to complete the

conversion and access the conversion result. The track-and-

CS

hold goes back into track on the 14th SCLK falling edge.

then idle high until the next conversion or can idle low until

CS

can

sometime prior to the next conversion, effectively idling

low.

Once a data transfer is complete (DOUT has returned to three-

state), another conversion can be initiated after the quiet time,

V

_DRIVEdoes not exceed AV_DDby more than 0.3 V. See the

Absolute Maximum Ratings section.

CS

t_QUIET, has elapsed by bringing

low again.

Reference

CS

An external reference source should be used to supply the 2.5 V

reference to the AD7908/AD7918/AD7928. Errors in the

reference source results in gain errors in the AD7908/

AD7918/AD7928 transfer function and adds to the specified

full-scale errors of the part. A capacitor of at least 0.1 μF should

be placed on the REF_INpin. Suitable reference sources for the

AD7908/AD7918/AD7928 include the AD780, REF192,

AD1582, ADR03, ADR381, ADR391, and ADR421.

1

16

12

SCLK

1 LEADING ZERO + 3 CHANNEL

DOUT

IDENTIFIER BITS + CONVERSION RESULT

DATA IN TO CONTROL/SHADOW REGISTER

DIN

NOTES

1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES.

2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES.

If 2.5 V is applied to the REF_INpin, the analog input range can

either be 0 V to 2.5 V or 0 V to 5 V, depending on the setting of

the RANGE bit in the control register.

Figure 21. Normal Mode Operation

Full Shutdown Mode (PM1 = 1, PM0 = 0)

In this mode, all internal circuitry on the AD7908/AD7918/

AD7928 is powered down. The part retains information in the

control register during full shutdown. The AD7908/AD7918/

AD7928 remains in full shutdown until the power management

bits in the control register, PM1 and PM0, are changed.

MODES OF OPERATION

The AD7908/AD7918/AD7928 have a number of different

modes of operation. These modes are designed to provide

flexible power management options. These options can be

chosen to optimize the power dissipation/throughput rate ratio

for differing application requirements. The mode of operation

of the AD7908/AD7918/AD7928 is controlled by the power

management bits, PM1 and PM0, in the control register, as

detailed in Table 9. When power supplies are first applied to the

AD7908/AD7918/AD7928, care should be taken to ensure that

the part is placed in the required mode of operation (see

Powering Up the AD7908/AD7918/AD7928 section).

If a write to the control register occurs while the part is in full

shutdown, with the power management bits changed to PM0 =

CS

PM1 = 1, normal mode, the part begins to power up on the

rising edge. The track-and-hold that was in hold while the part was

in full shutdown returns to track on the 14th SCLK falling edge.

To ensure that the part is fully powered up, t_{POWER UP}, should

CS

have elapsed before the next

falling edge. Figure 22 shows

Normal Mode (PM1 = PM0 = 1)

the general diagram for this sequence.

This mode is intended for the fastest throughput rate

Auto Shutdown Mode (PM1 = 0, PM0 = 1)

performance, as the user does not have to worry about any

power-up times with the AD7908/AD7918/AD7928 remaining

fully powered at all times. Figure 21 shows the general diagram

of the operation of the AD7908/AD7918/AD7928 in this mode.

In this mode, the AD7908/AD7918/AD7928 automatically

enters shutdown at the end of each conversion when the control

register is updated. When the part is in shutdown, the track and

hold is in hold mode. Figure 23 shows the general diagram of

Rev. D | Page 21 of 32

AD7908/AD7918/AD7928

the operation of the AD7908/AD7918/AD7928 in this mode. In

shutdown mode, all internal circuitry on the AD7908/AD7918/

AD7928 is powered down. The part retains information in the

control register during shutdown. The AD7908/AD7918/

other conversion result being valid. In this mode, the power

consumption of the part is greatly reduced with the part

entering shutdown at the end of each conversion. When the

control register is programmed to move into auto shutdown, it

does so at the end of the conversion. The user can move the

CS

AD7928 remains in shutdown until the next

falling edge it

falling edge, the track-and-hold that was in

CS

ADC in and out of the low power state by controlling the

signal.

CS

receives. On this

hold while the part was in shutdown returns to track. Wakeup

time from auto shutdown is 1 μs, and the user should ensure

that 1 μs has elapsed before attempting a valid conversion.

When running the AD7908/AD7918/AD7928 with a 20 MHz

clock, one dummy cycle should be sufficient to ensure the part

is fully powered up. During this dummy cycle the contents of

the control register should remain unchanged; therefore the

WRITE bit should be 0 on the DIN line. This dummy cycle

effectively halves the throughput rate of the part, with every

Powering Up the AD7908/AD7918/AD7928

When supplies are first applied to the AD7908/AD7918/

AD7928, the ADC can power up in any of the operating modes

of the part. To ensure the part is placed into the required

operating mode, the user should perform a dummy cycle

operation as outlined in Figure 24.

PART IS IN

FULL SHUTDOWN

PART BEG I NSTO POWER UP ON

CS RISING EDGE AS PM1 = PM0 = 1

THE PART IS FULLY POWERED UP

ONCE t_{POWER UP}HAS ELAPSED

t₁₂

CS

14

16

1

14

16

SCLK

DOUT

DIN

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

DATA IN TO CONTROL/SHADOW REGISTER

DATA IN TO CONTROL REGISTER

CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS.

PM1 = 1, PM0 = 1

TO KEEPTHE PART IN NORMAL MODE,

LOAD PM1 = PM0 = 1 IN CONTROL REGISTER

Figure 22. Full Shutdown Mode Operation

PART ENTERS SHUTDOWN

ON CS RISING EDGE

AS PM1 = 0, PM0 = 1

PART BEGINS TO POWER

UP ON CS FALLING EDGE

PART ENTERS SHUTDOWN ON CS

RISING EDGE AS PM1 = 0, PM0 = 1

PART IS FULLY

POWERED UP

CS

DUMMY CONVERSION

12

1

12

16

1

16

1

12

16

SCLK

CHANNEL IDENTIFIER

BITS + CONVERSION RESULT

CHANNEL IDENTIFIER

BITS + CONVERSION RESULT

DOUT

INVALID DATA

DATA IN TO CONTROL/SHADOW REGISTER

DIN

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCKS, PM1 = 0, PM0 = 1

TO KEEP PART IN THIS MODE, LOAD PM1 = 0,

PM0 = 1 IN CONTROL REGISTER OR SET WRITE BIT = 0

CONTROL REGISTER CONTENTS SHOULD

NOT CHANGE. WRITE BIT = 0

Figure 23. Auto Shutdown Mode Operation

Rev. D | Page 22 of 32

AD7908/AD7918/AD7928

CORRECT VALUE IN CONTROL

REGISTER, VALID DATA FROM

NEXT CONVERSION, USER CAN

WRITE TO SHADOW REGISTER

IN NEXT CONVERSION

CS

DUMMY CONVERSION

12

DUMMY CONVERSION

12

1

16

1

16

1

12

16

SCLK

DOUT

INVALID DATA

DATA IN TO CONTROL REGISTER

DIN

KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS

CONTROL REGISTER IS LOADED ON THE FIRST

12 CLOCK EDGES

Figure 24. Placing AD7928 into the Required Operating Mode After Supplies are Applied

10

POWER VS. THROUGHPUT RATE

By operating in auto shutdown mode on the AD7908/AD7918/

AD7928, the average power consumption of the ADC decreases

at lower throughput rates. Figure 25 shows how as the

throughput rate is reduced, the part remains in its shutdown

state longer and the average power consumption over time

drops accordingly.

AV = 5V

DD

AV = 3V

DD

1

0.1

For example, if the AD7928 is operated in a continuous

sampling mode with a throughput rate of 100 kSPS and an

SCLK of 20 MHz (AV_DD= 5 V), and the device is placed in auto

shutdown mode, that is, if PM1 = 0 and PM0 = 1, then the

power consumption is calculated as follows:

0.01

0

50

100

150

200

250

300

350

THROUGHPUT (kSPS)

The maximum power dissipation during normal operation is

13.5 mW (AV_DD= 5 V). If the power-up time from auto

shutdown is one dummy cycle, that is, 1 μs, and the remaining

conversion time is another cycle, that is, 1 μs, then the AD7928

can be said to dissipate 13.5 mW for 2 μs during each

conversion cycle. For the remainder of the conversion cycle,

8 μs, the part remains in auto shutdown mode. The AD7928 can

be said to dissipate 2.5 μW for the remaining 8 μs of the

conversion cycle. If the throughput rate is 100 kSPS, the cycle

time is 10 μs and the average power dissipated during each cycle is

Figure 25. AD7928 Power vs. Throughput Rate

SERIAL INTERFACE

Figure 26, Figure 27, and Figure 28 show the detailed timing

diagrams for serial interfacing to the AD7908, AD7918, and

AD7928, respectively. The serial clock provides the conversion

clock and also controls the transfer of information to and from

the AD7908/AD7918/AD7928 during each conversion.

CS

The

signal initiates the data transfer and conversion process.

CS

The falling edge of

puts the track-and-hold into hold mode,

(2/10) × (13.5 mW) + (8 / 10) × (2.5 μW) = 2.702 mW

takes the bus out of three-state; the analog input is sampled at

this point. The conversion is also initiated at this point and

requires 16 SCLK cycles to complete. The track-and-hold goes

back into track on the 14th SCLK falling edge as shown in

Figure 26, Figure 27, and Figure 28 at Point B, except when the

write is to the SHADOW register, in which case the track-and-

Figure 25 shows the maximum power vs. throughput rate when

using the auto shutdown mode with 3 V and 5 V supplies.

CS

hold does not return to track until the rising edge of , that is,

Point C in Figure 29. On the 16th SCLK falling edge, the DOUT

CS

line goes back into three-state. If the rising edge of

occurs

before 16 SCLKs have elapsed, the conversion is terminated, the

DOUT line goes back into three-state, and the control register is

not updated; otherwise DOUT returns to three-state on the

16th SCLK falling edge as shown in Figure 26, Figure 27, and

Figure 28. Sixteen serial clock cycles are required to perform the

conversion process and to access data from the AD7908/

AD7918/AD7928. For the AD7908/AD7918/AD7928, the

Rev. D | Page 23 of 32

AD7908/AD7918/AD7928

8/10/12 bits of data are preceded by a leading zero and the

3-channel address bits (ADD2 to ADD0) identify which

MICROPROCESSOR INTERFACING

The serial interface on the AD7908/AD7918/AD7928 allows the

part to be directly connected to a range of many different

microprocessors. This section explains how to interface the

AD7908/AD7918/AD7928 with some of the more common

microcontroller and DSP serial interface protocols.

CS

channel the result corresponds to.

going low provides the

leading zero to be read in by the microcontroller or DSP. The

three remaining address bits and data bits are then clocked out

by subsequent SCLK falling edges beginning with the first

address bit (ADD2). Thus the first falling clock edge on the

serial clock has a leading zero provided and also clocks out

Address Bit ADD2. The final bit in the data transfer is valid on

the 16th falling edge, having been clocked out on the previous

(15th) falling edge.

AD7908/AD7918/AD7928 to TMS320C541

The serial interface on the TMS320C541 uses a continuous

serial clock and frame synchronization signals to synchronize

the data transfer operations with peripheral devices like the

CS

AD7908/AD7918/AD7928. The

input allows easy

Writing of information to the control register takes place on the

first 12 falling edges of SCLK in a data transfer, assuming the

MSB, that is, the WRITE bit, has been set to 1. If the control

register is programmed to use the SHADOW register, then

writing of information to the SHADOW register takes place on

all 16 SCLK falling edges in the next serial transfer, as shown for

example on the AD7928 in Figure 29. Two sequence options

can be programmed in the SHADOW register. If the user does

not want to program a second sequence, then the eight LSBs

should be filled with zeros. The SHADOW register is updated

interfacing between the TMS320C541 and the AD7908/

AD7918/AD7928 without any glue logic required. The serial

port of the TMS320C541 is set up to operate in burst mode with

internal CLKX0 (Tx serial clock on Serial Port 0) and FSX0 (Tx

frame sync from Serial Port 0). The serial port control register

(SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1,

and TXM = 1. The connection diagram is shown in Figure 30. It

should be noted that for signal processing applications, it is

imperative that the frame synchronization signal from the

TMS320C541 provides equidistant sampling. The V_DRIVEpin of

the AD7908/AD7918/AD7928 takes the same supply voltage as

that of the TMS320C541. This allows the ADC to operate at a

higher voltage than the serial interface, that is, TMS320C541, if

necessary.

CS

upon the rising edge of

and the track-and-hold begins to

track the first channel selected in the sequence.

The AD7908 outputs a leading zero and three channel address

bits that the conversion result corresponds to, followed by the

8-bit conversion result and four trailing zeros. The AD7918

outputs a leading zero and three channel address bits that the

conversion result corresponds to, followed by the 10-bit

conversion result and two trailing zeros. The 16-bit word read

from the AD7928 always contains a leading zero and three

channel address bits that the conversion result corresponds to,

followed by the 12-bit conversion result.

Rev. D | Page 24 of 32

AD7908/AD7918/AD7928

CS

t_CONVERT

5 6

t₂

t₆

B

11

12

13

14

t₅

15

16

t₁₁

1

2

3

4

SCLK

t₇

DB6

t₃

t₄

ADD0

THREE IDENTIFICATION BITS

t₈

t_QUIET

ADD2

ADD1

DB7

DB0

ZERO

DOUT

THREE-STATE

FOUR TRAILING ZEROS

ZERO

t₁₀

ADD0

t₉

CODING

WRITE SEQ1

DONTC

ADD2

ADD1

DONTC DONTC

DONTC

DIN

Figure 26. AD7908 Serial Interface Timing Diagram

CS

t_CONVERT

t₂

t₆

B

11

12

13

14

t₅

15

16

1

2

3

4

5

6

SCLK

t₁₁

t₇

t₃

t₄

t₈

t_QUIET

ADD2

ADD1

ADD0

DB7

DB6

DB2

DB1

DB0

ZERO

DOUT

THREE-STATE

THREE IDENTIFICATION BITS

TWO TRAILING ZEROS

ZERO

t₁₀

t₉

WRITE

SEQ

DONTC

ADD2

ADD1

ADD0

CODING

DONTC DONTC

DONTC

DIN

Figure 27. AD7918 Serial Interface Timing Diagram

CS

t_CONVERT

t₆

t_QUIET

B

t₂

13

16

t₁₁

1

2

3

4

5

6

14

t₅

15

SCLK

t₇

t₃

t₈

DB0

t₄

DOUT

ADD2

ADD1

ADD0

DB11

DB10

DB2

DB1

THREE-STATE

THREE IDENTIFICATION BITS

t₉

t₁₀

ZERO

DIN

WRITE

SEQ

DONTC

ADD2

ADD1

ADD0

DONTC DONTC

DONTC

Figure 28. AD7928 Serial Interface Timing Diagram

C

CS

t_CONVERT

t₆

t₂

13

16

t₁₁

1

2

3

4

5

6

SCLK

14

t₅

15

t₃

t₇

t₈

t₄

ADD2

ADD1

ADD0

DB11

DB10

DB2

DB1

DB0

DOUT

DIN

THREE-STATE

THREE IDENTIFICATION BITS

t₉

t₁₀

4

ZERO

V

0

V

1

V

2

V

3

V

5

IN

V

6

V 7

IN

SEQUENCE 1

SEQUENCE 2

Figure 29. AD7928 Writing to SHADOW Register Timing Diagram

Rev. D | Page 25 of 32

AD7908/AD7918/AD7928

TMS320C541¹

CLKX

AD7908/

AD7918/

AD7928¹

The timer register, for example, is loaded with a value that

provides an interrupt at the required sample interval. When an

interrupt is received, a value is transmitted with TFS/DT (ADC

control word). The TFS is used to control the RFS and thus the

reading of data. The frequency of the serial clock is set in the

SCLKDIV register. When the instruction to transmit with TFS

is given (that is, AX0 = TX0), the state of the SCLK is checked.

The DSP waits until the SCLK has gone high, low, and high

before transmission can start. If the timer and SCLK values are

chosen, such that the instruction to transmit occurs on or near

the rising edge of SCLK, then the data can be transmitted or it

can wait until the next clock edge.

SCLK

CLKR

DR

DOUT

DIN

DT

FSX

FSR

CS

V

DRIVE

1

ADDITIONAL PINS REMOVED FOR CLARITY.

V

DD

Figure 30. Interfacing to the TMS320C541

AD7908/AD7918/AD7928 to ADSP-21xx

For example, if the ADSP-2189 had a 20 MHz crystal such that

it had a master clock frequency of 40 MHz, then the master

cycle time would be 25 ns. If the SCLKDIV register was loaded

with the value 3, then an SCLK of 5 MHz is obtained, and eight

master clock periods elapse for every one SCLK period.

Depending on the throughput rate selected, if the timer register

is loaded with the value, say 803 (803 + 1 = 804), 100.5 SCLKs

occur between interrupts and subsequently between transmit

instructions. This situation results in nonequidistant sampling

as the transmit instruction is occurring on a SCLK edge. If the

number of SCLKs between interrupts is a whole integer figure

of N, then equidistant sampling is implemented by the DSP.

The ADSP-21xx family of DSPs are interfaced directly to the

AD7908/AD7918/AD7928 without any glue logic required. The

V_DRIVEpin of the AD7908/AD7918/AD7928 takes the same

supply voltage as that of the ADSP-21xx. This allows the ADC

to operate at a higher voltage than the serial interface, that is,

ADSP-21xx, if necessary.

The SPORT0 control register should be set up as follows:

TFSW = RFSW = 1, alternate framing

INVRFS = INVTFS = 1, active low frame signal

DTYPE = 00, right justify data

SLEN = 1111, 16-bit data-words

ISCLK = 1, internal serial clock

TFSR = RFSR = 1, frame every word

IRFS = 0

AD7908/AD7918/AD7928 to DSP563xx

The connection diagram in Figure 32 shows how the

AD7908/AD7918/AD7928 can be connected to the synchronous

serial interface (ESSI) of the DSP563xx family of DSPs from

Motorola. Each ESSI (two on board) is operated in synchronous

mode (SYN bit in CRB = 1) with internally generated word

length frame sync for both Tx and Rx (Bit FSL1 = 0 and

Bit FSL0 = 0 in CRB). Normal operation of the ESSI is selected

by making MOD = 0 in the CRB. Set the word length to 16 by

setting Bit WL1 = 1 and Bit WL0 = 0 in CRA. The FSP bit in the

CRB should be set to 1 so the frame sync is negative. It should

be noted that for signal processing applications, it is imperative

that the frame synchronization signal from the DSP563xx

provides equidistant sampling.

ITFS = 1

The connection diagram is shown in Figure 31. The ADSP-21xx

has the TFS and RFS of the SPORT tied together, with TFS set

as an output and RFS set as an input. The DSP operates in

alternate framing mode and the SPORT control register is set

up as described. The frame synchronization signal generated on

CS

the TFS is tied to , as with all signal processing applications

where equidistant sampling is necessary. However, in this

example the timer interrupt is used to control the sampling rate

of the ADC, and under certain conditions equidistant sampling

cannot be achieved.

ADSP-21xx¹

AD7908/

In the example shown in Figure 32, the serial clock is taken

from the ESSI so the SCK0 pin must be set as an output, SCKD

= 1. The V_DRIVEpin of the AD7908/AD7918/AD7928 takes the

same supply voltage as that of the DSP563xx. This allows the

ADC to operate at a higher voltage than the serial interface, that

is, DSP563xx, if necessary.

AD7918/

AD7928¹

SCLK

DOUT

CS

SCLK

DR

RFS

TFS

DT

DIN

V

DRIVE

1

ADDITIONAL PINS REMOVED FOR CLARITY.

V

DD

Figure 31. Interfacing to the ADSP-21xx

Rev. D | Page 26 of 32

AD7908/AD7918/AD7928

DSP563xx¹

supply line. Fast switching signals, like clocks, should be

shielded with digital ground to avoid radiating noise to other

sections of the board, and clock signals should never be run

near the analog inputs. Avoid crossover of digital and analog

signals. Traces on opposite sides of the board should run at

right angles to each other. This reduces the effects of

AD7908/

AD7918/

AD7928¹

SCK

SCLK

SRD

DOUT

DIN

STD

SC2

CS

feedthrough through the board. A microstrip technique is by far

the best, but is not always possible with a double sided board. In

this technique, the component side of the board is dedicated to

ground planes while signals are placed on the solder side.

V

DRIVE

1

ADDITIONAL PINS REMOVED FOR CLARITY.

V

DD

Figure 32. Interfacing to the DSP563xx

Good decoupling is also important. All analog supplies should

be decoupled with 10 μF tantalum in parallel with 0.1 μF

capacitors to AGND. To achieve the best performance from

these decoupling components, they must be placed as close as

possible to the device, ideally right up against the device. The

0.1 μF capacitors should have low effective series resistance

(ESR) and effective series inductance (ESI), such as the

common ceramic types or surface mount types, which provide a

low impedance path to ground at high frequencies to handle

transient currents due to internal logic switching.

APPLICATION HINTS

Grounding and Layout

The AD7908/AD7918/AD7928 have very good immunity to

noise on the power supplies, as can be seen by the PSRR vs.

Supply Ripple Frequency plot, Figure 6. However, care should

still be taken with regard to grounding and layout.

The printed circuit board that houses the AD7908/AD7918/

AD7928 should be designed so that the analog and digital

sections are separated and confined to certain areas of the

board. This facilitates the use of ground planes that can be

separated easily. A minimum etch technique is generally best

for ground planes as it gives the best shielding.

Evaluating the AD7908/AD7918/AD7928 Performance

The recommended layout for the AD7908/AD7918/AD7928 is

outlined in the AD7908/AD7918/AD7928 evaluation board.

The evaluation board package includes a fully assembled and

tested evaluation board, documentation, and software for

controlling the board from the PC via the eval-board controller.

All four AGND pins of the AD7908/AD7918/AD7928 should

be sunk in the AGND plane. If the AD7908/AD7918/AD7928

is in a system where multiple devices require an AGND to

DGND connection, the connection should be made at only one

point in the plane. Using a star ground point, the connection

should be established as close as possible to the AD7908/

AD7918/AD7928.

The eval-board controller can be used in conjunction with the

AD7908/AD7918/AD7928 evaluation board, as well as many

other Analog Devices evaluation boards ending in the CB

designator, to demonstrate/evaluate the ac and dc performance

of the AD7908/AD7918/AD7928.

Avoid running digital lines under the device, as these couple

noise onto the die. The analog ground plane should be allowed

to run under the AD7908/AD7918/AD7928 to avoid noise

coupling. The power supply lines to the AD7908/AD7918/

AD7928 should use as large a trace as possible to provide low

impedance paths and reduce the effects of glitches on the power

The software allows the user to perform ac (fast Fourier

transform) and dc (histogram of codes) tests on the

AD7908/AD7918/AD7928. The software and documentation

are on a CD shipped with the evaluation board.

Rev. D | Page 27 of 32

AD7908/AD7918/AD7928

OUTLINE DIMENSIONS

6.60

6.50

6.40

20

11

10

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20 MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

COPLANARITY

0.10

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-153-AC

Figure 33. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

Rev. D | Page 28 of 32

AD7908/AD7918/AD7928

ORDERING GUIDE

Model^{1, 2, 3, 4}

AD7908BRU-REEL

AD7908BRU-REEL7

AD7908BRUZ

AD7908BRUZ-REEL

AD7908BRUZ-REEL7

AD7908WYRUZ-REEL7

AD7918BRU-REEL7

AD7918BRUZ

AD7918BRUZ-REEL

AD7918BRUZ-REEL7

AD7918WYRUZ-REEL7

AD7928BRU

Temperature Range

−40°C to +85°C

−40°C to +125°C

−40°C to +85°C

−40°C to +125°C

−40°C to +85°C

−40°C to +125°C

Linearity Error (LSB)⁵

Package Description

Package Option

RU-20

0.2

0.5

1

20-Lead TSSOP

Evaluation Board

Controller Board

RU-20

AD7928BRU-REEL

AD7928BRUZ

1

AD7928BRUZ-REEL

AD7928BRUZ-REEL7

AD7928WYRUZ-REEL7

EVAL-AD79x8CBZ

EVAL-CONTROL BRD

1

¹Z = RoHS Compliant Part.

²W = Qualified for Automotive Applications.

³The EVAL-AD79x8CBZ can be used as a standalone evaluation board or in conjunction with the evaluation controller board for evaluation/demonstration purposes.

The board comes with one chip of each the AD7908, AD7918, and AD7928.

⁴The EVAL-CONTROL BRD is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To

order a complete evaluation kit, order the particular ADC evaluation board, such as the EVAL-AD79x8CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the

relevant evaluation board technical note for more information.

⁵Linearity error here refers to integral linearity error.

AUTOMOTIVE PRODUCTS

The AD72x8W models are available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

Rev. D | Page 29 of 32

AD7908/AD7918/AD7928

NOTES

Rev. D | Page 30 of 32

AD7908/AD7918/AD7928

NOTES

Rev. D | Page 31 of 32

AD7908/AD7918/AD7928

NOTES

registered trademarks are the property of their respective owners.

D03089-0-12/10(D)

Rev. D | Page 32 of 32


型号：	AD7908WYRUZ-REEL7
厂家：	ADI
描述：	8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs 8通道， 1 MSPS ， 8位/ 10位/ 12位ADC 转换器模数转换器光电二极管
文件：	总32页 (文件大小：456K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7908WYRUZ-REEL7 [ADI]

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