AD7927BRU-REEL [ADI]
8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP;
| 型号： | AD7927BRU-REEL |
| 厂家： | 
ADI |
| 描述： | 8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP 光电二极管 转换器 |
| 文件： | 总28页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Channel, 200 kSPS, 12-Bit ADC
with Sequencer in 20-Lead TSSOP
AD7927
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AV
DD
Fast throughput rate: 200 kSPS
Specified for AVDD of 2.7 V to 5.25 V
Low power
3.6 mW maximum at 200 kSPS with 3 V supply
7.5 mW maximum at 200 kSPS with 5 V supply
8 (single-ended) inputs with sequencer
Wide input bandwidth
REF
IN
V
0
IN
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
INPUT
MUX
70 dB minimum SINAD at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface SPI™-, QSPI™-, MICROWIRE™-,
DSP-compatible
V
7
IN
SCLK
DOUT
DIN
CONTROL LOGIC
SEQUENCER
Shutdown mode: 0.5 μA maximum
20-lead TSSOP
CS
AD7927
V
DRIVE
GENERAL DESCRIPTION
AGND
Figure 1.
The AD7927 is a 12-bit, high speed, low power, 8-channel,
successive approximation ADC. The part operates from a
single 2.7 V to 5.25 V power supply and features throughput
rates up to 200 kSPS. The part contains a low noise, wide
bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 8 MHz.
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
The AD7927 offers up to 200 kSPS throughput rates. At the
maximum throughput rate with 3 V supplies, the AD7927
dissipates 3.6 mW of power maximum.
The conversion process and data acquisition are controlled using
2. Eight Single-Ended Inputs with a Channel Sequencer.
A consecutive sequence of channels can be selected on
which the ADC cycles and converts.
CS
and the serial clock signal, allowing the device to easily interface
with microprocessors or DSPs. The input signal is sampled on the
CS
falling edge of
and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
3. Single-Supply Operation with VDRIVE Function.
The AD7927 operates from a single 2.7 V to 5.25 V supply.
The VDRIVE function allows the serial interface to connect
directly to either 3 V or 5 V processor systems independent
The AD7927 uses advanced design techniques to achieve
very low power dissipation at maximum throughput rates. At
maximum throughput rates, the AD7927 consumes 1.2 mA
maximum with 3 V supplies; with 5 V supplies, the current
consumption is 1.5 mA maximum.
of AVDD
.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through the
serial clock speed increase. The part also features various
shutdown modes to maximize power efficiency at lower
throughput rates. Current consumption is 0.5 μA maxi-
mum when in full shutdown.
Through the configuration of the control register, the analog
input range for the part can be selected as 0 V to REFIN or 0 V
to 2 × REFIN, with either straight binary or twos complement
output coding. The AD7927 features eight single-ended analog
inputs with a channel sequencer to allow a preprogrammed
selection of channels to be converted sequentially.
5. No Pipeline Delay.
The conversion time for the AD7927 is determined by the
SCLK frequency, as this is also used as the master clock to
control the conversion. The conversion time may be as short
as 800 ns with a 20 MHz SCLK.
The part features a standard successive approximation ADC
CS
with a
input pin, which allows for accurate control of
each sampling instant.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2008 Analog Devices, Inc. All rights reserved.
AD7927
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Input Selection.............................................................. 17
Digital Inputs .............................................................................. 17
VDRIVE ............................................................................................ 18
The Reference ............................................................................. 18
Modes of Operation ....................................................................... 19
Normal Mode (PM1 = PM0 = 1) ............................................. 19
Full Shutdown (PM1 = 1, PM0 = 0) ........................................ 19
Auto Shutdown (PM1 = 0, PM0 = 1)....................................... 20
Powering Up the AD7927 ......................................................... 21
Power vs. Throughput Rate....................................................... 21
Serial Interface ................................................................................ 22
Writing Between Conversions.................................................. 22
Microprocessor Interfacing........................................................... 24
AD7927 to TMS320C541.......................................................... 24
AD7927 to ADSP-21xx.............................................................. 24
AD7927 to DSP563xx................................................................ 25
Application Hints ........................................................................... 26
Grounding and Layout .............................................................. 26
Evaluating the AD7927 Performance...................................... 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ........................................... 10
Control Register.............................................................................. 12
Sequencer Operation...................................................................... 13
Shadow Register.............................................................................. 14
Circuit Information.................................................................... 15
Converter Operation.................................................................. 15
Analog Input ............................................................................... 15
ADC Transfer Function............................................................. 16
Handling Bipolar Input Signals ................................................ 16
Typical Connection Diagram........................................................ 17
REVISION HISTORY
12/08—Rev. A to Rev. B
Changes to ESD Parameter, Table 3 ............................................... 6
Changes to Ordering Guide .......................................................... 27
1/07—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Updated Layout................................................................................. 8
Updated Layout............................................................................... 10
Changes to Figure 12 Caption....................................................... 14
Changes to Figure 13 Caption....................................................... 15
Changes to Ordering Guide .......................................................... 27
1/03—Revision 0: Initial Version
Rev. B | Page 2 of 28
AD7927
SPECIFICATIONS
AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz; TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
B Version1
Unit
Test Conditions/Comments
fIN = 50 kHz sine wave, fSCLK = 20 MHz
@ 5 V
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)2
70
dB min
dB min
dB min
dB max
dB max
dB max
dB max
69
70
−77
−73
−78
−76
@ 3 V Typically 70 dB
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD) 2
@ 5 V Typically −84 dB
@ 3 V Typically −77 dB
@ 5 V Typically −86 dB
@ 3 V Typically −80 dB
fA = 40.1 kHz, fB = 41.5 kHz
Peak Harmonic or Spurious Noise
(SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
−90
−90
10
dB typ
dB typ
ns typ
Aperture Delay
Aperture Jitter
50
ps typ
Channel-to-Channel Isolation2
−82
8.2
1.6
dB typ
MHz typ
MHz typ
fIN = 400 kHz
@ 3 dB
Full Power Bandwidth
@ 0.1 dB
DC ACCURACY2
Resolution
12
Bits
Integral Nonlinearity
Differential Nonlinearity
0 V to REFIN Input Range
Offset Error
Offset Error Match
Gain Error
1
LSB max
LSB max
−0.9/+1.5
Guaranteed no missed codes to 12 bits
Straight binary output coding
Typically 0.5 LSB
8
LSB max
LSB max
LSB max
LSB max
0.5
1.5
0.5
Gain Error Match
0 V to 2 × REFIN Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
ANALOG INPUT
−REFIN to +REFIN biased about REFIN with
Twos complement output coding
1.5
0.5
8
0.5
1
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Typically 0.8 LSB
0.5
Input Voltage Ranges
0 to REFIN
V
RANGE bit set to 1
0 to 2 × REFIN
1
20
V
RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
fSAMPLE = 200 kSPS
DC Leakage Current
Input Capacitance
μA max
pF typ
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
2.5
1
36
V
1ꢀ specified performance
μA max
kΩ typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 × VDRIVE
0.3 × VDRIVE
1
10
V min
V max
μA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
3
Input Capacitance, CIN
Rev. B | Page 3 of 28
AD7927
Parameter
B Version1
Unit
Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDRIVE − 0.2
0.4
1
V min
ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V
ISINK = 200 μA
V max
μA max
pF max
10
Straight (Natural) Binary
Twos Complement
Coding bit set to 1
Coding bit set to 0
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
800
300
300
200
ns max
ns max
ns max
kSPS max
16 SCLK cycles with SCLK at 20 MHz
Sine wave input
Full-scale step input
Throughput Rate
POWER REQUIREMENTS
AVDD
See Serial Interface section
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
4
IDD
Digital inputs = 0 V or VDRIVE
During Conversion
2.7
2
600
1.5
1.2
mA max
mA max
μA typ
mA max
mA max
μA typ
μA typ
μA max
μA max
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
AVDD = 2.7 V to 5.25 V, SCLK on or off
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
SCLK on or off (20 nA typ)
Normal Mode (Static)
Normal Mode (Operational) fSAMPLE = 200 kSPS
Using Auto Shutdown Mode fSAMPLE = 200 kSPS 900
650
Auto Shutdown (Static)
Full Shutdown Mode
Power Dissipation4
0.5
0.5
SCLK on or off (20 nA typ)
Normal Mode (Operational)
7.5
3.6
2.5
1.5
2.5
1.5
mW max
mW max
μW max
μW max
μW max
μW max
AVDD = 5 V, fSCLK = 20 MHz
AVDD = 3 V, fSCLK = 20 MHz
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
Auto Shutdown (Static)
Full Shutdown Mode
AVDD = 3 V
1 Temperature ranges as follows: B Version: −40°C to +85°C.
2 See Terminology section.
3 Sample tested @ 25°C to ensure compliance.
4 See Power vs. Throughput Rate section.
Rev. B | Page 4 of 28
AD7927
TIMING SPECIFICATIONS1
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Limit at TMIN, TMAX AD7927
Parameter
AVDD = 3 V
AVDD = 5 V
Unit
Description
2
fSCLK
10
20
10
20
kHz min
MHz max
tCONVERT
tQUIET
16 × tSCLK
50
16 × tSCLK
50
ns min
Minimum quiet time required between CS rising edge and start of
next conversion
t2
10
10
ns min
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
μs max
CS to SCLK setup time
3
t3
35
30
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulsewidth
SCLK high pulsewidth
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Sixteenth SCLK falling edge to CS high
Power-up time from full power-down/auto shutdown mode
3
t4
40
0.4 × tSCLK
0.4 × tSCLK
10
15/45
10
5
20
1
40
0.4 × tSCLK
0.4 × tSCLK
10
15/35
10
5
20
1
t5
t6
t7
t8
t9
t10
t11
t12
4
1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10ꢀ to 90ꢀ of AVDD) and timed from a voltage level of 1.6 V,
(see Figure 2). The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE
.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means the time, quoted in the t8 timing characteristics, is the true bus relinquish time
of the part and is independent of the bus loading.
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. B | Page 5 of 28
AD7927
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
AVDD to AGND
VDRIVE to AGND
Analog Input Voltage to AGND
Digital Input Voltage to AGND
Digital Output Voltage to AGND
REFIN to AGND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature
TSSOP, Power Dissipation
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
−0.3 V to +7 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to +7 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
10 mA
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
450 mW
143°C/W (TSSOP)
45°C/W (TSSOP)
215°C
220°C
1.5 kV
Infrared (15 sec)
ESD
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. B | Page 6 of 28
AD7927
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
20
19
18
17
16
15
14
13
12
11
SCLK
DIN
AGND
V
DRIVE
3
CS
DOUT
AGND
AD7927
TOP VIEW
(Not to Scale)
4
AGND
5
AV
AV
V
V
V
V
V
V
0
1
2
3
4
5
DD
DD
IN
IN
IN
IN
IN
IN
6
7
REF
IN
8
AGND
9
V
V
7
6
IN
10
IN
Figure 3. 20-Lead TSSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is
also used as the clock source for the AD7927 conversion process.
2
DIN
Data In. Logic input. Data to be written to the AD7927 control register is provided on this input and is clocked
into the register on the falling edge of SCLK (see the Control Register section).
3
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7927 and framing the serial data transfer.
4, 8, 17, 20
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7927. All analog input signals
and any external reference signal should be referred to this AGND voltage. All AGND pins should be
connected together.
5, 6
AVDD
Analog Power Supply Input. The AVDD range for the AD7927 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN
range, AVDD should be from 4.75 V to 5.25 V.
7
REFIN
Reference Input for the AD7927. An external reference must be applied to this input. The voltage range for
the external reference is 2.5 V 1ꢀ for specified performance.
16 to 9
VIN0 to VIN7
Analog Input 0 through Analog Input 7. Eight single-ended analog input channels that are multiplexed into
the on-chip track-and-hold. The analog input channel to be converted is selected by using the address bits
(ADD2 through ADD0) of the control register. ADD2 through ADD0, in conjunction with the SEQ and
SHADOW bits, allow the sequencer to be programmed. The input range for all input channels can extend
from 0 V to REFIN or 0 V to 2 × REFIN, as selected via the RANGE bit in the control register. Any unused input
channels should be connected to AGND to avoid noise pickup.
18
19
DOUT
Data Out. Logic output. The conversion result from the AD7927 is provided on this output as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7927
consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to,
followed by the 12 bits of conversion data (MSB first). The output coding may be selected as straight binary or
twos complement via the CODING bit in the control register.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of
the AD7927 operates.
VDRIVE
Rev. B | Page 7 of 28
AD7927
TERMINOLOGY
Integral Nonlinearity (INL)
Negative Gain Error
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition. Figure 9 shows a typical INL
plot for the AD7927.
This applies when using the twos complement output coding
option, in particular to the 2 × REFIN input range with −REFIN
to +REFIN biased about the REFIN point. It is the deviation of
the first code transition (100 . . . 000) to (100 . . . 001) from the
ideal (that is, −REFIN + 1 LSB) after the zero code error has been
adjusted out.
Differential Nonlinearity (DNL)
Negative Gain Error Match
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Figure 10 shows a typical DNL plot for the AD7927.
This is the difference in negative gain error between any two
channels.
Channel-to-Channel Isolation
Offset Error
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 400 kHz sine wave signal to all seven nonselected input
channels and determining how much that signal is attenuated
in the selected channel with a 50 kHz signal. The figure given is
the worst case across all eight channels for the AD7927.
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
Power Supply Rejection (PSR)
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (that is, REFIN − 1 LSB) after the
offset error has been adjusted out.
Variations in power supply affect the full-scale transition,
but not the converter’s linearity. Power supply rejection is the
maximum change in full-scale transition point due to a change
in power supply voltage from the nominal value (see the Typical
Performance Characteristics section).
Gain Error Match
This is the difference in gain error between any two channels.
Power Supply Rejection Ration (PSRR)
Zero Code Error
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency (f) to the
power of a 200 mV p-p sine wave applied to the ADC AVDD
supply of frequency (fS):
This applies when using the twos complement output coding
option, in particular to the 2 × REFIN input range with −REFIN
to +REFIN biased about the REFIN point. It is the deviation of
the midscale transition (all 0s to all 1s) from the ideal VIN
voltage, that is, REFIN − 1 LSB.
PSRR(dB) = 10log(Pf/PfS)
where:
Zero Code Error Match
Pf is equal to the power at Frequency f in ADC output.
PfS is equal to the power at Frequency fS coupled onto the
This is the difference in zero code error between any two
channels.
ADC AVDD
.
Positive Gain Error
Here a 200 mV p-p sine wave is coupled onto the AVDD supply.
Figure 6 shows the power supply rejection ratio vs. supply ripple
frequency for the AD7927 with no decoupling.
This applies when using the twos complement output coding
option, in particular to the 2 × REFIN input range with −REFIN
to +REFIN biased about the REFIN point. It is the deviation of the
last code transition (011. . .110) to (011 . . . 111) from the ideal
(that is, +REFIN − 1 LSB) after the zero code error has been
adjusted out.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode at the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within 1 LSB, after the end of conversion.
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
Rev. B | Page 8 of 28
AD7927
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7927, it is defined as:
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by
V22 +V32 +V42 +V52 +V62
THD(dB) = 20log
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Signal-to-(Noise + Distortion) = (6.02N + 1.76)dB
Figure 7 shows a graph of total harmonic distortion vs. analog
input frequency for various supply voltages, and Figure 8 shows
a graph of total harmonic distortion vs. analog input frequency
for various source impedances (see the Analog Input section).
Thus, for a 12-bit converter, this is 74 dB. Figure 5 shows the
signal-to-(noise + distortion) ratio performance vs. input fre-
quency for various supply voltages while sampling at 200 kSPS
with an SCLK of 20 MHz.
Rev. B | Page 9 of 28
AD7927
TYPICAL PERFORMANCE CHARACTERISTICS
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
AV = 5V
DD
200mV p-p SINE WAVE ON AV
REF = 2.5V, 1µF CAPACITOR
IN
4096 POINT FFT
AV = 4.75V
DD
DD
fSAMPLE = 200kSPS
fIN = 50kHz
SINAD = 70.714dB
THD = –82.853dB
SFDR = –84.815dB
–10
T
= 25°C
A
–30
–50
–70
–90
–110
0
20
40
60
80
100 120 140 160 180 200
0
10
20
30
40
50
60
70
80
90
100
SUPPLY RIPPLE FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 4. Dynamic Performance at 200 kSPS
Figure 6. PSRR vs. Supply Ripple Frequency
75
70
65
60
–50
–55
–60
–65
–70
–75
–80
–85
–90
fSAMPLE = 200kSPS
= 25°C
RANGE = 0 TO REF
IN
T
A
AV =V
AV =V
DD
= 5.25V
= 4.75V
DD
DRIVE
DRIVE
AV =V
DD
AV =V
DD
= 3.6V
= 2.7V
DRIVE
DRIVE
AV =V
DD
= 2.7V
DRIVE
AV =V
DD
= 3.6V
DRIVE
fSAMPLE = 200kSPS
= 25°C
RANGE = 0 TO REF
IN
T
A
AV =V
DD
= 4.75V
DRIVE
AV =V
= 5.25V
100
DD DRIVE
0
100
10
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 5. SINAD vs. Analog Input Frequency for Various Supply Voltages
at 200 kSPS
Figure 7. THD vs. Analog Input Frequency for Various Supply Voltages
at 200 kSPS
Rev. B | Page 10 of 28
AD7927
–55
–60
–65
–70
–75
–80
–85
–90
–95
fSAMPLE = 200kSPS
= 25°C
AV = 5.25V
DD
1.0
0.8
T
AV =V
DD DRIVE
= 5V
A
T
= 25°C
A
RANGE = 0TO REF
IN
0.6
0.4
R
= 1000Ω
IN
0.2
0
–0.2
R
= 100Ω
R
= 10Ω
IN
IN
–0.4
–0.6
R
= 50Ω
IN
–0.8
–1.0
10
100
INPUT FREQUENCY (kHz)
0
512
1024
1536
2048
2560
3072
3584
4096
CODE
Figure 8. THD vs. Analog Input Frequency for Various Source Impedances
Figure 10. Typical DNL
1.0
AV =V
DD DRIVE
= 5V
0.8
T
= 25°C
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
512
1024 1536
2048
2560 3072
3584 4096
CODE
Figure 9. Typical INL
Rev. B | Page 11 of 28
AD7927
CONTROL REGISTER
The control register on the AD7927 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7927 on the falling edge of
SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on
the DIN line corresponds to the AD7927 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only
CS
the information provided on the first 12 falling clock edges (after
bit in the data stream. The bit functions are outlined in Table 5.
falling edge) is loaded to the control register. MSB denotes the first
Table 5. Control Register Bit Functions
MSB
LSB
WRITE
SEQ
DONTC
ADD2
ADD1
ADD0
PM1
PM0
SHADOW
DONTC
RANGE
CODING
Table 6. Control Register Bit Function Description
Bit
Mnemonic
Description
11
WRITE
The value written to this bit of the control register determines whether the following 11 bits are loaded to
the control register. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, then the
remaining 11 bits are not loaded to the control register and it remains unchanged.
10
9
SEQ
The SEQ bit in the control register is used in conjunction with the SHADOW bit to control the use of the sequencer
function and access the shadow register (see Table 10).
Don’t care.
DONTC
8 to
6
ADD2 to
ADD0
These three address bits are loaded at the end of the present conversion and select which analog input channel
is to be converted in the next serial transfer, or they may select the final channel in a consecutive sequence as
described in Table 9. The selected input channel is decoded as shown in Table 7. The address bits corresponding
to the conversion result are also output on DOUT prior to the 12 bits of data (see the Serial Interface section). The
next channel to be converted on is selected by the mux on the 14th SCLK falling edge.
5, 4
3
PM1, PM0
SHADOW
Power Management Bits. These two bits decode the mode of operation of the AD7927 as shown in Table 8.
The SHADOW bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer
function and access the shadow register (see Table 10).
2
1
DONTC
RANGE
Don’t care.
This bit selects the analog input range to be used on the AD7927. If it is set to 0, the analog input range extends
from 0 V to 2 × REFIN. If it is set to 1, the analog input range extends from 0 V to REFIN (for the next conversion). For
the 0 V to 2 × REFIN range, AVDD = 4.75 V to 5.25 V.
0
CODING
This bit selects the type of output coding the AD7927 uses for the conversion result. If this bit is set to 0, the
output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight
binary (for the next conversion).
Table 7. Channel Selection
ADD2
ADD1
ADD0
Analog Input Channel
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
Table 8. Power Mode Selection
PM1 PM0 Mode
1
1
Normal Operation. In this mode, the AD7927 remains in full power mode, regardless of the status of any of the logic inputs.
This mode allows the fastest possible throughput rate from the AD7927.
1
0
Full Shutdown. In this mode, the AD7927 is in full shutdown mode with all circuitry on the AD7927 powering down. The
AD7927 retains the information in the control register while in full shutdown. The part remains in full shutdown until these
bits are changed.
0
0
1
0
Auto Shutdown. In this mode, the AD7927 automatically enters full shutdown mode at the end of each conversion when the
control register is updated. Wake-up time from full shutdown is 1 μs and the user should ensure that 1 μs has elapsed before
attempting to perform a valid conversion on the part in this mode.
Invalid Selection. This configuration is not allowed.
Rev. B | Page 12 of 28
AD7927
SEQUENCER OPERATION
The configuration of the SEQ and SHADOW bits in the control register allows the user to select a particular mode of operation of the
sequencer function. Table 9 outlines the four modes of operation of the sequencer.
Table 9. Sequence Selection
SEQ SHADOW
Sequence Type
0
0
0
1
This configuration means that the sequence function is not used. The analog input channel selected for each
individual conversion is determined by the contents of the channel address bits, ADD0 through ADD2, in each
prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without
the sequencer function being used, where each write to the AD7927 selects the next channel for conversion (see
Figure 11).
This configuration selects the shadow register for programming. The following write operation loads the contents of
the shadow register. This programs the sequence of channels converted on continuously with each successive valid
CS falling edge (see the Shadow Register section, Table 10, and Figure 12). The channels selected need not be
consecutive.
1
1
0
1
If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of
the WRITE operation. This allows other bits in the control register to be altered between conversions while in a
sequence, without terminating the cycle.
This configuration is used in conjunction with the channel address bits, ADD2 to ADD0, to program continuous
conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by
the channel address bits in the control register (see Figure 13).
Rev. B | Page 13 of 28
AD7927
SHADOW REGISTER
Table 10. Shadow Register Bit Functions
MSB
LSB
VIN7
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
--------------------------------SEQUENCE ONE--------------------------------
--------------------------------SEQUENCE TWO--------------------------------
The shadow register on the AD7927 is a 16-bit, write-only register.
Data is loaded from the DIN pin of the AD7927 on the falling
edge of SCLK. The data is transferred on the DIN line at the
same time that a conversion result is read from the part. This
requires 16 serial clock falling edges for the data transfer. The
information is clocked into the shadow register, provided that
the SEQ and SHADOW bits were set to 0, 1, respectively, in the
previous write to the control register. MSB denotes the first bit
in the data stream. Each bit represents an analog input from
Channel 0 to Channel 7. Through programming the shadow
register, two sequences of channels may be selected, through
which the AD7927 cycles with each consecutive conversion
after the write to the shadow register. Sequence One is per-
formed first and then Sequence Two. If the user does not
wish to perform a second sequence option, then all 0s must be
written to the last eight LSBs of the shadow register. To select a
sequence of channels, the associated channel bit must be set for
each analog input. The AD7927 continuously cycles through
the selected channels in ascending order, beginning with the
lowest channel, until a write operation occurs (that is, the WRITE
bit is set to 1) with the SEQ and SHADOW bits configured in
any way except 1, 0 (see Table 9). The bit functions are outlined
in Table 10.
Figure 12 shows how to program the AD7927 to continuously
convert on a particular sequence of channels. To exit this mode
of operation and revert back to the traditional mode of opera-
tion of a multichannel ADC (as outlined in Figure 11), ensure
that the WRITE bit = 1 and the SEQ = SHADOW = 0 on the
next serial transfer. Figure 13 shows how a sequence of consecu-
tive channels can be converted on without having to program
the shadow register or write to the part on each serial transfer.
Again, to exit this mode of operation and revert back to the
traditional mode of operation of a multichannel ADC (as
outlined in Figure 11), ensure the WRITE bit = 1 and the
SEQ = SHADOW = 0 on the next serial transfer.
POWER-ON
DUMMY CONVERSION
DIN = ALL 1s
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
CS
SELECT CHANNEL A2 TO CHANNEL A0
FOR CONVERSION.
SEQ = 0, SHADOW = 1
DOUT: CONVERSION RESULT FROM PREVIOUSLY
SELECTED CHANNEL A2 TO CHANNEL A0.
POWER-ON
CS
DIN: WRITE TO SHADOW REGISTER, SELECTING
WHICH CHANNELS TO CONVERT ON; CHANNELS
SELECTED NEED NOT BE CONSECUTIVE CHANNELS
DUMMY CONVERSION
DIN = ALL 1s
WRITE BIT = 0
WRITE BIT = 1,
SEQ = 1 SHADOW = 0
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
CONTINUOUSLY
CONVERTS ON THE
SELECTED
SEQUENCE OF
CHANNELS
CONTINUOUSLY
CONVERTS ON THE
SELECTED
SEQUENCE OF
CHANNELS BUT
SELECT CHANNEL A2 TO CHANNEL A0
FOR CONVERSION.
SEQ = SHADOW = 0
CS
CS
ALLOWS RANGE,
CODING, AND SO ON,
TO CHANGE IN THE
CONTROL REGISTER
WITHOUT INTERRUPT-
ING THE SEQUENCE,
PROVIDED SEQ = 1,
SHADOW = 0
FROM
DOUT: CONVERSION RESULT
WRITE BIT = 0
HANNEL
PREVIOUSLY SELECTED C
A2 TO CHANNEL A0.
WRITE BIT = 0
CS
WRITE BIT = 1,
SEQ = SHADOW = 0
EGISTER,
DIN: WRITE TO CONTROL R
WRITE BIT = 1,
NGE, AND POWER MODE.
SELECT CODING, RA
SELECT CHANNEL A2 TO C
FOR CONVERSION.
HANNEL A0
WRITE BIT = 1,
SEQ = 1,
SHADOW = 0
SEQ = SHADOW = 0
Figure 11. SEQ Bit = 0, SHADOW Bit = 0 Flowchart
Figure 12. SEQ and SHADOW Conversion Flowchart to Continuously Convert
a Sequence of Channels
Figure 11 reflects the traditional operation of a multichannel
ADC, where each serial transfer selects the next channel for
conversion. In this mode of operation, the sequencer function
is not used.
Rev. B | Page 14 of 28
AD7927
POWER-ON
CONVERTER OPERATION
The AD7927 is a 12-bit successive approximation ADC based
around a capacitive DAC. The AD7927 can convert analog input
signals in the range 0 V to REFIN or 0 V to 2 × REFIN. Figure 14
and Figure 15 show simplified schematics of the ADC. The ADC
is comprised of control logic, SAR, and a capacitive DAC that
are used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a bal-
anced condition. Figure 14 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in Position A. The comparator
is held in a balanced condition and the sampling capacitor
acquires the signal on the selected VIN channel.
DUMMY CONVERSION
DIN = ALL 1s
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A2 TO CHANNEL A0
FOR CONVERSION.
CS
CS
CS
SEQ = 1, SHADOW = 1
DOUT: CONVERSION RESULT FROM CHANNEL 0
CONTINUOUSLY CONVERTS ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0 UP
TO AND INCLUDING THE PREVIOUSLY SELECTED
A2 TO CHANNEL A0 IN THE CONTROL REGISTER
WRITE BIT = 0
CAPACITIVE
DAC
A
4kΩ
V
V
0
7
IN
CONTINUOUSLY CONVERTS ON THE SELECTED
SEQUENCE OF CHANNELS BUT ALLOWS
RANGE, CODING AND SO ON, TO CHANGE IN THE
CONTROL REGISTER WITHOUT INTERRUPTING
THE SEQUENCE, PROVIDED SEQ = 1, SHADOW = 0
CONTROL
LOGIC
SW1
B
SW2
WRITE BIT = 1,
SEQ = 1,
IN
COMPARATOR
SHADOW = 0
AGND
Figure 13. SEQ and SHADOW Conversion Flowchart to Convert a Sequence of
Consecutive Channels
Figure 14. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 15), SW2
opens and SW1 moves to Position B, causing the comparator
to become unbalanced. The control logic and the capacitive
DAC are used to add and subtract fixed amounts of charge
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 17 and Figure 18 show the ADC transfer
functions.
CIRCUIT INFORMATION
The AD7927 is a high speed, 8-channel, 12-bit, single-supply
ADC. The part can be operated from a 2.7 V to 5.25 V supply.
When operated from either a 5 V or 3 V supply, the AD7927 is
capable of throughput rates of 200 kSPS. The conversion time
may be as short as 800 ns when provided with a 20 MHz clock.
The AD7927 provides the user with an on-chip, track-and-hold
ADC and a serial interface housed in a 20-lead TSSOP. The
AD7927 has eight single-ended input channels with a channel
sequencer, allowing the user to select a channel sequence
CAPACITIVE
DAC
A
4kΩ
V
V
0
7
IN
CONTROL
LOGIC
SW1
CS
through which the ADC can cycle with each consecutive
B
SW2
falling edge. The serial clock input accesses data from the part,
controls the transfer of data written to the ADC, and provides
the clock source for the successive approximation ADC. The
analog input range for the AD7927 is 0 V to REFIN or 0 V to
2 × REFIN, depending on the status of Bit 1 in the control register.
For the 0 to 2 × REFIN range, the part must be operated from a
4.75 V to 5.25 V supply.
IN
COMPARATOR
AGND
Figure 15. ADC Conversion Phase
ANALOG INPUT
Figure 16 shows an equivalent circuit of the analog input struc-
ture of the AD7927. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 300 mV. This causes these diodes to become forward
biased and start conducting current into the substrate. 10 mA is
the maximum current these diodes can conduct without caus-
ing irreversible damage to the part. Capacitor C1, in Figure 16
is typically about 4 pF and can primarily be attributed to pin
capacitance. The Resistor R1 is a lumped component made up
of the on resistance of a switch (track-and-hold switch) and also
includes the on resistance of the input multiplexer. The total
resistance is typically about 400 Ω. The capacitor, C2, is the
ADC sampling capacitor and has a capacitance of 30 pF typically.
The AD7927 provides flexible power management options
to allow the user to achieve the best power performance for a
given throughput rate. These options are selected by program-
ming the power management bits, PM1 and PM0, in the control
register.
Rev. B | Page 15 of 28
AD7927
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC low-
pass filter on the relevant analog input pin. In applications where
harmonic distortion and signal-to-noise ratio are critical, the
analog input should be driven from a low impedance source. Large
source impedances significantly affect the ac performance of the
ADC. This may necessitate the use of an input buffer amplifier.
The choice of the op amp is a function of the particular application.
111…111
111…110
•
•
111…000
•
011…111
1LSB = V
REF
/4096
•
•
000…010
000…001
000…000
1LSB
+V
– 1LSB
REF
ANALOG INPUT
0V
When no amplifier is used to drive the analog input, limit
the source impedance to low values. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD increases as the source impedance
increases, and performance degrades (see Figure 8).
NOTES
V
IS EITHER REF OR 2 × REF .
IN IN
REF
Figure 17. Straight Binary Transfer Characteristic
AV
DD
011…111
011…110
C2
30pF
•
•
D1
D2
R1
V
IN
000…001
000…000
111…111
C1
4pF
CONVERSION PHASE: SWITCH OPEN
TRACK PHASE: SWITCH CLOSED
•
•
1LSB = 2 × V
REF
/4096
Figure 16. Equivalent Analog Input Circuit
100…010
100…001
100…000
ADC TRANSFER FUNCTION
–V
+ 1LSB
+V
– 1LSB
REF
REF
The output coding of the AD7927 is either straight binary
or twos complement, depending on the status of the LSB in
the control register. The designed code transitions occur at
successive LSB values (that is, 1 LSB, 2 LSBs, and so forth).
The LSB size is REFIN/4096 for the AD7927. The ideal transfer
characteristic for the AD7927 when straight binary coding is
selected is shown in Figure 17, and the ideal transfer characteristic
for the AD7927 when twos complement coding is selected is
shown in Figure 18.
V
– 1LSB
REF
ANALOG INPUT
Figure 18. Twos Complement Transfer Characteristic with REFIN REFIN
Input Range
HANDLING BIPOLAR INPUT SIGNALS
Figure 19 shows how useful the combination of the 2 × REFIN
input range and the twos complement output coding scheme
is for handling bipolar input signals. If the bipolar input signal
is biased about REFIN and twos complement output coding is
selected, then REFIN becomes the zero code point, −REFIN is
negative full scale and +REFIN becomes positive full scale, with
a dynamic range of 2 × REFIN.
V
DD
V
REF
0.1µF
AV
DD
REF
IN
V
DD
V
DRIVE
R4
DSP/
MICROPROCESSOR
AD7927
V
R3
R2
TWOS
COMPLEMENT
V
V
0
DOUT
IN
V
0V
011…111
(= 2 × REF
)
+REF
REF
IN
IN
IN
7
IN
R1
R1 = R2 = R3 = R4
000…000
100…000
(= 0V)
–REF
IN
Figure 19. Handling Bipolar Signals
Rev. B | Page 16 of 28
AD7927
TYPICAL CONNECTION DIAGRAM
Figure 20 shows a typical connection diagram for the AD7927.
In this setup, the AGND pin is connected to the analog ground
plane of the system. In Figure 20, REFIN is connected to a decoup-
led 2.5 V supply from a reference source, the AD780, to provide
an analog input range of 0 V to 2.5 V (if the RANGE bit is 1)
or 0 V to 5 V (if the RANGE bit is 0). Although the AD7927 is
connected to a AVDD of 5 V, the serial interface is connected to a
3 V microprocessor. The VDRIVE pin of the AD7927 is connected
to the same 3 V supply of the microprocessor to allow a 3 V
logic interface (see the Digital Inputs section). The conversion
result is output in a 16-bit word. This 16-bit data stream consists
of one leading zero, three address bits indicating which channel
the conversion result corresponds to, followed by the 12 bits of
conversion data. For applications where power consumption is
of concern, the power-down modes should be used between
conversions or bursts of several conversions to improve power
performance (see the Modes of Operation section).
It is not necessary to write to the control register once a
sequencer operation has been initiated. The WRITE bit must
be set to zero or the DIN line tied low to ensure that the control
register is not accidentally overwritten, or the sequence opera-
tion interrupted. If the control register is written to at any time
during the sequence, the user must ensure that the SEQ and
SHADOW bits are set to 1, 0, respectively to avoid interrupting
the automatic conversion sequence. This pattern continues until
such time as the AD7927 is written to and the SEQ and SHADOW
bits are configured with any bit combination except 1, 0. On
completion of the sequence, the AD7927 sequencer returns to
the first selected channel in the shadow register and commence
the sequence again.
Rather than selecting a particular sequence of channels, a
number of consecutive channels beginning with Channel 0
may also be programmed via the control register alone without
needing to write to the shadow register. This is possible if the
SEQ and SHADOW bits are set to 1, 1, respectively. The channel
address bits, ADD2 through ADD0, then determine the final
channel in the consecutive sequence. The next conversion is on
Channel 0, then Channel 1, and so on until the channel selected
via the Address Bit ADD2 through Address Bit ADD0 is reached.
The cycle begins again on the next serial transfer provided the
WRITE bit is set to low, or if high, that the SEQ and SHADOW
bits are set to 1, 0, respectively; then the ADC continues its pre-
programmed automatic sequence uninterrupted.
5V
SERIAL
INTERFACE
SUPPLY
10µF
0.1µF
AV
DD
V
V
0
7
SCLK
DOUT
CS
IN
•
•
•
•
•
0VTO REF
IN
AD7927
IN
DIN
AGND
V
REF
DRIVE
IN
0.1µF
10µF
0.1µF
2.5V
AD780
3V
Regardless of which channel selection method is used, the
16-bit word output from the AD7927 during each conversion
always contains one leading zero, three channel address bits
that the conversion result corresponds to, followed by the 12-bit
conversion result (see the Serial Interface section).
SUPPLY
NOTES
ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO AGND.
Figure 20. Typical Connection Diagram
ANALOG INPUT SELECTION
DIGITAL INPUTS
Any one of eight analog input channels may be selected for
conversion by programming the multiplexer with the address
bits (ADD2 though ADD0) in the control register. The channel
configurations are shown in Table 7.
The digital inputs applied to the AD7927 are not limited by
the maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted by the
AVDD + 0.3 V limit as on the analog inputs.
The AD7927 may also be configured to automatically cycle
through a number of channels as selected. The sequencer feature is
accessed via the SEQ and SHADOW bits in the control register
(see Table 9). The AD7927 can be programmed to continuously
convert on a selection of channels in ascending order. The analog
input channels to be converted on are selected through program-
ming the relevant bits in the shadow register (see Table 10). The
next serial transfer then acts on the sequence programmed by
executing a conversion on the lowest channel in the selection.
The next serial transfer results in the conversion on the next
highest channel in the sequence, and so on.
CS
Another advantage of SCLK, DIN, and
by the AVDD + 0.3 V limit is that possible power supply sequenc-
ing issues are avoided. If , DIN, or SCLK are applied before
AVDD, there is no risk of latch-up as there would be on the analog
not being restricted
CS
inputs if a signal greater than 0.3 V was applied prior to AVDD
.
Rev. B | Page 17 of 28
AD7927
THE REFERENCE
VDRIVE
An external reference source should be used to supply the
2.5 V reference to the AD7927. Errors in the reference source
result in gain errors in the AD7927 transfer function and add
to the specified full-scale errors of the part. A capacitor of at
least 0.1 μF should be placed on the REFIN pin. Suitable refer-
ence sources for the AD7927 include the AD780, REF192, and
the AD1582.
The AD7927 also has the VDRIVE feature. VDRIVE controls the volt-
age at which the serial interface operates. VDRIVE allows the ADC
to easily interface to both 3 V and 5 V processors. For example,
if the AD7927 were operated with an AVDD of 5 V, the VDRIVE pin
could be powered from a 3 V supply. The AD7927 has a larger
dynamic range with an AVDD of 5 V while still being able to
interface to 3 V processors. Take care to ensure VDRIVE does not
exceed AVDD by more than 0.3 V (see the Absolute Maximum
Ratings section).
If 2.5 V is applied to the REFIN pin, the analog input range can
be either 0 V to 2.5 V or 0 V to 5 V, depending on the setting of
the RANGE bit in the control register.
Rev. B | Page 18 of 28
AD7927
MODES OF OPERATION
The AD7927 has a number of different modes of operation,
which are designed to provide flexible power management
options. These options can be chosen to optimize the power
dissipation/throughput rate ratio for differing application
requirements. The mode of operation of the AD7927 is con-
trolled by the power management bits, PM1 and PM0, in the
control register, as detailed in Table 8. When power supplies
are first applied to the AD7927, care should be taken to ensure
that the part is placed in the required mode of operation (see
the Powering Up the AD7927 section).
For specified performance, the throughput rate should not
exceed 200 kSPS, which means there should be no less than
CS
The actual frequency of SCLK used determines the duration of
the conversion within this 5 μs cycle; however, once a conversion
5 μs between consecutive falling edges of
when converting.
CS
is complete and
has returned high, a minimum of the quiet
CS
time, tQUIET, must elapse before bringing
another conversion.
low again to initiate
CS
1
16
12
SCLK
DOUT
NORMAL MODE (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate perform-
ance because the user does not have to worry about any power-
up times with the AD7927 remaining fully powered at all times.
Figure 21 shows the general diagram of the operation of the
AD7927 in this mode.
1 LEADING ZERO + 3 CHANNEL IDENTIFIER BITS
+ CONVERSION RESULT
DATA INTO CONTROL REGISTER/
SHADOW REGISTER
DIN
NOTES
1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES.
2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES.
CS
The conversion is initiated on the falling edge of and the track-
Figure 21. Normal Mode Operation
and-hold enters hold mode as described in the Serial Interface
section. The data presented to the AD7927 on the DIN line
during the first 12 clock cycles of the data transfer are loaded
into the control register (provided the WRITE bit is 1). If data is
to be written to the shadow register (SEQ = 0, SHADOW = 1 on
the previous write), data presented on the DIN line during the
first 16 SCLK cycles is loaded into the shadow register. The part
remains fully powered up in normal mode at the end of the
conversion as long as PM1 and PM0 are set to 1 in the write
transfer during that conversion. To ensure continued operation
in normal mode, PM1 and PM0 are both loaded with 1 on
every data transfer. Sixteen serial clock cycles are required to
complete the conversion and access the conversion result. The
track-and-hold goes back into track on the 14th SCLK falling
FULL SHUTDOWN (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the AD7927 is powered
down. The part retains information in the control register during
full shutdown. The AD7927 remains in full shutdown until the
power management bits, PM1 and PM0, in the control register
are changed.
If a write to the control register occurs while the part is in full
shutdown, with the power management bits changed to PM0 =
CS
rising edge. The track-and-hold that was in hold while the
part was in full shutdown returns to track on the 14th SCLK
falling edge. A full 16-SCLK transfer must occur to ensure the
control register contents are updated; however, the DOUT line
is not driven during this wake-up transfer.
CS
edge.
may then idle high until the next conversion or may
idle low until sometime prior to the next conversion (effectively
To ensure that the part is fully powered up, tPOWER UP should have
CS
idling low).
CS
elapsed before the next
falling edge; otherwise, invalid data
is read if a conversion is initiated before this time. Figure 22 shows
the general diagram for this sequence.
PART BEGINSTO POWER UP ON
CS RISING EDGE AS PM1 = PM0 = 1
THE PART IS FULLY POWERED UP
ONCE tPOWER UP HAS ELAPSED
PART IS IN FULL
SHUTDOWN
t12
CS
1
1
14
16
14
16
SCLK
DOUT
DIN
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER/SHADOW REGISTER
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ONTHE
FIRST 12 CLOCKS. PM1 = 1, PM0 = 1
TO KEEPTHE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
Figure 22. Full Shutdown Mode Operation
Rev. B | Page 19 of 28
AD7927
Depending on the SCLK frequency used, this dummy transfer
may affect the achievable throughput rate of the part, with every
other data transfer being a valid conversion result. If, for example,
the maximum SCLK frequency of 20 MHz was used, the auto
shutdown mode could be used at the full throughput rate of
200 kSPS without affecting the throughput rate at all. Only a
portion of the cycle time is taken up by the conversion time and
the dummy transfer for wake-up.
AUTO SHUTDOWN (PM1 = 0, PM0 = 1)
In this mode, the AD7927 automatically enters shutdown at the
end of each conversion when the control register is updated.
When the part is in shutdown, the track-and-hold is in hold
mode. Figure 23 shows the general diagram of the operation
of the AD7927 in this mode. In shutdown mode all internal
circuitry on the AD7927 is powered down. The part retains
information in the control register during shutdown. The AD7927
CS
remains in shutdown until the next
falling edge it receives.
In this mode, the power consumption of the part is greatly
reduced with the part entering shutdown at the end of each
conversion. When the control register is programmed to move
into auto shutdown, it does so at the end of the conversion. The
user can move the ADC in and out of the low power state by
CS
On this
falling edge, the track-and-hold that was in hold
while the part was in shutdown returns to track. Wake-up time
from auto shutdown is 1 μs maximum, and the user should
ensure that 1 μs has elapsed before attempting a valid conversion.
When running the AD7927 with a 20 MHz clock, one dummy
16 SCLK transfer should be sufficient to ensure the part is fully
powered up. During this dummy transfer, the contents of the
control register should remain unchanged; therefore, the
WRITE bit should be 0 on the DIN line.
CS
controlling the
signal.
PART BEGINS TO POWER UP
ON CS FALLING EDGE
PART IS FULLY
POWERED UP
PART ENTERS SHUTDOWN ON
CS RISING EDGE AS PM1 = 0, PM0 = 1
PART ENTERS SHUTDOWN ON CS
RISING EDGE AS PM1 = 0, PM0 = 1
CS
SCLK
DOUT
DUMMY CONVERSION
12
1
12
16
1
16
1
12
16
CHANNEL IDENTIFIER BITS + CONVERSION RESU LT
DATA INTO CONTROL/SHADOW REGISTER
CHANNEL IDENTIFIER BITS + CONVERSION RESU LT
DATA INTO CONTROL/SHADOW REGISTER
INVALID DATA
DIN
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS, PM1 = 0, PM0 = 1
CONTROL REGISTER SHOULD NOT
CHANGE, WRITE BIT = 0
TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1
IN CONTROL REGISTER OR SET WRITE BIT = 0
Figure 23. Auto Shutdown Mode Operation
Rev. B | Page 20 of 28
AD7927
CORRECT VALUE IN CONTROL REGISTER,
VALID DATA FROM NEXT CONVERSION,
USER CAN WRITETO SHADOW REGISTER
IN NEXT CONVERSION
CS
SCLK
DOUT
DUMMY CONVERSION
12
DUMMY CONVERSION
12
1
16
1
16
1
12
16
INVALID DATA
INVALID DATA
INVALID DATA
DATA INTO CONTROL REGISTER
DIN
KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS
CONTROL REGISTER IS LOADED ONTHE FIRST
12 CLOCK EDGES
Figure 24. Three-Dummy-Conversions to Place AD7927 into the Required Operating Mode After Power Supplies Are Applied
maximum of 200 kSPS. If the AD7927 is placed into shutdown
for the remainder of the cycle time, then on average far less power
is consumed in every cycle compared to leaving the device in
normal mode. Furthermore, Figure 25 shows how as the through-
put rate is reduced, the part remains in its shutdown longer and
the average power consumption drops accordingly over time.
POWERING UP THE AD7927
When supplies are first applied to the AD7927, the ADC may
power up in any of the operating modes of the part. To ensure
that the part is placed into the required operating mode, the
user should perform a dummy cycle operation as outlined in
Figure 24.
For example, if the AD7927 is operated in a continuous sampling
mode, with a throughput rate of 200 kSPS and an SCLK of 20 MHz
(AVDD = 5 V), and the device is placed in auto shutdown mode,
that is, if PM1 = 0 and PM0 = 1, then the power consumption is
calculated as follows.
The three-dummy-conversion operation outlined in Figure 24
must be performed to place the part into the auto shutdown
mode. The first two conversions of this dummy cycle operation
are performed with the DIN line tied high, and for the third
conversion of the dummy cycle operation, the user should
write the desired control register configuration to the AD7927
The maximum power dissipation during the conversion time is
13.5 mW (IDD = 2.7 mA maximum, AVDD = 5 V). If the power-
up time from auto shutdown is 1 μs and the remaining conversion
time is another cycle, that is, 800 ns, the AD7927 can be said to
dissipate 13.5 mW for 1.8 μs during each conversion cycle. For
the remainder of the conversion cycle, 3.2 μs, the part remains
in shutdown. The AD7927 can be said to dissipate 2.5 μW for
the remaining 3.2 μs of the conversion cycle. If the throughput
rate is 200 kSPS, the cycle time is 5 μs and the average power
dissipated during each cycle is (1.8/5) × (13.5 mW) + (3.2/5) ×
(2.5 μW) = 4.8616 mW.
CS
to place the part into the auto shutdown mode. On the third
rising edge after the supplies are applied, the control register
contains the correct information and valid data results from the
next conversion.
Therefore, to ensure the part is placed into the correct operating
mode, when supplies are first applied to the AD7927, the user
must first issue two serial write operations with the DIN line
tied high, and on the third conversion cycle the user can then
write to the control register to place to part into any of the oper-
ating modes. The user should not write to the shadow register
until the fourth conversion cycle after the supplies are applied
to the ADC, to guarantee the control register contains the
correct data.
Figure 25 shows the maximum power vs. throughput rate when
using the auto shutdown mode with 3 V and 5 V supplies.
10
If the user wishes to place the part into either the normal or full
shutdown mode, the second dummy cycle with DIN tied high
can be omitted from the three-dummy-conversion operation
outlined in Figure 24.
AV = 5V
DD
AV = 3V
DD
1
POWER VS. THROUGHPUT RATE
In auto shutdown mode, the average power consumption of
the ADC may be reduced at any given throughput rate. The
power saving depends on the SCLK frequency used, that is,
conversion time. In some cases where the conversion time is
quite a proportion of the cycle time, the throughput rate needs
to be reduced to take advantage of the power-down modes.
Assuming a 20 MHz SCLK is used, the conversion time is
800 ns, but the cycle time is 5 μs when the sampling rate is at a
0.1
0.01
0
20
40
60
80
100 120 140 160 180 200
THROUGHPUT (kSPS)
Figure 25. Power vs. Throughput Rate
Rev. B | Page 21 of 28
AD7927
SERIAL INTERFACE
information to the shadow register takes place on all 16 SCLK
falling edges in the next serial transfer as shown for example on
the AD7927 in Figure 27. Two sequence options can be pro-
grammed in the shadow register. If the user does not want to
program a second sequence, then the eight LSBs should be filled
with zeros. The shadow register is updated upon the rising edge
Figure 26 shows the detailed timing diagram for serial inter-
facing to the AD7927. The serial clock provides the conversion
clock and also controls the transfer of information to and from
the AD7927 during each conversion.
CS
The
signal initiates the data transfer and conversion process.
CS
CS
of
and the track-and-hold begins to track the first channel
The falling edge of
puts the track-and-hold into hold mode
selected in the sequence.
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and
requires 16 SCLK cycles to complete. The track-and-hold goes
back into track on the 14th SCLK falling edge as shown in
Figure 26 at Point B, except when the write is to the shadow
register, in which case the track-and-hold does not return to
The 16-bit word read from the AD7927 always contains a leading
zero and three-channel address bits that the conversion result
corresponds to, followed by the 12-bit conversion result.
WRITING BETWEEN CONVERSIONS
CS
track until the rising edge of , that is, Point C in Figure 27.
As outlined in the Modes of Operation section, no less than 5 μs
should be left between consecutive valid conversions. However,
there is one case where this does not necessarily mean that at
On the 16th SCLK falling edge the DOUT line goes back into
CS
three-state. If the rising edge of
occurs before 16 SCLKs have
elapsed, the conversion is terminated and the DOUT line goes
back into three-state and the control register is not be updated;
otherwise DOUT returns to three-state on the 16th SCLK falling
edge, as shown in Figure 26. Sixteen serial clock cycles are
required to perform the conversion process and to access data
from the AD7927. For the AD7927, the 12 bits of data are
preceded by a leading zero and the three-channel address bits
(ADD2 to ADD0) identifying which channel the result
CS
least 5 μs should always be left between
falling edges. Con-
sider the prior to a valid conversion. The user must write to the
part to tell it to power up before it can convert successfully. Once
the serial write to power up has finished, it may be desirable to
perform the conversion as soon as possible and not have to wait
CS
a further 5 μs before bringing
case, as long as there is a minimum of 5 μs between each valid
CS
low for the conversion. In this
conversion, then only the quiet time between the
CS
rising edge
falling edge
CS
corresponds to.
going low provides the leading zero to be
at the end of the write to power up and the next
read in by the microcontroller or DSP. The three remaining
address bits and data bits are then clocked out by subsequent
SCLK falling edges beginning with the first address bit (ADD2)
thus the first falling clock edge on the serial clock has a leading
zero provided and also clocks out Address Bit ADD2. The final
bit in the data transfer is valid on the 16th falling edge, having
been clocked out on the previous (15th) falling edge.
for a valid conversion needs to be met (see Figure 28). Note that
when writing to the AD7927 between these valid conversions,
the DOUT line is not driven during the extra write operation,
as shown in Figure 28.
It is critical that an extra write operation as outlined previously
is never issued between valid conversions when the AD7927 is
CS
executing through a sequence function, as the falling edge of
Writing of information to the control register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the MSB
(that is, the WRITE bit) has been set to 1. If the control register
is programmed to use the shadow register, then the writing of
in the extra write would move the mux on to the next channel
in the sequence. This means when the next valid conversion
takes place, a channel result would have been missed.
CS
tCONVERT
t6
tQUIET
B
t2
1
2
3
4
5
13
14
t5
15
16
t11
SCLK
t7
t3
t8
t4
ADD2
ADD1
ADD0
DB11
DB10
DB2
DB1
DB0
DOUT
DIN
THREE-
STATE
THREE-STATE
3 IDENTIFICATION BITS
t9
t10
ZERO
WRITE
SEQ
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
Figure 26. Serial Interface Timing Diagram
Rev. B | Page 22 of 28
AD7927
C
CS
tCONVERT
t6
t2
SCLK
1
2
3
4
5
13
14
t5
15
16
t11
t7
t3
t8
t4
DOUT
DIN
ADD2
ADD1
ADD0
DB11
DB10
DB2
DB1
DB0
THREE-
STATE
THREE-STATE
3 IDENTIFICATION BITS
t9
t10
ZERO
V
0
V
1
V
2
V
3
V
4
V
5
V
5
V
6
V
7
IN
IN
IN
IN
IN
IN
IN
IN
IN
SEQUENCE 1
SEQUENCE 2
Figure 27. Writing to Shadow Register Timing Diagram
tCYCLE 5µs MINIMUM
tQUIET MINIMUM
CS
1
16
1
16
1
16
SCLK
DOUT
DIN
VALID DATA
VALID DATA
POWER-UP
Figure 28. General Timing Diagram
Rev. B | Page 23 of 28
AD7927
MICROPROCESSOR INTERFACING
The serial interface on the AD7927 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7927 with some of the
more common microcontroller and DSP serial interface protocols.
The SPORT0 control register should be set up as follows:
TFSW = RFSW = 1, alternate framing
INVRFS = INVTFS = 1, active low frame signal
DTYPE = 00, right justify data
SLEN = 1111, 16-bit data-words
ISCLK = 1, internal serial clock
TFSR = RFSR = 1, frame every word
IRFS = 0
AD7927 TO TMS320C541
The serial interface on the TMS320C541 uses a continuous serial
clock and frame synchronization signals to synchronize the
data transfer operations with peripheral devices like the AD7927.
CS
The
input allows easy interfacing between the TMS320C541
and the AD7927 without any glue logic required. The serial port
of the TMS320C541 is set up to operate in burst mode with inter-
nal CLKX0 (TX serial clock on Serial Port 0) and FSX0 (TX
frame sync from Serial Port 0). The serial port control register
(SPC) must have the following setup: FO = 0, FSM = 1, MCM =
1, and TXM = 1. The connection diagram is shown in Figure 29.
It should be noted that for signal processing applications, it is
imperative that the frame synchronization signal from the
TMS320C541 provides equidistant sampling. The VDRIVE pin
of the AD7927 takes the same supply voltage as that of the
TMS320C541. This allows the ADC to operate at a higher
voltage than the serial interface, that is, TMS320C541, if
necessary.
ITFS = 1
The connection diagram is shown in Figure 30. The ADSP-218x
has the TFS and RFS of the SPORT0 tied together, with TFS set
as an output and RFS set as an input. The DSP operates in alter-
nate framing mode and the SPORT0 control register is set up as
described. The frame synchronization signal generated on the
CS
TFS is tied to , and as with all signal processing applications
equidistant sampling is necessary. However, in this example, the
timer interrupt is used to control the sampling rate of the ADC,
and under certain conditions, equidistant sampling may not be
achieved.
TMS320C541*
AD7927
*
CLKX
SCLK
CLKR
DR
ADSP-218x*
SCLK
AD7927
*
DOUT
SCLK
DOUT
CS
DT
DIN
CS
DR
FSX
FSR
RFS
TFS
V
DRIVE
DIN
DT
V
*ADDITIONAL PINS REMOVED FOR CLARITY.
DRIVE
V
DD
Figure 29. Interfacing to the TMS320C541
*ADDITIONAL PINS REMOVED FOR CLARITY.
V
DD
AD7927 TO ADSP-21xx
Figure 30. Interfacing to the ADSP-218x
The ADSP-21xx family of DSPs is interfaced directly to the
AD7927 without any glue logic required. The VDRIVE pin of the
AD7927 takes the same supply voltage as that of the ADSP-218x.
This allows the ADC to operate at a higher voltage than the
serial interface, that is, ADSP-218x, if necessary.
The timer register, for instance, is loaded with a value that
provides an interrupt at the required sample interval. When
an interrupt is received, a value is transmitted with TFS or DT,
(ADC control word). The TFS is used to control the RFS and
therefore the reading of data. The frequency of the serial clock
is set in the SCLKDIV register. When the instruction to transmit
with TFS is given (that is, AX0 = TX0), the state of the SCLK is
checked. The DSP waits until the SCLK has gone high, low, and
high before transmission starts. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, then the data may be transmitted
or it may wait until the next clock edge.
Rev. B | Page 24 of 28
AD7927
WL1 = 1 and WL0 = 0 in CRA. The FSP bit in the CRB should
be set to 1 so the frame sync is negative. It should be noted that
for signal processing applications, it is imperative that the frame
synchronization signal from the DSP563xx provides equidistant
sampling.
For example, if the ADSP-2189 had a 20 MHz crystal such that
it had a master clock frequency of 40 MHz, then the master
cycle time would be 25 ns. If the SCLKDIV register is loaded
with the value of 3, then an SCLK of 5 MHz is obtained and
eight master clock periods elapse for every one SCLK period.
Depending on the throughput rate selected, if the timer registers
are loaded with the value, of 803, for example, then 100.5 SCLKs
occur between interrupts and subsequently between transmit
instructions. This situation results in sampling that is not equi-
distant as the transmit instruction is occurring on a SCLK edge.
If the number of SCLKs between interrupts is a whole integer
figure of N, then equidistant sampling is implemented by the DSP.
In the example shown in Figure 31, the serial clock is taken
from the ESSI so the SCK0 pin must be set as an output, SCKD
= 1. The VDRIVE pin of the AD7927 takes the same supply voltage
as that of the DSP563xx. This allows the ADC to operate at a
higher voltage than the serial interface, that is, DSP563xx, if
necessary.
DSP563xx*
AD7927
*
AD7927 TO DSP563xx
The connection diagram in Figure 31 shows how the AD7927
can be connected to the enhanced synchronous serial interface
(ESSI) of the DSP563xx family of DSPs from Motorola. Each
ESSI (two on board) is operated in synchronous mode (SYN
bit in CRB = 1) with internally generated word length frame
sync for both TX and RX (Bit FSL1 = 0 and Bit FSL0 = 0 in
CRB). Normal operation of the ESSI is selected by making
MOD = 0 in the CRB. Set the word length to 16 by setting bits
SCK
SCLK
DOUT
SRD
STD
SC2
CS
DIN
V
DRIVE
*ADDITIONAL PINS REMOVED FOR CLARITY.
V
DD
Figure 31. Interfacing to the DSP563xx
Rev. B | Page 25 of 28
AD7927
APPLICATION HINTS
Good decoupling is also important. All analog supplies should
be decoupled with 10 μF tantalum in parallel with 0.1 μF capaci-
tors to AGND. To achieve the best from these decoupling
components, they must be placed as close as possible to the
device, ideally right up against the device. The 0.1 μF capacitors
should have low effective series resistance (ESR) and effective
series inductance (ESI), such as the common ceramic types or
surface mount types, which provide a low impedance path to
ground at high frequencies to handle transient currents due to
internal logic switching.
GROUNDING AND LAYOUT
The AD7927 has very good immunity to noise on the power
supplies as can be seen in Figure 6. However, care should still
be taken with regard to grounding and layout.
The printed circuit board that houses the AD7927 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be separated easily. A minimum
etch technique is generally best for ground planes as it gives the
best shielding. All three AGND pins of the AD7927 should be
sunk in the AGND plane. Digital and analog ground planes
should be joined at only one place. If the AD7927 is in a system
where multiple devices require an AGND to DGND connec-
tion, the connection should still be made at one point only, a
star ground point that should be established as close as possible
to the AD7927.
EVALUATING THE AD7927 PERFORMANCE
The recommended layout for the AD7927 is outlined in the
evaluation board for the AD7927. The evaluation board pack-
age includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from
the PC via the evaluation-board controller. The evaluation-
board controller can be used in conjunction with the AD7927
Evaluation Board as well as many other Analog Devices, Inc.
evaluation boards ending in the CB designator to demonstrate/
evaluate the ac and dc performance of the AD7927.
Avoid running digital lines under the device as these couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7927 to avoid noise coupling. The power
supply lines to the AD7927 should use as large a trace as possi-
ble to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals, like
clocks, should be shielded with digital ground to avoid radiating
noise to other sections of the board, and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board should
run at right angles to each other. This reduces the effects of
feedthrough through the board. A microstrip technique is by
far the best, but is not always possible with a double-sided
board. In this technique, the component side of the board is
dedicated to ground planes while signals are placed on the
solder side.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7927.
The software and documentation are on a CD shipped with
the evaluation board.
Rev. B | Page 26 of 28
AD7927
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 32. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7927BRU
AD7927BRU-REEL
AD7927BRU–REEL7
AD7927BRUZ2
AD7927BRUZ-REEL2
AD7927BRUZ–REEL72
EVAL-AD7927CBZ2, 3
EVAL-CONTROL BRD24
Temperature Range
Linearity Error (LSB)1
Package Description
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
Evaluation Board
Controller Board
Package Option
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
1
1
1
1
1
1
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
1 Linearity error refers to integral linearity error.
2 Z = RoHS Compliant Part.
3 This can be used as a standalone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes.
4 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete
evaluation kit, please order the particular ADC evaluation board, for example, EVAL-AD7927CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the relevant
evaluation board application note or data sheet for more information.
Rev. B | Page 27 of 28
AD7927
NOTES
©2003–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03088-0-12/08(B)
Rev. B | Page 28 of 28
相关型号：
AD7927BRU-REEL7
IC 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20, MO-153AC, TSSOP-20, Analog to Digital Converter
ADI
AD7927BRUZ-REEL
8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20, ROHS COMPLIANT, MO-153AC, TSSOP-20
ROCHESTER
AD7927BRUZ-REEL7
8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20, ROHS COMPLIANT, MO-153AC, TSSOP-20
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