AD7995YRJZ-1_技术文档

4-Channel, 12-/10-/8-Bit ADC with I²C-

Compatible Interface in 8-Lead SOT23

Preliminary Technical Data

AD7991/AD7995/AD7999

FEATURES

FUNCTIONAL BLOCK DIAGRAM

12-/10-/8-bit ADC with fast conversion time: 2 µs typ

4 Channel / 3 Channel with Reference input

Specified for V_DDof 2.7 V to 5.5 V

V

DD

V

Sequencer operation

Temperature Range: -40 °C to 125 °C

I²C®-compatible serial interface supports standard, fast,

and High-speed modes

IN0

12-/10-/8-BIT

SAR

V

I/P

MUX

IN1

T/H

V

IN2

IN3/Vref

ADC

V

2 versions allow 2 I²C addresses

Low power consumption

Shutdown mode: 1 µA max

8-lead SOT23 package

CONTROL

LOGIC &

SCL

SDA

2

I C

INTERFACE

AD7991/7995/7999

APPLICATIONS

GND

Figure 1.

System Monitoring

Battery Powered Systems

Data Acquisition

Medical Instruments

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD7991/AD7995/AD7999 are 12-/10-/8-bit, low power,

successive approximation ADCs with an I²C-compatible

interface. The parts operate from a single 2.7 V to 5.5 V power

supply and feature a 2 µs conversion time. The part contains a

4-channel multiplexer and track-and-hold amplifier that can

handle input frequencies up to 11 MHz.

1. 4 single ended analog input channels, with the option of

having 3 single ended analog input channels and 1

reference input channel.

2. I²C compatible serial Interface. Standard, Fast and Hs-

Modes

The AD7991/AD7995/AD7999 provides a 2-wire serial

interface compatible with I²C interfaces. The parts come in two

versions with each part having an individual I²C address. This

will allow two of the same devices be connected to the same I²C

bus. Both parts support standard, fast and high-speed I²C

interface modes

3. Automatic shutdown.

4. Reference derived from the power supply or external

reference.

5. 8-lead SOT23 Package.

Table 1 Related Devices

Device Number

Resolution

Input Channels

The AD7991/AD7995/AD7999 normally remain in a shutdown

state while not converting, and power up only for conversions.

The conversion process is controlled by a command mode,

where every time an I²C read operation is executed on the

AD7991/AD7995/AD7999, a conversion is performed and the

result is returned on the I²C bus.

AD7998

12

8

AD7997

AD7994

AD7993

AD7992

10

12

10

12

8

4

2

The reference for the part is taken from V_DD, this allows the

widest dynamic input range to the ADC. Thus the analog input

range to the ADC is 0V to V_DD. An external reference may also

be used with this part. The external reference may be applied

through the Ain3 input.

Rev. PrB

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7991/AD7995/AD7999

Preliminary Technical Data

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Connection Diagram ................................................... 16

Analog Input ............................................................................... 16

Internal Register Structure............................................................ 18

Configuration Register .............................................................. 18

SAMPLE DELAY and BIT TRIAL DELAY ............................ 18

Conversion Result Register....................................................... 19

Serial Interface ................................................................................ 20

Serial Bus Address...................................................................... 20

Writing to the AD7991/AD7995/AD7999.................................. 21

Writing a Single Byte of Data to the Configuration Register21

reading from the AD7991/AD7995/AD7999............................. 22

Placing the AD7991/AD7995/AD7999................................... 23

into High Speed Mode............................................................... 23

Mode of operation.......................................................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide............................................................................... 25

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

ad7991 Specifications....................................................................... 3

ad7995 Specifications....................................................................... 5

ad7999 Specifications....................................................................... 7

I²C Timing Specifications................................................................ 9

Absolute Maximum Ratings.......................................................... 11

ESD Caution................................................................................ 11

Pin Configuration and Function Descriptions........................... 12

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

Converter Operation.................................................................. 15

REVISION HISTORY

PrB/Sept 06—Revision 0: Initial Version

Rev.PrB | Page 2 of 25

Preliminary Technical Data

AD7991 SPECIFICATIONS

AD7991/AD7995/AD7999

Temperature range is as follows: B version −40°C to +85°C, Y version -40°C to +125°C. Unless otherwise noted, V_DD= 2.7 V to 5.5 V; f_SCL

= 3.4 Mhz Unless otherwise noted; T_A= T_MINto T_MAX

.

Table 2.

Parameter

DYNAMIC PERFORMANCE¹

B Version

Y Version Unit

Test Conditions/Comments

F_IN= 10 kHz sine wave for f_SCLfrom 1.7

MHz to

3.4 MHz

F_IN= 1 kHz sine wave for f_SCLup to 400

kHz

Signal-to-Noise + Distortion

(SINAD)²

70.5

dB min

Signal-to-Noise Ratio (SNR)²

71

–78

–79

71

–78

–79

dB min

dB max

Total Harmonic Distortion (THD)²

Peak Harmonic or Spurious Noise

(SFDR)²

Intermodulation Distortion (IMD)²

fa = 10.1 kHz, fb = 9.9 kHz for f_SCLfrom

1.7 MHz to 3.4 MHz

fa = 1.1 kHz, fb = 0.9 kHz for f_SCLup to

400 kHz

Second Order Terms

Third Order Terms

Channel-to-Channel Isolation²

–90

-90

–90

-90

dB typ

F_IN= 108 Hz; see the Terminology

Section

@ 3 dB

Full Power Bandwidth²

11

2

11

2

MHz typ

@ 0.1 dB

DC ACCURACY

Resolution

12

1

0.2

+1/–0.9

12

1

0.2

+1/–0.9

Bits

Integral Nonlinearity^{1, 2}

LSB max

LSB typ

LSB max

Differential Nonlinearity^{1, 2}

Guaranteed no missed codes to 12

bits

0.2

4

0.5

TBD

2

0.2

4

0.5

TBD

2

LSB typ

Offset Error²

LSB max

ppm/°C typ

LSB max

ppm/°C typ

Offset Error Matching

Offset Temperature drift

Gain Error²

Gain Error Matching

Gain Temperature drift

ANALOG INPUT

0.5

TBD

0.5

TBD

Input Voltage Range

DC Leakage Current

Input Capacitance

REFERENCE INPUT

REF_INInput Voltage Range

0 to REF_IN

1

30

0 to REF_IN

1

30

V

µA max

pF typ

1.2 to V_DD

V min/V

max

DC Leakage Current

REF_INInput Capacitance

Input Impedance

1

30

69

1

µA max

pF typ

69

kΩ typ

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Leakage Current, I_IN

0.7 (V_DD

0.3 (V_DD

1

)

0.7 (V_DD

0.3 (V_DD

1

)

V min

V max

µA max

pF max

V_IN= 0 V or V_DD

3

Input Capacitance, C_IN

10

Rev. PrB | Page 3 of 25

AD7991/AD7995/AD7999

Preliminary Technical Data

Parameter

B Version

Y Version Unit

Test Conditions/Comments

Input Hysteresis, V_HYST

LOGIC OUTPUTS (OPEN DRAIN)

Output Low Voltage, V_OL

0.1 (V_DD

)

0.1 (V_DD

)

V min

0.4

0.6

1

0.4

0.6

1

V max

µA max

pF max

I_SINK= 3 mA

I_SINK= 6 mA

Floating-State Leakage Current

Floating-State Output Capacitance³

Output Coding

10

Straight (Natural) Binary

THROUGHPUT RATE

See the Serial Interface section

18 * (1/f_SCL

)

us max

POWER REQUIREMENTS

V_DD

I_DD

2.7/5.5

V min/max

Digital inputs = 0 V or V_DD

ADC Operating, Interface Active

Power Down, Interface Active

Power-Down , Interface Inactive

0.06/0.1

0.3/0.6

TBD

1/2

0.06/0.1

0.3/0.6

TBD

1/2

mA max

µA max

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V

Power Dissipation

Fully Operational

mW max

µW max

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V

ADC Operating, Interface Active

0.495/2.2

1.98/6.05

3.3/11

0.495/2.2

1.98/6.05

3.3/11

Power Down, Interface Inactive

¹Max/min AC dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I²C Hs-mode SCL frequencies. Specifications

outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.

²See the terminology section

³Guaranteed by Initial Characterization.

Rev.PrB | Page 4 of 25

Preliminary Technical Data

AD7995 SPECIFICATIONS

AD7991/AD7995/AD7999

Temperature range for Y version is −40°C to +125°C. Unless otherwise noted, V_DD= 2.7 V to 5.5 V; f_SCL= 3.4 Mhz Unless otherwise noted;

T_A= T_MINto T_MAX

.

Table 3.

Parameter

DYNAMIC PERFORMANCE¹

Y Version

Unit

Test Conditions/Comments

F_IN= 10 kHz sine wave for f_SCLfrom 1.7 MHz to

3.4 MHz

F_IN= 1 kHz sine wave for f_SCLup to 400 kHz

Signal-to-Noise + Distortion (SINAD)²

Total Harmonic Distortion (THD)²

Peak Harmonic or Spurious Noise (SFDR)²

Intermodulation Distortion (IMD)²

61

–75

–76

dB min

dB max

fa = 10.1 kHz, fb = 9.9 kHz for f_SCLfrom 1.7 MHz

to 3.4 MHz

fa = 1.1 kHz, fb = 0.9 kHz for f_SCLup to 400 kHz

Second Order Terms

Third Order Terms

Channel-to-Channel Isolation²

Full Power Bandwidth²

–86

-90

11

dB typ

MHz typ

F_IN= 108 Hz; see the Terminology Section

@ 3 dB

@ 0.1 dB

2

DC ACCURACY

Resolution

10

Bits

Integral Nonlinearity^{1, 2}

Differential Nonlinearity^{1, 2}

Offset Error²

Offset Error Matching

Offset Temperature drift

Gain Error²

Gain Error Matching

Gain Temperature drift

ANALOG INPUT

0.5

2

0.5

TBD

1.5

0.5

TBD

LSB max

ppm/°C typ

LSB max

ppm/°C typ

Guaranteed no missed codes to 10 bits

Input Voltage Range

DC Leakage Current

Input Capacitance

REFERENCE INPUT

0 to REF_IN

1

30

V

When Vin3/VREF = VIN3, Vref = VDD

µA max

pF typ

REF_INInput Voltage Range

DC Leakage Current

REF_INInput Capacitance

Input Impedance

1.2 to V_DD

V min/V max

µA max

pF typ

1

30

69

kΩ typ

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Leakage Current, I_IN

0.7 (V_DD

0.3 (V_DD

1

)

V min

V max

µA max

pF max

V min

V_IN= 0 V or V_DD

3

Input Capacitance, C_IN

10

Input Hysteresis, V_HYST

LOGIC OUTPUTS (OPEN DRAIN)

Output Low Voltage, V_OL

0.1 (V_DD

)

0.4

0.6

1

V max

µA max

pF max

I_SINK= 3 mA

I_SINK= 6 mA

Floating-State Leakage Current

Floating-State Output Capacitance³

Output Coding

10

Straight (Natural) Binary

THROUGHPUT RATE

See the Serial Interface section

18 * (1/f_SCLus max

)

Rev. PrB | Page 5 of 25

AD7991/AD7995/AD7999

Preliminary Technical Data

Parameter

Y Version

Unit

Test Conditions/Comments

POWER REQUIREMENTS

V_DD

I_DD

2.7/5.5

V min/max

Digital inputs = 0 V or V_DD

ADC Operating, Interface Active

Power Down, Interface Active

Power-Down , Interface InActive

0.06/0.1

0.3/0.6

TBD

1/2

mA max

µA max

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V

Power Dissipation

Fully Operational

mW max

µW max

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V

ADC Operating, Interface Active

0.495/2.2

1.98/6.05

3.3/11

Power Down, Interface Inactive

¹Max/min AC dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I²C Hs-mode SCL frequencies. Specifications

outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.

²See the Terminology section

³Guaranteed by Initial Characterization.

Rev.PrB | Page 6 of 25

Preliminary Technical Data

AD7999 SPECIFICATIONS

AD7991/AD7995/AD7999

Temperature range for Y version is −40°C to +125°C. Unless otherwise noted, V_DD= 2.7 V to 5.5 V; f_SCL= 3.4 Mhz Unless otherwise noted;

T_A= T_MINto T_MAX

.

Table 4.

Parameter

DYNAMIC PERFORMANCE¹

Y Version

Unit

Test Conditions/Comments

F_IN= 10 kHz sine wave for f_SCLfrom 1.7 MHz to

3.4 MHz

F_IN= 1 kHz sine wave for f_SCLup to 400 kHz

Signal-to-Noise + Distortion (SINAD)²

Total Harmonic Distortion (THD)²

Peak Harmonic or Spurious Noise (SFDR)²

Intermodulation Distortion (IMD)²

49

–65

dB min

dB max

fa = 10.1 kHz, fb = 9.9 kHz for f_SCLfrom 1.7 MHz

to 3.4 MHz

fa = 1.1 kHz, fb = 0.9 kHz for f_SCLup to 400 kHz

Second Order Terms

Third Order Terms

Channel-to-Channel Isolation²

Full Power Bandwidth²

–76

-90

11

dB typ

MHz typ

F_IN= 108 Hz; see the Terminology section

@ 3 dB

@ 0.1 dB

2

DC ACCURACY

Resolution

8

Bits

Integral Nonlinearity^{1, 2}

Differential Nonlinearity^{1, 2}

Offset Error²

Offset Error Matching

Offset Temperature drift

Gain Error²

Gain Error Matching

Gain Temperature drift

ANALOG INPUT

0.3

0.5

0.3

TBD

0.3

TBD

LSB max

ppm/°C typ

LSB max

ppm/°C typ

Guaranteed no missed codes to 8 bits

Input Voltage Range

DC Leakage Current

Input Capacitance

REFERENCE INPUT

0 to REF_IN

1

30

V

When Vin3/VREF = VIN3, Vref = VDD

µA max

pF typ

REF_INInput Voltage Range

DC Leakage Current

REF_INInput Capacitance

Input Impedance

1.2 to V_DD

V min/V max

µA max

pF typ

1

30

69

kΩ typ

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Leakage Current, I_IN

0.7 (V_DD

0.3 (V_DD

1

)

V min

V max

µA max

pF max

V min

V_IN= 0 V or V_DD

3

Input Capacitance, C_IN

10

Input Hysteresis, V_HYST

LOGIC OUTPUTS (OPEN DRAIN)

Output Low Voltage, V_OL

0.1 (V_DD

)

0.4

0.6

1

V max

µA max

pF max

I_SINK= 3 mA

I_SINK= 6 mA

Floating-State Leakage Current

Floating-State Output Capacitance³

Output Coding

10

Straight (Natural) Binary

THROUGHPUT RATE

See the Serial Interface section

18 * (1/f_SCLus max

)

Rev. PrB | Page 7 of 25

AD7991/AD7995/AD7999

Preliminary Technical Data

Parameter

Y Version

Unit

Test Conditions/Comments

POWER REQUIREMENTS

V_DD

I_DD

2.7/5.5

V min/max

Digital inputs = 0 V or V_DD

ADC Operating, Interface Active

Power Down, Interface Active

Power-Down , Interface Inactive

0.06/0.1

0.3/0.6

TBD

1/2

mA max

µA max

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V

Power Dissipation

Fully Operational

mW max

µW max

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V

ADC Operating, Interface Active

Power Down, Interface Inactive

0.495/2.2

1.98/6.05

3.3/11

¹Max/min AC dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I²C Hs-mode SCL frequencies. Specifications

outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.

²See the Terminology section

³Guaranteed by Initial Characterization.

Rev.PrB | Page 8 of 25

Preliminary Technical Data

I²C TIMING SPECIFICATIONS

AD7991/AD7995/AD7999

Guaranteed by initial characterization. All values measured with the input filtering enabled. C_Brefers to the capacitive load on the bus

line. t_rand t_fmeasured between 0.3 V_DDand 0.7 V_DD

.

Standard, Fast and High speed mode timing specifications apply to the AD7991/AD7995/AD7999-1. See Figure 2.Unless otherwise noted,

V_DD= 2.7 V to 5.5 V; T_A=T_MINto T_MAX

.

Table 5.

Limit at T_MIN, T_MAX

Parameter

Conditions

Min

Max

100

400

Unit

kHz

Description

f_SCL

Standard mode

Fast mode

Serial clock frequency

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

Fast mode

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

Fast mode

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

Fast mode

High speed mode

Standard mode

Fast mode

3.4

1.7

MHz

µs

t₁

t₂

t₃

4

0.6

t_HIGH, SCL high time

t_LOW, SCL low time

µs

60

ns

µs

120

4.7

1.3

160

320

250

100

10

ns

µs

t_SU;DAT, data setup time

t_HD;DAT, data hold time

1

t₄

0

3.45

0.9

High Speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

Fast mode

High Speed mode

Standard mode

Fast mode

0

70²

150

ns

µs

ns

µs

ns

µs

ns

t₅

t₆

4.7

0.6

160

4

0.6

160

4.7

1.3

4

t_SU;STA, setup time for a repeated START condition

t_HD;STA, hold time for a repeated START condition

High speed mode

Standard mode

Fast mode

t₇

t₈

t_BUF, bus free time between a STOP and a START condition

t_SU;STO, setup time for STOP condition

Standard mode

Fast mode

High speed mode

Standard mode

Fast mode

0.6

160

t₉

1000

300

t_RDA, rise time of SDA signal

20 + 0.1 C_B

High speed mode

C_B= 100 pF max

C_B= 400 pF max

10

20

80

160

ns

Rev. PrB | Page 9 of 25

AD7991/AD7995/AD7999

Preliminary Technical Data

Limit at T_MIN, T_MAX

Parameter

Conditions

Min

Max

Unit

ns

Description

t₁₀

Standard mode

Fast mode

300

t_FDA, fall time of SDA signal

20 + 0.1 C_B

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

Fast mode

10

20

80

ns

160

1000

300

t₁₁

t_RCL, rise time of SCL signal

20 + 0.1 C_B

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

10

20

40

80

ns

t_11A

1000

t_RCL1, rise time of SCL signal after a repeated START

condition and after an acknowledge bit

Fast mode

20 + 0.1 C_B

300

ns

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

Fast mode

10

20

80

ns

160

300

t₁₂

t_FCL, fall time of SCL signal

20 + 0.1 C_B

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Fast mode

10

20

0

40

80

50

10

ns

t_SP

Pulse width of suppressed spike

High speed mode

0

t_POWER-UP

1

µs typ Power-up time

¹A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.

²For 3 V supplies, the maximum hold time with C_B= 100 pF max is 100 ns max.

t

11

12

t

6

2

SCL

SDA

t

6

t

3

t

5

8

4

t

1

t

9

t

10

t

7

S

P

S

P

S = START CONDITION

P = STOP CONDITION

Figure 2. Two-Wire Serial Interface Timing Diagram

Rev.PrB | Page 10 of 25

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

AD7991/AD7995/AD7999

T_A= 25°C, unless otherwise noted.

Table 6.

Parameter

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

V_DDto GND

−0.3 V to 7 V

Analog Input Voltage to GND

Reference Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

Input Current to Any Pin Except Supplies¹

Operating Temperature Range

Commercial (B Version)

Industrial (Y Version)

−0.3 V to V_DD+ 0.3 V

−0.3 V to +7 V

−0.3 V to V_DD+ 0.3 V

10 mA

−40°C to +85°C

−40°C to +125°C

−65°C to +150°

150°C

Storage Temperature Range

Junction Temperature

8-Lead SOT-23 Package

θ_JAThermal Impedance

θ_JCThermal Impedance

Pb/SN Temperature, Soldering

Reflow (10 sec to 30 sec)

Pb-Free Temperature, Soldering Reflow

ESD

TBD °C/W

TBD °C

TBD kV

¹Transient currents of up to 100 mA do not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. PrB | Page 11 of 25

AD7991/AD7995/AD7999

Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCL

SDA

1

2

3

4

VDD

8

7

6

5

AD7991/

AD7995/

AD7999

GND

VIN3/VREF

VIN2

VIN0

VIN1

TOP VIEW

(Not to Scale)

Figure 3.AD7991/AD7995/AD7999 Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Function

1

2

3

4

5

6

SCL

SDA

V_IN0

V_IN1

V_IN2

V_IN3/V_REF

Digital Input. Serial bus clock. External pull-up resistor required.

Digital I/O. Serial bus bidirectional data. Open-drain output. External pull-up resistor required.

Analog Input 1. Single-ended analog input channel. The input range is 0 V to V_ref.

Analog Input 2. Single-ended analog input channel. The input range is 0 V to V_ref.

Analog Input 3. Single-ended analog input channel. The input range is 0 V to V_ref.

Analog Input 4. Single-ended analog input channel. The input range is 0 V to V_ref. Can also be used to input an

external Vref signal.

7

8

GND

V_DD

Analog Ground. Ground reference point for all circuitry on the AD7991/AD7995/AD7999. All analog input

signals should be referred to this AGND voltage.

Power Supply Input. The V_DDrange for the AD7991/AD7995/AD7999 is from 2.7 V to 5.5 V.

Table 8. I²C Address Selection

Part Number

AD7991 -0

AD7991-1

AD7995-0

AD7995-1

AD7999-0

AD7999-1

I²C Address

010 1000

010 1001

010 1000

010 1001

010 1000

010 1001

Rev.PrB | Page 12 of 25

Preliminary Technical Data

AD7991/AD7995/AD7999

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Rev. PrB | Page 13 of 25

AD7991/AD7995/AD7999

TERMINOLOGY

Preliminary Technical Data

tanced in frequency from the original sine waves while the

third-order terms are usually at a frequency close to the input

frequencies. As a result, the second and third-order terms are

specified separately. The calculation of intermodulation distor-

tion is, like the THD specification, the ratio of the rms sum of

the individual distortion products to the rms amplitude of the

sum of the fundamentals, expressed in dB.

Signal-to-Noise and Distortion Ratio (SINAD)

The measured ratio of signal-to-noise and distortion at the out-

put of the A/D converter. The signal is the rms amplitude of the

fundamental. Noise is the sum of all nonfundamental signals up

to half the sampling frequency (f_S/2), excluding dc. The ratio is

dependent on the number of quantization levels in the digiti-

zation process; the more levels, the smaller the quantization

noise. The theoretical signal-to-noise and distortion ratio for

an ideal N-bit converter with a sine wave input is given by

Channel-to-Channel Isolation

A measure of the level of crosstalk between channels, taken

by applying a full-scale sine wave signal to the unselected input

channels, and determining how much the 108 Hz signal is

attenuated in the selected channel. The sine wave signal applied

to the unselected channels is then varied from 1 kHz up to

2 MHz, each time determining how much the 108 Hz signal in

the selected channel is attenuated. This figure represents the

worst-case level across all channels.

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, the SINAD is 49.92 dB for an 8-bit converter, 61.96 dB for

a 10-bit converter and 74 dB for a 12-bit converter.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. For

the AD7991/AD7995/AD7999, it is defined as

Full-Power Bandwidth

The input frequency at which the amplitude of the reconstructed

fundamental is reduced by 0.1 dB or 3 dB for a full-scale input.

2

V²+V³+V⁴+V⁵+V⁶

THD (dB) = 20 log

V1

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅, and V₆are the rms amplitudes of the second through

sixth harmonics.

Integral Nonlinearity

The maximum deviation from a straight line passing through

the endpoints of the ADC transfer function. The endpoints are

zero scale, a point 1 LSB below the first code transition, and full

scale, a point 1 LSB above the last code transition.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the

ADC output spectrum (up to f_S/2 and excluding dc) to the rms

value of the fundamental. Typically, the value of this specification

is determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, it is a

noise peak.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (00…000) to

(00…001) from the ideal—that is, AGND + 1 LSB.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa

and fb, any active device with nonlinearities creates distortion

products at sum and difference frequencies of mfa nfb, where

m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms

are those for which neither m nor n equal zero. For example,

second-order terms include (fa + fb) and (fa − fb), while

third-order terms include (2fa + fb), (2fa − fb),(fa + 2fb) and

(fa − 2fb).

Offset Error Match

The difference in offset error between any two channels.

Gain Error

The deviation of the last code transition (111…110) to

(111…111) from the ideal (that is, REF_IN− 1 LSB) after the

offset error has been adjusted out.

Gain Error Match

The difference in gain error between any two channels.

The AD7993/AD7994 is tested using the CCIF standard where

two input frequencies near the top end of the input bandwidth

are used. In this case, the second-order terms are usually dis-

Rev.PrB | Page 14 of 25

Preliminary Technical Data

THEORY OF OPERATION

AD7991/AD7995/AD7999

The AD7991/AD7995/AD7999 are low power, 12-/10-/8-bit,

single-supply, 4-channel A/D converters. The parts can be

operated from a 2.35 V to 5.5 V supply.

When the ADC starts a conversion, as shown in Figure 10,

SW2 opens and SW1 moves to position B, causing the

comparator to become unbalanced. The input is disconnected

once the conversion begins. The control logic and the capacitive

DAC are used to add and subtract fixed amounts of charge from

the sampling capacitor to bring the comparator back into a

balanced condition. When the comparator is rebalanced, the

conversion is complete. The control logic generates the ADC

output code. Figure 11 shows the ADC transfer function.

The AD7991/AD7995/AD7999 provides the user with a 4-

channel multiplexer, an on-chip track-and-hold, an A/D

converter, and an I²C-compatible serial interface, all housed in a

8-lead SOT23 package that offers the user considerable space

saving advantages over alternative solutions.

The AD7991/AD7995/AD7999 normally remains in a power-

down state while not converting. When supplies are first

applied, the part comes up in a power-down state. Power-up is

initiated prior to a conversion, and the device returns to power-

down upon completion of the conversion. This automatic

power-down feature allows power saving between conversions.

This means any read or write operations across the I²C interface

can occur while the device is in power-down.

CAPACITIVE

DAC

A

V

IN

CONTROL

LOGIC

SW1

B

SW2

COMPARATOR

AGND

Figure 10. ADC Conversion Phase

CONVERTER OPERATION

The AD7991/AD7995/AD7999 is a successive approximation,

analog-to-digital converter based around a capacitive DAC.

Figure 9 and Figure 10 show simplified schematics of the ADC

during its acquisition and conversion phases, respectively.

Figure 9 shows the ADC during its acquisition phase. SW2 is

closed and SW1 is in position A, the comparator is held in a

balanced condition, and the sampling capacitor acquires the

signal on V_IN.

ADC Transfer Function

The output coding of the AD7991/AD7995/AD7999 is straight

binary. The designed code transitions occur at successive

integer LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size

for the AD7991/AD7995/AD7999 is REF_IN/4096. Figure 11

shows the ideal transfer characteristic for the

AD7991/AD7995/AD7999.

CAPACITIVE

DAC

111...111

111...110

A

V

111...000

011...111

IN

CONTROL

SW1

LOGIC

B

SW2

COMPARATOR

AD7991 1 LSB = REF /4096

IN

AD7995 1 LSB = REF /1024

AD7995 1 LSB = REF /256

IN

000...010

000...001

000...000

AGND

Figure 9. ADC Acquisition Phase

AGND +1 LSB

+REF -1LSB

IN

ANALOG INPUT

0 V TO REF

IN

Figure 11. AD7991/AD7995/AD7999 Transfer Characteristic

Rev. PrB | Page 15 of 25

AD7991/AD7995/AD7999

Preliminary Technical Data

TYPICAL CONNECTION DIAGRAM

ANALOG INPUT

Figure 13 shows the typical connection diagram for the

AD7991/AD7995/AD7999.

Figure 12 shows an equivalent circuit of the

AD7991/AD7995/AD7999 analog input structure. The two

diodes, D1 and D2, provide ESD protection for the analog

inputs. Care must be taken to ensure that the analog input

signal does not exceed the supply rails

by more than 300 mV. This causes these diodes to become

forward-biased and start conducting current into the substrate.

These diodes can conduct a maximum current of 10 mA

without causing irreversible damage to the part.

The reference voltage can be taken from the supply voltage V_DD.

However, the AD7991/AD7995/AD7999 can be configured to

be a three-channel device with the reference voltage applied to

the V_IN3/REF_INpin.

SDA and SCL form the 2-wire I²C compatible interface.

External pull-up resisters are required for both SDA and SCL

lines.

V

DD

The AD7991/AD7995/AD7999-0 and the

AD7991/AD7995/AD7999-1 both support the standard, fast

and high speed I²C interface modes. Both the -0 and the -1

device will have an independent I²C address. This will allow

both device to connect to the same I²C bus without any

contention issues.

D1

D2

C2

30pF

R1

V

IN

C1

4pF

CONVERSION PHASE - SWITCH OPEN

TRACK PHASE - SWITCH CLOSED

Wake up from power-down prior to a conversion is

approximately 1 µs, and conversion time is approximately 2 µs.

The AD7991/AD7995/AD7999 enters shutdown mode again

after each conversion, which is useful in applications where

power consumption is a concern.

Figure 12. Equivalent Analog Input Circuit

Capacitor C1 in Figure 12 is typically about 4 pF and can

primarily be attributed to pin capacitance. Resistor R1 is a

lumped component made up of the on resistance (R_ON) of

a track-and-hold switch, and also the R_ONof the input multi-

plexer. The total resistor is typically about 400 Ω. C2, the ADC

sampling capacitor, has a typical capacitance of 30 pF.

+5V SUPPLY

10µF

0.1µF

TWO WIRE SERIAL

INTERFACE

R

P

V

P

IN0

V

DD

V

IN1

SDA

SCL

V

IN2

V

IN3/Vref

µC/µP

AD7991/

AD7995/

AD7999

GND

Figure 13. AD7991/AD7995/AD7999 Typical Connection Diagram

Rev.PrB | Page 16 of 25

Preliminary Technical Data

AD7991/AD7995/AD7999

For ac applications, removing high frequency components from

the analog input signal is recommended by use of an RC band-

pass filter on the relevant analog input pin. In applications

where harmonic distortion and signal-to-noise ratio are critical,

the analog input should be driven from a low impedance

source. Large source impedances significantly affect the ac

performance of the ADC. This may necessitate the use of an

input buffer amplifier. The choice of the op amp is a function

of the particular application.

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance depends on the amount of total harmonic

distortion (THD) that can be tolerated. THD increases as the

source impedance increases, and performance degrades. Figure

14 and Figure 15 shows the THD vs. the analog input signal

frequency for different source impedances. at 3V and 5V

respectively.

Figure 15. THD vs Analog Input Frequency for various source

Impedances for VDD = 5V

Figure 14. THD vs Analog Input Frequency for various source

Impedances for VDD = 3V

Rev. PrB | Page 17 of 25

AD7991/AD7995/AD7999

Preliminary Technical Data

INTERNAL REGISTER STRUCTURE

CONFIGURATION REGISTER

The configuration register is an 8-bit write only register that is used to set the operating modes of the AD7991/AD7995/AD7995. The bit

functions are outlined in Table 9. A single-byte write is necessary when writing to the configuration register. D7 is the MSB. When the

master writes to the AD7991/AD799/AD7999, the first byte is written to the status register.

Table 9. Configuration Register Bit Function Descriptions and * shows the default Settings at Power-Up

D7

CH3

1*

D6

D5

CH1

1

D4

CH0

1*

D3

D2

FLTR

0*

D1

D0

CH2

1 *

REF_SEL

0*

Bit Trial Delay

0 *

Sample Delay

0*

Table 10. Bit Function Descriptions

Bit

Mnemonic

Comment

D7–D4

CH3–CH0

These four channel address bits select the analog input channel(s) to be converted. A 1 in any of Bits D7 to D4

selects a channel for conversion. If more than one channel bit is set to 1, the AD7991/AD7995/AD7999 sequence

through the selected channels, starting with the lowest channel. All unused channels should be set to 0. Table 11

shows how these four channel address bits are decoded. Prior to initiating a conversion, the channel(s) must be

selected in the configuration register.

D3

REF_SEL

FLTR

This bit allows the user to select the supply voltage as the reference or use an external reference. If this bit is a 0

the supply is used as the reference and the device acts as a four channel input part, if it is set to a 1 an external

reference must be used and applied to the Vin3/VREF pin, in this case the device acts as a three channel input

part.

The value written to this bit of the control register determines whether the filtering on SDA and SCL is enabled or

is to be bypassed. If this bit is a 0, then the filtering is enabled; if it is a 1, the filtering is bypassed.

D2

D1

D0

Bit Trial

Delay

Sample

Delay

See paragraph below entitled: SAMPLE DELAY AND BIT TRIAL DELAY

Table 11. Channel Selection

D7 D6 D5 D4 Analog Input Channel

Comments

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No channel selected.

Convert on V_IN0.

Convert on V_IN1.

Sequence between V_IN0 and V_IN1.

Convert on V_IN2.

Sequence between V_IN0 and V_IN2.

Sequence between V_IN1 and V_IN2.

Sequence between V_IN0, V_IN1, and V_IN2.

Convert on V_IN3.

Sequence between V_IN0 and V_IN3.

Sequence between V_IN1 and V_IN3.

Sequence between V_IN0, V_IN1, and V_IN3.

Sequence between V_IN2 and V_IN3.

Sequence between V_IN0, V_IN2, and V_IN3.

Sequence between V_IN1, V_IN2, and V_IN3.

Sequence between V_IN0, V_IN1, V_IN2, and V_IN3.

The AD7991/AD7995/AD7999 converts on the selected

channel in the sequence in ascending order, starting

with the lowest channel in the sequence.

SAMPLE DELAY AND BIT TRIAL DELAY

It is recommended that no I²C bus activity occur when a conversion is taking place. However, if this is not always possible, then in order

to maintain the performance of the ADC, Bits D0 and D1 in the configuration register are used to delay critical sample intervals and bit

trials from occurring while there is activity on the I²C bus. This results in a quiet period for each bit decision. In certain cases where there

Rev.PrB | Page 18 of 25

Preliminary Technical Data

AD7991/AD7995/AD7999

is excessive activity on the interface lines, this may have the effect of increasing the overall conversion time. However, if bit trial delays

extend longer than 1 µs, the conversion terminates.

When Bits D0 and D1 are both 0, the bit trial and sample interval delaying mechanism is implemented. The default setting of D0 and D1

is 0. To turn off both delay mechanisms, set D0 and D1 to 1.

CONVERSION RESULT REGISTER

The conversion result register is a 16-bit read-only register that stores the conversion result from the ADC in straight binary format. A 2-

byte read is necessary to read data from this register. Table 12 shows the contents of the first byte to be read, from

AD7991/AD7995/AD7999 and Table 13 shows the contents of the second byte to be read.

Table 12. Conversion Value Register (First Read)

D15

D14

D13

D12

D11

D10

D9

D8

Leading Zero

CH_ID1

CH_ID0

MSB

B10

B9

B8

Table 13. Conversion Value Register (Second Read)

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3 /0

B2 /0

B1/0

B0/0

The AD7991/AD7995/AD7999 conversion result consists of 2 leading zeros, two channel identifier bits, and the 12-/10-/8- bit data result.

For the AD7995, the 2 LSB (D1 and D0) of the second read contain two trailing 0s. For the AD7999, the 4 LSB (D3, D2, D1 and D0) of

the second read contain 4 trailing zeros

Rev. PrB | Page 19 of 25

AD7991/AD7995/AD7999

SERIAL INTERFACE

Preliminary Technical Data

Control of the AD7991/AD7995/AD7999 is carried out via the

I²C-compatible serial bus. The AD7991/AD7995/AD7999 is

connected to this bus as a slave device under the control of a

master device, such as the processor.

Data is sent over the serial bus in sequences of nine clock

pulses, eight bits of data followed by an acknowledge bit from

the receiver of data. Transitions on the data line must occur

during the low period of the clock signal and remain stable

during the high period, because a low-to-high transition when

the clock is high may be interpreted as a STOP signal.

SERIAL BUS ADDRESS

Like all I²C-compatible devices, the AD7991/AD7995/AD7999

has a 7-bit serial address. The devices comes in two versions,

the AD7991/AD7995/AD7999-0 and the

When all data bytes have been read or written, stop conditions

are established. In write mode, the master pulls the data line

high during the 10th clock pulse to assert a STOP condition. In

read mode, the master device pulls the data line high during the

low period before the ninth clock pulse. This is known as no

acknowledge. The master then takes the data line low during

the low period before the 10th clock pulse, then high during the

10th clock pulse to assert a STOP condition.

AD7991/AD7995/AD7999-1. Each version has a different

address. See Table 8. By giving different addresses for the two

versions, up to 2 AD7991/AD7995/AD7999 devices can be

connected to a single serial bus.

The serial bus protocol operates as follows:

The master initiates data transfer by establishing a START

condition, defined as a high-to-low transition on the serial

data line SDA, while the serial clock line, SCL, remains high.

This indicates that an address/data stream follows. All slave

peripherals connected to the serial bus respond to the START

condition and shift in the next eight bits, consisting of a 7-bit

Any number of bytes of data may be transferred over the serial

bus in one operation, but it is not possible to mix read and write

in one operation because the type of operation is determined at

the beginning and cannot subsequently be changed without

starting a new operation.

address (MSB first) plus an R/ bit that determines the

W

direction of the data transfer—that is, whether data is written to

or read from the slave device.

The peripheral whose address corresponds to the transmitted

address responds by pulling the data line low during the low

period before the ninth clock pulse, known as the acknowledge

bit. All other devices on the bus remain idle while the selected

device waits for data to be read from or written to it. If the R/

W

bit is a 0, the master writes to the slave device. If the R/ bit is

W

a 1, the master reads from the slave device.

Rev.PrB | Page 20 of 25

Preliminary Technical Data

AD7991/AD7995/AD7999

WRITING TO THE AD7991/AD7995/AD7999

This part can be used in read-only mode if the user wishes to

use all 4 channels sequentially as the default on the configure

register allows. However, the user must write to the

configuration register of the part AD7991/AD7995/AD7999 if

they want to change from the default settings on the

configuration register.

WRITING A SINGLE BYTE OF DATA TO THE

CONFIGURATION REGISTER

The configuration register is an 8-bit register, so only one byte

of data can be written. Writing a single byte of data to this

register consists of the serial bus write address, followed by the

data byte written to the configuration register. See Figure 16

below.

1

0

9

1

9

SCL

SDA

1

D3

0

1

0

A0

D7

D6

D5

D2

D1

D0

R/W

D4

0

START BY

MASTER

ACK. BY

ADC

ACK. BY

AD7992

STOP

FRAME 1

SERIAL BUS ADDRESS BYTE

CONTROL REGISTER BYTE

Figure 16.Writing to the AD7991/AD7995/AD7999 Configuration Register

Rev. PrB | Page 21 of 25

AD7991/AD7995/AD7999

Preliminary Technical Data

READING FROM THE AD7991/AD7995/AD7999

Reading data from the conversion result register is a 2-byte

operation, as shown in Figure 17. Since this register is the only

one that a user can read, a read operation is always at least two

bytes.

After the master has addressed the AD7991/AD7995/AD7999,

the part begins to power up on the 9^thSCLK falling edge. After

about 0.5us, the input is sampled and a conversion begins. This

is done in parallel to the read operation and should not affect

the read operation. The master reads back 2 bytes of data. On

the 9^thSCLK falling edge of the second byte, if the master sends

an ACK, this means that the master desires to keep reading

back more conversion results, the AD7991/AD7995/AD7999

powers up and performs a second conversion. If the master

sends a NO ACK the AD7991/AD7995/AD7999 doesn’t power

up on the 9^thfalling edge of SCLK of the second byte. If a

further conversion is required the part will convert on the next

channel, that is the next channel as selected in the configuration

register. See table 10 for Channel selection.

Once the AD7991/AD7995/AD7999 has received a read address

any number of reads can be performed from the conversion

result register.

Following a start condition, the master writes the 7 bit address

of the AD7991/AD7995/AD7999, followed by the R/ set to 1.

W

The AD7991/AD7995/AD7999 acknowledges by pulling low

the SDA line (A). It then outputs on the I2C bus the conversion

result, proceeded by 4 status bits. The status bits are 2 leading

zeros, then the channel identifier bits. For the AD7995 there are

two trailing zeros and for the AD7999 there are four trailing

zeros.

If the master send a NO ACK on the 9^thSCLK falling edge of

the 2^ndbyte then the conversion is finished and no further

conversion is preformed.

1

9

1

9

SCL

1

0

1

0

A0

D11

D10

D9

D8

R/W

0

SDA

0

START BY

MASTER

ACK. BY

ADC

ACK. BY

MASTER

CH

ID1

ID0

FRAME 2

MOST SIGNIFICANT DATA BYTE FROM ADC

FRAME 1

SERIAL BUS ADDRESS BYTE

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D1

D0

D3

D7

D6

D5

D2

D4

NO ACK. BY STOP BY

MASTER MASTER

FRAME 3

LEAST SIGNIFICANT DATA BYTE FROM ADC

Figure 17. Reading Two Bytes of Data from the Conversion Result Register

Rev.PrB | Page 22 of 25

Preliminary Technical Data

AD7991/AD7995/AD7999

PLACING THE AD7991/AD7995/AD7999

INTO HIGH SPEED MODE.

High speed mode communication commences after the master

addresses all devices connected to the bus with the master code,

00001XXX, to indicate that a high speed mode transfer is to

begin. No device connected to the bus is allowed to

acknowledge the high speed master code; therefore, the code is

followed

by a not-acknowledge (see Figure 18). The master must then

issue a repeated start followed by the device address with a R/

bit. The selected device then acknowledges its address.

W

All devices continue to operate in high speed mode until the

master issues a STOP condition. When the STOP condition is

issued, the devices all return to fast mode.

HIGH-SPEED MODE

9

FAST MODE

1

9

1

SCL

1

0

1

X

0

1

A0

0

SDA

Sr

NACK.

START BY

MASTER

ACK. BY

ADC

HS-MODE MASTER CODE

SERIAL BUS ADDRESS BYTE

Figure 18. Placing the Part into High Speed Mode

Rev. PrB | Page 23 of 25

AD7991/AD7995/AD7999

MODE OF OPERATION

Preliminary Technical Data

of the conversion result. For the AD7991 this second byte will

contain the lower 8 bits of conversion data. For the AD7995 this

second byte will contain 6 bits of conversion data plus 2 trailing

zeros. For the AD7999 this second byte will contain 4 bits of

conversion data and 4 trailing zeros.

The AD7991/AD7995/AD7999 powers up in shut down mode.

Once the master addresses the AD7991/AD7995/AD7999 with

the correct I²C address the ADC will acknowledge. During this

acknowledge the AD7991/AD7995/AD7999 will power up and

start a conversion.

The master will then send a NAK to the

During this wake up time the AD7991/AD7995/AD7999 exits

shut down mode and begins to acquire the analog input. The

channels being converted will depend on the status of the

channel bits in the Control register.

AD7991/AD7995/AD7999 if no further reads are required. If

the master does not issue a NAK and sends an ACK to the

AD7991/AD7995/AD7999 the ADC will once again power up

and complete a conversion. If more than one channel bit has

been set in the control register then this conversion will be

preformed on the second channel in the selected sequence. If

only one channel was selected the ADC will convert again on

the selected channel.

After the read address acknowledge the ADC will output two

bytes of data. The first byte will contain 4 status bits and the 4

MSBs of the conversion result. The status bits will contain 2

leading zeros and 2 channel identifier bits. After this first byte

the AD7991/AD7995/AD7999 will then output the second byte

9

1

9

1

9

SCL

SDA

Sr/

P

Sr

7-BIT ADDRESS

R

A

FIRST DATA BYTE (MSBs)

SECOND DATA BYTE (LSBs)

ACK BY

ADC

ACK BY

MASTER

NACK BY

MASTER

Figure 19. Mode Of Operation

Rev.PrB | Page 24 of 25

Preliminary Technical Data

OUTLINE DIMENSIONS

AD7991/AD7995/AD7999

2.90 BSC

8

1

7

2

6

3

5

4

1.60 BSC

2.80 BSC

PIN 1

INDICATOR

0.65 BSC

1.95

BSC

1.30

1.15

0.90

1.45 MAX

0.22

0.08

0.60

0.45

0.30

8°

4°

0°

0.38

0.22

0.15 MAX

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-178-BA

Figure 20.8-Lead Small Outline Transistor Package (SOT-23)

(RJ-8)

Dimensions shown in millimeter

ORDERING GUIDE

Model

Temperature Range

-40°C to 85° C

Package Description

Package Option

AD7991BRJZ-1¹

AD7991BRJZ-0¹

AD7991YRJZ-1¹

AD7991YRJZ-0¹

AD7995YRJZ-1¹

AD7995YRJZ-0¹

AD7999YRJZ-1¹

AD7999YRJZ-0¹

8-LEAD SOT-23

-40°C to 85° C

-40°C to 125° C

¹Z = Pb-free part.

and registered trademarks are the property of their

respective owners.

PR06461-0-10/06(PrB)


型号：	AD7995YRJZ-1
厂家：	ADI
描述：	4-Channel, 12-/10-/8-Bit ADC with I2CCompatible Interface in 8-Lead SOT23 4通道， 12 /10位/ 8位ADC， I2CCompatible接口采用8引脚SOT23
文件：	总25页 (文件大小：259K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7995YRJZ-1 [ADI]

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