AD8015ARZ-REEL7 [ADI]
155 Mbps Transimpedance Amplifier;
| 型号： | AD8015ARZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 155 Mbps Transimpedance Amplifier 电信 光电二极管 电信集成电路 |
| 文件： | 总9页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wideband/Differential Output
Transimpedance Amplifier
a
AD8015
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Low Cost, Wide Bandw idth, Low Noise
Bandw idth: 240 MHz
Pulse Width Modulation: 500 ps
Rise Tim e/ Fall Tim e: 1.5 ns
Input Current Noise: 3.0 pA/ √Hz @ 100 MHz
Total Input RMS Noise: 26.5 nA to 100 MHz
Wide Dynam ic Range
AD8015
+VS
8
7
6
5
1
2
3
NC
IIN
10kΩ
50Ω
+OUTPUT
–OUTPUT
+1
+1
G = 30
G = 3
NC
50Ω
Optical Sensitivity: –36 dBm @ 155.52 Mbps
Peak Input Current: ؎350 A
Differential Outputs
–VS
VBYP
– +
+V
S
4
1.7V
NC = NO CONNECT
Low Pow er: 5 V @ 25 m A
Wide Operating Tem perature Range: –40؇C to +85؇C
APPLICATIONS
25.0E+3
20.0E+3
15.0E+3
10.0E+3
5.0E+3
Fiber Optic Receivers: SONET/ SDH, FDDI, Fibre Channel
Stable Operation w ith High Capacitance Detectors
Low Noise Pream plifiers
Single-Ended to Differential Conversion
I-to-V Converters
DIFFERENTIAL
SINGLE-ENDED
P RO D UCT D ESCRIP TIO N
The AD8015 is a wide bandwidth, single supply transimpedance
amplifier optimized for use in a fiber optic receiver circuit. It is a
complete, single chip solution for converting photodiode current
into a differential voltage output. The 240 MHz bandwidth enables
AD8015 application in FDDI receivers and SONET /SDH
receivers with data rates up to 155 Mbps. T his high bandwidth
supports data rates beyond 300 Mbps. T he differential outputs
drive ECL directly, or can drive a comparator/ fiber optic post
amplifier.
000.E+0
10.0E+6
100.0E+6
FREQUENCY – Hz
1.0E+9
Figure 1. Differential/Single-Ended Transim pedance vs.
Frequency
5.0
In addition to fiber optic applications, this low cost, silicon al-
ternative to GaAs-based transimpedance amplifiers is ideal for
systems requiring a wide dynamic range preamplifier or single-
ended to differential conversion. T he IC can be used with a
standard ECL power supply (–5.2 V) or a PECL (+5 V) power
supply; the common mode at the output is ECL compatible.
T he AD8015 is available in die form, or in an 8-pin SOIC
package.
3.0pF
4.5
4.0
2.0pF
1.5pF
3.5
3.0
2.5
1.0pF
0.5pF
2.0
000.0E+0
20.0E+6
40.0E+6
60.0E+6
80.0E+6
100.0E+6
FREQUENCY – Hz
Figure 2. Noise vs. Frequency (SO-8 Package with
Added Capacitance)
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
AD8015* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DOCUMENTATION
Data Sheet
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• AD8015: Wideband/Differential Output Transimpedance
Amplifier Data Sheet
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number.
REFERENCE MATERIALS
Informational
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DESIGN RESOURCES
• AD8015 Material Declaration
• PCN-PDN Information
• Quality And Reliability
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(SO Package @ T = +25؇C and V = +5 V, unless otherwise noted)
AD8015–SPECIFICATIONS
A
S
AD 8015AR
Typ
P aram eter
Conditions
Min
Max
Units
DYNAMIC PERFORMANCE
Bandwidth
Pulse Width Modulation
Rise and Fall T ime
Settling T ime1
3 dB
180
240
500
1.5
3
MHz
ps
ns
10 µA to 200 µA Peak
10% to 90%
to 3%, 0.5 V Diff Output Step
ns
INPUT
Linear Input Current Range
Max Input Current Range
Optical Sensitivity
±2.5%, Nonlinearity
Saturation
155 Mbps, Avg Power
Die, by Design
±25
±200
±30
±350
–36
0.2
µA
µA
dBm
pF
Input Stray Capacitance
SOIC, by Design
+VS to IIN and VBYP
0.4
1.8
pF
V
Input Bias Voltage
NOISE
1.6
2.0
Die, Single Ended at POUT
,
or Differential (POUT –NOUT ),
CST RAY = 0.3 pF
f = 100 MHz
Input Current Noise
3.0
pA/√Hz
T otal Input RMS Noise
DC to 100 MHz
26.5
nA
T RANSFER CHARACT ERIST ICS
T ransresistance
Single Ended
Differential
Single Ended
Differential
8
16
10
20
37.0
40
12
24
kΩ
kΩ
dB
dB
Power Supply
Rejection Ratio
OUT PUT
Differential Offset
Output Common-Mode Voltage
Voltage Swing (Differential)
6
20
–1.1
mV
V
V p-p
mV p-p
Ω
From Positive Supply
Positive Input Current, RL = ∞
Positive Input Current, RL = 50 Ω
–1.5
40
–1.3
1.0
600
50
Output Impedance
60
POWER SUPPLY
Operating Range
TMIN to TMAX
Single Supply
Dual Supply
+4.5
±2.25
+5
25
+11
±5.5
26
V
V
mA
Current
NOT ES
1Settling T ime is defined as the time elapsed from the application of a perfect step input to the time when the output has entered and remained within a specified error
band symmetrical about the final value. T his parameter includes propagation delay, slew time, overload recovery, and linear settling times.
Specifications subject to change without notice.
NOT ES
ABSO LUTE MAXIMUM RATINGS1
1Stresses above those listed under “Absolute Maximum Ratings” may cause
Supply Voltage (+VS to –VS). . . . . . . . . . . . . . . . . . . . . . . 12 V
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
Internal Power Dissipation2
operational section of this specification is not implied. Exposure to absolute
Small Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 Watts
Output Short Circuit Duration . . . . . . . . . . . . . . . Indefinite
Maximum Input Current . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
maximum rating conditions for extended periods may affect device reliability.
2Specification is for device in free air: 8-pin SOIC package: θJA = 155°C/W.
Storage T emperature Range . . . . . . . . . . . . –65°C to +125°C
Operating T emperature Range (TMIN to T MAX
AD8015ACHIP/AR . . . . . . . . . . . . . . . . . . –40°C to +85°C
Maximum Junction T emperature . . . . . . . . . . . . . . . . . +165°C
Lead T emperature Range (Soldering 10 sec) . . . . . . . . +300°C
O RD ERING GUID E
)
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
AD8015AR
–40°C to +85°C 8-Pin Plastic SOIC SO-8
AD8015ACHIPS –40°C to +85°C Die Form
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8015 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–2–
REV. A
AD8015
+VS
1.7V
P IN CO NFIGURATIO N
+VS
AD8015
10kΩ
AD8015
V1
1
2
3
8
7
6
+VS
8
7
6
5
1
2
3
NC
IIN
10kΩ
LPF:
3dB@
0.7 x F
R
R
50Ω
50Ω
+1
+1
CLK
DATA
CLOCK
RECOVERY
+OUTPUT
–OUTPUT
–VS
+1
+1
G = 30
LPF:
3dB@
0.7 x F
G = 30
G = 3
G = 3
QUANTIZER
50Ω
NC
50Ω
R > 40Ω
C1 >100pF
4.5V < VS < 11V
.
–
+
+V
S
4
5
VBYP
– +
+V
S
4
1.7V
C1
1.7V
NC = NO CONNECT
Figure 3. Fiber Optic Receiver Application: Photodiode
Referred to Positive Supply
METALIZATIO N P H O TO GRAP H
D imensions shown in microns. N ot to scale.
+V
S
OPTIONAL
+V CONNECTION
P H O TO D IO D E REFERRED TO NEGATIVE SUP P LY
Figure 4 shows the AD8015 used in a circuit where the photo-
diode is referred to the negative supply. T his results in a larger
back bias voltage than when referring the photodiode to the
positive supply. T he larger back bias voltage on the photodiode
decreases the photodiode’s capacitance thereby increasing its
bandwidth. T he R2, C2 network shown in Figure 4 is added to
decouple the photodiode to the positive supply. T his improves
PSRR.
S
I
IN
+OUTPUT
838µ
998µ
+VS
–OUTPUT
+VS
AD8015
V1
1
2
3
8
7
6
10kΩ
LPF:
3dB@
0.7 x F
C2
R
R
50Ω
+1
+1
CLK
CLOCK
RECOVERY
+VS
1.7V
G = 30
LPF:
3dB@
0.7 x F
DATA
G = 3
QUANTIZER
50Ω
R2
R > 40Ω
C1 >100pF
4.5V < VS < 11V
R2 AND C2 OPTIONAL
FOR IMPROVED PSRR
V
BYP
–V
S
–
+
+V
S
4
5
813µ
973µ
1.7V
C1
NOTE:
FOR BEST PERFORMANCE ATTACH PACKAGE
SUBSTRATE TO +V .
S
MATERIAL AT BACK OF DIE IS SILICON. USE OF
+V OR –V FOR DIE ATTACH IS ACCEPTABLE.
Figure 4. Fiber Optic Receiver Application: Photodiode
Referred to Negative Supply
S
S
FIBER O P TIC SYSTEM NO ISE P ERFO RMANCE
T he AD8015 maintains 26.5 nA referred to input (RT I) to 100
MHz. Calculations below translate this specification into mini-
mum power level and bit error rate specifications for SONET
and FDDI systems. T he dominant sources of noise are: 10 kΩ
feedback resistor current noise, input bipolar transistor base
current noise, and input voltage noise.
FIBER O P TIC RECEIVER AP P LICATIO NS
In a fiber optic receiver, the photodiode can be placed from the
IIN pin to either the positive or negative supply. T he AD8015
converts the current from the photodiode to a differential volt-
age in these applications. T he voltage at the VBYP pin is ≈1.8 V
below the positive supply. T his node must be bypassed with a
capacitor (C1 in Figures 3 and 4 below) to the signal ground. If
large levels of power supply noise exist, then connecting C1 to
+VS is recommended for improved noise immunity. For opti-
mum performance, choose C1 such that C1 > 1/(2 π × 1000 ×
T he AD8015 has dielectrically isolated devices and bond pads
that minimize stray capacitance at the IIN pin. Input voltage
noise is negligible at lower frequencies, but can become the
dominant noise source at high frequencies due to IIN pin stray
capacitance. Minimizing the stray capacitance at the IIN pin is
critical to maintaining low noise levels at high frequencies. T he
pins surrounding the IIN pin (Pins 1 and 3) have no internal
connection and should be left unconnected in an application.
T his minimizes IIN pin package capacitance. It is best to have no
ground plane or metal runs near Pins 1, 2, and 3 and to mini-
mize capacitance at the IIN pin.
fMIN); where fMIN is the minimum useful
frequency in Hz.
P H O TO D IO D E REFERRED TO P O SITIVE SUP P LY
Figure 3 shows the AD8015 used in a circuit where the photo-
diode is referred to the positive supply. T he back bias voltage on
the photodiode is ≈1.8 V. T his method of referring the photo-
diode provides greater power supply noise immunity (PSRR)
than referring the photodiode to the negative supply. T he signal
path is referred to the positive rail, and the photodiode capaci-
tance is not modulated by high frequency noise that may exist
on the negative rail.
T he AD8015AR (8-pin SOIC) IIN pin total stray capacitance is
0.4 pF without the photodiode. Photodiodes used for SONET
or FDDI systems typically add 0.3 pF, resulting in roughly
0.7 pF total stray capacitance.
REV. A
–3–
AD8015
SO NET O C-3 SENSITIVITY ANALYSIS
Sensitivity (minimum power level) = 492/0.85 nW
= 579 nW (peak)
OC-3 Minimum Bandwidth = 0.7 × 155 MHz ≈ 110 MHz
Total Current Noise = (π/2) × 26.5 nA
= –32.4 dBm (peak)
= 42 nA (assuming single pole response)
T o maintain a BER < 1 × 10–10 (1 error per 10 billion bits):
= –35.4 dBm (average)
T he FDDI specification allows for a minimum power level of
–28 dBm peak, or –31 dBm average. Using the AD8015 pro-
vides 4.4 dB margin.
Minimum current level needs to be > 13 × Total Current Noise
= 541 nA (peak)
Assume a typical photodiode current/power conversion ratio
TH EO RY O F O P ERATIO N
= 0.85 A/W
T he simplified schematic is shown in Figure 5. Q1 and Q3 make
up the input stage, with Q3 running at 300 µA and Q1 running
at 2.7 mA. Q3 runs essentially as a grounded emitter. A large
capacitor (0.01 µF) placed from VBYP to the positive supply
shorts out the noise of R17, R21, and Q16. T he first stage of the
amplifier (Q3, R2, Q4, and C1) functions as an integrator, inte-
grating current into the IIN pin. T he integrator drives a differen-
tial stage (Q5, Q6, R5, R3, and R4) with gains of +3 and –3.
T he differential stage then drives emitter followers (Q41, Q42,
Q60 and Q61). T he positive output of the differential stage pro-
vides the feedback by driving RFB. T he differential outputs are
buffered using Q7 and Q8.
Sensitivity (minimum power level) = 541/0.85 nW
= 637 nW (peak)
= –32.0 dBm (peak)
= –35.0 dBm (average)
T he SONET OC-3 specification allows for a minimum power
level of –31 dBm peak, or –34 dBm average. Using the AD8015
provides 1 dB margin.
FD D I SENSITIVITY ANALYSIS
FDDI Minimum Bandwidth = 0.7 × 125 MHz ≈ 88 MHz
T he bandwidth of the AD8015 is set to within +20% of the
nominal value, 240 MHz, by factory trimming R5 to 60 Ω. T he
following formula describes the AD8015 bandwidth:
88 MHz
Total Current Noise = (π / 2) ×
× 26.5 nA
100 MHz
Bandwidth = 1/(2 π × C1 × RFB × (R5 + 2 re)/R4)
= 39 nA (assuming single pole response)
where re (of Q5 and Q6) = 9 Ω each, constant over temperature,
and RFB/R4 = 43.5, constant over temperature.
T o maintain a BER < 2.5 × 10–10 (1 error per 4 billion bits):
T he bandwidth equation simplifies, and the bandwidth depends
only on the value of C1:
Minimum current level needs to be > 12.6 × Total Current Noise
= 492 nA (peak)
Bandwidth = 1/(2 π × 3393 × C1).
Assume a typical photodiode current/power conversion ratio
= 0.85 A/W
+VS
R17
635
R1
300
R2
3k
R3
230
R4
230
330
Q4
Q42
R21
1.8k
Q41
INPUT
CLAMPS
+OUTPUT
Q8
Q16
R44 50
Q7
Q60
V
I
Q3
Q1
BYP
IN
Q5
Q6
C1 0.2pF
330
+V
S
–OUTPUT
R5 60
R43 50
I10
Q61
0.75MA
Q56
RFB
10k
I5
I2
3MA
I3
1MA
I4
3MA
I6
1MA
I7
1MA
I8
1MA
I9
1MA
I1
1.5MA
3MA
–VS
Figure 5. AD8015 Sim plified Schem atiic
–4–
REV. A
AD8015
1.5
1.0
9
+85°C
+85°C
– 40°C
+ 25°C
0.5
–40°C AND 0°C
5
0
4k
IN
–0.5
–1.0
–1.5
VOUT
0
50Ω
AD8015
–100 –80 –60 –40 –20
0
20
40
60
80
100
1000
1
10
100
FREQUENCY – MHz
INPUT CURRENT – µA
Figure 6. Differential Output vs. Input Current
Figure 9. Gain vs. Frequency
0
10
–0.5
+85°C
+25°C
PIN 7
5V, +25°C
–1.0
–1.5
–2.0
–2.5
–40°C
0
–40°C
PIN 6
+25°C
+85°C
–100 –80 –60 –40 –20
0
20
40
60
80 100
10
100
1000
INPUT CURRENT – µA
FREQUENCY – MHz
Figure 10. Group Delay vs. Frequency
Figure 7. Single-Ended Output vs. Input Current
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
300
290
280
270
260
250
240
230
220
210
200
11.0V
5.0V
4.5V
–40 –30 –20 –10
0
10 20 30
40 50
60 70
80
10.0E+6
100.0E+6
1.0E+9
TEMPERATURE – °C
FREQUENCY – Hz
Figure 8. Bandwidth vs. Tem perature
Figure 11. Differential Gain vs. Supply
REV. A
–5–
AD8015
100
AP P LICATIO N
155 Mbps Fiber O ptic Receiver
5V, +25°C
T he AD8015 and AD807 can be used together for a complete
155 Mbps Fiber Optic Receiver (T ransimpedance Amplifier,
Post Amplifier with Signal Detect Output, and Clock Recovery
and Data Retiming) as shown in Figure 16.
PIN 7
50
T he PIN diode front end is connected to a single mode, 1300 nm
laser source. T he PIN diode has 3.3 V reverse bias, 0.8 A/W
responsivity, 0.7 pF capacitance, and 2.5 GHz bandwidth.
PIN 6
T he AD8015 outputs (POUT and NOUT ) drive a differential, con-
stant impedance (50 Ω) low-pass π filter with a 3 dB cutoff of
100 MHz. T he outputs of the low-pass filter are ac coupled to
the AD807 inputs (PIN and NIN). T he AD807 PLL damping
factor is set at 10 using a 0.22 µF capacitor.
0
1000
1
10
100
FREQUENCY – MHz
T he entire circuit was enclosed in a shielded box. T able I sum-
marizes results of tests performed using a 223–1 PRN sequence,
and varying the average power at the PIN diode.
Figure 12. Output Im pedance vs. Frequency
T he circuit acquires and maintains lock with an average input
100
power as low as –39.25 dBm.
30 DEVICES, 2 LOTS:
(+OUT, –OUT) × (25°C, –40°C, 85°C) × (5V, 4.5V, 11.0V)
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
0
–100
0
10
20
TIME – ns
10
0
Figure 13. Sm all Signal Pulse Response
2
0
FREQUENCY – Hz
1pF
–2
Figure 15. Bandwidth Distribution Matrix
–4
–6
5pF
8pF
0pF
3pF
–8
–10
–12
10.0E+6
100.0E+6
1.0E+9
FREQUENCY – Hz
Figure 14. Differential Gain vs. Input Capacitance
–6–
REV. A
AD8015
C1
0.1µF
SDOUT
TP7
TP8
C1
100pF
C2
0.1µF
R1 R2
R11 R10
154 154
R17
C12
R16
301
R5 100
R6 100
C13
0.1µF
100 100
3.65k 2.2µF
1
2
3
VEE 16
15
DATAOUTN
DATAOUTP
VCC2
DATAOUTN
DATAOUTP
C3
0.1µF
SDOUT
C11
C4
0.1µF
AVCC 14
PIN 13
R14
50
R15
50
C7
R7 100
R8 100
4
5
6
CLKOUTN
CLKOUTP
VCC1
CLKOUTN
CLKOUTP
NIN 12
C10
TP6
C5
0.1µF
11
10
9
AVCC
THRADJ
AVEE
C8
TP1
R4
100
R3
100
CF1
7
8
C15
0.1µF 0.1µF
C14
CD
R13
THRADJ
100
pF
R11
154
R12
154
CF2
TP2
AD807
TP5
C6
0.1µF
DAMPING
CAP,0.22µF
C9
10µF
50Ω
LINE
50Ω
LINE
GND
TP4
0.1µF
10µF
5V
TP3
ABB HAFO
1A227
FC HOUSING
1
2
NC
+VS
8
7
6
5
150nH
15pF
IIN
+OUT
NOTES
0.8 A/W, 0.7pF
2.5GHz
1. ALL CAPS ARE CHIP,
15pF ARE MICA.
NC
3
4
–OUT
–VS
150nH
15pF
VBYP
2. 150 nH ARE SMT
AD8015
NC = NO CONNECT
0.1µF
0.01µF
Figure 16. 155 Mbps Fiber Optic Receiver Schem atic
Table I. AD 8015, AD 807 Fiber O ptic Receiver Circuit:
O utput Bit Error Rate & O utput Jitter vs. Average Input P ower
Average O ptical
Input P ower (dBm )
O utput Bit
Error Rate
O utput Jitter
(ps rm s)
–6.4
Loses Lock
1.2 × 10–2
7.5 × 10–3
9.4 × 10–4
1 × 10–14
–6.45
–6.50
–6.60
–6.70
–7.0 to
–35.50
–36.00
1 × 10–14
< 40
< 40
3.0 × 10–12
–36.50
–37.00
–37.50
–38.00
–38.50
–39.00
–39.1
–39.20
–39.25
–39.30
4.8 × 10–10
2.8 × 10–8
8.2 × 10–7
1.3 × 10–5
1.1 × 10–4
1.0 × 10–3
1.3 × 10–3
1.9 × 10–3
2.2 × 10–3
Loses Lock
REV. A
–7–
AD8015
AC CO UP LED P H O TO D IO D E AP P LICATIO N FO R
IMP RO VED D YNAMIC RANGE
and typical sensitivity of –35 dBm. AC coupling the input also
results in improved pulse width modulation performance.
AC coupling the photodiode current input to the AD8015 (Fig-
ure 17) extends fiber optic receiver overload by 3 dB while sacri-
ficing only 1 dB of sensitivity (increasing receiver dynamic range
by 2 dB). T his application results in typical overload of –4 dBm,
Careful attention to minimize parasitic capacitance at the
AD8015 input (from the photodetector input), RAC and CAC are
critical for sensitivity performance in this application. Note that
CAC of 0.01 µF was chosen for a low frequency cutoff equal to
2.2 kHz.
+VS
+VS
AD8015
V1
1
2
3
8
7
6
10kΩ
LPF:
3dB@
0.7 x F
C
R
AC
R
50Ω
+1
+1
CLK
CLOCK
RECOVERY
G = 30
0.01µF
LPF:
3dB@
0.7 x F
DATA
R
AC
7k
G = 3
QUANTIZER
50Ω
R > 40Ω
C1 >100pF
4.5V < VS < 11V
–
+
+V
S
4
5
1.7V
C1
Figure 17. AC Coupled Photodiode Application for Im proved Dynam ic Range
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-Lead Sm all O utline IC P ackage (SO -8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.020 (0.51)
0.013 (0.33)
0.0500
(1.27)
BSC
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0098 (0.25)
0.0075 (0.19)
–8–
REV. A
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