AD8016ARE-REEL7 [ADI]
Low Power, High Output Current xDSL Line Driver; 低功耗，高输出电流的xDSL线路驱动器
| 型号： | AD8016ARE-REEL7 |
| 厂家： | 
ADI |
| 描述： | Low Power, High Output Current xDSL Line Driver |
| 文件： | 总20页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power, High Output Current
xDSL Line Driver
a
AD8016
FEATURES
PIN CONFIGURATION
24-Lead Batwing
(RB-24)
xDSL Line Driver that Features Full ADSL CO (Central
Office) Performance on ꢀ12 V Supplies
Low Power Operation
ꢀ5 V to ꢀ12 V Voltage Supply
12.5 mA/Amp (Typ) Total Supply Current
Power Reduced Keep Alive Current of 4.5 mA/Amp
High Output Voltage and Current Drive
IOUT = 600 mA
40 V p-p Differential Output Voltage RL = 50 ꢁ,
VS = ꢀ12 V
Low Single-Tone Distortion
–75 dBc @ 1 MHz SFDR, RL = 100 ꢁ, VO = 2 V p-p
MTPR = –75 dBc, 26 kHz to 1.1 MHz, ZLINE = 100 ꢁ,
PLINE = 20.4 dBm
20-Lead PSOP3
(RP-20)
1
2
20
+V2
V
+V1
1
1
2
24
23
22
21
20
19
18
17
16
15
+V1
1
+V2
V
V
2
19
18
17
16
15
14
13
12
11
V
OUT
OUT
2
OUT
OUT
V
1
V 2
INN
3
INN
3
V
1
1
V
V
2
INN
INN
+
+
–
–
+
+
–
–
V
1
V
2
4
INP
INP
4
V
2
INP
INP
AGND
AGND
AGND
AGND
PWDN0
DGND
–V1
5
AGND
AGND
AGND
AGND
PWDN1
BIAS
5
NC
NC
NC
NC
NC
NC
6
6
7
AD8016
AD8016
7
8
8
PWDN0
DGND
–V1
PWDN1
BIAS
–V2
9
9
10
11
10
14 –V2
13
NC 12
NC
NC = NO CONNECT
High Speed
NC = NO CONNECT
78 MHz Bandwidth (–3 dB), G = +5
40 MHz Gain Flatness
1000 V/ꢂs Slew Rates
28-Lead TSSOP-EP
(RE-28-1)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
NC
NC
NC
NC
NC
3
NC
PRODUCT DESCRIPTION
+V
–V
2
4
NC
IN
The AD8016 high output current dual amplifier is designed
for the line drive interface in Digital Subscriber Line systems
such as ADSL, HDSL2, and proprietary xDSL systems. The
drivers are capable, in full-bias operation, of providing 24.4 dBm
output power into low resistance loads, enough to power a
20.4 dBm line, including hybrid insertion loss.
2
5
PWDN1
BIAS
–V2
IN
6
V
2
OUT
7
+V2
+V1
AD8016ARE
8
–V1
9
V
1
DGND
NC
OUT
10
11
12
13
14
–V
1
1
IN
+V
PWDN0
NC
IN
NC
NC
NC
NC
NC
NC = NO CONNECT
The AD8016 is available in a low cost 24-lead SO-Batwing,
a thermally enhanced 20-lead PSOP3, and a 28-lead TSSOP-EP
with an exposed lead frame (ePAD). Operating from 12 V
supplies, the AD8016 requires only 1.5 W of total power
dissipation (refer to the Power Dissipation section for details)
while driving 20.4 dBm of power downstream using the
xDSL hybrid in Figure 33a and Figure 33b. Two digital bits
(PWDN0, PWDN1) allow the driver to be capable of full perfor-
mance, an output keep-alive state, or two intermediate bias
states. The keep-alive state biases the output transistors enough
to provide a low impedance at the amplifier outputs for back
termination.
–75dBc
549.3
551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3
FREQUENCY (kHz)
550.3
Figure 1. Multitone Power Ratio; VS = 12 V, 20.4 dBm
Output Power into 100 Ω, Downstream
The low power dissipation, high output current, high output voltage
swing, flexible power-down, and robust thermal packaging enable
the AD8016 to be used as the Central Office (CO) terminal driver
in ADSL, HDSL2, VDSL, and proprietary xDSL systems.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(@ 25ꢃC, VS = ꢀ12 V, RL = 100 ꢁ, PWDN0, PWDN1 = (1, 1), TMIN = –40ꢃC,
MAX = +85ꢃC, unless otherwise noted.)
T
AD8016–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p
G = +5, RF = 499 Ω, VOUT < 0.5 V p-p
G = +5, RF = 499 Ω, VOUT = 0.2 V p-p
380
78
38
MHz
MHz
MHz
MHz
dB
V/µs
ns
69
16
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Peaking
Slew Rate
Rise and Fall Time
Settling Time
V
OUT = 4 V p-p
90
VOUT = 0.2 V p-p < 50 MHz
VOUT = 4 V p-p, G = +2
VOUT = 2 V p-p
0.1%, VOUT = 2 V p-p
VOUT = 12.5 V p-p
0.1
1000
2
23
350
ns
ns
Input Overdrive Recovery Time
NOISE/DISTORTION PERFORMANCE
Distortion, Single-Ended
Second Harmonic
Third Harmonic
Multitone Power Ratio*
V
OUT = 2 V p-p, G = +5, RF = 499 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
26 kHz to 1.1 MHz, ZLINE = 100 Ω,
PLINE = 20.4 dBm
–75/–62 –77/–64
–88/–74 –93/–76
dBc
dBc
–75
dBc
IMD
IP3
500 kHz, ∆f = 10 kHz, RL = 100 Ω/25 Ω
500 kHz, RL = 100 Ω/25 Ω
f = 10 kHz
–84/–80 –88/–85
dBc
dBm
nV/√Hz
pA√Hz
42/40
43/41
2.6
Voltage Noise (RTI)
Input Current Noise
4.5
21
f = 10 kHz
18
INPUT CHARACTERISTICS
RTI Offset Voltage
+Input Bias Current
–Input Bias Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
–3.0
–45
–75
1.0
+3.0
+45
+75
mV
µA
µA
kΩ
pF
V
4
400
2
–10
58
+10
+11
64
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Single-Ended, RL = 100 Ω
G = 5, RL = 10 Ω, f1 = 100 kHz,
–60 dBc SFDR
–11
400
V
600
2000
80
mA
mA
pF
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
3
13
13.2
10
8
V
PWDN1, PWDN0 = (1, 1)
PWDN1, PWDN0 = (1, 0)
PWDN1, PWDN0 = (0, 1)
PWDN1, PWDN0 = (0, 0)
To 95% of IQ
250 µA Out of Bias Pin
∆VS = 1 V
12.5
8
5
mA/Amp
mA/Amp
mA/Amp
mA/Amp
µs
4
6
Recovery Time
Shutdown Current
Power Supply Rejection Ratio
25
1.5
75
4.0
mA/Amp
dB
63
OPERATING TEMPERATURE RANGE
–40
+85
°C
*See Figure 43, R20, R21 = 0 Ω, R1 = open.
Specifications subject to change without notice.
REV. B
–2–
AD8016
(@ 25ꢃC, VS = ꢀ6 V, RL = 100 ꢁ, PWDN0, PWDN1 = (1, 1), TMIN = –40ꢃC,
TMAX = +85ꢃC, unless otherwise noted.)
SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p
G = +5, RF = 499 Ω, VOUT < 0.5 V p-p
G = +5, RF = 499 Ω, VOUT = 0.2 V p-p
VOUT = 1 V rms
VOUT = 0.2 V p-p < 50 MHz
VOUT = 4 V p-p, G = +2
320
71
15
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
70
10
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Peaking
Slew Rate
Rise and Fall Time
Settling Time
80
0.7
300
2
1.0
VOUT = 2 V p-p
0.1%, VOUT = 2 V p-p
39
Input Overdrive Recovery Time
VOUT = 6.5 V p-p
350
ns
NOISE/DISTORTION PERFORMANCE
Distortion, Single-Ended
Second Harmonic
Third Harmonic
Multitone Power Ratio*
G = +5, VOUT = 2 V p-p, RF = 499 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
26 kHz to 138 kHz, ZLINE = 100 Ω,
PLINE = 13 dBm
–73/61
–80/–68
–75/–63
–82/–70
dBc
dBc
–68
dBc
IMD
IP3
500 kHz, ∆f = 110 kHz, RL = 100 Ω/25 Ω
–87/–82
42/39
–88/–83
42/39
4
dBc
dBm
nV/√Hz
pA√Hz
500 kHz
Voltage Noise (RTI)
Input Current Noise
f = 10 kHz
f = 10 kHz
5
20
17
INPUT CHARACTERISTICS
RTI Offset Voltage
+Input Bias Current
–Input Bias Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
–3.0
–25
–30
0.2
10
10
400
2
+3.0
+25
+30
mV
µA
µA
kΩ
pF
V
–4
60
+4
+5
66
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Single-Ended, RL = 100 Ω
G = +5, RL = 5 Ω, f = 100 kHz,
–60 dBc SFDR
–5
V
300
420
830
50
mA
mA
pF
Short-Circuit Current
Capacitive Load Drive
RS = 10 Ω
POWER SUPPLY
Quiescent Current
PWDN1, PWDN0 = (1, 1)
PWDN1, PWDN0 = (1, 0)
PWDN1, PWDN0 = (0, 1)
PWDN1, PWDN0 = (0, 0)
To 95% of IQ
250 µA Out of Bias Pin
∆VS = 1 V
8
6
4
3
23
1.0
80
9.7
6.9
5.0
4.1
mA/Amp
mA/Amp
mA/Amp
mA/Amp
µs
Recovery Time
Shutdown Current
Power Supply Rejection Ratio
2.0
mA/Amp
dB
63
OPERATING TEMPERATURE RANGE
–40
+85
°C
NOTES
*See Figure 43, R20, R21 = 0 Ω, R1 = open.
Specifications subject to change without notice.
LOGIC INPUTS (CMOS Compatible Logic) (PWDN0, PWDN1, VCC = ꢀ12 V or ꢀ6 V; Full Temperature Range)
Parameter
Min
Typ
Max
Unit
Logic 1 Voltage
Logic 0 Voltage
2.2
0
VCC
0.8
V
V
REV. B
–3–
AD8016
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V
Internal Power Dissipation
The maximum power that can be safely dissipated by the AD8016
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
device is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package.
PSOP3 Package2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2 W
SO-Batwing Package3 . . . . . . . . . . . . . . . . . . . . . . . . .1.4 W
TSSOP-EP Package4 . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W
Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VS
Output Short-Circuit Duration
The output stage of the AD8016 is designed for maximum load
current capability. As a result, shorting the output to common
can cause the AD8016 to source or sink 2000 mA. To ensure
proper operation, it is necessary to observe the maximum power
derating curves. Direct connection of the output to either power
supply rail can destroy the device.
. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device on a 4-layer board with 10 inches2 of 1 oz. copper at 85°C
20-lead PSOP3 package: θJA = 18°C/W.
8
7
6
3Specification is for device on a 4-layer board with 10 inches2 of 1 oz. copper at 85°C
24-lead Batwing package: θJA = 28°C/W.
PSOP3
5
4Specification is for device on a 4-layer board with 9 inches2 of 1 oz. copper at 85°C
28-lead (TSSOP-EP) package: θJA = 29°C/W.
4
SO-BATWING
3
TSSOP-EP
2
1
0
0
10
20
30
40
50
60
70
80
90
AMBIENT TEMPERATURE (ꢃC)
Figure 2. Maximum Power Dissipation vs.
Temperature for AD8016 for TJ = 125°C
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD8016ARP
–40°C to +85°C
–40°C to +85°C
20-Lead PSOP3
20-Lead PSOP3
RP-20A
RP-20A
AD8016ARP-REEL
AD8016ARP-EVAL
AD8016ARB
AD8016ARB-REEL
AD8016ARB-EVAL
AD8016ARE
AD8016ARE-REEL
AD8016ARE-REEL7
AD8016ARE-EVAL
Evaluation Board
24-Lead SO-Batwing
24-Lead SO-Batwing
Evaluation Board
28-Lead TSSOP-EP
28-Lead TSSOP-EP
28-Lead TSSOP-EP
Evaluation Board
–40°C to +85°C
–40°C to +85°C
RB-24
RB-24
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
RE-28-1
RE-28-1
RE-28-1
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8016 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–4–
Typical Performance Characteristics–AD8016
10ꢂF
+V
S
+
124ꢁ
499ꢁ
V
OUT
0.1ꢂF
R
+
L
+V
IN
+V
O
O
49.9ꢁ
V
IN
499ꢁ
499ꢁ
49.9ꢁ
+V
S
111ꢁ
R
L
0.1ꢂF
0.1ꢂF
10ꢂF
–V
0.1ꢂF
–V
+
IN
10ꢂF
49.9ꢁ
10ꢂF
–V
S
+
–V
S
Figure 6. Differential Test Circuit; G = +10
Figure 3. Single-Ended Test Circuit; G = +5
V
= 100mV
V
= 100mV
OUT
OUT
V
= 20mV
V
= 20mV
IN
IN
TIME (100ns/DIV)
TIME (100ns/DIV)
Figure 7. 100 mV Step Response; G = +5, VS = 12 V,
RL = 25 Ω, Single-Ended
Figure 4. 100 mV Step Response; G = +5, VS = 6 V,
RL = 25 Ω, Single-Ended
V
= 5V
OUT
V
= 4V
OUT
V
= 800mV
IN
V
= 800mV
IN
TIME (100ns/DIV)
TIME (100ns/DIV)
Figure 5. 4 V Step Response; G = +5, VS = 6 V,
RL = 25 Ω, Single-Ended
Figure 8. 4 V Step Response; G = +5, VS = 12 V,
RL = 25 Ω, Single-Ended
REV. B
–5–
AD8016
–30
–40
–30
–40
–50
–60
–70
–80
–90
–100
(0,0)
(0,0)
R
= 499ꢁ
R
= 499ꢁ
F
F
G = +10
= 4V p-p
G = +10
= 4V p-p
V
V
(0,1)
O
O
–50
(0,1)
(1,0)
–60
(1,0)
–70
PWDN1, PWDN0 = (1,1)
–80
PWDN1, PWDN0 = (1,1)
–90
–100
–110
–110
0.01
0.01
0.1
1
10
20
0.1
1
10
20
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Distortion vs. Frequency; Second Harmonic,
VS = 12 V, RL = 50 Ω, Differential
Figure 12. Distortion vs. Frequency; Third Harmonic,
VS = 12 V, RL = 50 Ω, Differential
–30
–30
(0,0)
R
= 499ꢁ
R
= 499ꢁ
F
F
–40
–50
–40
–50
G = +10
= 4V p-p
(0,1)
G = +10
= 4V p-p
(0,0)
(0,1)
V
V
O
O
(1,0)
(1,0)
–60
–60
–70
–70
PWDN1, PWDN0 = (1,1)
–80
–80
PWDN1, PWDN0 = (1,1)
–90
–90
–100
–100
–110
–110
0.01
0.1
1
10
20
0.01
0.1
1
10
20
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. Distortion vs. Frequency; Second Harmonic,
Figure 13. Distortion vs. Frequency; Third Harmonic,
VS = 6 V, RL = 50 Ω, Different
VS = 6 V, RL = 50 Ω, Differential
–30
–30
R
= 499ꢁ
F
R
= 499ꢁ
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
F
G = +5
G = +5
–40
–50
–60
–70
–80
–90
(1,0)
(0,0)
(0,1)
(1,0)
(0,0)
(0,1)
PWDN1, PWDN0 = (1,1)
PWDN1,
PWDN0 = (1,1)
0
100
200
300
400
500
600
700
800
0
100
200
300
400
500
600 700
PEAK OUTPUT CURRENT (mA)
PEAK OUTPUT CURRENT (mA)
Figure 11. Distortion vs. Peak Output Current; Second
Harmonic, VS = 12 V, RL = 10 Ω, f = 100 kHz, Single-Ended
Figure 14. Distortion vs. Peak Output Current, Third
Harmonic; VS = 12 V, RL = 10 Ω, G = +5, f = 100 kHz,
Single-Ended
REV. B
–6–
AD8016
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
R
= 499ꢁ
F
G = +5
(0,0)
(0,1)
(0,0)
(0,1)
(1,0)
(1,0)
PWDN1, PWDN0 = (1,1)
PWDN1, PWDN0 = (1,1)
400 500 600
0
100
200
300
400
500
600
0
100
200
300
PEAK OUTPUT CURRENT (mA)
PEAK OUTPUT CURRENT (mA)
Figure 15. Distortion vs. Peak Output Current; Second
Harmonic, VS = 6 V, RL = 5 Ω, f = 100 kHz, Single-Ended
Figure 18. Distortion vs. Peak Output Current; Third
Harmonic, VS = 6 V, G = +5, RL = 5 Ω, f = 100 kHz,
Single-Ended
–30
–40
–50
–30
–40
(0,0)
–50
(0,1)
(0,0)
–60
–60
(1,0)
(0,1)
–70
–80
–70
(1,0)
–80
PWDN1, PWDN0 = (1,1)
PWDN1, PWDN0 = (1,1)
–90
–90
–100
–100
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
DIFFERENTIAL OUTPUT (V p-p)
DIFFERENTIAL OUTPUT (V p-p)
Figure 16. Distortion vs. Output Voltage; Second
Harmonic, VS = 12 V, G = +10, f = 1 MHz, RL = 50 Ω,
Differential
Figure 19. Distortion vs. Output Voltage; Third
Harmonic, VS = 12 V, G = +10, f = 1 MHz, RL = 50 Ω,
Differential
–30
–30
–40
–50
–60
–40
(0,0)
–50
(0,1)
–60
(0,0)
(0,1)
(1,0)
–70
–70
(1,0)
PWDN1, PWDN0 = (1,1)
–80
–80
–90
PWDN1, PWDN0 = (1,1)
–90
0
5
10
15
20
0
5
10
15
20
DIFFERENTIAL OUTPUT (V p-p)
DIFFERENTIAL OUTPUT (V p-p)
Figure 17. Distortion vs. Output Voltage; Second
Harmonic, VS = 6 V, G = +10, f = 1 MHz, RL = 50 Ω,
Differential
Figure 20. Distortion vs. Output Voltage, Third Harmonic,
VS = 6 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential
REV. B
–7–
AD8016
6
3
3
0
0
–3
1,1
1,1
V
= 40mV p-p
IN
G = +5
= 100ꢁ
–3
–6
R
V
= 40mV p-p
1,0
0,1
L
–6
IN
–9
G = +5
= 100ꢁ
1,0
R
–9
L
–12
–15
–18
–21
–24
–12
–15
–18
–21
–24
0,1
0,0
0,0
–27
1
10
100
500
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 21. Frequency Response; VS = 12 V,
@ PWDN1, PWDN0 Codes
Figure 24. Frequency Response; VS = 6 V,
@ PWDN1, PWDN0 Codes
11
11
G = +5
G = +5
R
R
= 100ꢁ
= 499ꢁ
8
5
L
F
R
R
= 100ꢁ
= 499ꢁ
8
L
F
5
2
2
–1
–1
–4
–4
–7
–7
–10
–13
–16
–19
–10
–13
–16
–19
500
1
10
100
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 22. Output Voltage vs. Frequency; VS = 12 V
Figure 25. Output Voltage vs. Frequency; VS = 6 V
20
–10
R
= 499ꢁ
F
10
0
V
R
= 2V rms
= 602ꢁ
IN
–20
–30
–40
–50
–60
–70
–80
–90
1,1
F
1,0
+PSRR
–10
–20
–30
–40
–50
–60
–70
–80
0,1
–PSRR
0,0
0.03
0.1
1
10
100
500
0.01
0.1
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 26. PSRR vs. Frequency; VS = 12 V
Figure 23. CMRR vs. Frequency; VS = 12 V
@ PWDN1, PWDN0 Codes
REV. B
–8–
AD8016
180
160
140
120
100
80
10M
100k
10k
1k
360
320
280
240
200
160
120
80
90
80
70
60
50
40
30
20
10
0
PHASE
100
10
TRANSIMPEDANCE
60
1
0.1
0.01
0
+I
NOISE
40
V
IN NOISE
20
40
0
10
0
100
1k
10k
100k
1M
10M
0.0001 0.001
0.01
0.1
1
10
100
1000 10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 27. Noise vs. Frequency
Figure 30. Open-Loop Transimpedance and Phase
vs. Frequency
G = +2
F
G = +2
F
R
= 1kꢁ
R
= 1kꢁ
V
= 2V
V
= 2V
OUT
STEP
OUT STEP
R
= 100ꢁ
R
= 100ꢁ
L
L
+2mV
(–0.1%)
+2mV
(–0.1%)
0
0
–2mV
(–0.1%)
V
IN
–2mV
(–0.1%)
V
V
OUT
V
–V
IN
V
–V
IN
OUT
OUT IN
V
OUT
–5
0
5
10 15 20 25 30 35 40 45
TIME (ns)
–5
0
5
10 15 20 25 30 35 40 45
TIME (ns)
Figure 31. Settling Time 0.1%; VS = 6 V
Figure 28. Settling Time 0.1%; VS = 12 V
1000
100
–20
V
R
= 2V p-p
= 499ꢁ
OUT
–30
–40
–50
–60
–70
–80
–90
F
G = +5
R
= 100ꢁ
L
0,0
0,1
10
1
1,0
1,1
0.1
0.01
0.03
0.1
1
10
100
500
0.03
0.1
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 32. Output Impedance vs. Frequency
@ PWDN1, PWDN0 Codes
Figure 29. Output Crosstalk vs. Frequency
REV. B
–9–
AD8016
18
16
14
12
10
8
V
V
= 2V/DIV
IN
= 5V/DIV
OUT
PWDN1, PWDN0 = (1,1)
V
OUT
[1,0]
[0,1]
0V
V
IN
6
[0,0]
4
0V
2
0
–100
0
100 200 300 400 500 600 700 800 900
TIME (ns)
0
50
100
(ꢂA)
150
200
I
BIAS
Figure 33a. Overload Recovery; VS = 12 V,
Figure 35. IQ vs. IBIAS Current; VS = 6 V
G = +5, RL = 100 Ω
12
+V
OUT
, V = ꢀ12V
S
8
4
0
V
V
= 2V/DIV
= 5V/DIV
IN
+V
OUT
, V = ꢀ6V
S
OUT
0V
0V
V
OUT
–4
–8
V
IN
–V
OUT
, V = ꢀ6V
S
–V
OUT
, V = ꢀ12V
S
–12
10
100
1k
10k
R
(ꢁ)
LOAD
–100
0
100 200 300 400 500 600 700 800 900
TIME (ns)
Figure 36. Output Voltage vs. RLOAD
Figure 33b. Overload Recovery; VS = 12 V,
G = +5, RL = 100 Ω
25
PWDN1, PWDN0 = (1,1)
20
[1,0]
[0,1]
15
10
5
[0,0]
0
0
50
100
(ꢂA)
150
200
I
BIAS
Figure 34. IQ vs. IBIAS Current; VS = 12 V
REV. B
–10–
AD8016
FEEDBACK RESISTOR SELECTION
THEORY OF OPERATION
In current feedback amplifiers, selection of feedback and gain
resistors has an impact on the MTPR performance, bandwidth,
and gain flatness. Care should be taken in selecting these resis-
tors so that optimum performance is achieved. The table below
shows the recommended resistor values for use in a variety of
gain settings. These values are suggested as a good starting
point when designing for any application.
The AD8016 is a current feedback amplifier with high (500 mA)
output current capability. With a current feedback amplifier, the
current into the inverting input is the feedback signal and the
open-loop behavior is that of a transimpedance, dVO/dIIN or TZ.
The open-loop transimpedance is analogous to the open-loop
voltage gain of a voltage feedback amplifier. Figure 37 shows a
simplified model of a current feedback amplifier. Since RIN is
proportional to 1/gm, the equivalent voltage gain is just TZ × gm,
where gm is the transconductance of the input stage. Basic
analysis of the follower with gain circuit yields
Table I. Resistor Selection Guide
Gain
RF (ꢁ)
RG (ꢁ)
VO
TZ(S)
+1
–1
+2
+5
+10
1000
500
650
750
1000
∞
= G ×
500
650
187
111
VIN
TZ(S) + G × RIN + RF
where:
RF
G = 1 +
RG
BIAS PIN AND PWDN FEATURES
The AD8016 is designed to cover both CO (central office) and
CPE (customer premise equipment) ends of an xDSL applica-
tion. It offers full versatility in setting quiescent bias levels for
the particular application from full ON to reduced bias (in three
steps) to full OFF (via BIAS pin). This versatility gives the
modem designer the flexibility to maximize efficiency while
maintaining reasonable levels of multitone power ratio (MTPR)
performance. Optimizing driver efficiency while delivering the
required DMT power is accomplished with the AD8016 through
the use of on-chip power management features. Two digitally
programmable logic pins, PWDN1 and PWDN0, may be used
to select four different bias levels: 100%, 60%, 40%, and 25%
of full quiescent power (see Table II).
1
RIN
=
≈ 25 Ω
gm
Recognizing that G × RIN << RF for low gains, the familiar
result of constant bandwidth with gain for current feedback
amplifiers is evident, the 3 dB point being set when |TZ| = RF.
Of course, for a real amplifier there are additional poles that
contribute excess phase and there is a value for RF below which
the amplifier is unstable. Tolerance for peaking and desired flatness
determines the optimum RF in each application.
R
F
R
G
–
R
Table II. PWDN Code Selection Guide
IN
+
T
I
IN
V
OUT
Z
PWDN1
Code
PWDN0
Code
R
N
+
Quiescent Bias Level
V
IN
1
1
0
0
X
1
0
1
0
X
100% (Full ON)
60%
40%
25% (Low ZOUT but Not OFF)
Full OFF (High ZOUT via 250 µA
Pulled Out of BIAS Pin)
Figure 37. Simplified Block Diagram
The AD8016 is the first current feedback amplifier capable of
delivering 400 mA of output current while swinging to within
2 V of either power supply rail. This enables full CO ADSL
performance on only 12 V rails, an immediate 20% power saving.
The AD8016 is also unique in that it has a power management
system included on-chip. It features four user programmable
power levels (all of which provide a low output impedance of the
driver), as well as the provision for complete shutdown (high
impedance state). Also featured is a thermal shutdown with
alarm signal.
The bias level can be controlled with TTL logic levels (High = 1)
applied to the PWDN1 and PWDN0 pins alone or in combina-
tion with the BIAS control pin. The DGND or digital ground
pin is the logic ground reference for the PWDN1 and PWDN0
pins. In typical ADSL applications where 12 V or 6 V
supplies (also single supplies) are used, the DGND pin is
connected to analog ground.
POWER SUPPLY AND DECOUPLING
The BIAS control pin by itself is a means to continuously adjust
the AD8016 internal biasing and thus quiescent current IQ. By
pulling out a current of 0 µA (or open) to approximately 200 µA,
the quiescent current can be adjusted from 100% (full ON) to a
full OFF condition. The full OFF condition yields a high output
impedance. Because of an on-chip resistor variation of up to
20%, the actual amount of current required to fully shut down
the AD8016 can vary. To institute a full chip shutdown, a pull-
down current of 250 µA is recommended. See Figure 38 for the
logic drive circuit for complete amplifier shutdown. Figures 34
and 35 show the relationship between current pulled out of the
The AD8016 should be powered with a good quality (i.e., low
noise) dual supply of 12 V for the best distortion and multitone
power ratio (MTPR) performance. Careful attention must be
paid to decoupling the power supply pins. A 10 µF capacitor
located in near proximity to the AD8016 is required to pro-
vide good decoupling for lower frequency signals. In addition,
0.1 µF decoupling capacitors should be located as close to
each of the four power supply pins as is physically possible.
All ground pins should be connected to a common low imped-
ance ground plane.
REV. B
–11–
AD8016
BIAS pin (IBIAS) and the supply current (IQ). A typical shut-
down IQ is less than 1 mA total. Alternatively, an external pull-
down resistor to ground or a current sink attached to the BIAS
pin can be used to set IQ to lower levels (see Figure 39). The
BIAS pin may be used in combination with the PWDN1 and
PWDN0 pins; however, diminished MTPR performance may
result when IQ is lowered too much. Current pulled away from
the BIAS pin shunts away a portion of the internal bias current.
Setting PWDN1 or PWDN0 to Logic 0 also shunts away a
portion of the internal bias current. The reduction of quiescent
bias levels due to the use of PWDN1 and PWDN0 is consistent
with the percentages established in Table II. When PWDN0 alone
is set to Logic 0, and no other means of reducing the internal
bias currents is used, full-rate ADSL signals may be driven while
maintaining reasonable levels of MTPR.
APPLICATIONS
The AD8016ARP and AD8016ARB dual xDSL line driver
amplifiers are the most efficient xDSL line drivers available on
the market today. The AD8016 may be applied in driving modu-
lated signals including discrete multitone (DMT) in either
direction; upstream from CPE to the CO and downstream from
CO to CPE. The most significant thermal management chal-
lenge lies in driving downstream information from CO sites to
the CPE. Driving xDSL information downstream suggests the
need to locate many xDSL modems in a single CO site. The
implication is that several modems will be placed onto a single
printed circuit board residing in a card cage located in a variety
of ambient conditions. Environmental conditioners such as fans
or air conditioning may or may not be available, depending on
the density of modems and the facilities contained at the CO site.
To achieve long-term reliability and consistent modem perfor-
mance, designers of CO solutions must consider the wide array
of ambient conditions that exist within various CO sites.
3.3V LOGIC
R1
*
R2
50kꢁ
BIAS
2N3904
MULTITONE POWER RATIO OR MTPR
*R1 = 47kꢁ FOR ꢀ12V OR +12V ,
S
S
R1 = 22kꢁ FOR ꢀ6V .
ADSL systems rely on discrete multitone modulation to carry
digital data over phone lines. DMT modulation appears in the
frequency domain as power contained in several individual
frequency subbands, sometimes referred to as tones or bins, each
of which is uniformly separated in frequency. (See Figure 1 for
an example of downstream DMT signals used in evaluating
MTPR performance.) A uniquely encoded, quadrature amplitude
modulation (QAM) signal occurs at the center frequency of
each subband or tone. Difficulties arise when decoding these
subbands if a QAM signal from one subband is corrupted by the
QAM signal(s) from other subbands, regardless of whether
the corruption comes from an adjacent subband or harmonics
of other subbands. Conventional methods of expressing the
output signal integrity of line drivers, such as spurious-free
dynamic range (SFDR), single-tone harmonic distortion or
THD, two-tone intermodulation distortion (IMD), and third-
order intercept (IP3) become significantly less meaningful when
amplifiers are required to drive DMT and other heavily modulated
waveforms. A typical xDSL downstream DMT signal may
contain as many as 256 carriers (subbands or tones) of QAM
signals. MTPR is the relative difference between the mea-
sured power in a typical subband (at one tone or carrier)
versus the power at another subband specifically selected to
contain no QAM data. In other words, a selected subband (or
tone) remains open or void of intentional power (without a
QAM signal), yielding an empty frequency bin. MTPR, some-
times referred to as the empty bin test, is typically expressed
in dBc, similar to expressing the relative difference between
single-tone fundamentals and second or third harmonic dis-
tortion components.
S
Figure 38. Logic Drive of BIAS Pin for
Complete Amplifier Shutdown
THERMAL SHUTDOWN
The AD8016ARB and AD8016ARP have been designed to
incorporate shutdown protection against accidental thermal
overload. In the event of thermal overload, the AD8016 was
designed to shut down at a junction temperature of 165°C and
return to normal operation at a junction temperature 140°C.
The AD8016 continues to operate, cycling on and off, as long as
the thermal overload condition remains. The frequency of the
protection cycle depends on the ambient environment, severity
of the thermal overload condition, the power being dissipated,
and the thermal mass of the PCB beneath the AD8016. When
the AD8016 begins to cycle due to thermal stress, the internal
shutdown circuitry draws current out of the node connected in
common with the BIAS pin, while the voltage at the BIAS pin
goes to the negative rail. When the junction temperature returns
to 140°C, current is no longer drawn from this node, and the
BIAS pin voltage returns to the positive rail. Under these cir-
cumstances, the BIAS pin can be used to trip an alarm indicat-
ing the presence of a thermal overload condition.
Figure 39 also shows three circuits for converting this signal to a
standard logic level.
V
CC
AD8016
200ꢂA
V = V – 0.2V
CC
10kꢁ
BIAS
See Figure 1 for a sample of the ADSL downstream spectrum
showing MTPR results while driving 20.4 dBm of power onto a
100 Ω line. Measurements of MTPR are typically made at the
output (line side) of ADSL hybrid circuits. (See Figure 46a for
an example of Analog Devices’ hybrid schematic.) MTPR can
be affected by the components contained in the hybrid circuit,
including the quality of the capacitor dielectrics, voltage ratings,
and the turns ratio of the selected transformers. Other compo-
nents aside, an ADSL driver hybrid containing the AD8016 can be
optimized for the best MTPR performance by selecting the turns
ratio of the transformers. The voltage and current demands from
the differential driver changes, depending on the transformer
SHUT-
DOWN
0ꢂA–200ꢂA
OR
BIAS
V
EE
5V
PWDN0
PWDN1
V
CC
10kꢁ
5V
ALARM
MIN ꢄ 350
10kꢁ
1Mꢁ
BIAS
ALARM
BIAS
OR
100kꢁ
1/4 HCF 40109B
SGS–THOMSON
Figure 39. Shutdown and Alarm Circuit
REV. B
–12–
AD8016
GENERATING DMT
turns ratio. The point on the curve indicating maximum dynamic
headroom is achieved when the differential driver delivers both
the maximum voltage and current while maintaining the lowest
possible distortion. Below this point, the driver has reserve
current-driving capability and experiences voltage clipping.
Above this point, the amplifier runs out of current drive capabil-
ity before the maximum voltage drive capability is reached.
Since a transformer reflects the secondary load impedance back
to the primary side by the square of the turns ratio, varying the
turns ratio changes the load across the differential driver. In the
transformer configuration of Figure 46a and 46b, the turns ratio
of the selected transformer is effectively doubled due to the
parallel wiring of the transformer primaries within this ADSL
driver hybrid. The following equation may be used to calculate
the load impedance across the output of the differential driver,
reflected by the transformers, from the line side of the xDSL
driver hybrid. Z' is the primary side impedance as seen by the
differential driver; Z2 is the line impedance and N is the trans-
former turns ratio.
At this time, DMT modulated waveforms are not typically menu-
selectable items contained within arbitrary waveform generators.
Even using AWG software to generate DMT signals, AWGs that
are available today may not deliver DMT signals sufficient in
performance with regard to MTPR due to limitations in the D/A
converters and output drivers used by AWG manufacturers.
Similar to evaluating single-tone distortion performance of an
amplifier, MTPR evaluation requires a DMT signal generator
capable of delivering MTPR performance better than that of the
driver under evaluation. Generating DMT signals can be accom-
plished using a Tektronics AWG 2021 equipped with opt 4,
(12/24-Bit, TTL digital data out), digitally coupled to Analog
Devices AD9754, a 14-bit TxDAC®, buffered by an AD8002
amplifier configured as a differential driver. See Figure 45 for
schematics of a circuit used to generate DMT signals that can
achieve down to –80 dBc of MTPR performance, sufficient for
use in evaluating xDSL drivers. Note that the DMT waveforms
available with the AD8016ARP-EVAL and AD8016ARB-EVAL
boards or similar WFM files are needed to produce the neces-
sary digital data required to drive the TxDAC from the optional
TTL digital data output of the TEK AWG2021. Copies of these
WFM files can be obtained through the Analog Devices website,
at www.analog.com.
Z2
Z' ≡
2
2 × N
(
)
Figure 40 shows the dynamic headroom in each subband of a
downstream DMT waveform versus turns ratio running at 100%
and 60% of the quiescent power while maintaining –65 dBc of
MTPR at VS = 12 V.
EVALUATION BOARDS
The AD8016ARP-EVAL, AD8016ARB-EVAL, AD8016ARE-
EVAL boards available through Analog Devices provide a platform
for evaluating the AD8016 in an ADSL differential line driver
circuit. The board is laid out to accommodate Analog Devices’
two transformer line driver hybrid circuits (see Figures 46a
and 46b) including line matching network, an RJ11 jack for
interfacing to line simulators, transformer coupled input for
single-to-differential input conversion, and accommodations for
the receiver function. Schematics and layout information are
available for both versions of the evaluation board. Also included
in the package are WFM files for use in generating 14-bit
DMT waveforms. Upstream data is contained in the ...24.wfm
files and downstream data in the ...128.wfm files.
4
V
= ꢀ12V
S
PWDN1, PWDN0 = (1,1)
3
2
V
= ꢀ11.4V
S
PWDN1, PWDN0 = (1,1)
V
= ꢀ12V
S
PWDN1, PWDN0 = (1,0)
1
0
V
= ꢀ11.4V
S
PWDN1, PWDN0 = (1,0)
–1
These DMT modulated signals are used to evaluate xDSL
products for multitone power ratio or MTPR performance.
The data files are used in pairs (adslu24.wfm and adsll24.wfm
go together, etc.) and are loaded into a TEK AWG2021 arbi-
trary waveform generator. The adslu24.wfm is loaded via the
TEK AWG2021 floppy drive into Channel 1, while the
adsll24.wfm is simultaneously loaded into Channel 2. The num-
ber in the file name, prefixed with “u,” goes into CH1 or upper
channel and the “l” goes into CH2 or the lower channel. 12 bits
from CH1 are combined with 2 bits from CH2 to achieve 14-bit
digital data at the digital outputs of the TEK AWG2021. The
resulting waveforms produced at the AD9754-EB outputs are then
buffered and amplified by the AD8002 differential driver to achieve
14-bit performance from this DMT signal source.
–2
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
DOWNSTREAM TURNS RATIO
Figure 40. Dynamic Headroom vs. XFMR Turns Ratio,
VS = 12 V
Once an optimum turns ratio is determined, the amplifier has an
MTPR performance for each setting of the power-down pins.
The table below demonstrates the effects of reducing the total
power dissipated by using the PWDN pins on MTPR perfor-
mance when driving 20.4 dBm downstream onto the line with a
transformer turns ratio of 1:1.4.
Table III. Dynamic Power Dissipation for
Downstream Transmission
POWER DISSIPATION
PWDN1
PWDN0
PD (W)
MTPR
In order to properly size the heat sinking area for the user’s
application, it is important to consider the total power dissipa-
tion of the AD8016. The dc power dissipation for VIN = 0 is IQ
(VCC – VEE), or 2 × IQ × VS.
1
1
0
0*
1
0
1
0
1.454
1.262
1.142
0.120
–78 dBc
–75.3 dBc
–57.2 dBc
N/A
For the AD8016 powered on +12 V and –12 V supplies ( VS),
the number is 0.6 W. In a differential driver circuit (Figure 6),
*This mode is quiescent power dissipation.
REV. B
–13–
AD8016
one can use symmetry to simplify the computation for a dc
input signal.
of the die, allowing more drive within the CO design. The
AD8016, whether in a PSOP3 (ARP) or SO-Batwing (ARB)
package, can be designed to operate in the CO solution using
prudent measures to manage the power dissipation through careful
PCB design. The PSOP3 package is available for use in design-
ing the highest density CO solutions. Maximum heat transfer to
the PCB can be accomplished using the PSOP3 package when
the thermal slug is soldered to an exposed copper pad directly
beneath the AD8016. Optimum thermal performance can be
achieved in the ARE package only when the back of the package
is soldered to a PCB designed for maximum thermal capacity
(see Figure 44). Thermal experiments with the PS0P3 package
were conducted without soldering the heat slug to the PCB.
Heat transfer was through physical contact only. The following
offers some insight into the AD8016 power dissipation and
relative junction temperature, as well as the effects of PCB size
and composition on the junction-to-air thermal resistance or θJA.
VO
PD = 2 × IQ × VS + 4 × (VS – VO )
RL
where:
VO is the peak output voltage of an amplifier.
This formula is slightly pessimistic due to the fact that some of
the quiescent supply current is commutated during sourcing or
sinking current into the load. For a sine wave source, integration
over a half cycle yields
2
4 VO VS VO
PD = 2 × IQ × V + 2
−
S
π RL
R
L
The situation is more complicated with a complex modulated
signal. In the case of a DMT signal, taking the equivalent sine
wave power overestimates the power dissipation by ~23%. For
example:
THERMAL TESTING
A wind tunnel study was conducted to determine the relationship
between thermal capacity (i.e., printed circuit board copper area),
air flow, and junction temperature. Junction-to-ambient ther-
P
OUT = 23.4 dBm = 220 mW
V
OUT @ 50 Ω = 3.31 V rms
VO = 2.354 V
mal resistance, θ , was also calculated for the AD8016ARP,
JA
AD8016ARE, and AD8016ARB packages. The AD8016 was
operated in a noninverting differential driver configuration, typical
of an xDSL application yet isolated from any other modem
components. Testing was conducted using a 1 oz. copper
board in an ambient temperature of ~24°C over air flows of
200, 150, 100, and 50 (0.200 and 400 for AD8016ARE) linear
feet per minute (LFM) and for ARP and ARB packages as well
as in still air. The 4-layer PCB was designed to maximize the
area of copper on the outer two layers of the board, while the
inner layers were used to configure the AD8016 in a differential
driver circuit. The PCB measured 3 inches × 4 inches in the
beginning of the study and was progressively reduced in size
to approximately 2 × 2 inches. The testing was performed in a
wind tunnel to control air flow in units of LFM. The tunnel is
approximately 11 inches in diameter.
at each amplifier output, which yields a PD of 1.81 W.
Through measurement, a DMT signal of 23.4 dBm requires
1.47 W of power to be dissipated by the AD8016. Figure 41
shows the results of calculation and actual measurements
detailing the relationship between the power dissipated by the
AD8016 versus the total output power delivered to the back
termination resistors and the load combined. A 1:2 transformer
turns ratio was used in the calculations and measurements.
2.5
2.0
CALCULATED
1.5
MEASURED
SINE
AIR FLOW TEST CONDITIONS
DUT Power: Typical DSL DMT signal produces about 1.5 W
of power dissipation in the AD8016 package. The fully biased
(PWDN0 and PWDN1 = Logic 1) quiescent current of the
AD8016 is ~25 mA. A 1 MHz differential sine wave at an
amplitude of 8 V p-p/amplifier into an RLOAD of 100 Ω differential
(50 Ω per side) produces the 1.5 W of power typical in the
AD8016 device. (See the Power Dissipation section for details.)
MEASURED
DMT
1.0
0.5
0
0
100
200
300
OUTPUT POWER (mW)
Thermal Resistance: The junction-to-case thermal resistance
(θJC) of the AD8016ARB or SO-Batwing package is 8.6°C/W, for
the AD8016ARE or TSSOP-EP it is 5.6°C/W, and for the
AD8016ARP or PSOP3 package it is 0.86°C/W. These package
specifications were used in this study to determine junction
temperature based on the measured case temperature.
Figure 41. Power Dissipation vs. Output Power (Including
Back Terminations), See Figure 7 for Test Circuit
THERMAL ENHANCEMENTS AND PCB LAYOUT
There are several ways to enhance the thermal capacity of the
CO solution. Additional thermal capacity can be created using
enhanced PCB layout techniques such as interlacing (sometimes
referred to as stitching or interconnection) of the layers immedi-
ately beneath the line driver. This technique serves to increase
the thermal mass or capacity of the PCB immediately beneath
the driver. (See AD8016-EVAL boards for an example of this
method of thermal enhancement.) A cooling fan that draws
moving air over the PCB and xDSL drivers, while not always
required, may be useful in reducing the operating temperature
PCB Dimensions of a Differential Driver Circuit: Several
components are required to support the AD8016 in a differential
driver circuit. The PCB area necessary for these components (i.e.,
feedback and gain resistors, ac-coupling and decoupling capaci-
tors, termination and load resistors) dictated the area of the
smallest PCB in this study, 4.7 square inches. Further reduction
in PCB area, although possible, has consequences in terms of
the maximum operating junction temperature.
REV. B
–14–
AD8016
EXPERIMENTAL RESULTS
35
30
25
20
The experimental data suggests that for both packages, and a
PCB as small as 4.7 square inches, reasonable junction tempera-
tures can be maintained even in the absence of air flow. The graph
in Figure 42 shows junction temperature versus air flow for various
dimensions of 1 oz. copper PCBs at an ambient temperature of
24°C in both the ARB and ARP packages. For the worst-case
package, the AD8016ARB and the worst-case PCB at 4.7 square
inches, the extrapolated junction temperature for an ambient
environment of 85°C would be approximately 132°C with 0 LFM
of air flow. If the target maximum junction temperature of the
AD8016ARB is 125°C, a 4-layer PCB with 1 oz. copper covering
the outer layers and measuring 9 square inches is required
with 0 LFM of air flow.
ARB 0 LFM
ARB 50 LFM
ARB 100 LFM
ARB 150 LFM
ARB 200 LFM
ARP 0 LFM
ARP 50 LFM
ARP 100 LFM
15
10
ARP 150 LFM
ARP 200 LFM
4
7
10
PCB AREA (SQ-IN)
Note that the AD8016ARE is targeted at xDSL applications
other than full-rate CO ADSL. The AD8016ARE is targeted at
g.lite and other xDSL applications where reduced power dissi-
pation can be achieved through a reduction in output power.
Extreme temperatures associated with full-rate ADSL using the
AD8016ARE should be avoided whenever possible.
Figure 43. Junction-to-Ambient Thermal Resistance vs.
PCB Area
50
45
40
75
ARB 4.7 SQ-IN
+24ꢃC AMBIENT
ARB 6 SQ-IN
70
65
60
55
50
45
40
35
30
25
ARE 0 LFM
ARB 7.125 SQ-IN
ARE 200 LFM
ARB 9 SQ-IN
ARP 4.7 SQ-IN
ARE 400 LFM
20
15
ARP 6 SQ-IN
10
0
ARP 9 SQ-IN
1
2
3
4
5
6
7
8
9
10
ARP 12 SQ-IN
100
PCB AREA (SQ-IN)
0
50
150
200
Figure 44. Junction-to-Ambient Thermal Resistance vs.
PCB Area
AIR FLOW (LFM)
Figure 42. Junction Temperature vs. Air Flow
REV. B
–15–
AD8016
Figure 45. DMT Signal Generator Schematic
–16–
REV. B
AD8016
TP10
TP5
+VT
2
AGND3,4,5
S5
1
C8
B
TP13
PR1
TP15
TP6
TP7
R9
4
3
T2
+V
U1
–V
C11
C4
C5
R2
R3
R20
1
10
R11
1
R13
R24
8
9
2
3
AD8016
–VT
11
C6
C7
R4
2
TP14
TP1
3
A
7
4
JP6
R18
1
2
NC = 5,6
T1
R1
5 WATT
T3
6
4
1
2
3
TP16
R17
1
2
3
P4
P4
P4
1
2
3
4
5
6
1
10
R23
R14
1:1
R19
P1
2
3
8
9
NC = 5
JP5
–VT
23
C9
PR2
14
–V
U1
+V
24
R25
22
21
C12
R21
4
7
AGND3,4,5
S6
NC = 5,6
AD8016
+VT
7
8
R16
R15
TP8
TP9
TP2
C10
+VR;8
–VR;4
TP17
TP11
TP4
3
2
1
U2
S3
AD8022
3
P3
P3
P3
R6
2
1
R5
R7
TP18
AD8022
6
7
U2
S4
5
+VR;8
–VR;4
Figure 46a. Schematic AD8016ARB-EVAL
TP19
TP3
L5
+VT
–VT
1
2
TB1
TB1
S2
BEAD
C14
+
+
R9
C17
C15
C26
10ꢂF
0.1ꢂF
0.1ꢂF
0.1ꢂF
25V
CW
R10
C1
10ꢂF
25V
C19
0.1ꢂF
C16
0.1ꢂF
C25
0.1ꢂF
R22
+VL
L1
15
10
3
BIAS
TB1
BEAD
R12
U1
AD8016
DGND
TP20
+VR
9
3
1
2
PWDN0
PWDN1
P2
P2
P2
TP21
16
L4
1
2
3
TB2
TB2
TB2
JP2
JP1
BEAD
C13
10ꢂF
25V
+
+
C21
0.1ꢂF
C23
0.1ꢂF
C3
10ꢂF
25V
JP3
JP4
C24
0.1ꢂF
C22
0.1ꢂF
+VR
+VT
–VT
L3
–VR
+VL
BEAD
–VR
TP22
TP12
L2
TP24 TP23
TP25
TP26 TP27
TP28
TP29
TP30
1
2
TB3
TB3
BEAD
C2
10ꢂF
25V
+
C20
0.1ꢂF
C18
0.1ꢂF
Figure 46b. Schematic AD8016ARB-EVAL
REV. B
–17–
AD8016
LAYOUT AD8016ARB-EVAL
Figure 47. Assembly
Figure 50. Layer 1
Figure 51. Silkscreen Bottom
Figure 48. Layer 1
Figure 49. Power/Ground Plane
REV. B
–18–
AD8016
ALP – EVALUATION BOARD – BILL OF MATERIALS
Vendor
Quantity
Description
Ref Desc.
5
10
2
2
1
3
2
1
2
4
2
1
2
2
2
4
2
2
1
5
5
5
1
1
3
1
1
4
4
10 µF 25 V Size Tantalum Chip Capacitor
0.1 µF 50 V 1206 Size Ceramic Chip Capacitor
49.9 Ω 1% 1/8 W 1206 Size Chip Resistor
100 Ω 1% 1/8 W 1206 Size Chip Resistor
100 Ω 5% 3.0 W Metal Film Power Resistor
1.00 kΩ 1% 1/6 W 1206 Size Chip Resistor
10.0 kΩ 1% 1/6 W 1206 Size Chip Resistor
Test Point (Black) [GND]
Test Point (Brown)
Test Point (Red)
Test Point (Orange)
Test Point (Yellow)
ADS# 4-7-2
ADS# 4-5-18
ADS# 3-14-26
ADS# 3-18-40
ADS# 3-24-1
ADS# 3-18-11
ADS# 3-18-119
ADS# 12-18-44
ADS# 12-18-59
ADS# 12-18-43
ADS# 12-18-60
ADS# 12-18-32
ADS# 12-18-61
ADS# 12-18-62
ADS# 12-18-63
ADS# 12-18-64
ADS# 12-18-42
ADS# 12-19-14
ADS# 12-19-13
ADS# 11-2-38
ADS# 11-2-37
ADS# 12-6-22
D–K# A 9024
D–K# WM 2723-ND
D–K# WM 2701-ND
ADS# AD 8016 XRP
SIERRA/PROTO EXPRESS
ADS# 30-1-1
C1 to C3, C13, C14
C15 to C21, C24 to C26
R11, R15
R8, R14
R1
R17 to R19
R13 and R16
GND
TP10, TP11
TP17 to TP19, TP21
TP3, TP15, TP16
TP12
TP7, TP9
TP20, TP22
TP4, TP5
TP1, TP2, TP13, TP14
TP6, TP8
TB1, TB2
TB3
J1 to J5
J1 to J5
S2 to S6
P1
JP6
P2 to P4
DUT
Eval PC Board
Test Point (Green)
Test Point (Blue)
Test Point (Violet)
Test Point (Grey)
Test Point (White)
3 Green Terminal Block. ONSHORE# EDZ250/3
2 Green Terminal Block. ONSHORE# EDZ250/2
1 Inch Center Shunt Berg# 65474-001
Male Header. 1 Inch Center. Berg #69157-102
Conn. BNC Vert. MT Telegartner # J01001A1944
AMP# 555154-1 MOD. JACK (SHIELDED) 6 6
3-Pin Gold Male Header Waldom #WM 2723-ND
3-Pin Gold Male Locking Header Waldom #WM 2701-ND
AD8016 ARB
AD8016 SOIC REV. B Evaluation PC Board
No. 4 –40 × 1/4" Panhead SS Machine Screw
No. 4 –40 × 1/2" Threaded Alum. Standoffs
ADS# 30-16-2
OPTION
2
1:1.4 Turns Ratio RF Transformer from CoEv
C1374 Rev. 2
T1, T2
OUTLINE DIMENSIONS
24-Lead Batwing SOIC, Thermally Enhanced w/Fused Leads [SOIC/W/BAT]
(RB-24)
Dimensions shown in millimeters
15.60
15.20
24
1
13
12
7.60
7.40
10.65
10.00
PIN 1
0.75
0.25
ꢆ 45
2.65
2.35
8
0
0.30
0.10
0.33
0.20
1.27
BSC
0.51
0.31
1.27
0.40
SEATING
PLANE
COMPLIANT WITH JEDEC STANDARDS MS-013AD
REV. B
–19–
AD8016
OUTLINE DIMENSIONS
20-Lead Power SOIC, Thermally Enhanced Package [PSOP3]
(RP-20A)
Dimensions shown in millimeters
13.00
9.00
1.10 MAX ꢆ 45ꢃ
1
10
PIN 1
11.00
BSC
6.20
5.80
14.20
BSC
TOP VIEW
BOTTOM VIEW
11
20
1.10 MAX
2 PLACES
15.90
BSC
2.90 MAX
2 PLACES
3.60
3.35
3.10
VIEW A
SIDE VIEW
1.00
0.90
0.80
8ꢃ
0ꢃ
END VIEW
0.53
0.40
SEATING
PLANE
1.27
BSC
1.10
0.80
3.30
3.15
3.00
VIEW A
3.60
3.35
3.10
0.10
0.05
0.00
0.30
0.20
0.10
0.32
0.23
COMPLIANT TO JEDEC STANDARDS MO-166AA
28-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP-EP]
(RE-28-1)
Dimensions shown in millimeters
9.80
9.70
9.60
BOTTOM
VIEW
28
15
14
4.50
4.40
4.30
EXPOSED
PAD
(Pins Down)
6.40
BSC
3.00
BSC
1
PIN 1
3.50
BSC
0.65
BSC
1.05
1.00
0.80
1.20
MAX
8ꢃ
0ꢃ
0.30
0.19
0.75
0.60
0.45
0.15
0.00
SEATING
PLANE
0.20
0.09
COMPLIANT TO JEDEC STANDARDS MO-153AET
Revision History
Location
Page
11/03—Data Sheet changed from REV. A to REV. B.
Changes to ORDERING GUIDE....................................................................................................................................................4
Changes to TPC 21.........................................................................................................................................................................8
Updated OUTLINE DIMENSIONS........................................................................................................................................19-20
–20–
REV. B
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