AD802-155KR [ADI]
Clock Recovery and Data Retiming Phase-Locked Loop; 时钟恢复和数据重定时锁相环
| 型号： | AD802-155KR |
| 厂家： | 
ADI |
| 描述： | Clock Recovery and Data Retiming Phase-Locked Loop |
| 文件： | 总12页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Clock Recovery and Data Retiming
Phase-Locked Loop
a
AD800/AD802*
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Standard Products
C
D
44.736 Mbps—DS-3
51.84 Mbps—STS-1
155.52 Mbps—STS-3 or STM-1
Accepts NRZ Data, No Pream ble Required
Recovered Clock and Retim ed Data Outputs
Phase-Locked Loop Type Clock Recovery—No Crystal
Required
Random J itter: 20؇ Peak-to-Peak
Pattern J itter: Virtually Elim inated
10KH ECL Com patible
COMPENSATING
ZERO
LOOP
DATA
INPUT
Ø
DET
∑
FILTER
VCO
RECOVERED
CLOCK
f
OUTPUT
DET
RETIMED
DATA
OUTPUT
RETIMING
DEVICE
Single Supply Operation: –5.2 V or +5 V
Wide Operating Tem perature Range: –40؇C to +85؇C
AD800/AD802
FRAC
OUTPUT
P RO D UCT D ESCRIP TIO N
During the process of acquisition the frequency detector
provides a Frequency Acquisition (FRAC) signal which
indicates that the device has not yet locked onto the input data.
T his signal is a series of pulses which occur at the points of cycle
slip between the input data and the synthesized clock signal.
Once the circuit has acquired frequency lock no pulses occur at
the FRAC output.
T he AD800 and AD802 employ a second order phase-locked
loop architecture to perform clock recovery and data retiming
on Non-Return to Zero, NRZ, data. T his architecture is
capable of supporting data rates between 20 Mbps and 160
Mbps. T he products described here have been defined to work
with standard telecommunications bit rates. 45 Mbps DS-3 and
52 Mbps ST S-1 are supported by the AD800-45 and
AD800-52 respectively. 155 Mbps ST S-3 or ST M-1 are
supported by the AD802-155.
T he inclusion of a precisely trimmed VCO in the device
eliminates the need for external components for setting center
frequency, and the need for trimming of those components. T he
VCO provides a clock output within ±20% of the device center
frequency in the absence of input data.
Unlike other PLL-based clock recovery circuits, these devices
do not require a preamble or an external VCXO to lock onto
input data. T he circuit acquires frequency and phase lock using
two control loops. T he frequency acquisition control loop
initially acquires the clock frequency of the input data. T he
phase-lock loop then acquires the phase of the input data, and
ensures that the phase of the output signals track changes in the
phase of the input data. T he loop damping of the circuit is
dependent on the value of a user selected capacitor; this defines
jitter peaking performance and impacts acquisition time. T he
devices exhibit 0.08 dB jitter peaking, and acquire lock on
random or scrambled data within 4 × 105 bit periods when
using a damping factor of 5.
T he AD800 and AD802 exhibit virtually no pattern jitter, due
to the performance of the patented phase detector. T otal loop
jitter is 20° peak-to-peak. Jitter bandwidth is dictated by mask
programmable fractional loop bandwidth. T he AD800, used for
data rates < 90 Mbps, has been designed with a nominal loop
bandwidth of 0.1% of the center frequency. T he AD802, used
for data rates in excess of 90 Mbps, has a loop bandwidth of
0.08% of center frequency.
All of the devices operate with a single +5 V or –5.2 V supply.
*P r otected by U.S. P atent No. 5,027,085.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
MIN to T , Loop Damping
AD800/AD802–SPECIFICATIONS (FVact=orV= 5,tounVless, Vothe=rwGiNsDe,nTot=edT)
EE
MIN
MAX CC
A
MAX
AD 800-45BQ
AD 800-52BR
AD 802-155KR/BR
P aram eter1
Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
NOMINAL CENT ER FREQUENCY
OPERAT ING T EMPERAT URE K Grade
44.736
51.84
155.52
MHz
0
–40
70
85
°C
°C
RANGE (T MIN to T MAX
T RACKING RANGE
CAPT URE RANGE
)
B Grade
–40
43
85
–40
49
85
53
53
45.5
45.5
155
155
156
156
Mbps
Mbps
43
49
ST AT IC PHASE ERROR
ρ = 1, T A = +25°C,
VEE = –5.2 V
ρ = 1
2
3
10
11.5
2
3
10
11.5
14
18
30
37
Degrees
Degrees
RECOVERED CLOCK SKEW
SET UP T IME
tRCS (Figure 1)
tSU (Figure 1)
0.2
0.6
1
0.2
0.6
1
0.2
0.8
1
ns
2.06
2.37
ns
T RANSIT IONLESS DAT A RUN
OUT PUT JIT T ER
240
240
240
Bit Periods
ρ = 1
2
2.5
2.5
2
2.5
2.5
3.5
5.4
5.4
Degrees rms
Degrees rms
Degrees rms
27–1 PRN Sequence
223–1 PRN Sequence
4.7
4.7
4.7
4.7
9.7
9.7
JIT T ER T OLERANCE
f = 10 Hz
f = 2.3 kHz
f = 30 kHz
f = 1 MHz
f = 30 Hz
f = 300 Hz
f = 2 kHz
f = 20 kHz
f = 6.5 kHz
f = 65 kHz
2,500
2,500
3,000
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
6.5
0.47
0.47
830
83
7.4
0.47
2.0
0.26
7.6
0.9
JIT T ER T RANSFER
Damping Factor
Capacitor, CD
ζ = 1, Nominal
ζ = 5, Nominal
ζ = 10, Nominal
Peaking
8.2
0.22
0.82
6.8
0.15
0.68
2.2
0.047
0.22
nF
µF
µF
ζ = 1, Nominal
ζ = 5, Nominal
ζ = 10, Nominal
Bandwidth
T A = +25°C, VEE = –5.2 V
T A = +25°C, VEE = –5.2 V
T A = +25°C, VEE = –5.2 V
2
2
2
dB
dB
dB
kHz
0.08
0.02
45
0.08
0.02
52
0.08
0.02
130
ACQUISIT ION T IME
ρ = 1/2
T A = +25°C
ζ = 1
ζ = 5
ζ = 10
1 × 104
1 × 104
1.5 × 104
Bit Periods
3 × 105 8 × 105
8 × 105
3 × 105 8 × 105
8 × 105
4 × 105 8 × 105 Bit Periods
VEE = –5.2 V
1.4 × 106
Bit Periods
POWER SUPPLY
Voltage (VMIN to VMAX
Current
)
T A = +25°C
T A = +25°C, VEE = –5.2 V
–4.5
–5.2
125
–5.5
170
180
–4.5
–5.2
125
–5.5
170
180
–4.5
–5.2
140
–5.5
180
205
Volts
mA
mA
INPUT VOLT AGE LEVELS
Input Logic High, VIH
Input Logic Low, VIH
T A = +25°C
T A = +25°C
T A = +25°C
–1.084
–1.95
–0.72
–1.594 –1.95
–1.084
–0.72
–1.594 –1.95
–1.084
–0.72
–1.594 Volts
Volts
OUT PUT VOLT AGE LEVELS
Output Logic High, VOH
Output Logic Low, VOL
–1.084
–1.95
–0.72
–1.60
–1.084
–1.95
–0.72
–1.60
–1.084
–1.95
–0.72
–1.60
Volts
Volts
INPUT CURRENT LEVELS
Input Logic High, IIH
Input Logic Low, IIL
125
80
125
80
125
80
µA
µA
OUT PUT SLEW T IMES
Rise T ime (tR)
Fall T ime (tF)
T A = +25°C
20%–80%
80%–20%
0.75
0.75
1.5
1.5
0.75
0.75
1.5
1.5
0.75
0.75
1.5
1.5
ns
ns
SYMMET RY
ρ = 1/2, T A = +25°C
Recovered Clock Output
VEE = –5.2 V
45
55
45
55
45
55
%
NOT ES
1Refer to Glossary for parameter definition.
Specifications subject to change without notice.
–2–
REV. B
AD800/AD802
ABSO LUTE MAXIMUM RATINGS*
TH ERMAL CH ARACTERISTICS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
θJC
θJA
Input Voltage (Pin 16 or Pin 17 to VCC
Maximum Junction T emperature
) . . . . VEE to +300 mV
SOIC Package
Cerdip Package
22°C/W
25°C/W
75°C/W
90°C/W
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature Range (Soldering 60 sec) . . . . . . . +300°C
ESD Rating
Use of a heatsink may be required depending on operating
environment.
GLO SSARY
AD800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
Maxim um and Minim um Specifications
AD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to an absolute
maximum rating condition for an extended period may adversely affect device
reliability.
Maximum and minimum specifications result from statistical
analyses of measurements on multiple devices and multiple test
systems. T ypical specifications indicate mean measurements.
Maximum and minimum specifications are calculated by adding
or subtracting an appropriate guardband from the typical
specification. Device-to-device performance variation and test
system-to-test system variation contribute to each guardband.
Nom inal Center Fr equency
DATAOUT 50%
(PIN 2)
T his is the frequency that the VCO will operate at with no input
signal present and the loop damping capacitor, CD, shorted.
CLKOUT 50%
(PIN 5)
Tr acking Range
T his is the range of input data rates over which the PLL will
remain in lock.
SETUP TIME
tSU
RECOVERED CLOCK
SKEW, tRCS
Captur e Range
T his is the range of input data rates over which the PLL can
acquire lock.
Figure 1. Recovered Clock Skew and Setup
(See Previous Page)
Static P hase Er r or
P IN D ESCRIP TIO NS
T his is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling
instant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals
prohibit direct measurement of static phase error.
Num ber Mnem onic
D escription
1
DATAOUT Differential Retimed Data Output
2
DAT AOUT Differential Retimed Data Output
3
VCC2
Digital Ground
4
5
6
CLKOUT
CLKOUT
VEE
Differential Recovered Clock Output
Differential Recovered Clock Output
Digital VEE
Digital VEE
Digital Ground
D ata Tr ansition D ensity,
T his is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to clock periods.
7
VEE
8
VCC1
Jitter
9
AVEE
Analog VEE
T his is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms, or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
10
11
12
13
14
15
16
17
18
19
ASUBST
CF2
CF1
AVCC
VCC1
Analog Substrate
Loop Damping Capacitor Input
Loop Damping Capacitor Input
Analog Ground
Digital Ground
Digital VEE
Differential Data Input
Differential Data Input
Digital Substrate
Differential Frequency Acquisition
Indicator Output
VEE
O utput Jitter
DAT AIN
DATAIN
SUBST
FRAC
T his is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some psuedo-random input data sequence
(PRN Sequence).
Jitter Toler ance
Jitter tolerance is a measure of the PLL’s ability to track a jittery
input data signal. Jitter on the input data is best thought of as
phase modulation, and is usually specified in unit intervals.
20
FRAC
Differential Frequency Acquisition
Indicator Output
O RD ERING GUID E
Fractional Loop
D evice
Center Frequency Bandwidth
D escription
O perating Tem perature
P ackage O ption
AD800-45BQ
AD800-52BR
AD802-155BR 155.52 MHz
AD802-155KR 155.52 MHz
44.736 MHz
51.84 MHz
0.1%
0.1%
0.08%
0.08%
20-Pin Cerdip
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
Q-20
R-20
R-20
R-20
20-Pin Plastic SOIC
20-Pin Plastic SOIC
20-Pin Plastic SOIC
REV. B
–3–
AD800/AD802
T he PLL must provide a clock signal which tracks this phase
modulation in order to accurately retime jittered data. In order
for the VCO output to have a phase modulation which tracks
the input jitter, some modulation signal must be generated at
the output of the phase detector (see Figure 21). T he
modulation output from the phase detector can only be
produced by a phase error between the data input and the clock
input. Hence, the PLL can never perfectly track jittered data.
However, the magnitude of the phase error depends on the gain
around the loop. At low frequencies the integrator provides very
high gain, and thus very large jitter can be tracked with small
phase errors between input data and recovered clock. At
frequencies closer to the loop bandwidth, the gain of the
integrator is much smaller, and thus less input jitter can be
tolerated. T he PLL data output will have a bit error rate less
than 1 ϫ 10–10 when in lock and retiming input data that has the
specified jitter applied to it.
Sym m etr y
Symmetry is calculated as (100 ϫ on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
Bit Er r or Rate vs. Signal-to-Noise Ratio
T he AD800 and AD802 were designed to operate with standard
ECL signal levels at the data input. Although not recom-
mended, smaller input signals are tolerable. Figure 8, 14, and
20 show the bit error rate performance versus input signal-to-
noise ratio for input signal amplitudes of full 900 mV ECL, and
decreased amplitudes of 80 mV and 20 mV. Wideband ampli-
tude noise is summed with the data signals as shown in Figure
2. T he full ECL and 80 mV signals give virtually indistinguish-
able results. T he 20 mV signals also provide adequate perfor-
mance when in lock, but signal acquisition may be impaired.
POWER
COMBINER
Jitter Tr ansfer
∑
DATA IN
T he PLL exhibits a low-pass filter response to jitter applied to
its input data.
0.47µF
0.47µF
50Ω
50Ω
DIFFERENTIAL
SIGNAL
SOURCE
D.U.T.
AD800/AD802
Bandwidth
T his describes the frequency at which the PLL attenuates
sinusoidal input jitter by 3 dB.
∑
DATA IN
POWER
COMBINER
75Ω
180Ω
1.0µF
P eaking
POWER
SPLITTER
T his describes the maximum jitter gain of the PLL in dB.
–5.2V
GND
D am ping Factor ,
describes how the PLL will track an input signal with a phase
step. A greater value of corresponds to less overshoot in the
ζ
100MHz – AD802-155
33MHz – AD800-52
FILTER
ζ
PLL response to a phase step.
order feedback systems.
ζ is a standard constant in second
NOISE
SOURCE
Acquisition Tim e
T his is the transient time, measured in bit periods, required for
the PLL to lock on input data from its free-running state.
Figure 2. Bit Error Rate vs. Signal-to-Noise Ratio Test:
Block Diagram
USING TH E AD 800 AND TH E AD 802 SERIES
Gr ound P lanes
Tr ansm ission Lines
Use of one ground plane for connections to both analog and
digital grounds is recommended. Output signal sensitivity to
power supply noise (PECL configuration, Figure 22) is less
using one ground plane than when using separate analog and
digital ground planes.
Use of 50 Ω transmission lines are recommended for DAT AIN,
CLKOUT , DAT AOUT , and FRAC signals.
Ter m inations
T ermination resistors should be used for DAT AIN, CLKOUT ,
DAT AOUT , and FRAC signals. Metal, thick film, 1% tolerance
resistors are recommended. T ermination resistors for the
DAT AIN signals should be placed as close as possible to the
DAT AIN pins.
P ower Supply Connections
Use of a 10 µF tantalum capacitor between VEE and ground is
recommended.
Use of 0.1 µF ceramic capacitors between IC power supply or
substrate pins and ground is recommended. Power supply
decoupling should take place as close to the IC as possible.
Refer to schematics, Figure 22 and Figure 26, for advised
connections.
Connections from VEE to lead resistors for DAT AIN, DAT A-
OUT , FRAC, and CLKOUT signals should be individual, not
daisy chained. T his will avoid crosstalk on these signals.
Loop D am ping Capacitor , C D
A ceramic capacitor may be used for the loop damping
capacitor.
Sensitivity of IC output signals (PECL configuration,
Figure 22) to high frequency power supply noise (at 2 ϫ the
nominal data rate) can be reduced through the connection of
signals AVCC and VCC1, and the addition of a bypass network.
T he type of bypass network to consider depends on the noise
tolerance required. T he more complex bypass network schemes
tolerate greater power supply noise levels. Refer to Figures 23
and 24 for bypassing schemes and power supply sensitivity
curves.
Input Buffer
Use of an input buffer, such as a 10H116 Line Receiver IC, is
suggested for an application where the DAT AIN signals do not
come directly from an ECL gate, or where noise immunity on
the DAT AIN signals is an issue.
–4–
REV. B
AD800/AD802
Typical Characteristics–
52
50
48
46
44
42
40
38
10
9
8
7
6
5
4
3
2
1
0
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE – °C
TEMPERATURE – °C
Figure 3. AD800-45 Center Frequency vs. Tem perature
Figure 4. AD800-45 J itter vs. Tem perature
100
52
50
48
46
44
42
40
38
AD800-45
10
DS-3 MASK
1
0.1
1
2
3
4
5
6
0
10
10
10
10
10
10
10
–40
–20
0
20
40
60
80
100
JITTER FREQUENCY – Hz
TEMPERATURE – °C
Figure 6. AD800-45 J itter Tolerance
Figure 5. AD800-45 Capture and Tracking Range vs.
Tem perature
1E-1
55
C
D
= 0.68µF
5E-2
3E-2
2E-2
53
51
49
47
45
43
41
39
37
35
20
80
1E-2
1
2
1
S
N
erfc
2
2
1E-3
80
1E-4
1E-5
ECL
20
1E-7
1E-9
1E-11
10
12
14
16
S/N – dB
18
20
22
24
0
0.05
0.10
0.15
0.20
0.25
0.30
INPUT JITTER – UI p-p
Figure 7. AD800-45 Acquisition Range vs. Input J itter
Figure 8. AD800-45 Bit Error Rate vs. Input J itter
REV. B
–5–
AD800/AD802
10
9
8
7
6
5
4
3
2
1
0
58
56
54
52
50
48
46
44
42
40
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE –
°C
TEMPERATURE – °C
Figure 9. AD800-52 Center Frequency vs. Tem perature
Figure 10. AD800-52 J itter vs. Tem perature
100
58
56
54
52
50
48
46
44
42
40
AD800-52
10
OC-1 MASK
1
0.1
0
1
2
3
4
5
–40
–20
0
20
40
60
80
100
10
10
10
10
10
10
TEMPERATURE –
°
C
JITTER FREQUENCY – Hz
Figure 11. AD800-52 Capture and Tracking Range vs.
Tem perature
Figure 12. AD800-52 J itter Tolerance
60
1E-1
C
D
= 0.68µF
58
56
54
52
50
48
46
44
42
40
5E-2
3E-2
2E-2
80
20
1E-2
1
2
1
S
N
erfc
2
2
1E-3
1E-4
80
ECL
1E-5
1E-6
20
1E-8
1E-10
0
0.05
0.10
0.15
0.20
0.25
0.30
10
12
14
16
S/N – dB
18
20
22
24
INPUT JITTER – UI p-p
Figure 13. AD800-52 Acquisition Range vs. Input J itter
Figure 14. AD800-52 Bit Error Rate vs. Input J itter
–6–
REV. B
AD800/AD802
180
170
160
150
140
130
120
110
10
9
8
7
6
5
4
3
2
1
0
100
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE – °C
TEMPERATURE – °C
Figure 15. AD802-155 Center Frequency vs. Tem perature
Figure 16. AD802-155 Output J itter vs. Tem perature
200
100
190
180
AD802-155
10
170
160
150
140
130
1
CCITT G.958 STM1 TYPE A MASK
0.1
2
3
4
5
6
7
8
–40
–20
0
20
40
60
80
100
10
10
10
10
10
10
10
TEMPERATURE –
°
C
JITTER FREQUENCY – Hz
Figure 17. AD802-155 Capture Range, Tracking Range vs.
Tem perature
Figure 18. AD802-155 J itter Tolerance
100
1E-1
5E-2
3E-2
2E-2
80mV
20mV
10
AD802 – 155
ECL
1E-2
1
2
1
S
N
erfc
2
2
1
1E-3
1E-4
1E-5
1E-6
80mV
&
ECL
CCITT G.958 STM1 TYPE A MASK
0.1
20mV
1E-8
1E-10
1E-12
0
1
10
100
1000
10
12
14
16
S/N – dB
18
20
22
24
JITTER FREQUENCY – Hz
Figure 19. AD802-155 Minim um Acquisition Range vs.
J itter Frequency, TMIN to TMAX VMIN to VMAX
Figure 20. AD802-155 Bit Error Rate vs. Input J itter
REV. B
–7–
AD800/AD802
TH EO RY O F O P ERATIO N
T he damping ratio of the phase-locked loop is user program-
mable with a single external capacitor. At 155 MHz a damping
ratio of 10 is obtained with a 0.22 µF capacitor. More generally,
T he AD800 and AD802 are phase-locked loop circuits for re-
covery of clock from NRZ data. T he architecture uses a fre-
quency detector to aid initial frequency acquisition, refer to
Figure 21 for a block diagram. Note the frequency detector is al-
ways in the circuit. When the PLL is locked, the frequency error
is zero and the frequency detector has no further effect. Since
the frequency detector is always in circuit, no control functions
are needed to initiate acquisition or change mode after acquisi-
tion. T he frequency detector also supplies a frequency acquisi-
tion (FRAC) output to indicate when the loop is acquiring lock.
During the frequency acquisition process the FRAC output is a
series of pulses of width equal to the period of the VCO. T hese
pulses occur on the cycle slips between the data frequency and
the VCO frequency. With a maximum density (1010 . . .) data
pattern, every cycle slip will produce a pulse at FRAC. How-
ever, with random data, not every cycle slip produces a pulse.
T he density of pulses at FRAC increases with the density of
data transitions. T he probability that a cycle slip will produce a
pulse increases as the frequency error approaches zero. After the
frequency error has been reduced to zero, the FRAC output will
have no further pulses. At this point the PLL begins the process
of phase acquisition, with a settling time of roughly 2000 bit pe-
riods. Valid retimed data can be guaranteed by waiting 2000 bit
periods after the last FRAC pulse has occurred.
1. 7 × f DATA × CD
the damping ratio scales as
. At 155 MHz a
damping ratio of 1 is obtained with a 2.2 nF capacitor. A lower
damping ratio allows a faster frequency acquisition; generally
the acquisition time scales directly with the capacitor value.
However, at damping ratios approaching one, the acquisition
time no longer scales directly with the capacitor value. T he
acquisition time has two components: frequency acquisition and
phase acquisition. T he frequency acquisition always scales with
capacitance, but the phase acquisition is set by the loop
bandwidth of the PLL and is independent of the damping ratio.
T hus, the 0.08% fractional loop bandwidth sets a minimum
acquisition time of 15,000 bit periods. Note the acquisition time
for a damping factor of 1 is specified as 15,000 bit periods. T his
comprises 13,000 bit periods for frequency acquisition and
2,000 periods for phase acquisition. Compare this to the
400,000 bit periods acquisition time specified for a damping
ratio of 5; this consists entirely of frequency acquisition, and the
2,000 bit periods of phase acquisition is negligible.
While lower damping ratio affords faster acquisition, it also
allows more peaking in the jitter transfer response (jitter
peaking). For example, with a damping ratio of 10 the jitter
peaking is 0.02 dB, but with a damping factor of 1, the peaking
is 2 dB.
Jitter caused by variations of density of data transitions (pattern
jitter) is virtually eliminated by use of a new phase detector
(patented). Briefly, the measurement of zero phase error does
not cause the VCO phase to increase to above the average run
rate set by the data frequency. T he jitter created by a 27–1
pseudo-random code is 1/2 degree, and this is small compared
to random jitter.
DATA
INPUT
1
S
Ø
TS + 1
∑
DET
VCO
f
RECOVERED
DET
T he jitter bandwidth for the AD802-155 is 0.08% of the center
frequency. T his figure is chosen so that sinusoidal input jitter at
130 kHz will be attenuated by 3 dB. T he jitter bandwidths of
the AD800-45 and AD800-52 are 0.1% of the respective center
frequencies. T he jitter bandwidth of the AD800 or the AD802 is
mask programmable from 0.01% to 1% of the center frequency.
A device with a very low loop bandwidth (0.01% of the center
frequency) could effectively filter (clean up) a jittery timing
reference. Consult the factory if your application requires a
special loop bandwidth.
CLOCK OUTPUT
RETIMED
DATA OUTPUT
RETIMING
DEVICE
FRAC OUTPUT
Figure 21. AD800 and AD802 Block Diagram
–8–
REV. B
AD800/AD802
5.0V
C5
0.1
5.0V
C13 0.1
R13
154
R14
154
5.0V
R1
100
R2
100
R10
154
R9
154
R18
100
R17
100
C17 0.1
C14 0.1
C3 0.1
R15 100
R16 100
J1
J2
R5 100
R6 100
1
2
3
4
FRAC
FRAC
20
19
18
17
DATAOUT
DATAOUT
DATAOUT
FRAC
FRAC
DATAOUT
VCC2
5.0V
C15 0.1
C4 0.1
1
16
15
14
13
12
11
10
9
C9
0.1
SUBST
R12
154
2
3
C6 0.1
R19
130
R20
130
J3
R11
154
CLKOUT
CLKOUT
DATAIN
CLKOUT
CLKOUT
R7 100
5
6
16
15
14
13
12
DATAIN
VEE
J4
4
5
6
7
8
Z2
10H116
R23
VEE
R8 100
C7 0.1
R21
80.6
R22
80.6
130
R24
VCC1
R4
100
R3
7
8
VEE
130
C19
100
C12
0.1
5.0V
AVCC
VCC1
AVEE
C8
0.1
5.0V
0.1
C10
0.1
J5
5.0V
C11
9
DATAIN
DATAIN
CF1
CF2
C16
0.1
J6
CD
10
11
ASUBST
Z1
C20
0.1
AD800/802
IN
OUT
R26
80.6
R25
80.6
BYPASS
NETWORK
5.0V
C2
10µF
C21 0.1
5.0V
Figure 22. Evaluation Board Schem atic, Positive Supply
Table I. Evaluation Board, P ositive Supply: Com ponents List
D escription
Reference
D esignator
Quantity
R1–8, R15–18
R9–14
Resistor, 100 Ω, 1%
Resistor, 154 Ω, 1%
12
6
R19, 20, 23, 24
Resistor, 130 Ω, 1%
4
R21, 22, 25, 26
Resistor, 80.6 Ω, 1%
4
CD
C2
C3–C21
Z1
Capacitor, Loop Damping (See Specifications Page)
Capacitor, 10 µF, T antalum
Capacitor, 0.1 µF, Ceramic Chip
AD800/AD802
1
1
17
1
Z2
10H116, ECL Line Receiver
1
3.0
(A)
IN
TO
DEVICE
0.1µF
(A)
TO DEVICE
2.5
2.0
1.5
BEADS WITH ONE LOOP
(B)
IN
(B)
BYPASS
NETWORK
(A, B, C,
OR D)
TO
DEVICE
0.1µF
(C)
BEAD WITH
BEAD WITH
IN
ONE LOOP TWO LOOPS
(C)
IN
TO
DEVICE
C2
10µF
0.1µF
1.0
0.5
(D)
5.0V
BEAD WITH
TWO LOOPS TWO LOOPS
BEAD WITH
(D)
IN
TO
DEVICE
0.1µF
BYPASS NETWORK
COMPONENTS:
CAPACITOR ..........CERAMIC CHIP
FERRITE BEAD......1/4 IN. STACKPOLE CARBO 57-1392
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NOISE – V p-p @ 311MHz
Figure 23. Bypass Network Schem es
Figure 24. AD802-155 Output J itter vs. Supply Noise
(PECL Configuration)
REV. B
–9–
AD800/AD802
NOISE IN SENSE
AD802-155
50Ω
0.47µF
BYPASS
NETWORK
(A, B, C,
OR D)
0.47µF
PINS
8, 13,
14
10 TURNS
IN
TO
DEVICE
5V
PINS
6, 7, 9
10, 15,
18
10µF
MICRO
METALS
T50-10
PIN
3
Figure 25. Power Supply Noise Sensitivity Test Circuit, PECL Configuration
–5.2V
–5.2V
C3
0.1
C12
0.1
R2
100
R1
100
R10
154
R9
154
R21
274
R22
274
J1
J2
DATAOUT
DATAOUT
R5 100
FRAC
DATAOUT
DATAOUT
FRAC 20
1
2
3
4
5
6
R6 100
FRAC
19
18
17
FRAC
SUBST
DATAIN
–5.2V
–5.2V
—5.2V
C8 0.1
C9 0.1
C4
0.1
1
16
15
14
13
12
11
10
9
V
CC2
R12
154
R15
130
C11
0.1
R16
130
2
3
R11
154
CLKOUT
CLKOUT
J3
CLKOUT
CLKOUT
R7 100
DATAIN 16
J4
Z2
10H116
4
5
6
7
8
V
V
15
14
–5.2V
EE
EE
R8 100
R20
130
R19
130
C7
0.1
R4
100
R3
100
V
R14
80.6
V
V
R13
80.6
7
8
CC1
EE
C5
0.1
AV
13
12
CC1
CC
J5
J6
9
CF
DATAIN
DATAIN
AV
–5.2V
1
EE
C
D
–5.2V
10
CF
11
ASUBST
2
C2
10
Z1
AD800/802
C6
0.1
–5.2V
R18
80.6
R17
80.6
C10
0.1
Figure 26. Evaluation Board Schem atic, Negative Supply
Table II. Evaluation Board, Negative Supply: Com ponents List
Reference
D esignator
D escription
Quantity
R1–8
R9–12
Resistor, 100 Ω, 1%
Resistor, 154 Ω, 1%
8
4
R13, 14, 17, 18
Resistor, 80.6 Ω, 1%
4
R15, 16, 19, 20
Resistor, 130 Ω, 1%
4
R21, 22
CD
C2
C3–C12
Z1
Resistor, 274 Ω, 1%
2
1
1
10
1
Capacitor, Loop Damping (See Specifications Page)
Capacitor, 10 µF, T antalum
Capacitor, 0.1 µF, Ceramic Chip
AD800/AD802
Z2
10H116, ECL Line Receiver
1
–10–
REV. B
AD800/AD802
Figure 27. Negative Supply Configuration: Com ponent
Side (Top Layer)
Figure 29. Positive Supply Configuration: Com ponent
Side (Top Layer)
Figure 30. Positive Supply Configuration: Solder Side
Figure 28. Negative Supply Configuration: Solder Side
REV. B
–11–
AD800/AD802
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
20-P in Sm all O utline IC P ackage (R-20)
0.512 (13.00)
0.496 (12.60)
20
11
0.300 (7.60)
0.292 (7.40)
0.419 (10.65)
0.394 (10.00)
1
10
0.019 (0.48)
0.014 (0.36)
0.50 (1.27)
BSC
0.104 (2.64)
0.093 (2.36)
0.011 (0.28)
0.004 (0.10)
0.015 (0.38)
0.007 (0.18)
0.050 (1.27)
0.016 (0.40)
20-P in Cer dip P ackage (Q -20)
0.005 (0.13) MIN
0.098 (2.49) MAX
20
11
0.310 (7.87)
PIN 1
0.220 (5.59)
10
1
0.320 (8.13)
0.290 (7.37)
1.060 (26.92) MAX
0.060 (1.52)
0.200
(5.08)
MAX
0.015 (0.38)
0.150
(3.81)
MIN
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
15
°
0
°
0.100
(2.54)
BSC
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
–12–
REV. B
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