AD8116 [ADI]
200 MHz, 16 x 16 Buffered Video Crosspoint Switch; 200兆赫， 16 ×16缓冲式视频交叉点开关
| 型号： | AD8116 |
| 厂家： | 
ADI |
| 描述： | 200 MHz, 16 x 16 Buffered Video Crosspoint Switch |
| 文件： | 总26页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
200 MHz, 16
؋
16 Buffered a
Video Crosspoint Switch
AD8116*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Large 16
؋
16 High Speed Nonblocking Switch Array Switch Array Controllable via an 80-Bit Serial Word
Serial Data Out Allows “Daisy Chaining” of Multiple
AD8116s to Create Large Switch Arrays Over 256
؋
256 Complete Solution
AD8116
CLK
CLK
DATA OUT
DATA IN
80-BIT SHIFT REG.
Buffered Inputs
16 Individual Output Amplifiers
Drives 150 ⍀ Loads
UPDATE
UPDATE
CE
80
CE
Excellent Video Performance
PARALLEL LATCH
60 MHz 0.1 dB Gain Flatness
RESET
16 INPUTS
+4
RESET
80
0.01% Differential Gain Error (RL = 150 ⍀)
0.01؇ Differential Phase Error (RL = 150 ⍀)
Excellent AC Performance
200 MHz –3 dB Bandwidth
300 V/s Slew Rate
Low Power of 900 mW (3.5 mW per Point)
Low All Hostile Crosstalk of –70 dB @ 5 MHz
Output Disable Allows Direct Connection of Multiple
Device Outputs
Chip Enable Allows Selection of Individual AD8116s in
Large Arrays (or Parallel Programming of AD8116s)
Reset Pin Allows Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “Power-
On” Reset Capability)
16
DECODE
16
؋
5:16 DECODERS 256
OUTPUT
BUFFER
+1
+1
+1
+1
+1
SWITCH
MATRIX
+1
+1
16 OUTPUTS
+1
+1
+1
+1
+1
+1
+1
+1
+1
128-Lead LQFP Package (14 mm
؋
14 mm) APPLICATIONS
Routing of High Speed Signals Including:
Composite Video (NTSC, PAL, S, SECAM, etc.)
Component Video (YUV, RGB, etc.)
3-Level Digital (HDB3)
Video on Demand
Ultrasound
+0.5
R =150⍀
L
+3
+2
+1
+0.4
+0.3
+0.2
Communication Satellites
200mV p-p
0
–1
–2
–3
–4
+0.1
0
PRODUCT DESCRIPTION
FLATNESS
2V p-p
The AD8116 is a high speed 16 × 16 video crosspoint switch
matrix. It offers a –3 dB signal bandwidth greater than 200 MHz
and channel switch times of 60 ns with 0.1% settling. With –70 dB
of crosstalk and –105 dB of isolation (@ 5 MHz), the AD8116
is useful in many high speed applications. The differential gain
and differential phase errors of better than 0.01% and 0.01°,
respectively, along with 0.1 dB flatness out to 60 MHz make the
AD8116 ideal for video signal switching.
–0.1
–0.2
–0.3
2V p-p
200mV p-p
100k
1M
10M
FREQUENCY – Hz
100M
1G
Figure 1. Frequency Response
The AD8116 includes output buffers that can be placed into a
high impedance state for paralleling crosspoint outputs so that
off channels do not load the output bus. It operates on voltage
supplies of ±5 V while consuming only 90 mA of idle current.
The channel switching is performed via a serial digital control
that can accommodate “daisy chaining” of several devices.
The AD8116 is packaged in a 128-lead LQFP package occupy-
ing only 0.36 square inches, and is specified over the commer-
cial temperature range of 0°C to +70°C.
*Patent Pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(V = ؎ 5 V, T = +25؇C, R = 1 k⍀ unless otherwise noted)
AD8116–SPECIFICATIONS
S
A
L
Limit
Min Typ
Reference
Figure
Parameter
Conditions
Max Units
DYNAMIC PERFORMANCE
–3 dB Bandwidth
200 mV p-p, RL = 150 Ω
1 V p-p, RL = 150 Ω
2 V p-p, RL = 150 Ω
200
120
80
300
60
25
20
60
45
MHz
MHz
MHz
V/µs
6
–
6
10
11
6
6
6
Slew Rate
Settling Time
Gain Flatness
2 V Step, RL = 150 Ω
0.1%, 2 V Step, RL = 150 Ω
0.05 dB, 200 mV p-p, RL = 150 Ω
0.05 dB, 2 V p-p, RL = 150 Ω
0.1 dB, 200 mV p-p, RL = 150 Ω
0.1 dB, 2 V p-p, RL = 150 Ω
ns
MHz
MHz
MHz
MHz
6
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
NTSC or PAL, RL = 1 kΩ
NTSC or PAL, RL = 150 Ω
NTSC or PAL, RL = 1 kΩ
NTSC or PAL, RL = 150 Ω
ƒ = 5 MHz
0.01
0.01
0.01
0.01
–70
%
%
Degrees
Degrees
dB
–
–
–
–
Differential Phase Error
Crosstalk, All Hostile
7
ƒ = 10 MHz
–60
dB
7
Off Isolation, Input-Output
Input Voltage Noise
ƒ = 10 MHz, RL = 150 Ω, One Channel
0.01 MHz to 50 MHz
–105
15
dB
nV/√Hz
16
13
DC PERFORMANCE
Gain
No Load
RL = 1 kΩ
No Load, Ch-Ch
RL = 1 kΩ, Ch-Ch
0.995 0.999
0.992 0.999
1.000 V/V
1.000 V/V
–
–
–
–
Gain Matching
0.15
0.5
%
%
OUTPUT CHARACTERISTICS
Output Offset Voltage
Output Impedance
Worst Case All Switch Configurations
DC, Enabled
Disabled
15
0.2
10
3
1
45
mV
Ω
MΩ
pF
µA
V
22
17
14
14
–
–
–
–
1
Output Disable Capacitance
Output Leakage Current
Output Voltage Range
Output Current
Disabled
±2.5 ±3
20
40
65
mA
mA
Short Circuit Current
INPUT CHARACTERISTICS
Input Voltage Range
Input Capacitance
Input Resistance
Input Bias Current
±2.5 ±3
V
–
Any Switch Configuration
5
pF
MΩ
µA
18
18
–
1
10
2
5
SWITCHING CHARACTERISTICS
Enable On Time
Switching Time
60
50
ns
ns
–
21
50% UPDATE to 1% Output Settling,
2 V Step
Switching Transient (Glitch)
15
mV p-p
15
POWER SUPPLIES
Supply Current
AVCC, Outputs Enabled, No Load
AVCC, Outputs Disabled
AVEE, Outputs Enabled, No Load
AVEE, Outputs Disabled
DVCC, Outputs Enabled, No Load
DVEE, Outputs Enabled, No Load
75
25
70
22.5
25
10
±4.5 to ±5.5
60
40
95
95
mA
mA
mA
mA
mA
mA
V
–
–
–
–
–
–
–
12
12
35
15
Supply Voltage Range
PSRR
ƒ = 100 kHz
ƒ = 1 MHz
dB
dB
OPERATING TEMPERATURE RANGE
Temperature Range
θJA
Operating (Still Air)
Operating (Still Air)
0 to +70
37
°C
°C/W
–
–
Specifications subject to change without notice.
REV. A
–2–
AD8116
TIMING CHARACTERISTICS
Limit
Typ
Parameter
Symbol
Min
Max
Units
Data Setup Time
CLK Pulsewidth
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulsewidth
CLK to DATA OUT Valid
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz
CLK, UPDATE Rise and Fall Times
RESET Time
t1
t2
t3
t4
t5
t6
t7
–
20
100
20
100
0
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
50
200
50
–
–
–
16
100
200
t2
t4
1
CLK
0
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
t1
t3
1
DATA IN
0
OUT15 (D4)
OUT15 (D3)
OUT00 (D0)
t5
t6
1 = LATCHED
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
UPDATE
0 = TRANSPARENT
t7
DATA OUT
0
1
2 3
4
5
6
7
8
9 10
15
20
25
75
79
CLOCK
DATA IN
UPDATE
T = 0
INCREASING TIME
Figure 2. Timing Diagram and Programming Example
Table I. Logic Levels
VIH
VIL
VOH
VOL
IIH
IIL
IOH
IOL
CLK, DATA IN,
CLK, DATA IN, DATA OUT
DATA OUT
CLK, DATA IN, CLK, DATA IN, DATA OUT
DATA OUT
CE, UPDATE
CE, UPDATE
CE, UPDATE
CE, UPDATE
2.0 V min
0.8 V max
2.7 V min
0.5 V max
20 µA max
–400 µA min
–400 µA max
3.0 mA min
REV. A
–3–
AD8116
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8116 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175°C for an extended
period can result in device failure.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V
Internal Power Dissipation2
AD8116 128-Lead Plastic LQFP (ST) . . . . . . . . . . . . 3.5 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . .+300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air (TA = +25°C):
While the AD8116 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction temp-
erature (+150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 3.
128-lead plastic LQFP (ST): θJA = 37°C/W.
5.0
T
= 150؇C
ORDERING GUIDE
J
4.0
3.0
2.0
1.0
0
Temperature Package
Range Description
Package
Option
Model
AD8116JST 0°C to +70°C 128-Lead Plastic LQFP ST-128A
(14 mm × 14 mm)
AD8116-EB
Evaluation Board
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ؇C
Figure 3. Maximum Power Dissipation vs. Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8116 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–4–
AD8116
Table II. Operation Truth Table
Control Lines
CE
UPDATE
CLK
DATA IN
DATA OUT
RESET
Operation/Comment
1
0
X
1
X
f
X
Data i
X
1
1
No change in logic.
Data i-80
The data on the DATA IN line is loaded into the
serial register. The first bit clocked into the serial
register appears at DATA OUT 80 clocks later.
Data in the serial shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
0
0
X
X
X
X
X
X
1
0
X
X
Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
DATA OUT
DATA IN
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
OUTPUT CH
CH BIT #
OUT0 OUT0 OUT0 OUT0 OUT0 OUT1
OUT14 OUT15 OUT15 OUT15 OUT15 OUT15
0
LSB
1
2
3
EN
MSB
0
EN
0
LSB
1
3
2
2
3
1
EN
MSB
SERIAL BIT #
79
78
77
76
75
74
5
4
0
Q
Q
Q
Q
CLR Q
Q
CLR Q
Q
Q
Q
Q CLR Q
DECODE
256
SWITCH MATRIX
16
OUTPUT
ENABLE
Figure 4. Logic Diagram
REV. A
–5–
AD8116
PIN FUNCTION DESCRIPTIONS
Pin Name
Pin Numbers
Pin Description
INxx
2, 4, 6, 8, 10, 12, 14, 16, 18,
20, 22, 24, 26, 28, 30, 32
Analog Inputs; xx = Channel No. 00 thru 15.
DATA IN
CLK
DATA OUT 35, 124
37, 126
36, 125
Serial Data Input, TTL Compatible.
Serial Clock, TTL Compatible. Falling edge triggered.
Serial Data Out, TTL Compatible.
UPDATE
38, 123
Enable (Transparent) “Low.” Allows serial register to connect directly to switch
matrix. Data latched when “high.”
RESET
CE
39, 122
40, 121
65, 67, 69, 71, 73, 75, 77, 79,
81, 83, 85, 87, 89, 91, 93, 95
Disable Outputs, Enable “Low.”
Chip Enable, Enable “Low.” Must be “low” to clock in & latch data.
Analog Outputs yy = Channel Nos. 00 thru 15.
OUTyy
AGND
1, 3, 5, 7, 9, 11, 13, 15, 17, 19,
21, 23, 25, 27, 29, 31, 33, 128
Analog Ground for inputs and switch matrix.
DVCC
34, 39, 127
+5 V for Digital Circuitry.
DGND
41, 120
Ground for Digital Circuitry.
DVEE
42, 119
–5 V for Digital Circuitry.
AVEE
AVCC
43, 44, 45, 116, 117, 118
46, 47, 48, 113, 114, 115
56–63, 97–104
96
–5 V for Inputs and Switch Matrix.
+5 V for Inputs and Switch Matrix.
AGNDxx
AVCC00
AVCC15
AVCCxx/yy
AVEExx/yy
Ground for Output Amp, xx = Output Channel Nos. 00 thru 15. Must be connected.
+5 V for Output Channel 00. Must be connected.
+5 V for Output Channel 15. Must be connected.
+5 V for Output Amplifier that is shared by Channel Nos. xx and yy. Must be connected.
–5 V for Output Amplifier that is shared by Channel Nos. xx and yy. Must be connected.
64
68, 72, 76, 80, 84, 88, 92
66, 70, 74, 78, 82, 86, 90, 94
V
V
CC
CC
V
CC
ESD
ESD
ESD
ESD
20k⍀
INPUT
OUTPUT
RESET
ESD
ESD
V
V
EE
EE
a. Analog Input
b. Analog Output
c. Reset Input
V
CC
V
CC
ESD
ESD
2k⍀
ESD
ESD
OUTPUT
INPUT
V
EE
V
EE
d. Logic Input
e. Logic Output
Figure 5. I/O Pin Schematics
REV. A
–6–
AD8116
PIN CONFIGURATION
96
95
94
AGND
IN00
1
AVCC00
OUT00
PIN 1
IDENTIFIER
2
3
AGND
IN01
AVEE00/01
OUT01
4
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
5
AGND
IN02
AVCC01/02
OUT02
6
7
AGND
IN03
AVEE02/03
OUT03
8
9
AGND
IN04
AVCC03/04
OUT04
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AGND
IN05
AVEE04/05
OUT05
AGND
IN06
AVCC05/06
OUT06
AD8116
128L LQFP
(14mm x 14mm)
AGND
IN07
AVEE06/07
OUT07
TOP VIEW
(Not to Scale)
AGND
IN08
AVCC07/08
OUT08
AGND
IN09
AVEE08/09
OUT09
AGND
IN10
AVCC09/10
OUT10
AGND
IN11
AVEE10/11
OUT11
AGND
IN12
AVCC11/12
OUT12
AGND
IN13
AVEE12/13
OUT13
AGND
IN14
AVCC13/14
OUT14
AGND
IN15
AVEE14/15
OUT15
NC = NO CONNECT
REV. A
–7–
–Typical Performance Characteristics
AD8116
+4
+0.5
R =150⍀
100mV p-p
L
C =0pF
L
+3
+0.4
+2
+1
0
+0.3
+0.2
+0.1
0
200mV p-p
25mV/DIV
2V p-p
FLATNESS
–1
–2
–0.1
2V p-p
–3
–4
–0.2
–0.3
200mV p-p
10M
100ns/DIV
100k
1M
100M
1G
FREQUENCY – Hz
Figure 9. Step Response, 100 mV Step
Figure 6. Frequency Response
–10
–20
R
R
= 1k⍀
= 37.5⍀
L
S
ALL HOSTILE CROSSTALK
= 632mV p-p
–30
–40
V
IN
2V p-p
–50
–60
–70
500mV/DIV
ADJACENT CHANNEL
CROSSTALK
= 632mV p-p
–80
V
IN
–90
–100
300k
100ns/DIV
1M
10M
FREQUENCY – Hz
100M 200M
Figure 10. Step Response, 2 V Step
Figure 7. Crosstalk vs. Frequency
0
–10
–20
V
= 2V p-p, R = 150⍀
IN
L
2V STEP
R
L
= 150⍀
–30
–40
2mV/DIV
= 0.1%/DIV
–50
–60
–70
2ND HARMONIC
3RD HARMONIC
–80
–90
–100
100k
0
20 40 60 80 100 120 140 160 180
20ns/DIV
1M
10M
100M
FREQUENCY – Hz
Figure 11. Settling Time
Figure 8. Total Harmonic Distortion
REV. A
–8–
Typical Performance Characteristics–AD8116
–20
–30
–40
–50
5
4
3
1V/DIV
2
1
0
20
10
10mV/DIV
0
–10
–20
–60
–70
50ns/DIV
10k
100k
1M
10M
FREQUENCY – Hz
Figure 15. Switching Transient (Glitch)
Figure 12. PSRR vs. Frequency
–50
316
100
–60
–70
V
= 2V p-p
IN
–80
–90
–100
–110
–120
–130
–140
–150
31.6
10
100k
1M
10M
100M
500M
3.16
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 16. Off Isolation, Input-Output
Figure 13. Voltage Noise vs. Frequency
10,000
10M
1000
100
10
1M
100k
10k
1k
1
0.1
100k
1M
10M
100M
500M
100
100k
FREQUENCY – Hz
1M
10M
100M
500M
FREQUENCY – Hz
Figure 17. Output Impedance, Enabled
Figure 14. Output Impedance, Disabled
REV. A
–9–
AD8116
10M
1M
VOUT
100k
10k
1k
100mV, 50ns
100
30k
100k
1M
10M
100M
500M
FREQUENCY – Hz
Figure 18. Input Impedance vs. Frequency
Figure 21. Switching Time
+15
+12
+9
+6
+3
0
170
160
V
= 200mV
IN
R
= 150⍀
L
150
140
130
120
110
30pF
18pF
100
90
80
70
12pF
–3
60
50
–6
–9
40
30
20
–12
–15
10
0
30k
100k
1M
10M
100M
500M
–0.035
–0.025
–0.015
–0.005
0.005
0.015
0.025
FREQUENCY – Hz
OFFSET VOLTAGE – Volts
Figure 19. Frequency Response vs. Capacitive Load
Figure 22. Offset Voltage Distribution
+0.5
2.0
1.5
1.0
V
= 200mV
IN
+0.4
R
= 150⍀
L
+0.3
+0.2
C
L
= 30pF
C
L
= 18pF
+0.1
0
0.5
0.0
–0.1
C
L
= 12pF
–0.5
–0.2
–0.3
–1.0
–1.5
–2.0
–0.4
–0.5
30k
100k
1M
10M
100M
–60
–40
–20
0
20
40
60
80
100
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 20. Flatness vs. Capacitive Load
Figure 23. Offset Voltage Drift vs. Temperature
REV. A
–10–
AD8116
THEORY OF OPERATION
APPLICATIONS
Loading Data
Multichannel Video
Data to control the switches is clocked serially into an 80-bit
shift register and then transferred in parallel to an 80-bit latch.
The falling edge of CLK (the serial clock input) loads data into
the shift register. The first five bits of the 80 bits are loaded via
DATA IN (the serial data input) program OUT15. The first of
the five bits (D4) enables or disables the output. The next four
bits (D3–D0, D3 = MSB, D0 = LSB) determine which one of
the 16 inputs will be connected to OUT15 (only one of the 16
inputs can be connected to a given output). The remaining bits
program OUT14 thru OUT00.
The excellent video specifications of the AD8116 make it an
ideal candidate for creating composite video crosspoint switches.
These can be made quite dense by taking advantage of the
AD8116’s high level of integration and the fact that composite
video requires only one crosspoint channel per system video
channel. There are, however, other video formats that can be
routed with the AD8116 requiring more than one crosspoint
channel per video channel.
Some systems use twisted pair wiring to carry video signals.
These systems utilize differential signals and can lower costs
because they use lower cost cables, connectors and termination
methods. They also have the ability to lower crosstalk and reject
common-mode signals, which can be important for equip-
ment that operates in noisy environments or where common-
mode voltages are present between transmitting and receiving
equipment.
After the shift register is filled with the new 80 bits of control
data, UPDATE is activated (low) to transfer the data to the
parallel latches. The switch control latches are static and will
hold their data as long as power is applied.
To extend the number of switches in an array, the DATA
OUT and DATA IN pins of multiple AD8116s can be daisy-
chained together. The DATA OUT pin is the end of the shift
register and may be directly connected to the DATA IN pin of
the follow-on AD8116. CE can be used to control the clocking
of data into selected devices.
In such systems, the video signals are differential; there is a
positive and negative (or inverted) version of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first order zero common-
mode voltage. At the receive end, the signals are differentially
received and converted back into a single-ended signal.
Serial Logic
The AD8116 employs a serial interface for programming the
state of the crosspoint array. The 80-bit shift register (Figure 4)
consists of static D flip-flops while the parallel latch uses transpar-
ent latches that are latched by a logic high state of UPDATE,
and transparent on logic low of the same signal. The 4-to-16
decoder is a small current-mode multilevel gate array that steers
a small select current to the selected point in the crosspoint array.
When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single AD8116, eight differential video
channels can be assigned to the 16 inputs and 16 outputs. This
will effectively form an 8 × 8 differential crosspoint switch.
The RESET signal is connected to only the enable/disable bit on
each output buffer. This means that the AD8116 will have a
random configuration on power-up. In normal operation though,
RESET and UPDATE can be used together to alternately en-
able and disable an entire array at once, if desired.
Programming such a device will require that inputs and outputs
be programmed in pairs. This information can be deduced by
inspection of the programming format of the AD8116 and the
requirements of the system.
Separate chip enable (CE), update (UPDATE) and serial data
out (DATA OUT) signals allow several options for program-
ming larger arrays of AD8116s. The function of each bit in the
80-bit word that programs the state of the AD8116 is shown in
Figure 4. In normal operation, the DATA OUT pin of one
AD8116 is connected to the DATA IN of the next. In this way, for
example, an array of eight AD8116s would be programmed with
one 640-bit sequence. In this mode CE is logic low and the
CLK and UPDATE pins are connected in parallel.
There are other analog video formats requiring more than one
analog circuit per video channel. One two-circuit format that is
more commonly being used in systems such as satellite TV,
digital cable boxes and higher quality VCRs, is called S-video or
Y/C video. This format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color
(chrominance or C) on a second channel.
Since S-video also uses two separate circuits for one video chan-
nel, creating a crosspoint system requires assigning one video
channel to two crosspoint channels as in the case of a differen-
tial video system. Aside from the nature of the video format,
other aspects of these two systems will be the same.
In one alternate mode of programming, the CE pin can be used
to select one AD8116 at a time. This might be desirable when
the ability to program just one device at a time is required. In
this mode CLK, UPDATE and DATA IN are all connected in
parallel. The user then selects each AD8116 in turn (with the
CE signal) and programs it with the desired data. Larger arrays
can also be programmed by connecting each DATA IN signal to
a larger parallel bus. In this way only 80 clock cycles would be
needed to program the entire array. The logic signals are con-
figured so that all programming can be accomplished with
synchronous logic and a continuous clock, so that no missing
cycles or delays need be generated.
There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can also
be converted to Y, R-Y, B-Y format, sometimes called YUV
format. These three-circuit video standards are referred to as
component analog video.
The three-circuit video standards require three crosspoint chan-
nels per video channel to handle the switching function. In a
fashion similar to the two-circuit video formats, the inputs and
outputs are assigned in groups of three and the appropriate logic
programming is performed to route the video signals.
REV. A
–11–
AD8116
Creating Larger Crosspoint Arrays
Using additional crosspoint devices in the design can lower the
number of outputs that have to be wire-ORed together. Figure
26 shows a block diagram of a system using ten AD8116s to
create a nonblocking 128 × 16 crosspoint that restricts the wire-
ORing at the output to only four outputs. This will prevent an
enabled output from having to drive a large number of disabled
devices. Additionally, by using the lower eight outputs from
each of the two Rank 2 AD8116s, a blocking 128 × 32 crosspoint
array can be realized.
The AD8116 is a high density building block for crosspoint
arrays over 256 × 256. Various features such as output disable,
chip enable, serial data out and multiple pinouts for logic signals
are very useful for the creation of these larger arrays.
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices that are required.
The 16 × 16 architecture of the AD8116 contains 256 “points,”
which is a factor of four greater than an 8 × 8 crosspoint and a
factor of 64 greater than a 4 × 1 crosspoint. The PC board area
and power consumption savings are readily apparent when
compared to using these smaller devices.
There are, however, some drawbacks to this technique. The
offset voltages of the various cascaded devices will accumulate
and the bandwidth limitations of the devices will compound. In
addition, the extra devices will consume more current and take
up more board space. Once again, the overall system design
specifications will determine how to make the various trade-offs.
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the avail-
ability of that input to be a source for any other outputs.
AD8116
IN OUT
AD8116
IN
Thus a 32 × 32 crosspoint will require 1024 points. This number is
then divided by 256, or the number of points in one AD8116
device, to yield four in this case. This says that the minimum
number of 16 × 16 devices required for a fully programmable
32 × 32 crosspoint is four.
0–15
0–15
IN
OUT
16
Some nonblocking crosspoint architectures will require more
than this minimum as calculated above. Also, there are blocking
architectures that can be constructed with fewer devices than this
minimum. These systems have connectivity available on a statis-
tical basis that is determined when designing the overall system.
AD8116
IN OUT
AD8116
IN OUT
16–31
16–31
IN
16
16
OUT 16–31
16
OUT 0–15
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to “wire-
OR” the outputs together in the vertical direction. The meaning
of horizontal and vertical can best be understood by looking at a
diagram. Figure 24 illustrates this concept for a 32 × 32 crosspoint
array. A 48 × 48 crosspoint is illustrated in Figure 25.
Figure 24. 32 × 32 Crosspoint Array Using Four AD8116s
AD8116
OUT
AD8116
IN OUT
AD8116
IN OUT
The 32 × 32 crosspoint requires each input driver drive two
inputs in parallel and each output be wire-ORed with one other
output. The 48 × 48 crosspoint requires driving three inputs in
parallel and having the outputs wire-ORed in groups of three. It
is required of the system programming that only one output of a
wired-OR node be active at a time.
IN 0–15
IN
16
AD8116
IN OUT
AD8116
IN OUT
AD8116
IN OUT
It is not essential that crosspoint architectures be square. For
example, a 64 × 16 crosspoint array can be constructed with
four AD8116s by driving each input with a separate signal and
wire-ORing together the corresponding outputs of each device.
It can be seen, however, that by going to larger arrays the
number of disabled outputs an active output has to drive
starts to increase.
IN16–31
16
AD8116
IN OUT
AD8116
IN OUT
AD8116
IN OUT
32–47
IN
At some point, the number of outputs that are wire-ORed be-
comes too great to maintain system performance. This will vary
according to which system specifications are most important.
For example, a 128 × 16 crosspoint can be created with eight
AD8116s. This design will have 128 separate inputs and have
the corresponding outputs of each device wire-ORed together
in groups of eight.
16
16
OUT 0–15
16
OUT 16–31
16
OUT 32–47
Figure 25. 48 × 48 Crosspoint Array Using Nine AD8116s
REV. A
–12–
AD8116
RANK 1
(128:32)
capacitor to the logical high state. If several AD8116s are used,
the pull-up resistors will be in parallel, so a larger value capaci-
tance should be used.
8
8
IN 0–15
IN 16–31
IN 32–47
16
16
16
16
If the system requires the ability to be reset while power is still
applied, the RESET driver will have to be able to charge and
discharge this capacitance in the required time. With too many
devices in parallel, this might become more difficult; if this
occurs, the reset circuits should be broken up into smaller sub-
sets with each controlled by a separate driver.
8
8
RANK 2
32:16 NONBLOCKING
(32:32 BLOCKING)
8
8
NONBLOCKING
OUTPUTS
8
8
8
CROSSTALK
OUT 0–16
IN 48–63
IN 64–79
IN 80–95
Many systems, such as broadcast video, that handle numerous
analog signal channels have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the signals
of other nearby channels to a given channel.
8
8
8
8
8
ADDITIONAL
16 OUTPUTS
16
16
8
8
When there are many signals in close proximity in a system, as
will undoubtedly be the case in a system that uses the AD8116,
the crosstalk issues can be quite complex. A good understanding
of the nature of crosstalk and some definition of terms is required
in order to specify a system that uses one or more AD8116s.
8
8
FOUR AD8116 OUTPUTS
WIRE-ORED TOGETHER
IN 96–111
16
16
8
8
IN 112–127
Types of Crosstalk
Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field and
sharing of common impedances. This section will explain these
effects.
Figure 26. Nonblocking 128 × 16 Array (128 × 32 Blocking)
Logic Operation
There are two basic options for controlling the logic in multi-
crosspoint arrays. One is to serially connect the data paths
(DATA OUT to DATA IN) of all the devices and tie all the
CLK and UPDATE signals in parallel. CE can be tied low for
all the devices. A long serial sequence with the desired pro-
gramming data consisting of 80 bits times the number of
AD8116 devices can then be shifted through all the parallel
devices by using the DATA IN of the first device and the CLK.
When finished clocking in the data, UPDATE can be pulled low
to program all the device crosspoint matrices.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter propagates
across a stray capacitance and couples with the receiver and
induces a voltage. This voltage is an unwanted crosstalk signal
in any channel that receives it.
Currents flowing in conductors create magnetic fields that circu-
late around the currents. These magnetic fields will then gener-
ate voltages in any other conductors whose paths they link. The
undesired induced voltages in these other channels are crosstalk
signals. The channels that crosstalk can be said to have a
mutual inductance that couples signals from one channel to
another.
This technique has an advantage in that a separate CE signal
is not required for each chip, but has a disadvantage in that
several chips’ data cannot be shifted in parallel. In addition, if
another device is added into the system between already existing
devices, the programming sequence will have to be lengthened
at some midpoint to allow for programming of the added device.
The power supplies, grounds and other signal return paths of a
multichannel system are generally shared by the various channels.
When a current from one channel flows in one of these paths, a
voltage that is developed across the impedance becomes an
input crosstalk signal for other channels that share the common
impedance.
The second programming method is to connect all the CLK
and the DATA IN pins in parallel and use the CE pins in se-
quence to program each device. If a byte or 16-bit word of data
is available for providing the programming data, then multiple
AD8116s can be programmed in parallel with just 80 clock
cycles. This method can be used to speed up the programming
of large arrays. Of course, in a practical system, various combi-
nations of these basic methods can be used.
All these sources of crosstalk are vector quantities, so the
magnitudes cannot be simply added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can actually reduce
the crosstalk.
Power-On Reset
Areas of Crosstalk
Most systems will want all the AD8116s to be in the reset state
(all outputs disabled) when power is applied to the system. This
ensures that two outputs that are wire-ORed together will not
fight each other at power up.
For a practical AD8116 circuit, it is required that it be mounted
to some sort of circuit board in order to connect it to power
supplies and measurement equipment. Great care has been
taken to create a characterization board (also available as an
evaluation board) that adds minimum crosstalk to the intrinsic
device. This, however, raises the issue that a system’s crosstalk
is a combination of the intrinsic crosstalk of the devices and the
circuit board to which they are mounted. It is important to try
The power-on reset function can be implemented by adding a
0.1 µF capacitor from the RESET pin to ground. This will hold
this signal low after the power is applied to reset the device. An
on-chip 20 kΩ resistor from RESET to DVCC will charge the
REV. A
–13–
AD8116
to separate these two areas of crosstalk when attempting to
minimize its effect.
Input and Output Crosstalk
The flexible programming capability of the AD8116 can be used
to diagnose whether crosstalk is occurring more on the input
side or the output side. Some examples are illustrative. A given
input channel (IN07 in the middle for this example) can be
programmed to drive OUT07. The input to IN07 is just
terminated to ground and no signal is applied.
In addition, crosstalk can occur among the input circuits to a
crosspoint and among the output circuits. Techniques will be
discussed for diagnosing which part of a system is contributing
to crosstalk.
Measuring Crosstalk
All the other inputs are driven in parallel with the same test
signal (practically provided by a distribution amplifier), but all
other outputs except OUT07 are disabled. Since grounded IN07
is programmed to drive OUT07, there should be no signal
present. Any signal that is present can be attributed to the other
15 hostile input signals, because no other outputs are driven.
Thus, this method measures the all-hostile input contribution to
crosstalk into IN07. Of course, the method can be used for
other input channels and combinations of hostile inputs.
Crosstalk is measured by applying a signal to one or more channels
and measuring the relative strength of that signal on a desired
selected channel. The measurement is usually expressed as dB
down from the magnitude of the test signal. The crosstalk is
expressed by:
|XT| = 20 log10 (Asel(s)/Atest(s))
where s = jω is the Laplace transform variable, Asel(s) is the
amplitude of the crosstalk-induced signal in the selected channel
and Atest(s) is the amplitude of the test signal. It can be seen
that crosstalk is a function of frequency, but not a function of
the magnitude of the test signal. In addition, the crosstalk signal
will have a phase relative to the test signal associated with it.
For output crosstalk measurement, a single input channel is
driven (IN00 for example) and all outputs other than a given
output (IN07 in the middle) are programmed to connect to
IN00. OUT07 is programmed to connect to IN15 which is
terminated to ground. Thus OUT07 should not have a signal
present since it is listening to a quiet input. Any signal measured
at the OUT07 can be attributed to the output crosstalk of the
other 15 hostile outputs. Again, this method can be modified to
measure other channels and other crosspoint matrix combinations.
A network analyzer is most commonly used to measure crosstalk
over a frequency range of interest. It can provide both magni-
tude and phase information about the crosstalk signal.
As a crosspoint system or device grows larger, the number
of theoretical crosstalk combinations and permutations can
become extremely large. For example, in the case of the 16 × 16
matrix of the AD8116, we can examine the number of crosstalk
terms that can be considered for a single channel, say IN00
input. IN00 is programmed to connect to one of the AD8116
outputs where the measurement can be made.
Effect of Impedances on Crosstalk
The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input
side is capacitive coupling. The high impedance inputs do not
have significant current flow to create magnetically induced
crosstalk.
First, we can measure the crosstalk terms associated with driv-
ing a test signal into each of the other 15 inputs one at a time.
We can then measure the crosstalk terms associated with driving
a parallel test signal into all 15 other inputs taken two at a time
in all possible combinations; and then three at a time, etc., until,
finally, there is only one way to drive a test signal into all 15 other
inputs.
From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies
the magnitude of the crosstalk will be given by:
|XT| = 20 log10 [(RS CM) × s]
Each of these cases is legitimately different from the others and
might yield a unique value depending on the resolution of the
measurement system, but it is hardly practical to measure all
these terms and then to specify them. In addition, this describes
the crosstalk matrix for just one input channel. A similar crosstalk
matrix can be proposed for every other input. In addition, if
the possible combinations and permutations for connecting
inputs to the other (not used for measurement) outputs are
taken into consideration, the numbers rather quickly grow to
astronomical proportions. If a larger crosspoint array of multiple
AD8116s is constructed, the numbers grow larger still.
where RS is the source resistance, CM is the mutual capacitance
between the test signal circuit and the selected circuit, and s is
the Laplace transform variable.
From the equation it can be observed that this crosstalk mecha-
nism has a high pass nature; it can be also minimized by reducing
the coupling capacitance of the input circuits and lowering
the output impedance of the drivers. If the input is driven from
a 75 Ω terminated cable, the input crosstalk can be reduced by
buffering this signal with a low output impedance buffer.
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8116 is specified with excellent
differential gain and phase when driving a standard 150 Ω video
load, the crosstalk will be higher than the minimum due to the
high output currents. These currents will induce crosstalk via
the mutual inductance of the output pins and bond wires of the
AD8116.
Obviously, some subset of all these cases must be selected to be
used as a guide for a practical measure of crosstalk. One common
term is “all hostile” crosstalk. This term means that all other
system channels are driven in parallel, and the crosstalk to the
selected channel is measured. In general, this will yield the
worst crosstalk number, but this is not always the case.
From a circuit standpoint, this output crosstalk mechanism
looks like a transformer with a mutual inductance between the
windings that drives a load resistor. For low frequencies, the
magnitude of the crosstalk is given by:
Other useful crosstalk measurements are those created by one
nearest neighbor or by the two nearest neighbors on either side.
These crosstalk measurements will generally be higher than
those of more distant channels, so they can serve as a worst case
measure for any other one-channel or two-channel crosstalk
measurements.
|XT| = 20 log10 (Mxy × s/RL)
REV. A
–14–
AD8116
where Mxy is the mutual inductance of output x to output y and
RL is the load resistance on the measured output. This crosstalk
mechanism can be minimized by keeping the mutual inductance
low and increasing RL. The mutual inductance can be kept low
by increasing the spacing of the conductors and minimizing
their parallel length.
The input and output signals minimize crosstalk if they are
located between ground planes on layers above and below, and
separated by ground in between. Vias should be located as close
to the IC as possible to carry the inputs and outputs to the inner
layer. The only place the input and output signals surface is at
the input termination resistors and the output series back termi-
nation resistors. These signals should also be separated, to the
extent possible, as soon as they emerge from the IC package.
One way to increase the load resistance is to buffer the outputs
with a high input impedance buffer as shown in Figure 27. The
AD8079AR is a dual buffer that can be strapped for a gain of +2
(B grade = +2.2). This offsets the halving of the signal when
driving a standard back-terminated video cable.
+5V
0.1F
10F
75⍀
+
The input of the buffer requires a path for bias current. This can
be provided by a 500 Ω to 5 kΩ resistor to ground. This resistor
also serves the purpose of biasing the outputs of the crosspoints
at zero volts when all the outputs are disabled.
+V
S
G = +2
OUTXX
1
8
5
1k⍀
In addition, the load resistor actually lowers the crosstalk com-
pared to the conditions of the AD8116 outputs driving a high
impedance (greater than 10 kΩ) or driving a video load (150 Ω).
This is because the electric field crosstalk that dominates in the
high impedance case has a phase of –90 degrees, while the mag-
netic field crosstalk that dominates in the video load case has a
phase of +90 degrees. With a 500 Ω to 5 kΩ load, the contribu-
tions from each of these is roughly equal, and there is some
cancellation of crosstalk due to the phase differences.
75⍀
75⍀
2
3
AD8079AR
AD8116
75⍀
4
OUTYY
G = +2
1k⍀
–V
S
OUTZZ
10F
0.1F
+
AD8116
OUTWW
PCB Layout
–5V
Extreme care must be exercised to minimize additional crosstalk
generated by the system circuit board(s). The areas that must be
carefully detailed are grounding, shielding, signal routing and
supply bypassing.
TO OTHER
AD8116 OUTPUTS
The packaging of the AD8116 is designed to help keep the
crosstalk to a minimum. Each input is separated from each
other’s input by an analog ground pin. All of these AGNDs
should be directly connected to the ground plane of the circuit
board. These ground pins provide shielding, low impedance
return paths and physical separation for the inputs. All of these
help to reduce crosstalk.
Figure 27. Buffering Wired OR Outputs with the AD8079
Evaluation Board
A four-layer evaluation board for the AD8116 is available. This
board has been carefully laid out and tested to demonstrate the
specified high speed performance of the device. Figure 28 shows
the schematic of the evaluation board. Figure 29 shows the
component side silk-screen. The layouts of the board’s four
layers are given in Figures 30, 31, 32 and 33.
Each output is separated from its two neighboring outputs by
analog supply pins of either polarity. Each of these analog sup-
ply pins provides power to the output stages of only the two
adjacent outputs. These supply pins provide shielding, physical
separation and low impedance supply for the channel outputs.
Individual bypassing of each of these supply pins with a
0.01 µF chip capacitor directly to the ground plane minimizes
high frequency output crosstalk via the mechanism of sharing
common impedances.
The evaluation board package includes the following:
• Fully populated board with BNC-type connectors.
• Windows® based software for controlling the board from a
PC via the printer port.
• Custom cable to connect evaluation board to PC.
• Disk containing Gerber files of board layout.
Each output also has an on-chip compensation capacitor that
is individually tied to a package pin via the signals called
AGND00 through AGND15. This technique reduces crosstalk
by preventing the currents that flow in these paths from sharing
a common impedance on the IC and in the package pins. These
AGNDxx signals should all be connected directly to the ground
plane.
Windows is a registered trademark of Microsoft Corporation.
REV. A
–15–
AD8116
+
10F
1
+
+
+
10F
10F
10F
DGND
AGND
6
POWER SUPPLY
CONNECTOR*
0.1F
0.1F
*6-PIN 0.100 CENTER HEADER
MOLEX PART NR. 22-23-2061
MATING CONNECTOR
CLIP-ON TEST POINTS
TO PINS 96,92,88,84 TO PINS 94,90,86,82
MOLEX PART NR. 22-01-03067
0.01F 0.01F
(AVCC)
(AVEE)
0.01F
0.01F
97–104,
128
105–
112
116–
118 120
113–
115
119
126 125 124 123 122 121 127
AV
AV
AV
AV
AV
AV
CC
EE
CC
EE
CC
EE
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
1
2
AGND
AVCC00
OUT00
INPUT 00
75⍀
INPUT 01
75⍀
INPUT 02
75⍀
INPUT 03
75⍀
INPUT 04
75⍀
INPUT 05
75⍀
INPUT 06
75⍀
INPUT 07
75⍀
INPUT 08
75⍀
INPUT 09
75⍀
INPUT 10
75⍀
INPUT 11
75⍀
INPUT 12
75⍀
INPUT 13
75⍀
INPUT 14
75⍀
INPUT 15
75⍀
OUTPUT 00
0.01F
0.01F
0.01F
0.01F
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
IN00
3
4
AVEE00/01
AGND
IN01
OUTPUT 01
OUTPUT 02
OUTPUT 03
OUTPUT 04
OUTPUT 05
OUTPUT 06
OUTPUT 07
OUTPUT 08
OUTPUT 09
OUTPUT 10
OUTPUT 11
OUTPUT 12
OUTPUT 13
OUTPUT 14
OUT01
5
AVCC01/02
AGND
IN02
6
OUT02
7
AVEE02/03
AGND
IN03
8
OUT03
9
AVCC03/04
AGND
IN04
0.01µF
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OUT04
AVEE04/05
AGND
IN05
OUT05
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
CC
EE
CC
EE
CC
EE
CC
EE
CC
EE
AVCC05/06
AGND
IN06
OUT06
AVEE06/07
AGND
IN07
AD8116JST
OUT07
AVCC07/08
AGND
IN08
OUT08
78
77
76
75
74
73
AVEE08/09
AGND
IN09
OUT09
AVCC09/10
AGND
IN10
OUT10
AVEE10/11
AGND
IN11
OUT11
72
71
70
69
68
67
66
65
AVCC11/12
AGND
IN12
OUT12
AVEE12/13
AGND
IN13
OUT13
AVCC13/14
AGND
IN14
OUT14
AVEE14/15
AGND
IN15
OUTPUT 15
TO PINS
OUT15
AVCC
TO PINS
78,74,70,66
(AVEE)
64
49–
55
41
37
38
40
35
36
39
34 42
43–45
0.01
F
46–48
0.01
F
33
CLIP-ON
56–63
80,76,72,68
(AVCC)
0.01
F
TEST POINTS
DIGITAL INTERFACE
CONNECTOR*
0.1F
NC
NC = NO CONNECT
0.1F
NC
AV
EE
AV
CC
NC
AV
CC
6
1
Figure 28. Evaluation Board Schematic
–16–
REV. A
AD8116
Figure 29. Component Side Silkscreen
REV. A
–17–
AD8116
Figure 30. Board Layout (Top Layer)
REV. A
–18–
AD8116
Figure 31. Board Layout (Signal Layer)
REV. A
–19–
AD8116
Figure 32. Board Layout (Power Layer)
REV. A
–20–
AD8116
Figure 33. Board Layout (Bottom Layer)
REV. A
–21–
AD8116
Optimized for video applications, all signal inputs and outputs
are terminated with 75 Ω resistors. Figure 34 shows a cross-
section of one of the input or output tracks along with the ar-
rangement of the PCB layers. It should be noted that unused
regions of the four layers are filled up with ground planes. As a
result, the input and output traces, in addition to having con-
trolled impedances, are well shielded.
The four power supply pins AVCC, DVCC, AVEE and DVEE
should be connected to good quality, low noise, ±5 V supplies.
Where the same ±5 V power supplies are used for analog and
digital, separate cables should be run for the power supply to the
evaluation board’s analog and digital power supply pins.
As can be seen in Figure 35, there is extensive power supply
decoupling on the evaluation board. Figure 35 shows the
location of all the decoupling capacitors relative to the AD8116’s
pins. Four large 10 µF capacitors are located near the evalua-
tion board’s power supply connection terminals. These de-
couple the AVCC, DVCC, AVEE and DVEE supplies. Because
it is required that the voltage difference between DGND and
AGND never exceed 0.7 V, these grounds are connected by
two antiparallel diodes. On the output side of the device (Pin 65
to Pin 96), the sixteen output pins are interleaved with the
AVCC and AVEE power supply pins. Each of these pins is
locally decoupled with a 0.01 µF capacitor. These pins are also
decoupled in groups of four with 0.1 µF capacitors. Due to
space constraints the power supply Pins 34 (DVCC) and 42
(DVEE) are neither connected nor decoupled. These pins are,
however, internally connected to DVCC and DVEE (Pins 127
and 119).
w = 0.008"
(0.2mm)
TOP LAYER
t = 0.00135" (0.0343mm)
b = 0.0132"
(0.335mm)
a = 0.008"
(0.2mm)
SIGNAL LAYER
c = 0.028"
(0.714mm)
POWER LAYER
d = 0.0132"
(0.335mm)
BOTTOM LAYER
Figure 34. Cross Section of Input and Output Traces
The board has 32 BNC type connectors: 16 inputs and 16 outputs.
The connectors are arranged in two crescents around the device.
As can be seen from Figure 31, this results in all sixteen input
signal traces and all sixteen signal output traces having the same
length. This is useful in tests such as All-Hostile Crosstalk
where the phase relationship and delay between signals needs to
be maintained from input to output.
As a general rule, each power supply pin (or group of adjacent
power supply pins) should be locally decoupled with a 0.01 µF
capacitor. If there is a space constraint, it is more important to
decouple analog power supply pins before digital power supply
pins. A 0.1 µF capacitor, located reasonably close to the pins,
can be used to decouple a number of power supply pins. Finally
a 10 µF capacitor should be used to decouple power supplies as
they come on to the board.
REV. A
–22–
AD8116
DVCC
DVEE
AVEE
AVCC
10F
10F
10F
10F
0.1F
128
127
119
113
97
1
96
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0.1F
0.1F
*
0.1F
*
*
65
32
33
34
NC
(DVCC)
42
48
64
NC
*
*
(DVEE)
*
0.01F
NC = NO CONNECT
Figure 35. Detail of Decoupling on Evaluation Board
–23–
REV. A
AD8116
Controlling the Evaluation Board from a PC
can be connected with one or more outputs by simply clicking
on the appropriate radio buttons in the 16 × 16 on-screen array.
Each time a button is clicked on, the software automatically
sends and latches the required 80-bit data stream to the
evaluation board. An output can be turned off by clicking the
appropriate button in the Off column. To turn off all outputs,
click on RESET.
The evaluation board include Windows-based control software
and a custom cable that connects the board’s digital interface
to the printer port of the PC. The wiring of this cable is shown
in Figure 36. The software requires Windows 3.1 or later to
operate. To install the software, insert the disk labeled “Disk #1
of 2” in the PC and run the file called SETUP.EXE. Additional
installation instructions will be given on-screen. Before begin-
ning installation, it is important to terminate any other Win-
dows applications that are running.
The software offers volatile and nonvolatile storage of configu-
rations. For volatile storage, up to two configurations can be
stored and recalled using the Memory 1 and Memory 2 Buffers.
These function in an identical fashion to the memory on a
pocket calculator. For nonvolatile storage of a configuration, the
Save Setup and Load Setup functions can be used. This stores
the configuration as a data file on disk.
MOLEX 0.100" CENTER
D-SUB 25 PIN
(MALE)
CRIMP TERMINAL HOUSING
RESET
1
1
14
CLK
CE
Overshoot on PC Printer Ports’ Data Lines
UPDATE
DATA IN
DGND
The data lines on some printer ports have excessive overshoot.
Overshoot on the pin that is used as the serial clock (Pin 6 on
the D-Sub-25 connector) can cause communication problems.
This overshoot can be eliminated by connecting a capacitor
from the CLK line on the evaluation board to ground. A pad
has been provided on the solder-side of the evaluation board to
allow this capacitor to be soldered into place. Depending upon
the overshoot from the printer port, this capacitor may need to
be as large as 0.01 µF.
6
MOLEX
D-SUB-25
SIGNAL
TERMINAL HOUSING
2
3
4
5
6
25
3
1
4
5
2
6
CE
RESET
UPDATE
25
13
DATA IN
CLK
DGND
EVALUATION BOARD
PC
Figure 36. Evaluation Board-PC Connection Cable
When you launch the crosspoint control software, you will be
asked to select the printer port you are using. Most modern PCs
have only one printer port, usually called LPT1; however, some
laptop computers use the PRN port.
Figure 37 shows the main screen of the control software in its
initial reset state (all outputs off). Using the mouse, any input
REV. A
–24–
AD8116
Figure 37. Screen Display of Control Software
REV. A
–25–
AD8116
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches).
Metric measurements are not rounded. English measurements are rounded.
128-Lead Plastic LQFP
(ST-128A)
0.630 (16.00) BSC
0.063 (1.60)
TYP
0.551 (14.00) BSC
0.488 (12.40) BSC
0.030 (0.75)
0.018 (0.45)
97
96
128
1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
STANDOFF
0.003 (0.08)
MAX
65
64
32
33
0.006 (0.15)
0.002 (0.05)
7°
0°
0.057 (1.45)
0.053 (1.35)
0.016 (0.40)
BSC
0.009 (0.23)
0.005 (0.13)
REV. A
–26–
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