AD8138AR-REEL7 [ADI]
Low Distortion Differential ADC Driver; 低失真差分ADC驱动器
| 型号： | AD8138AR-REEL7 |
| 厂家： | 
ADI |
| 描述： | Low Distortion Differential ADC Driver |
| 文件： | 总14页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Distortion
Differential ADC Driver
a
AD8138
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Easy to Use Single-Ended-to-Differential Conversion
Adjustable Output Common-Mode Voltage
Externally Adjustable Gain
Low Harmonic Distortion
–94 dBc—Second, <–114 dBc—Third @ 5 MHz into
800 ⍀ Load
+IN
NC
1
2
3
4
–IN
8
7
6
5
V
OCM
V+
V–
+OUT
–OUT
–87 dBc—Second, –85 dBc—Third @ 20 MHz into
800 ⍀ Load
AD8138
NC = NO CONNECT
–3 dB Bandwidth of 320 MHz, G = +1
Fast Settling to 0.01% of 16 ns
Slew Rate 1150 V/s
Fast Overdrive Recovery of 4 ns
Low Input Voltage Noise of 5 nV/√Hz
1 mV Typical Offset Voltage
Wide Supply Range +3 V to ؎5 V
Low Power 90 mW on +5 V
TYPICAL APPLICATION CIRCUIT
+5V
+5V
499⍀
0.1 dB Gain Flatness to 40 MHz
Available in 8-Lead SOIC
499⍀
AVDD
DVDD
V
+
IN
AIN
V
OCM
DIGITAL
OUTPUTS
ADC
AD8138
–
APPLICATIONS
ADC Driver
499⍀
AIN
V
AVSS
REF
Single-Ended-to-Differential Converter
IF and Baseband Gain Block
Differential Buffer
499⍀
Line Driver
PRODUCT DESCRIPTION
performance ADCs, preserving the low frequency and dc infor-
mation. The common-mode level of the differential output is
adjustable by a voltage on the VOCM pin, easily level-shifting
the input signals for driving single supply ADCs. Fast overload
recovery preserves sampling accuracy.
AD8138 is a major advancement over op amps for differential
signal processing. The AD8138 can be used as a single-ended-
to-differential amplifier or as a differential-to-differential ampli-
fier. The AD8138 is as easy to use as an op amp, and greatly
simplifies differential signal amplification and driving.
The AD8138 distortion performance makes it an ideal ADC
driver for communication systems, with distortion performance
good enough to drive state-of-the-art 10- to 16-bit converters
at high frequencies. The AD8138’s high bandwidth and IP3
also make it appropriate for use as a gain block in IF and
baseband signal chains. The AD8138 offset and dynamic per-
formance make it well suited for a wide variety of signal pro-
cessing and data acquisition applications.
Manufactured on ADI’s proprietary XFCB bipolar process, the
AD8138 has a –3 dB bandwidth of 320 MHz and delivers a
differential signal with the lowest harmonic distortion available
in a differential amplifier. The AD8138 has a unique internal
feedback feature that provides output gain and phase matching
that are balanced, suppressing even order harmonics. The inter-
nal feedback circuit also minimizes any gain error that would be
associated with the mismatches in the external gain setting
resistors.
The AD8138 is offered in an 8-lead SOIC that operates over
the industrial temperature range of –40°C to +85°C.
The AD8138’s differential output helps balance the input-to-
differential ADCs, maximizing the performance of the ADC.
The AD8138 eliminates the need for a transformer with high
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(@ +25؇C, V = ؎5 V, VOCM = 0, G = +1, RL,dm = 500 ⍀, unless otherwise noted.
Refer to Figure 1 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs unless noted.)
AD8138–SPECIFICATIONS
S
AD8138
Typ
Parameter
Conditions
Min
Max
Units
؎DIN to ؎OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
VOUT = 0.5 V p-p, CF = 0 pF
290
320
225
30
265
1150
16
MHz
MHz
MHz
MHz
V/µs
ns
V
OUT = 0.5 V p-p, CF = 1 pF
VOUT = 0.5 V p-p, CF = 0 pF
OUT = 2 V p-p, CF = 0 pF
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Settling Time
Overdrive Recovery Time
V
VOUT = 2 V p-p, CF = 0 pF
0.01%, VOUT = 2 V p-p, CF = 1 pF
VIN = 5 V to 0 V Step, G = +2
4
ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic
V
OUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL,dm = 800 Ω
OUT = 2 V p-p, 70 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω
OUT = 2 V p-p, 20 MHz, RL,dm = 800 Ω
–94
–87
–62
–114
–85
–57
–77
37
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
V
Third Harmonic
V
VOUT = 2 V p-p, 70 MHz, RL,dm = 800 Ω
20 MHz
20 MHz
f = 100 kHz to 40 MHz
f = 100 kHz to 40 MHz
IMD
IP3
Voltage Noise (RTI)
Input Current Noise
5
2
INPUT CHARACTERISTICS
Offset Voltage
VOS,dm = VOUT,dm/2; VDIN+ = VDIN– = VOCM = 0 V
–2.5
±1
±4
3.5
–0.01
6
3
1
2.5
7
mV
µV/°C
µA
µA/°C
MΩ
MΩ
pF
T
MIN–TMAX Variation
Input Bias Current
Input Resistance
T
MIN–TMAX Variation
Differential
Common Mode
Input Capacitance
Input Common-Mode Voltage
CMRR
–4.7 – +3.4
–75
V
dB
∆VOUT,dm/∆VIN,cm; ∆VIN,cm = ±1 V
–70
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Maximum ∆VOUT; Single-Ended Output
∆VOUT,cm/∆VOUT,dm; ∆VOUT,dm = 1 V
7.75
95
–66
V p-p
mA
dB
Output Balance Error
VOCM to ؎OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Slew Rate
250
330
MHz
V/µs
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
±3.8
200
±1
0.5
–75
1
V
kΩ
mV
µA
dB
V/V
V
OS,cm = VOUT,cm; VDIN+ = VDIN– = VOCM = 0 V
–3.5
3.5
V
OCM CMRR
[∆VOUT,dm/∆VOCM]; ∆VOCM = ±1 V
∆VOUT,cm/∆VOCM; ∆VOCM = ±1 V
Gain
0.9955
1.0045
POWER SUPPLY
Operating Range
Quiescent Current
±1.4
18
±5.5
23
V
20
40
–90
mA
µA/°C
dB
T
MIN to TMAX Variation
Power Supply Rejection Ratio
∆VOUT,dm/∆VS; ∆VS = ±1 V
–70
OPERATING TEMPERATURE RANGE
NOTES
–40
+85
°C
Harmonic Distortion Performance is equal or slightly worse with higher values of RL,dm. See Figures 14 and 15 for more information.
Specifications subject to change without notice.
–2–
REV. A
AD8138
(@ +25؇C, VS = +5 V, VOCM = +2.5 V, G = +1, RL,dm = 500 ⍀, unless otherwise noted. Refer to Figure 1
for test setup and label descriptions. All specifications refer to single-ended input and differential outputs unless noted.)
SPECIFICATIONS
AD8138
Typ
Parameter
Conditions
Min
Max
Units
؎DIN to ؎OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
V
OUT = 0.5 V p-p, CF = 0 pF
VOUT = 0.5 V p-p, CF = 1 pF
OUT = 0.5 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
OUT = 2 V p-p, CF = 0 pF
280
310
225
29
265
950
16
MHz
MHz
MHz
MHz
V/µs
ns
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
V
V
Settling Time
0.01%, VOUT = 2 V p-p, CF = 1 pF
Overdrive Recovery Time
VIN = 2.5 V to 0 V Step, G = +2
4
ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic
V
OUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL,dm = 800 Ω
OUT = 2 V p-p, 70 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω
OUT = 2 V p-p, 20 MHz, RL,dm = 800 Ω
–90
–79
–60
–100
–82
–53
–74
35
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
V
Third Harmonic
V
VOUT = 2 V p-p, 70 MHz, RL,dm = 800 Ω
20 MHz
20 MHz
f = 100 kHz to 40 MHz
f = 100 kHz to 40 MHz
IMD
IP3
Voltage Noise (RTI)
Input Current Noise
5
2
INPUT CHARACTERISTICS
Offset Voltage
V
OS,dm = VOUT,dm/2; VDIN+ = VDIN– = VOCM = 2.5 V –2.5
±1
±4
3.5
–0.01
6
3
1
2.5
7
mV
µV/°C
µA
µA/°C
MΩ
MΩ
pF
TMIN–TMAX Variation
Input Bias Current
Input Resistance
T
MIN–TMAX Variation
Differential
Common Mode
Input Capacitance
Input Common-Mode Voltage
CMRR
–0.3 – +3.2
–75
V
dB
∆VOUT,dm/∆VIN,cm; ∆VIN,cm = 1 V
–70
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Maximum ∆VOUT; Single-Ended Output
∆VOUT,cm/∆VOUT,dm; ∆VOUT,dm = 1 V
2.9
95
–65
V p-p
mA
dB
Output Balance Error
VOCM to ؎OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Slew Rate
220
250
MHz
V/µs
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
+1.0 – +3.8
V
100
±1
0.5
–70
1
kΩ
mV
µA
dB
V/V
VOS,cm = VOUT,cm; VDIN+ = VDIN– = VOCM = 2.5 V
–5
5
V
OCM CMRR
[∆VOUT,dm/∆VOCM]; ∆VOCM = 2.5 ± 1 V
∆VOUT,cm/∆VOCM; ∆VOCM = 2.5 ± 1 V
Gain
0.9968
1.0032
POWER SUPPLY
Operating Range
Quiescent Current
2.7
15
11
21
V
20
40
–90
mA
µA/°C
dB
T
MIN to TMAX Variation
Power Supply Rejection Ratio
∆VOUT,dm/∆VS; ∆VS = ±1 V
–70
OPERATING TEMPERATURE RANGE
NOTES
–40
+85
°C
Harmonic Distortion Performance is equal or slightly worse with higher values of RL,dm. See Figures 14 and 15 for more information.
Specifications subject to change without notice.
REV. A
–3–
AD8138
ABSOLUTE MAXIMUM RATINGS1
PIN FUNCTION DESCRIPTIONS
Pin No. Name Function
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5.5 V
VOCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 550 mW
1
2
–IN
VOCM
Negative Input Summing Node.
2
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
Voltage applied to this pin sets the common-
mode output voltage with a ratio of 1:1. For
example, +1 V dc on VOCM will set the dc
bias level on +OUT and –OUT to +1 V.
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . +300°C
NOTES
3
4
V+
Positive Supply Voltage.
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only, functional operation of the
device at these or any other conditions above listed in the operational section of this
specification is not implied. Exposure to Absolute Maximum Ratings for any
extended periods may affect device reliability.
+OUT Positive Output. Note: the voltage at –DIN is
inverted at +OUT.
5
–OUT Negative Output. Note: the voltage at +DIN
is inverted at –OUT.
2 Thermal resistance measured on SEMI standard 4-layer board.
6
7
8
V–
NC
+IN
Negative Supply Voltage.
No Connect.
Positive Input Summing Node
R
= 499⍀
F
R
= 499⍀
= 499⍀
G
49.9⍀
R
= 499⍀
AD8138
L,dm
R
PIN CONFIGURATION
G
24.9⍀
R
= 499⍀
F
+IN
NC
1
2
3
4
–IN
8
7
6
5
V
OCM
Figure 1. Basic Test Circuit
V+
V–
+OUT
–OUT
AD8138
NC = NO CONNECT
ORDERING GUIDE
Model
Temperature Range
Package Descriptions
Package Options
AD8138AR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
SO-8
SO-8
SO-8
AD8138AR-REEL1
AD8138AR-REEL72
AD8138-EVAL
13" Tape and Reel
7" Tape and Reel
Evaluation Board
NOTES
113" Reels of 2500 each.
27" Reels of 750 each.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8138 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
Typical Performance Characteristics–AD8138
Unless otherwise noted, GAIN = 1, RG = RF = RL,dm = 499 ⍀, TA = +25؇C; Refer to Figure 1 for test setup.
6
6
0.5
V
C
= 0.2V p-p
= 0pF
V
V
= ؎5V
= 0.2V p-p
V
V
= ؎5V
= 0.2V p-p
IN
S
S
F
IN
IN
3
3
0.3
0.1
C
= 0pF
F
V
= +5V
C = 0pF
F
S
0
0
V
= ؎5V
S
C
= 1pF
F
–3
–6
–9
–3
–6
–9
–0.1
–0.3
–0.5
C
= 1pF
F
10
100
1000
10
100
1000
10
FREQUENCY – MHz
100
1
1
1
FREQUENCY – MHz
FREQUENCY – MHz
Figure 2. Small Signal Frequency
Response
Figure 3. Small Signal Frequency
Response
Figure 4. 0.1 dB Flatness vs.
Frequency
30
20
10
6
6
V
= ؎5V
S
V
V
= 2V p-p
= ؎5V
V
C
= 2V p-p
= 0pF
IN
S
IN
C
V
= 0pF
F
F
= 0.2V p-p
,dm
OUT
G = 10, R = 4.99k⍀
3
0
3
0
F
R
= 499⍀
V
= +5V
G
S
C
= 0pF
F
G = 5, R = 2.49k⍀
F
V
S
= ؎5V
G = 2, R = 1k⍀
C
= 1pF
F
F
–3
–6
–9
–3
–6
–9
G = 1, R = 499⍀
F
0
–10
10
100
1000
10
100
1000
10
100
1000
1
1
1
FREQUENCY – MHz
FREQUENCY – MHz
FREQUENCY – MHz
Figure 5. Large Signal Frequency
Response
Figure 6. Large Signal Frequency
Response
Figure 7. Small Signal Frequency
Response for Various Gains
–50
–30
–40
V
= 2V p-p
V
= 2V p-p
,dm
V
= 4V p-p
,dm
,dm
OUT
OUT
OUT
R
= 800⍀
R
= 800⍀
R
= 800⍀
L
L
L
–50
–60
–60
–70
–80
–90
–40
–50
–60
–70
–80
–90
–100
F
= 20MHz
O
HD3(V = +5V)
S
HD2(V = +5V)
HD2(V = +5)
S
S
–70
HD2(V = ؎5V)
HD3(V = +5)
S
S
HD2(V = +5V)
S
–80
HD2(V = ؎5V)
S
–90
–100
–110
–120
HD3(V = ؎5)
S
HD3(V = +5V)
S
–100
–110
HD2(V = ؎5)
HD3(V = ؎5V)
HD3(V = ؎5V)
S
S
S
0
10
20
30
40
50
60
70
–4
–3
–2
V
–1
0
1
2
3
4
0
10
20
30
40
50
60
70
FUNDAMENTAL FREQUENCY – MHz
DC OUTPUT – Volts
FUNDAMENTAL FREQUENCY – MHz
OCM
Figure 8. Harmonic Distortion vs.
Frequency
Figure 9. Harmonic Distortion vs.
Frequency
Figure 10. Harmonic Distortion vs.
VOCM
REV. A
–5–
AD8138
–60
–60
–70
–80
–90
–60
–70
V
= +3V
V
= +5V
V
= ؎5V
S
S
S
R
= 800⍀
R
= 800⍀
R
= 800⍀
HD3(F = 20MHz)
L
L
L
–70
–80
HD3(F = 20MHz)
HD2(F = 20MHz)
HD2(F = 20MHz)
HD3(F = 20MHz)
HD2(F = 20MHz)
–80
–90
–90
HD2(F = 5MHz)
HD3(F = 5MHz)
HD2(F = 5MHz)
HD2(F = 5MHz)
–100
–100
HD3(F = 5MHz)
–100
–110
HD3(F = 5MHz)
–110
–120
–110
–120
0
1
2
3
4
5
6
0
1
2
3
4
0.25 0.50
0.75 1.00
1.25 1.50
1.75
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
Figure 11. Harmonic Distortion vs.
Differential Output Voltage
Figure 12. Harmonic Distortion vs.
Differential Output Voltage
Figure 13. Harmonic Distortion vs.
Differential Output Voltage
10
–60
–60
V
V
= ؎5V
F
= 50MHz
C
V
V
= +5V
S
S
= 2V p-p
V
= ؎5V
,dm
= 2V p-p
OUT
S
,dm
OUT
–10
–30
–50
–70
–70
–70
–80
–90
HD2(F = 20MHz)
HD3(F = 20MHz)
HD2(F = 20MHz)
HD3(F = 20MHz)
–80
–90
HD2(F = 5MHz)
HD3(F = 5MHz)
–100
HD2(F = 5MHz)
–100
–110
–90
–110
–120
HD3(F = 5MHz)
–110
49.5
49.7
49.9
50.1
50.3
50.5
200
600
1000
R
1400
– ⍀
1800
200
600
1000
R
1400
– ⍀
1800
FREQUENCY – MHz
LOAD
LOAD
Figure 14. Harmonic Distortion vs.
RLOAD
Figure 15. Harmonic Distortion vs.
RLOAD
Figure 16. Intermodulation
Distortion
45
V
V
= 0.2V p-p
V
= ؎5V
S
OUT,dm
= ؎5V
R
= 800⍀
L
C
= 0pF
F
S
V
OUT,dm
40
C
= 1pF
V
F
OUT–
V
= +5V
S
35
30
25
V
OUT+
V
= ؎5V
S
V
+DIN
1V
5ns
40mV
5ns
0
20
40
60
80
FREQUENCY – MHz
Figure 17. Third Order Intercept vs.
Frequency
Figure 18. Large Signal Transient
Response
Figure 19. Small Signal Transient
Response
–6–
REV. A
AD8138
V
= 2V p-p
C
= 0pF
V
V
= 2V p-p
V
C
= ؎5V
= 1pF
V
= ؎5V
200V
OUT,dm
F
OUT,dm
= ؎5V
S
F
S
C
= 0pF
F
S
V
OUT,dm
V
= +5V
S
C
= 1pF
F
V
+DIN
400mV
5ns
400mV
1V
5ns
4ns
Figure 20. Large Signal Transient
Response
Figure 21. Large Signal Transient
Response
Figure 22. Settling Time
V
C
= ؎5V
= 0pF
S
F
C
= 10pF
L
C
= 5pF
V
L
OUT,dm
499⍀
C
= 20pF
L
V
= ؎5V
S
499⍀
499⍀
24.9⍀
24.9⍀
F = 20MHz
= 8V p-p
V
+DIN
49.9⍀
C
453⍀
AD8138
L
G = 3(R = 1500)
F
24.9⍀
499⍀
V
+DIN
4V
400mV
30ns
2.5ns
Figure 23. Output Overdrive
Figure 24. Test Circuit for Cap Load
Drive
Figure 25. Large Signal Transient
Response for Various Cap Loads
–20
–30
–20
V
= 2V p-p
V
= ؎5V
IN
S
⌬V
/⌬V
IN,
OUT,dm
cm
–30
–40
–50
–60
–70
–40
–50
–60
–70
–80
499⍀
499⍀
499⍀
249⍀
249⍀
V
= ؎5V
S
49.9⍀
AD8138
24.9⍀
499⍀
V
= +5V
S
1
10
100
1k
1
10
100
1k
FREQUENCY – MHz
FREQUENCY – MHz
Figure 26. CMRR vs. Frequency
Figure 27. Test Circuit for Output
Balance
Figure 28. Output Balance Error vs.
Frequency
REV. A
–7–
AD8138
100
–10
5.0
2.5
0
⌬V
/⌬V
S
OUT,dm
SINGLE-ENDED OUTPUT
–20
–PSRR
(V = ؎5V)
–30
–40
–50
S
10
1
V
= ؎5V
S
V
= +5
S
V
= +5V
S
–60
–70
–80
–90
V
= +3V
S
+PSRR
(V = +5V, 0V AND ؎5V)
–2.5
–5.0
S
V
= ؎5V
S
0.1
40
TEMPERATURE – ؇C
–40 –20
0
20
60
80
100
1
10
100
1k
1
10
FREQUENCY – MHz
100
FREQUENCY – MHz
Figure 29. PSRR vs. Frequency
Figure 30. Output Impedance vs.
Frequency
Figure 31. Output Referred Differen-
tial Offset Voltage vs. Temperature
5
4
30
25
6
V
= +5V
S
V
= ؎5V
S
3
0
V
= ؎5V
S
V
= ؎5V, +5V
S
20
15
10
5
3
V
= +5V
S
–3
–6
–9
V
= +3V
S
V
= +3V
S
2
1
40
TEMPERATURE – ؇C
40
TEMPERATURE – ؇C
–40 –20
0
20
60
80
100
–40 –20
0
20
60
80
100
10
100
1
1k
FREQUENCY – MHz
Figure 32. Input Bias Current vs.
Temperature
Figure 33. Supply Current vs.
Temperature
Figure 34. VOCM Frequency Response
V
= ؎5V
= –1V TO +1V
S
V
OCM
V
OUT,cm
400mV
5ns
Figure 35. VOCM Transient Response
–8–
REV. A
AD8138
OPERATIONAL DESCRIPTION
Definition of Terms
circuit. Excellent performance over a wide frequency range has
proven difficult with this approach.
C
F
The AD8138 uses two feedback loops to separately control the
differential and common-mode output voltages. The differential
feedback, set with external resistors, controls only the differen-
tial output voltage. The common-mode feedback controls only
the common-mode output voltage. This architecture makes it
easy to arbitrarily set the output common-mode level. It is forced,
by internal common-mode feedback, to be equal to the voltage
applied to the VOCM input, without affecting the differential
output voltage.
R
F
R
+IN
–IN
G
G
–OUT
+D
IN
V
V
R
L,dm
AD8138
,dm
OUT
OCM
–D
IN
+OUT
R
R
C
F
F
The AD8138 architecture results in outputs that are very highly
balanced over a wide frequency range without requiring tightly
matched external components. The common-mode feedback
loop forces the signal component of the output common-mode
voltage to be zeroed. The result is nearly perfectly balanced
differential outputs, of identical amplitude and exactly 180
degrees apart in phase.
Figure 36. Circuit Definitions
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently output differential-mode voltage) is defined as:
VOUT,dm = (V+OUT – V–OUT
)
Analyzing an Application Circuit
V+OUT and V–OUT refer to the voltages at the +OUT and –OUT
The AD8138 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and –IN in Figure
36. For most purposes, this voltage can be assumed to be zero.
Similarly, the difference between the actual output common-
mode voltage and the voltage applied to VOCM can also be as-
sumed to be zero. Starting from these two assumptions, any
application circuit can be analyzed.
terminals with respect to a common reference.
Common-mode voltage refers to the average of two node volt-
ages. The output common-mode voltage is defined as:
VOUT,cm = (V+OUT + V–OUT)/2
Balance is a measure of how well differential signals are matched
in amplitude and exactly 180 degrees apart in phase. Balance is
most easily determined by placing a well-matched resistor di-
vider between the differential voltage nodes and comparing the
magnitude of the signal at the divider’s midpoint with the mag-
nitude of the differential signal. (See Figure 27.) By this definition,
output balance is the magnitude of the output common-mode
voltage divided by the magnitude of the output differential-
mode voltage:
Setting the Closed Loop Gain
Neglecting the capacitors CF, the differential mode gain of the
circuit in Figure 36 can be determined to be described by the
following equation:
S
VOUT,dm
VIN,dm
RF
RG
VOUT,cm
=
Output Balance Error =
S
VOUT,dm
This assumes the input resistors, RGS and feedback resistors,
RFS on each side are equal.
THEORY OF OPERATION
The AD8138 differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions. Like an
op amp, it relies on high open loop gain and negative feedback
to force these outputs to the desired voltages. The AD8138 be-
haves much like a standard voltage feedback op amp and makes
it easy to perform single-ended-to-differential conversion,
common-mode level-shifting, and amplification of differential
signals. Also like an op amp, the AD8138 has high input imped-
ance and low output impedance.
Estimating the Output Noise Voltage
Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input referred terms, at +IN and –IN, by the
circuit noise gain. The noise gain is defined as:
RF
GN = 1 +
RG
Previous differential drivers, both discrete and integrated de-
signs, have been based on using two independent amplifiers,
and two independent feedback loops, one to control each of the
outputs. When these circuits are driven from a single-ended
source, the resulting outputs are typically not well balanced.
Achieving a balanced output has typically required exceptional
matching of the amplifiers and feedback networks.
To compute the total output referred noise for the circuit of
Figure 36, consideration must also be given to the contribution
of the resistors RF and RG. Refer to Table I for estimated output
noise voltage densities at various closed-loop gains.
Table I
RG RF
Bandwidth Output Noise Output Noise
Gain (⍀) (⍀)
–3 dB
8138 Only
8138 + RG, RF
DC common-mode level-shifting has also been difficult with
previous differential drivers. Level-shifting has required the use
of a third amplifier and feedback loop to control the output
common-mode level. Sometimes the third amplifier has also
been used to attempt to correct an inherently unbalanced
1
499 499
320 MHz
10 nV/√Hz
15 nV/√Hz
30 nV/√Hz
55 nV/√Hz
11.5 nV/√Hz
16.6 nV/√Hz
31.6 nV/√Hz
56.6 nV/√Hz
2
5
10
499 1.0 k 180 MHz
499 2.49 k 70 MHz
499 4.99 k 30 MHz
REV. A
–9–
AD8138
The Impact of Mismatches in the Feedback Networks
As mentioned previously, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop will still force the outputs to remain balanced. The ampli-
tudes of the signals at each output will remain equal and 180
degrees out of phase. The input-to-output differential-mode
gain will vary proportionately to the feedback mismatch, but the
output balance will be unaffected.
Setting the Output Common-Mode Voltage
The AD8138’s VOCM pin is internally biased at a voltage ap-
proximately equal to the midsupply point (average value of the
voltages on V+ and V–). Relying on this internal bias will result
in an output common-mode voltage that is within about 100 mV
of the expected value.
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source, or resistor divider (made up of 10 kΩ resistors), be used.
The output common-mode offset specified on pages 2 and 3
assume the VOCM input is driven by a low impedance voltage
source.
Ratio matching errors in the external resistors will result in a
degradation of the circuit’s ability to reject input common-mode
signals, much the same as for a four-resistor difference amplifier
made from a conventional op amp.
Also, if the dc levels of the input and output common-mode
voltages are different, matching errors will result in a small
differential-mode output offset voltage. For G = 1 case, with a
ground referenced input signal and the output common-mode
level set for 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% toler-
ance resistors are used. Resistors of 1% tolerance will result in a
worst case input CMRR of about 40 dB, worst case differential
mode output offset of 25 mV due to 2.5 V level-shift, and no
significant degradation in output balance error.
Driving a Capacitive Load
A purely capacitive load can react with the pin and bondwire
inductance of the AD8138 resulting in high frequency ringing in
the pulse response. One way to minimize this effect is to place a
small capacitor across each of the feedback resistors. The added
capacitance should be small to avoid destabilizing the amplifier.
An alternative technique is to place a small resistor in series with
the amplifier’s outputs as shown in Figure 24.
LAYOUT, GROUNDING AND BYPASSING
As a high speed part, the AD8138 is sensitive to the PCB envi-
ronment in which it has to operate. Realizing its superior specifi-
cations requires attention to various details of good high speed
PCB design.
Calculating an Application Circuit’s Input Impedance
The effective input impedance of a circuit such as that in Figure
36, at +DIN and –DIN, will depend on whether the amplifier is
being driven by a single-ended or differential signal source. For
balanced differential input signals, the input impedance (RIN,dm)
between the inputs (+DIN and –DIN) is simply:
The first requirement is for a good solid ground plane that cov-
ers as much of the board area around the AD8138 as possible.
The only exception to this is that the two input pins (Pins 1 and
8) should be kept a few mm from the ground plane, and ground
should be removed from inner layers and the opposite side of
the board under the input pins. This will minimize the stray
capacitance on these nodes and help preserve the gain flatness
vs. frequency.
R
IN,dm = 2 × RG
In the case of a single-ended input signal, (for example if –DIN is
grounded and the input signal is applied to +DIN), the input
impedance becomes:
The power supply pins should be bypassed as close as possible
to the device to the nearby ground plane. Good high frequency
ceramic chip capacitors should be used. This bypassing should
be done with a capacitance value of 0.01 µF to 0.1 µF for each
supply. Further away, low frequency bypassing should be pro-
vided with 10 µF tantalum capacitors from each supply to
ground.
RG
RF
RIN,dm
=
1 −
2 × RG + RF
(
)
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
The signal routing should be short and direct in order to avoid
parasitic effects. Wherever there are complementary signals, a
symmetrical layout should be provided to the extent possible to
maximize the balance performance. When running differential
signals over a long distance, the traces on PCB should be close
together or any differential wiring should be twisted together to
minimize the area of the loop that is formed. This will reduce
the radiated energy and make the circuit less susceptible to
interference.
Input Common-Mode Voltage Range in Single Supply
Applications
The AD8138 is optimized for level-shifting “ground” referenced
input signals. For a single-ended input this would imply, for
example, that the voltage at –DIN in Figure 1 would be zero
volts when the amplifier’s negative power supply voltage (at V–)
was also set to zero volts.
–10–
REV. A
AD8138
BALANCED TRANSFORMER DRIVER
SIGNAL WILL BE COUPLED
ON THIS SIDE VIA C
STRAY
Transformers are among the oldest devices that have been used
to perform a single-ended-to-differential conversion (and vice
versa). Transformers also can perform the additional functions
of galvanic isolation, step-up or step-down of voltages and im-
pedance transformation. For these reasons, transformers will
always find uses in certain applications.
C
STRAY
500⍀
V
UNBAL
0.005%
PRIMARY
SECONDARY V
52.3⍀
DIFF
500⍀
0.005%
C
STRAY
However, when driving a transformer single-endedly and then
looking at its output, there is a fundamental imbalance due to
the parasitics inherent in the transformer. The primary (or
driven) side of the transformer has one side at dc potential (usu-
ally ground), while the other side is driven. This can cause prob-
lems in systems that require good balance of the transformer’s
differential output signals.
NO SIGNAL IS COUPLED
ON THIS SIDE
Figure 37. Transformer Single-Ended-to-Differential Con-
verter Is Inherently Imbalanced
499⍀
If the interwinding capacitance (CSTRAY) is assumed to be uni-
formly distributed, a signal from the driving source will couple
to the secondary output terminal that is closest to the primary’s
driven side. On the other hand, no signal will be coupled to the
opposite terminal of the secondary, because its nearest primary
terminal is not driven. (See Figure 37.) The exact amount of
this imbalance will depend on the particular parasitics of the
transformer, but will mostly be a problem at higher frequencies.
C
STRAY
49.9⍀
499⍀
+IN
–IN
500⍀
0.005%
OUT–
V
UNBAL
AD8138
V
DIFF
499⍀
500⍀
0.005%
OUT+
49.9⍀
C
STRAY
499⍀
The balance of a differential circuit can be measured by con-
necting an equal-valued resistive voltage divider across the dif-
ferential outputs and then measuring the center point of the
circuit with respect ground. Since the two differential outputs
are supposed to be of equal amplitude, but 180 degrees opposite
phase, there should be no signal present for perfectly balanced
outputs.
Figure 38. AD8138 Forms a Balanced Transformer Driver
0
The circuit in Figure 37 shows a Minicircuits T1-6T trans-
former connected with its primary driven single-endedly and the
secondary connected with a precision voltage divider across its
terminals. The voltage divider is made up of two 500 Ω, 0.005%
precision resistors. The voltage VUNBAL, which is also equal to
the ac common-mode voltage, is a measure of how closely the
outputs are balanced.
–20
V
, FOR TRANSFORMER
UNBAL
–40
–60
WITH SINGLE-ENDED DRIVE
The plots in Figure 39 show a comparison between the case
where the transformer is driven single-endedly by a signal gen-
erator and driven differentially using an AD8138. The top signal
trace of Figure 39 shows the balance of the single-ended con-
figuration, while the bottom shows the differentially driven
balance response. The 100 MHz balance is 35 dB better when
using the AD8138.
–80
V
, DIFFERENTIAL DRIVE
UNBAL
–100
0.3
1
10
100
500
FREQUENCY – MHz
Figure 39. Output Balance Error for Circuits of Figures 37
and 38
The well-balanced outputs of the AD8138 will provide a drive
signal to each of the transformer’s primary inputs that are of
equal amplitude and 180 degrees out of phase. Thus, depending
on how the polarity of the secondary is connected, the signals
that conduct across the interwinding capacitance will either both
assist the transformer’s secondary signal equally, or both buck
the secondary signals. In either case, the parasitic effect will be
symmetrical and provide a well-balanced transformer output.
(See Figure 39.)
REV. A
–11–
AD8138
HIGH PERFORMANCE ADC DRIVING
The signal generator has a ground-referenced, bipolar output,
i.e., it drives symmetrically above and below ground. Connect-
ing VOCM to the CML pin of the AD9224 sets the output com-
mon- mode of the AD8138 at 2.5 V, which is the midsupply
level for the AD9224. This voltage is bypassed by a 0.1 µF
capacitor.
The circuit in Figure 40 shows a simplified front-end connec-
tion for an AD8138 driving an AD9224, a 12-bit, 40 MSPS
A/D converter. The A/D works best when driven differentially,
which minimizes its distortion as described in its data sheet.
The AD8138 eliminates the need for a transformer to drive the
ADC and performs single-ended-to-differential conversion,
common-mode level-shifting and buffering of the driving signal.
The full-scale analog input range of the AD9224 is set to 4 V p-p,
by shorting the SENSE terminal to AVSS. This has been deter-
mined to be the scaling to provide minimum harmonic distortion.
The positive and negative outputs of the AD8138 are connected
to the respective differential inputs of the AD9224 via a pair of
49.9 Ω resistors to minimize the effects of the switched-capaci-
tor front-end of the AD9224. For best distortion performance it
is run from supplies of ±5 V.
For the AD8138 to swing a 4 V p-p, each output swings 2 V p-p,
while providing signals that are 180 degrees out of phase. With a
common-mode voltage at the output of 2.5 V, this means that
each AD8138 output will swing between 1.5 V and 3.5 V
The AD8138 is configured with unity gain for a single-ended
input-to-differential output. The additional 23 Ω, 523 Ω total,
at the input to –IN is to balance the parallel impedance of the
50 source and its 50 Ω termination that drives the noninverting
input.
A ground-referenced 4 V p-p, 5 MHz signal at DIN+ was used
to test the circuit in Figure 40. When the combined-device
circuit was run with a sampling rate of 20 MHz MSPS, the
SFDR (spurious free dynamic range) was measured at –85 dBc.
+5V
+5V
0.1pF
0.1pF
499⍀
49.9⍀
49.9⍀
499⍀
AVDD DRVDD
+
VINB
DIGITAL
OUTPUTS
V
OCM
AD9224
500⍀
SOURCE
49.9⍀
AD8138
523⍀
VINA
AVSS SENSE CML DRVSS
0.1pF
499⍀
–5V
Figure 40. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS A/D Converter
–12–
REV. A
AD8138
+3V
3 V OPERATION
+3V
The circuit in Figure 41 shows a simplified front end connection
for an AD8138 driving an AD9203, a 10-bit, 40 MSPS A/D
converter that is specified to work on a single +3 V supply. The
A/D works best when driven differentially to make the best use
of the signal swing available within the 3 V supply. The appro-
priate outputs of the AD8138 are connected to the appropriate
differential inputs of the AD9203 via a low-pass filter.
0.1F
0.1F
499⍀
0.1F
10k⍀
499⍀
49.9⍀
AVDD DRVDD
AINN
+
20pF
DIGITAL
OUTPUTS
49.9⍀
AD9203
AD8138
AINP
AVSS DRVSS
523⍀
49.9⍀
20pF
0.1F
10k⍀
The AD8138 is configured for unity gain for a single-ended
input-to-differential output. The additional 23 Ω at the input to
–IN is to balance the impedance of the 50 Ω source and its 50 Ω
termination that drives the noninverting input.
499⍀
Figure 41. AD8138 Driving an AD9203, a 10-Bit, 40 MSPS
A/D Converter
The signal generator has ground-referenced, bipolar output, i.e.,
it can drive symmetrically above and below ground. Even
though the AD8138 has ground as its negative supply, it can
still function as a level-shifter with such an input signal.
–40
–45
–50
The output common-mode is raised up to midsupply by the
voltage divider that biases VOCM. In this way, the AD8138 pro-
vides dc-coupling and level-shifting of a bipolar signal, without
inverting the input signal.
–55
AD8138-2V
–60
The low-pass filter between the AD8138 and the AD9203 pro-
vides filtering that helps to improve the signal-to-noise ratio.
Lower noise can be realized by lowering the pole frequency, but
the bandwidth of the circuit will be lowered.
–65
AD8138-1V
–70
–75
–80
The circuit was tested with a –0.5 dBFS signal at various fre-
quencies. Figure 42 shows a plot of the total harmonic distor-
tion (THD) vs. frequency at signal amplitudes of 1 V and 2 V
differential drive levels.
0
5
10
15
20
25
FREQUENCY – MHz
Figure 43 shows the signal to noise plus distortion (SINAD)
under the same conditions as above. For the smaller signal
swing, the AD8138 performance is quite good, but its perfor-
mance degrades when trying to swing too close to the supply
rails.
Figure 42. AD9203 THD @ –0.5 dBFS AD8138
65
63
61
59
57
AD8138-1V
55
AD8138-2V
53
51
49
47
45
0
5
10
15
20
25
FREQUENCY – MHz
Figure 43. AD9203 SINAD @ –0.5 dBFS AD8138
REV. A
–13–
AD8138
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
–14–
REV. A
相关型号：
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