AD8138ARM-REEL7 [ADI]
Low Distortion Differential ADC Driver; 低失真差分ADC驱动器
| 型号： | AD8138ARM-REEL7 |
| 厂家： | 
ADI |
| 描述： | Low Distortion Differential ADC Driver |
| 文件： | 总16页 (文件大小：535K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Distortion
Differential ADC Driver
AD8138
FEATURES
PIN CONFIGURATION
Easy to Use Single-Ended-to-Differential Conversion
Adjustable Output Common-Mode Voltage
Externally Adjustable Gain
Low Harmonic Distortion
–94 dBc—Second, –114 dBc—Third @ 5 MHz into
800 ⍀ Load
+IN
NC
–IN
1
2
3
4
8
7
6
5
V
OCM
V+
V–
+OUT
–OUT
–87 dBc—Second, –85 dBc—Third @ 20 MHz into
800 ⍀ Load
AD8138
NC = NO CONNECT
–3 dB Bandwidth of 320 MHz, G = +1
Fast Settling to 0.01% of 16 ns
Slew Rate 1150 V/s
TYPICAL APPLICATION CIRCUIT
Fast Overdrive Recovery of 4 ns
+5V
+5V
Low Input Voltage Noise of 5 nV/
1 mV Typical Offset Voltage
Wide Supply Range +3 V to ؎5 V
Low Power 90 mW on 5 V
0.1 dB Gain Flatness to 40 MHz
Available in 8-Lead SOIC and MSOP Packages
÷Hz
499⍀
499⍀
AVDD
DVDD
V
+
IN
AIN
V
OCM
DIGITAL
OUTPUTS
ADC
AD8138
499⍀
AIN
–
V
AVSS
REF
499⍀
APPLICATIONS
ADC Driver
Single-Ended-to-Differential Converter
IF and Baseband Gain Block
Differential Buffer
Line Driver
PRODUCT DESCRIPTION
The AD8138 eliminates the need for a transformer with high
performance ADCs, preserving the low frequency and dc infor-
mation. The common-mode level of the differential output is
adjustable by a voltage on the VOCM pin, easily level-shifting the
input signals for driving single-supply ADCs. Fast overload
recovery preserves sampling accuracy.
The AD8138 is a major advancement over op amps for differential
signal processing. The AD8138 can be used as a single-ended-
to-differential amplifier or as a differential-to-differential
amplifier. The AD8138 is as easy to use as an op amp, and
greatly simplifies differential signal amplification and driving.
Manufactured on ADI’s proprietary XFCB bipolar process, the
AD8138 has a –3 dB bandwidth of 320 MHz and delivers a
differential signal with the lowest harmonic distortion available
in a differential amplifier. The AD8138 has a unique internal
feedback feature that provides balanced output gain and phase
matching, suppressing even order harmonics. The internal feed-
back circuit also minimizes any gain error that would be associated
with the mismatches in the external gain setting resistors.
The AD8138 distortion performance makes it an ideal ADC driver
for communication systems, with distortion performance good
enough to drive state-of-the-art 10-bit to 16-bit converters at
high frequencies. The AD8138’s high bandwidth and IP3 also
make it appropriate for use as a gain block in IF and baseband
signal chains. The AD8138 offset and dynamic performance
make it well suited for a wide variety of signal processing and
data acquisition applications.
The AD8138’s differential output helps balance the input-to-
differential ADCs, maximizing the performance of the ADC.
The AD8138 is available in both SOIC and MSOP packages for
operation over –40∞C to +85∞C temperatures.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(@ 25؇C, V = ؎5 V, VOCM = 0, G = +1, RL,dm = 500 ⍀, unless otherwise noted. Refer
to Figure 1 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs unless otherwise noted.)
AD8138–SPECIFICATIONS
S
Parameter
Conditions
Min
Typ
Max
Unit
؎DIN to ؎OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
V
OUT = 0.5 V p-p, CF = 0 pF
290
320
225
30
265
1150
16
MHz
MHz
MHz
MHz
V/ms
ns
VOUT = 0.5 V p-p, CF = 1 pF
VOUT = 0.5 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
0.01%, VOUT = 2 V p-p, CF = 1 pF
VIN = 5 V to 0 V Step, G = +2
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Settling Time
Overdrive Recovery Time
4
ns
NOISE/HARMONIC PERFORMANCE*
Second Harmonic
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 W
VOUT = 2 V p-p, 20 MHz, RL,dm = 800 W
VOUT = 2 V p-p, 70 MHz, RL,dm = 800 W
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 W
VOUT = 2 V p-p, 20 MHz, RL,dm = 800 W
VOUT = 2 V p-p, 70 MHz, RL,dm = 800 W
20 MHz
20 MHz
f = 100 kHz to 40 MHz
f = 100 kHz to 40 MHz
–94
–87
–62
–114
–85
–57
–77
37
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/÷Hz
pA/÷Hz
Third Harmonic
IMD
IP3
Voltage Noise (RTI)
Input Current Noise
5
2
INPUT CHARACTERISTICS
Offset Voltage
VOS,dm = VOUT,dm/2; VDIN+ = VDIN– = VOCM = 0 V
TMIN to TMAX Variation
–2.5
±1
+2.5
7
mV
mV/∞C
mA
mA/∞C
MW
MW
pF
±4
Input Bias Current
Input Resistance
3.5
–0.01
6
3
TMIN to TMAX Variation
Differential
Common Mode
Input Capacitance
Input Common-Mode Voltage
CMRR
1
–4.7 to +3.4
–77
V
dB
DVOUT,dm/DVIN,cm; DVIN,cm = ±1 V
–70
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Maximum DVOUT; Single-Ended Output
DVOUT,cm/DVOUT,dm; DVOUT,dm = 1 V
7.75
95
–66
V p-p
mA
dB
Output Balance Error
VOCM to ؎OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Slew Rate
250
330
MHz
V/ms
NPUT VOLTAGE NOISE (RTI)
f = 0.1 MHz to 100 MHz
17
nV/÷Hz
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
±3.8
200
±1
0.5
–75
1
V
kW
mV
mA
dB
V/V
VOS,cm = VOUT,cm; VDIN+ = VDIN– = VOCM = 0 V
–3.5
+3.5
DVOUT,dm/DVOCM; DVOCM = ±1 V
DVOUT,cm/DVOCM; DVOCM = ±1 V
Gain
0.9955
1.0045
POWER SUPPLY
Operating Range
Quiescent Current
±1.4
18
±5.5
V
20
40
–90
23
mA
mA/∞C
dB
TMIN to TMAX Variation
DVOUT,dm/DVS; DVS = ±1 V
Power Supply Rejection Ratio
–70
OPERATING TEMPERATURE RANGE
–40
+85
∞C
*Harmonic Distortion Performance is equal or slightly worse with higher values of RL,dm. See TPCs 13 and 14 for more information.
Specifications subject to change without notice.
–2–
REV. E
AD8138
(@ 25؇C, VS = 5 V, VOCM = 2.5 V, G = +1, RL,dm = 500 ⍀, unless otherwise noted. Refer to Figure 1 for test
setup and label descriptions. All specifications refer to single-ended input and differential output, unless
otherwise noted.)
SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
؎
DIN to ؎OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
VOUT = 0.5 V p-p, CF = 0 pF
VOUT = 0.5 V p-p, CF = 1 pF
VOUT = 0.5 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
0.01%, VOUT = 2 V p-p, CF = 1 pF
VIN = 2.5 V to 0 V Step, G = +2
280
310
225
29
265
950
16
MHz
MHz
MHz
MHz
V/ms
ns
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Settling Time
Overdrive Recovery Time
4
ns
NOISE/HARMONIC PERFORMANCE*
Second Harmonic
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 W
VOUT = 2 V p-p, 20 MHz, RL,dm = 800 W
VOUT = 2 V p-p, 70 MHz, RL,dm = 800 W
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 W
VOUT = 2 V p-p, 20 MHz, RL,dm = 800 W
VOUT = 2 V p-p, 70 MHz, RL,dm = 800 W
20 MHz
20 MHz
f = 100 kHz to 40 MHz
f = 100 kHz to 40 MHz
–90
–79
–60
–100
–82
–53
–74
35
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/÷Hz
pA/÷Hz
Third Harmonic
IMD
IP3
Voltage Noise (RTI)
Input Current Noise
5
2
INPUT CHARACTERISTICS
Offset Voltage
VOS,dm = VOUT,dm/2; VDIN+ = VDIN– = VOCM = 0 V
TMIN to TMAX Variation
–2.5
±1
+2.5
7
mV
mV/∞C
mA
mA/∞C
MW
MW
pF
±4
Input Bias Current
Input Resistance
3.5
–0.01
6
3
TMIN to TMAX Variation
Differential
Common Mode
Input Capacitance
Input Common-Mode Voltage
CMRR
1
0.3 to 3.2
–77
V
dB
⌬VOUT,dm/⌬VIN,cm; ⌬VIN,cm = 1 V
–70
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Maximum ⌬VOUT; Single-Ended Output
⌬VOUT,cm/⌬VOUT,dm; ⌬VOUT,dm = 1 V
2.9
95
–65
V p-p
mA
dB
Output Balance Error
VOCM to
؎OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Slew Rate
220
250
MHz
V/ms
INPUT VOLTAGE NOISE (RTI)
f = 0.1 MHz to 100 MHz
17
nV/÷Hz
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
1.0 to 3.8
V
100
±1
0.5
–70
1
kW
mV
mA
dB
VOS,cm = VOUT,cm; VDIN+ = VDIN– = VOCM = 0 V
–5
+5
⌬VOUT,dm/⌬VOCM; ⌬VOCM = 2.5 ± 1 V
⌬VOUT,cm/⌬VOCM; ⌬VOCM = 2.5 ± 1 V
Gain
0.9968
1.0032 V/V
POWER SUPPLY
Operating Range
Quiescent Current
2.7
15
11
21
V
20
40
–90
mA
mA/∞C
dB
T
MIN to TMAX Variation
Power Supply Rejection Ratio
⌬VOUT,dm/⌬VS; ⌬VS = ±1 V
–70
OPERATING TEMPERATURE RANGE
–40
+85
∞C
*Harmonic Distortion Performance is equal or slightly worse with higher values of RL,dm. See TPCs 13 and 14 for more information.
Specifications subject to change without notice.
REV. E
–3–
AD8138
ABSOLUTE MAXIMUM RATINGS1
PIN CONFIGURATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5.5 V
VOCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 550 mW
+IN
NC
–IN
1
2
3
4
8
7
6
5
2 (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155∞C/W
V
OCM
JA
Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300∞C
V+
V–
+OUT
–OUT
AD8138
NOTES
NC = NO CONNECT
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational section
of this specification is not implied. Exposure to Absolute Maximum Ratings for
extended periods may affect device reliability.
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
2 Thermal resistance measured on SEMI standard four-layer board.
1
2
–IN
Negative Input Summing Node
R
= 499⍀
F
VOCM
Voltage applied to this pin sets the
common-mode output voltage with a
ratio of 1:1. For example, 1 V dc on
VOCM will set the dc bias level on +OUT
and –OUT to 1 V.
R
= 499⍀
= 499⍀
G
49.9⍀
R
= 499⍀
AD8138
L,dm
R
G
24.9⍀
R
= 499⍀
F
3
4
V+
Positive Supply Voltage
+OUT
Positive Output. Note that the voltage at
–DIN is inverted at +OUT. (See Figure 2.)
Figure 1. Basic Test Circuit
5
–OUT
Negative Output. Note that the voltage
at +DIN is inverted at –OUT. (See
Figure 2.)
6
7
8
V–
Negative Supply Voltage
No Connect
NC
+IN
Positive Input Summing Node
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Branding
Information
Model
AD8138AR
–40∞C to +85∞C
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Evaluation Board
R-8
AD8138AR-REEL
AD8138AR-REEL7
AD8138ARM
AD8138ARM-REEL
AD8138ARM-REEL7
AD8138-EVAL
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
13" Tape and Reel
7" Tape and Reel
RM-8
13" Tape and Reel
7" Tape and Reel
HBA
HBA
HBA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8138 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. E
Typical Performance Characteristics–AD8138
Unless otherwise noted, Gain = 1, RG = RF = RL,dm = 499 V, TA = 25؇C; refer to Figure 1 for test setup.
6
6
0.5
V
C
= 0.2V p-p
= 0pF
V
V
= ؎5V
= 0.2V p-p
V
V
= ؎5V
= 0.2V p-p
IN
F
S
IN
S
IN
3
3
0.3
0.1
C
= 0pF
F
V
= +5V
C = 0pF
F
S
0
0
V
= ؎5V
S
C
= 1pF
F
–3
–6
–9
–3
–6
–9
–0.1
–0.3
–0.5
C
= 1pF
F
10
100
1000
10
100
1000
10
FREQUENCY – MHz
100
1
1
1
FREQUENCY – MHz
FREQUENCY – MHz
TPC 1. Small Signal Frequency
Response
TPC 2. Small Signal Frequency
Response
TPC 3. 0.1 dB Flatness vs.
Frequency
30
20
10
6
6
V
C
= ؎5V
= 0pF
= 0.2V p-p
= 499⍀
S
V
V
= 2V p-p
= ؎5V
V
C
= 2V p-p
= 0pF
IN
S
IN
F
F
V
,dm
OUT
G = 10, R = 4.99k⍀
3
0
3
0
F
R
V
= +5V
G
S
C
= 0pF
F
G = 5, R = 2.49k⍀
F
V
S
= ؎5V
G = 2, R = 1k⍀
C
= 1pF
F
F
–3
–6
–9
–3
–6
–9
G = 1, R = 499⍀
F
0
–10
10
100
1000
10
100
1000
10
100
1000
1
1
1
FREQUENCY – MHz
FREQUENCY – MHz
FREQUENCY – MHz
TPC 4. Large Signal Frequency
Response
TPC 5. Large Signal Frequency
Response
TPC 6. Small Signal Frequency
Response for Various Gains
–50
–30
–40
V
R
= 2V p-p
V
R
= 2V p-p
,dm
= 800⍀
= 20MHz
V
R
= 4V p-p
,dm
,dm
OUT
= 800⍀
OUT
OUT
= 800⍀
L
L
L
–50
–60
–60
–70
–80
–90
–40
–50
–60
–70
–80
–90
–100
F
O
HD3(V = +5V)
S
HD2(V = +5V)
HD2(V = +5)
S
S
–70
HD2(V = ؎5V)
HD3(V = +5)
S
S
HD2(V = +5V)
S
–80
HD2(V = ؎5V)
S
–90
–100
–110
–120
HD3(V = ؎5)
S
HD3(V = +5V)
S
–100
–110
HD2(V = ؎5)
HD3(V = ؎5V)
HD3(V = ؎5V)
S
S
S
0
10
20
30
40
50
60
70
–4
–3
–2
–1
0
1
2
3
4
0
10
20
30
40
50
60
70
FUNDAMENTAL FREQUENCY – MHz
FUNDAMENTAL FREQUENCY – MHz
V
OCM
DC OUTPUT – V
TPC 7. Harmonic Distortion vs.
Frequency
TPC 8. Harmonic Distortion vs.
Frequency
TPC 9. Harmonic Distortion vs.
VOCM
REV. E
–5–
AD8138
–60
–60
–70
–60
–70
–80
–90
V
= ؎5V
V
R
= 5V
= 800⍀
V = 3V
S
S
S
R
= 800⍀
R
= 800⍀
HD3(F = 20MHz)
L
L
L
–70
–80
HD3(F = 20MHz)
HD2(F = 20MHz)
HD3(F = 20MHz)
HD2(F = 20MHz)
HD2(F = 20MHz)
–80
–90
–90
HD2(F = 5MHz)
HD3(F = 5MHz)
HD2(F = 5MHz)
HD2(F = 5MHz)
–100
–100
HD3(F = 5MHz)
–100
–110
HD3(F = 5MHz)
–110
–120
–110
–120
0
1
2
3
4
5
6
0
1
2
3
4
0.25 0.50
0.75 1.00
1.25 1.50
1.75
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
TPC 10. Harmonic Distortion
vs. Differential Output Voltage
TPC 11. Harmonic Distortion
vs. Differential Output Voltage
TPC 12. Harmonic Distortion
vs. Differential Output Voltage
–60
–70
–80
–90
–60
–70
10
–10
–30
–50
–70
V
V
= ؎5V
V
V
= 5V
S
F
= 50MHz
S
C
= 2V p-p
,dm
= 2V p-p
OUT
V
= ؎5V
,dm
OUT
S
HD2(F = 20MHz)
HD3(F = 20MHz)
HD2(F = 20MHz)
HD3(F = 20MHz)
–80
–90
HD2(F = 5MHz)
HD3(F = 5MHz)
–100
HD2(F = 5MHz)
–100
–110
–110
–120
–90
HD3(F = 5MHz)
–110
200
600
1000
R
1400
– ⍀
1800
200
600
1000
R
1400
– ⍀
1800
49.5
49.7
49.9
50.1
50.3
50.5
FREQUENCY – MHz
LOAD
LOAD
TPC 14. Harmonic Distortion
vs. RLOAD
TPC 13. Harmonic Distortion
vs. RLOAD
TPC 15. Intermodulation Distortion
45
V
V
= 0.2V p-p
= ؎5V
V
= ؎5V
S
OUT,dm
R
= 800⍀
L
C
= 0pF
F
S
V
OUT,dm
40
C
= 1pF
V
F
OUT–
V
= ؎5V
S
35
30
25
V
OUT+
V
= +5V
S
V
+DIN
1V
5ns
40mV
5ns
0
20
40
60
80
FREQUENCY – MHz
TPC 16. Third Order Intercept vs.
Frequency
TPC 17. Large Signal Transient
Response
TPC 18. Small Signal Transient
Response
–6–
REV. E
AD8138
V
C
= 2V p-p
C = 0pF
F
V
V
= 2V p-p
= ؎5V
V
= ؎5V
= 1pF
200V
V
= ؎5V
OUT,dm
= 0pF
OUT,dm
S
F
S
C
F
S
V
OUT,dm
V
= +5V
S
C
= 1pF
F
V
+DIN
400mV
400mV
1V
5ns
5ns
4ns
TPC 19. Large Signal Transient
Response
TPC 20. Large Signal Transient
Response
TPC 21. Settling Time
V
= ؎5V
= 0pF
S
F
C
C
= 10pF
L
C
= 5pF
V
L
OUT,dm
499⍀
C
= 20pF
L
V
= ؎5V
S
499⍀
24.9⍀
24.9⍀
F = 20MHz
= 8V p-p
V
+DIN
49.9⍀
499⍀
C
453⍀
AD8138
L
G = 3(R = 1500)
F
24.9⍀
499⍀
V
+DIN
4V
400mV
30ns
2.5ns
TPC 23. Test Circuit for Cap
Load Drive
TPC 22. Output Overdrive
TPC 24. Large Signal Transient
Response for Various Cap Loads
–20
–30
–20
V
= 2V p-p
V
⌬V
= ؎5V
IN
S
/⌬V
IN,
OUT,dm
cm
499⍀
–30
–40
–50
–60
–70
499⍀
249⍀
249⍀
–40
–50
–60
–70
–80
49.9⍀
499⍀
AD8138
V
= ؎5V
S
24.9⍀
499⍀
V
= +5V
S
1
10
100
1k
1
10
100
1k
FREQUENCY – MHz
FREQUENCY – MHz
TPC 26. Test Circuit for Output
Balance
TPC 25. CMRR vs. Frequency
TPC 27. Output Balance Error
vs. Frequency
REV. E
–7–
AD8138
5.0
2.5
0
–10
100
⌬V
/⌬V
S
OUT,dm
SINGLE-ENDED OUTPUT
–20
–PSRR
(V = ؎5V)
–30
–40
–50
S
V
= ؎5V
10
1
S
V
= +5
S
V
= +5V
S
–60
–70
–80
–90
V
= +3V
S
+PSRR
–2.5
–5.0
(V = +5V, 0V AND ؎5V)
S
V
= ؎5V
S
0.1
40
TEMPERATURE – ؇C
–40 –20
0
20
60
80
100
1
10
100
1k
1
10
FREQUENCY – MHz
100
FREQUENCY – MHz
TPC 28. PSRR vs. Frequency
TPC 30. Output Referred
Differential Offset Voltage vs.
Temperature
TPC 29. Output Impedance
vs. Frequency
30
25
6
3
5
4
3
V
= +5V
S
V
= ؎5V
S
V
= ؎5V
S
V
= ؎5V, +5V
S
20
15
10
5
0
V
= +5V
S
–3
–6
–9
V
= +3V
S
V
= +3V
S
2
1
40
TEMPERATURE – ؇C
–40 –20
0
20
60
80
100
40
TEMPERATURE – ؇C
–40 –20
0
20
60
80
100
10
100
1
1k
FREQUENCY – MHz
TPC 32. Supply Current vs.
Temperature
TPC 31. Input Bias Current
vs. Temperature
TPC 33. VOCM Frequency Response
1000
100
100
10
1
V
OCM
= ؎5V
S
V
= –1V TO +1V
V
OUT,cm
5.7nV/ Hz
1.1pA / Hz
10
400mV
5ns
1
10
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 34. VOCM Transient Response
TPC 35. Current Noise (RTI)
TPC 36. Voltage Noise (RTI)
–8–
REV. E
AD8138
OPERATIONAL DESCRIPTION
Definition of Terms
circuit. Excellent performance over a wide frequency range has
proven difficult with this approach.
The AD8138 uses two feedback loops to separately control the
differential and common-mode output voltages. The differential
feedback, set with external resistors, controls only the differential
output voltage. The common-mode feedback controls only the
common-mode output voltage. This architecture makes it easy to
arbitrarily set the output common-mode level. It is forced, by inter-
nal common-mode feedback, to be equal to the voltage applied to
the VOCM input, without affecting the differential output voltage.
C
F
R
F
R
R
+IN
–IN
G
G
–OUT
+D
IN
V
V
R
L,dm
AD8138
,dm
OUT
OCM
–D
IN
+OUT
R
C
F
The AD8138 architecture results in outputs that are very highly
balanced over a wide frequency range without requiring tightly
matched external components. The common-mode feedback
loop forces the signal component of the output common-mode
voltage to be zeroed. The result is nearly perfectly balanced
differential outputs of identical amplitude and exactly 180∞ apart
in phase.
F
Figure 2. Circuit Definitions
Differential voltage refers to the difference between two
node voltages. For example, the output differential voltage
(or equivalently output differential-mode voltage) is defined as:
Analyzing an Application Circuit
VOUT,dm = V
-V-OUT
(
)
+OUT
The AD8138 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and –IN in Figure 2.
For most purposes, this voltage can be assumed to be zero. Simi-
larly, the difference between the actual output common-mode
voltage and the voltage applied to VOCM can also be assumed to
be zero. Starting from these two assumptions, any application
circuit can be analyzed.
V
+OUT and V–OUT refer to the voltages at the +OUT and –OUT
terminals with respect to a common reference.
Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as:
VOUT,cm = V
+V-OUT
2
(
)
+OUT
Balance is a measure of how well differential signals are matched
in amplitude and exactly 180Њ apart in phase. Balance is most
easily determined by placing a well-matched resistor divider
between the differential voltage nodes and comparing the magni-
tude of the signal at the divider’s midpoint with the magnitude
of the differential signal (see TPC 26). By this definition, output
balance is the magnitude of the output common-mode voltage
divided by the magnitude of the output differential-mode voltage:
Setting the Closed-Loop Gain
Neglecting the capacitors CF, the differential-mode gain of the
circuit in Figure 2 can be determined to be described by the
following equation:
S
VOUT,dm
RF
RG
=
VOUT,cm
S
VIN,dm
Output Balance Error =
VOUT,dm
This assumes the input resistors, RGS, and feedback resistors,
RFS, on each side are equal.
THEORY OF OPERATION
The AD8138 differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions. Like an
op amp, it relies on high open-loop gain and negative feedback
to force these outputs to the desired voltages. The AD8138
behaves much like a standard voltage feedback op amp and makes
it easy to perform single-ended-to-differential conversion, common-
mode level-shifting, and amplification of differential signals. Also
like an op amp, the AD8138 has high input impedance and low
output impedance.
Estimating the Output Noise Voltage
Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input referred terms, at +IN and –IN, by the
circuit noise gain. The noise gain is defined as:
Ê
ˆ
RF
GN = 1+
Á
Ë
˜
¯
R
G
To compute the total output referred noise for the circuit of
Figure 2, consideration must also be given to the contribution of
the resistors RF and RG. Refer to Table I for estimated output
noise voltage densities at various closed-loop gains.
Previous differential drivers, both discrete and integrated designs,
have been based on using two independent amplifiers and two
independent feedback loops, one to control each of the outputs.
When these circuits are driven from a single-ended source, the
resulting outputs are typically not well balanced. Achieving a
balanced output has typically required exceptional matching of
the amplifiers and feedback networks.
Table I.
RG RF
Bandwidth Output Noise Output Noise
Gain (⍀) (⍀)
–3 dB
8138 Only
8138 + RG, RF
DC common-mode level-shifting has also been difficult with
previous differential drivers. Level-shifting has required the use
of a third amplifier and feedback loop to control the output
common-mode level. Sometimes the third amplifier has also
been used to attempt to correct an inherently unbalanced
1
499 499
320 MHz
10 nV/÷Hz
15 nV/÷Hz
30 nV/÷Hz
55 nV/÷Hz
11.6 nV/÷Hz
18.2 nV/÷Hz
37.9 nV/÷Hz
70.8 nV/÷Hz
2
5
499 1.0 k 180 MHz
499 2.49 k 70 MHz
499 4.99 k 30 MHz
10
REV. E
–9–
AD8138
When using the AD8138 in gain configurations where
In the case of a single-ended input signal (for example if –DIN is
grounded and the input signal is applied to +DIN), the input
impedance becomes:
RF
RG
Ê
ˆ
of one feedback network is unequal to
Á
˜
RG
RF
RIN,dm
=
Á
˜
RF
RG
Á
Á
Ë
˜
˜
¯
1-
2 ¥ R + RF
(
)
G
of the other network, there will be a differential output noise
due to input-referred voltage in the VOCM circuitry. The output
noise is defined in terms of the following feedback terms (refer
to Figure 2):
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
RG
b1 =
RF + RG
Input Common-Mode Voltage Range in Single-Supply
Applications
for –OUT to +IN loop, and
The AD8138 is optimized for level-shifting “ground” referenced
input signals. For a single-ended input, this would imply, for
example, that the voltage at –DIN in Figure 2 would be 0 V when
the amplifier’s negative power supply voltage (at V–) is also
set to 0 V.
RG
b2 =
RF + RG
for +OUT to –IN loop. With these defined,
Setting the Output Common-Mode Voltage
È
˘
b1 – b2
b1 + b2
VnOUT ,dm = 2V
nIN ,VOCM
The AD8138’s VOCM pin is internally biased at a voltage approxi-
mately equal to the midsupply point (average value of the voltages
on V+ and V–). Relying on this internal bias will result in an
output common-mode voltage that is within about 100 mV of
the expected value.
Í
Î
˙
˚
where VnOUT,dm is the output differential noise and VnIN,V
the input-referred voltage noise in VOCM
is
OCM
.
The Impact of Mismatches in the Feedback Networks
In cases where more accurate control of the output common-mode
level is required, it is recommended that an external source, or
resistor divider (made up of 10 kW resistors), be used. The output
common-mode offset listed in the Specifications section assumes
the VOCM input is driven by a low impedance voltage source.
As mentioned previously, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop will still force the outputs to remain balanced. The ampli-
tudes of the signals at each output will remain equal and 180Њ
out of phase. The input-to-output differential-mode gain will
vary proportionately to the feedback mismatch, but the output
balance will be unaffected.
Driving a Capacitive Load
A purely capacitive load can react with the pin and bondwire
inductance of the AD8138, resulting in high frequency ringing
in the pulse response. One way to minimize this effect is to place
a small capacitor across each of the feedback resistors. The added
capacitance should be small to avoid destabilizing the amplifier.
An alternative technique is to place a small resistor in series with
the amplifier’s outputs as shown in TPC 23.
Ratio matching errors in the external resistors will result in a
degradation of the circuit’s ability to reject input common-mode
signals, much the same as for a four-resistor difference amplifier
made from a conventional op amp.
Also, if the dc levels of the input and output common-mode
voltages are different, matching errors will result in a small
differential-mode output offset voltage. For the G = 1 case, with
a ground referenced input signal and the output common-mode
level set for 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance will result in a worst-
case input CMRR of about 40 dB, worst-case differential mode
output offset of 25 mV due to 2.5 V level-shift, and no significant
degradation in output balance error.
LAYOUT, GROUNDING, AND BYPASSING
As a high speed part, the AD8138 is sensitive to the PCB
environment in which it has to operate. Realizing its superior
specifications requires attention to various details of good high
speed PCB design.
The first requirement is for a good solid ground plane that covers
as much of the board area around the AD8138 as possible. The
only exception to this is that the two input pins (Pins 1 and 8)
should be kept a few millimeters from the ground plane, and
ground should be removed from inner layers and the opposite
side of the board under the input pins. This will minimize the
stray capacitance on these nodes and help preserve the gain
flatness versus frequency.
Calculating an Application Circuit’s Input Impedance
The effective input impedance of a circuit such as the one in
Figure 2, at +DIN and –DIN, will depend on whether the amplifier
is being driven by a single-ended or differential signal source.
For balanced differential input signals, the input impedance
(RIN,dm) between the inputs (+DIN and –DIN) is simply:
RIN,dm = 2 ¥ RG
–10–
REV. E
AD8138
The power supply pins should be bypassed as close as possible
to the device to the nearby ground plane. Good high frequency
ceramic chip capacitors should be used. This bypassing should
be done with a capacitance value of 0.01 mF to 0.1 mF for each
supply. Further away, low frequency bypassing should be provided
with 10 mF tantalum capacitors from each supply to ground.
shows the differentially driven balance response. The 100 MHz
balance is 35 dB better when using the AD8138.
The well-balanced outputs of the AD8138 will provide a drive
signal to each of the transformer’s primary inputs that are of equal
amplitude and 180Њ out of phase. Thus, depending on how the
polarity of the secondary is connected, the signals that conduct
across the interwinding capacitance will either both assist the
transformer’s secondary signal equally, or both buck the secondary
signals. In either case, the parasitic effect will be symmetrical
and provide a well balanced transformer output (see Figure 5).
The signal routing should be short and direct to avoid parasitic
effects. Wherever there are complementary signals, a symmetrical
layout should be provided to the extent possible to maximize the
balance performance. When running differential signals over a
long distance, the traces on the PCB should be close together or
any differential wiring should be twisted together to minimize
the area of the loop that is formed. This will reduce the radiated
energy and make the circuit less susceptible to interference.
SIGNAL WILL BE COUPLED
ON THIS SIDE VIA C
STRAY
C
STRAY
500⍀
V
UNBAL
0.005%
BALANCED TRANSFORMER DRIVER
PRIMARY
SECONDARY V
52.3⍀
DIFF
500⍀
0.005%
Transformers are among the oldest devices used to perform a
single-ended-to-differential conversion (and vice versa). Trans-
formers also can perform the additional functions of galvanic
isolation, step-up or step-down of voltages, and impedance
transformation. For these reasons, transformers will always find
uses in certain applications.
C
STRAY
NO SIGNAL IS COUPLED
ON THIS SIDE
Figure 3. Transformer Single-Ended-to-Differential
Converter Is Inherently Imbalanced
However, when driving a transformer single-endedly and then
looking at its output, there is a fundamental imbalance due to the
parasitics inherent in the transformer. The primary (or driven) side
of the transformer has one side at dc potential (usually ground),
while the other side is driven. This can cause problems in systems
that require good balance of the transformer’s differential output
signals.
499⍀
C
STRAY
49.9⍀
499⍀
+IN
–IN
500⍀
0.005%
OUT–
V
UNBAL
If the interwinding capacitance (CSTRAY) is assumed to be uni-
formly distributed, a signal from the driving source will couple
to the secondary output terminal that is closest to the primary’s
driven side. On the other hand, no signal will be coupled to the
opposite terminal of the secondary because its nearest primary
terminal is not driven (see Figure 3). The exact amount of this
imbalance will depend on the particular parasitics of the trans-
former, but will mostly be a problem at higher frequencies.
AD8138
V
DIFF
499⍀
500⍀
0.005%
OUT+
49.9⍀
C
STRAY
499⍀
Figure 4. AD8138 Forms a Balanced Transformer Driver
The balance of a differential circuit can be measured by connecting
an equal-valued resistive voltage divider across the differential
outputs and then measuring the center point of the circuit with
respect to ground. Since the two differential outputs are supposed
to be of equal amplitude, but 180Њ opposite phase, there should
be no signal present for perfectly balanced outputs.
0
–20
V
, FOR TRANSFORMER
UNBAL
–40
–60
WITH SINGLE-ENDED DRIVE
The circuit in Figure 3 shows a Minicircuits T1-6T transformer
connected with its primary driven single-endedly and the second-
ary connected with a precision voltage divider across its terminals.
The voltage divider is made up of two 500 W, 0.005% preci-
sion resistors. The voltage VUNBAL, which is also equal to the
ac common-mode voltage, is a measure of how closely the outputs
are balanced.
–80
V
, DIFFERENTIAL DRIVE
UNBAL
–100
The plots in Figure 5 compare the transformer being driven
single-endedly by a signal generator and being driven differen-
tially using an AD8138. The top signal trace of Figure 5 shows
the balance of the single-ended configuration, while the bottom
0.3
1
10
100
500
FREQUENCY – MHz
Figure 5. Output Balance Error for Circuits of
Figures 3 and 4
REV. E
–11–
AD8138
HIGH PERFORMANCE ADC DRIVING
The signal generator has a ground-referenced, bipolar output,
i.e., it drives symmetrically above and below ground. Connecting
VOCM to the CML pin of the AD9224 sets the output common-
mode of the AD8138 at 2.5 V, which is the midsupply level for
the AD9224. This voltage is bypassed by a 0.1 mF capacitor.
The circuit in Figure 6 shows a simplified front-end connection
for an AD8138 driving an AD9224, a 12-bit, 40 MSPS A/D
converter. The ADC works best when driven differentially, which
minimizes its distortion as described in its data sheet. The AD8138
eliminates the need for a transformer to drive the ADC and
performs single-ended-to-differential conversion, common-mode
level-shifting, and buffering of the driving signal.
The full-scale analog input range of the AD9224 is set to 4 V p-p,
by shorting the SENSE terminal to AVSS. This has been deter-
mined to be the scaling to provide minimum harmonic distortion.
The positive and negative outputs of the AD8138 are connected
to the respective differential inputs of the AD9224 via a pair of
49.9 W resistors to minimize the effects of the switched-capacitor
front end of the AD9224. For best distortion performance, it is
run from supplies of ±5 V.
For the AD8138 to swing at 4 V p-p, each output swings 2 V p-p
while providing signals that are 180Њ out of phase. With a
common-mode voltage at the output of 2.5 V, this means that
each AD8138 output will swing between 1.5 V and 3.5 V.
A ground-referenced 4 V p-p, 5 MHz signal at DIN+ was used
to test the circuit in Figure 6. When the combined-device circuit
was run with a sampling rate of 20 MSPS, the SFDR (spurious-
free dynamic range) was measured at –85 dBc.
The AD8138 is configured with unity gain for a single-ended
input-to-differential output. The additional 23 W, 523 W total, at
the input to –IN is to balance the parallel impedance of the 50 W
source and its 50 W termination that drives the noninverting input.
+5V
+5V
0.1pF
0.1pF
499⍀
49.9⍀
49.9⍀
499⍀
AVDD DRVDD
+
VINB
DIGITAL
OUTPUTS
V
OCM
AD9224
50⍀
SOURCE
49.9⍀
AD8138
523⍀
VINA
AVSS
DRVSS
SENSE CML
0.1pF
499⍀
–5V
Figure 6. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS A/D Converter
–12–
REV. E
AD8138
3 V OPERATION
The circuit was tested with a –0.5 dBFS signal at various frequen-
cies. Figure 8 shows a plot of the total harmonic distortion (THD)
vs. frequency at signal amplitudes of 1 V and 2 V differential
drive levels.
The circuit in Figure 7 shows a simplified front end connection
for an AD8138 driving an AD9203, a 10-bit, 40 MSPS A/D con-
verter that is specified to work on a single 3 V supply. The ADC
works best when driven differentially to make the best use of the
signal swing available within the 3 V supply. The appropriate
outputs of the AD8138 are connected to the appropriate differen-
tial inputs of the AD9203 via a low-pass filter.
–40
–45
–50
The AD8138 is configured for unity gain for a single-ended
input to differential output. The additional 23 W at the input to
–IN is to balance the impedance of the 50 W source and its 50 W
termination that drives the noninverting input.
–55
AD8138–2V
–60
The signal generator has ground-referenced, bipolar output,
i.e., it can drive symmetrically above and below ground. Even
though the AD8138 has ground as its negative supply, it can
still function as a level-shifter with such an input signal.
–65
AD8138–1V
–70
–75
–80
The output common mode is raised up to midsupply by the
voltage divider that biases VOCM. In this way, the AD8138 pro-
vides dc coupling and level-shifting of a bipolar signal, without
inverting the input signal.
0
5
10
15
20
25
FREQUENCY – MHz
Figure 8. AD9203 THD @ –0.5 dBFS AD8138
The low-pass filter between the AD8138 and the AD9203 pro-
vides filtering that helps to improve the signal-to-noise ratio.
Lower noise can be realized by lowering the pole frequency, but
the bandwidth of the circuit will be lowered.
Figure 9 shows the signal to noise plus distortion (SINAD)
under the same conditions as above. For the smaller signal
swing, the AD8138 performance is quite good, but its performance
degrades when trying to swing too close to the supply rails.
+3V
+3V
65
63
61
0.1F
0.1F
499⍀
0.1F
10k⍀
499⍀
49.9⍀
AVDD DRVDD
AINN
+
59
20pF
DIGITAL
49.9⍀
AD9203
AD8138
OUTPUTS
57
AD8138–1V
AINP
AVSS DRVSS
523⍀
49.9⍀
55
20pF
0.1F
10k⍀
AD8138–2V
53
499⍀
51
49
47
45
Figure 7. AD8138 Driving an AD9203, a 10-Bit, 40 MSPS
A/D Converter
0
5
10
15
20
25
FREQUENCY – MHz
Figure 9. AD9203 SINAD @ –0.5 dBFS AD8138
REV. E
–13–
AD8138
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
؋
45؇ 1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8؇
0.51 (0.0201)
0.33 (0.0130)
0؇ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.19 (0.0075)
SEATING
PLANE
0.41 (0.0160)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4
4.90
BSC
3.00
BSC
1
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.80
0.40
8؇
0؇
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA
–14–
REV. E
AD8138
Revision History
Location
Page
3/03—Data Sheet changed from REV. D to REV. E.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to TPC 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Added new paragraph after Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7/02—Data Sheet changed from REV. C to REV. D.
Addition of TPC 35 and TPC 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6/01—Data Sheet changed from REV. B to REV. C.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
REV. E
–15–
–16–
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