AD8150AST [ADI]
33 x 17, 1.5 Gbps Digital Crosspoint Switch; 33 ×17 ， 1.5 Gbps的数字交叉点开关
| 型号： | AD8150AST |
| 厂家： | 
ADI |
| 描述： | 33 x 17, 1.5 Gbps Digital Crosspoint Switch |
| 文件： | 总35页 (文件大小：984K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
33 ꢀ 17, 1.5 Gbps
Digital Crosspoint Switch
a
AD8150*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low Cost
CS
RE
33 ꢀ 17, Fully Differential, Nonblocking Array
>1.5 Gbps per Port NRZ Data Rate
Wide Power Supply Range: +5 V, +3.3 V, –3.3 V, –5 V
Low Power
400 mA (Outputs Enabled)
30 mA (Outputs Disabled)
PECL and ECL Compatible
CMOS/TTL-Level Control Inputs: 3 V to 5 V
Low Jitter: <50 ps p-p
INN
INP
33
33
D
A
7
5
OUTP
OUTN
17
17
33ꢀ17
FIRST
RANK
17ꢀ7-BIT
LATCH
SECOND
RANK
17ꢀ7-BIT
LATCH
DIFFERENTIAL
SWITCH
MATRIX
No Heat Sinks Required
WE
Drives a Backplane Directly
Programmable Output Current
Optimize Termination Impedance
User-Controlled Voltage at the Load
Minimize Power Dissipation
Individual Output Disable for Busing and Building
Larger Arrays
AD8150
UPDATE
RESET
Double Row Latch
Buffered Inputs
Available in 184-Lead LQFP
APPLICATIONS
HD and SD Digital Video
Fiber Optic Network Switching
PRODUCT DESCRIPTION
500mV
AD8150 is a member of the X stream line of products and is
a breakthrough in digital switching, offering a large switch array
(33 × 17) on very little power, typically less than 1.5 W. Addi-
tionally, it operates at data rates in excess of 1.5 Gbps per port,
making it suitable for HDTV applications. Further, the pric-
ing of the AD8150 makes it affordable enough to be used for
SD applications as well. The AD8150 is also useful for OC-24
optical network switching.
100mV
/DIV
The AD8150’s flexible supply voltages allow the user to operate
with either PECL or ECL data levels and will operate down to
3.3 V for further power reduction. The control interface is CMOS/
TTL compatible (3 V to 5 V).
–500mV
100ps/DIV
Its fully differential signal path reduces jitter and crosstalk while
allowing the use of smaller single-ended voltage swings.
Figure 1. Output Eye Pattern, 1.5 Gbps
The AD8150 is offered in a 184-lead LQFP package that operates
over the industrial temperature range of 0°C to 85°C.
*Patent Pending.
X stream is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(@ 25ꢁC, VCC = 3.3 V to 5 V, VEE = 0 V, RL = 50 ꢂ (see Figure 22), IOUT = 16 mA, unless
otherwise noted)
AD8150–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Max Data Rate/Channel (NRZ)
Channel Jitter
1.5
Gbps
ps p-p
ps
Data Rate < 1.5 Gbps
VCC = 5 V
50
10
RMS Channel Jitter
Propagation Delay
Propagation Delay Match
Input to Output
650
50
ps
ps
100
Output Rise/Fall Time
20% to 80%
100
ps
INPUT CHARACTERISTICS
Input Voltage Swing
Input Voltage Range
Input Bias Current
Input Capacitance
Input VIN High
Differential
Common-Mode
200
1000
VCC
mV p-p
V
µA
pF
V
VCC – 2
2
2
VCC – 1.2
VCC – 2.4
VCC – 0.2
VCC – 1.4
Input VIN Low
V
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Range
Output Current
Differential (See Figure 22)
800
2
mV p-p
V
mA
VCC – 1.8
5
VCC
25
Output Capacitance
pF
POWER SUPPLY
Operating Range
PECL, VCC
ECL, VEE
VDD
VEE = 0 V
VCC = 0 V
3.3
–5
3
5
–3.3
5
V
V
V
V
VSS
0
Quiescent Current
VDD
VEE
2
400
mA
mA
mA
mA
All Outputs Enabled, IOUT = 16 mA
TMIN to TMAX
450
85
All Outputs Disabled
30
30
THERMAL CHARACTERISTICS
Operating Temperature Range
θJA
0
°C
°C/W
LOGIC INPUT CHARACTERISTICS
Input VIN High
Input VIN Low
VDD = 3 V dc to 5 V dc
1.9
0
VDD
0.9
V
V
REV. 0
–2–
AD8150
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltage VDD – VEE . . . . . . . . . . . . . . . . . . . . . . . 10.5 V
The maximum power that can be safely dissipated by the AD8150
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of
the plastic, approximately 150°C. Temporarily exceeding this
limit may cause a shift in parametric performance due to a change
in the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result in
device failure.
Internal Power Dissipation2
AD8150 184-Lead Plastic LQFP (ST) . . . . . . . . . . . . . 4.2 W
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . .VCC – VEE
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air (TA = 25°C):
While the AD8150 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction temp-
erature (150°C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum power
derating curves shown in Figure 2.
184-lead plastic LQFP (ST): θJA = 30°C/W.
6.0
5.0
4.0
3.0
T
= 150ꢁC
J
2.0
1.0
–10
0
10
20
30
40
50
60
70
80
90
AMBIENT TEMPERATURE – ꢁC
Figure 2. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD8150AST
0°C to 85°C
184-Lead Plastic LQFP
(20 mm × 20 mm)
Evaluation Board
ST-184
AD8150-EVAL
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8150 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD8150
PIN CONFIGURATION
1
2
V
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
V
EE
EE
PIN 1
IDENTIFIER
IN20P
IN20N
IN12N
IN12P
3
4
V
V
EE
EE
5
6
IN21P
IN21N
IN11N
IN11P
7
V
V
EE
EE
8
IN22P
IN22N
IN10N
IN10P
9
10
11
V
V
EE
EE
IN23P
IN23N
IN09N
IN09P
12
13
V
V
EE
EE
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
IN24P
IN24N
IN08N
IN08P
V
V
EE
EE
IN25P
IN25N
IN07N
IN07P
V
IN06N
IN06P
V
EE
EE
IN26P
IN26N
V
V
EE
EE
AD8150
IN27P
IN27N
116
115
IN05N
IN05P
184L LQFP
TOP VIEW
(Not to Scale)
V
114
113
112
111
110
109
108
107
106
V
EE
EE
IN28P
IN28N
IN04N
IN04P
V
V
EE
EE
IN29P
IN29N
IN03N
IN03P
V
V
EE
EE
IN30P
IN30N
IN02N
IN02P
V
105
104
103
102
101
100
99
V
EE
EE
IN31P
IN31N
IN01N
IN01P
V
V
EE
EE
IN32P
IN32N
IN00N
IN00P
V
V
EE
EE
V
98
VCC
CC
V
97
V
A0
EE
EE
OUT16N
OUT16P
96
OUT00P
OUT00N
95
94
V
A16
V
EE
EE
93
V
V
EE
EE
REV. 0
–4–
AD8150
PIN FUNCTION DESCRIPTIONS
Pin No.
Signal
Type
Description
1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31,
34, 37, 40, 42, 46, 47, 92, 93, 99, 102,
105, 108, 111, 114, 117, 120, 123,
126, 129, 132, 135, 138, 139, 142,
145, 148, 172, 175, 178, 181, 184
VEE
Power Supply
Most Negative PECL Supply (Common with Other
Points Labeled VEE
)
2
3
5
6
8
9
11
12
14
15
17
18
20
21
23
24
26
27
29
30
32
33
35
36
IN20P
IN20N
IN21P
IN21N
IN22P
IN22N
IN23P
IN23N
IN24P
IN24N
IN25P
IN25N
IN26P
IN26N
IN27P
IN27N
IN28P
IN28N
IN29P
IN29N
IN30P
IN30N
IN31P
IN31N
IN32P
IN32N
VCC
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
Power Supply
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
38
39
41, 98, 149, 171
Most Positive PECL Supply (Common with Other
Points Labeled VCC
)
43
44
45
48
49
50
51
52
53
54
55
56
57
58
59
60
61
OUT16N PECL
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to This Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
OUT16P
EEA16
PECL
Power Supply
V
OUT15N PECL
OUT15P
EEA15
PECL
Power Supply
V
OUT14N PECL
OUT14P
EEA14
PECL
Power Supply
V
OUT13N PECL
OUT13P
EEA13
PECL
Power Supply
V
OUT12N PECL
OUT12P
EEA12
PECL
Power Supply
V
OUT11N PECL
OUT11P PECL
REV. 0
–5–
AD8150
Pin No.
Signal
Type
Description
62
63
64
65
66
VEEA11
OUT10N
OUT10P
Power Supply
PECL
PECL
Power Supply
PECL
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
V
EEA10
OUT09N
67
68
OUT09P
PECL
Power Supply
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
V
EEA9
69
70
71
OUT08N
OUT08P
PECL
PECL
Power Supply
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
V
EEA8
72
73
OUT07N
OUT07P
PECL
PECL
High-Speed Output Complement
High-Speed Output
74
75
76
V
EEA7
Power Supply
PECL
PECL
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
OUT06N
OUT06P
77
78
79
V
EEA6
Power Supply
PECL
PECL
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
OUT05N
OUT05P
80
81
82
V
EEA5
Power Supply
PECL
PECL
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
OUT04N
OUT04P
83
84
85
V
EEA4
Power Supply
PECL
PECL
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
OUT03N
OUT03P
86
87
88
V
EEA3
Power Supply
PECL
PECL
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
OUT02N
OUT02P
89
90
91
V
EEA2
Power Supply
PECL
PECL
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
OUT01N
OUT01P
94
95
96
V
EEA1
Power Supply
PECL
PECL
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
OUT00N
OUT00P
97
V
EEA0
Power Supply
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
Most Negative PECL Supply (Unique to this Output)
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
100
101
103
104
106
107
109
110
112
113
115
116
118
119
121
122
IN00P
IN00N
IN01P
IN01N
IN02P
IN02N
IN03P
IN03N
IN04P
IN04N
IN05P
IN05N
IN06P
IN06N
IN07P
IN07N
High-Speed Input Complement
REV. 0
–6–
AD8150
Pin No.
Signal
Type
Description
124
125
127
128
130
131
133
134
136
137
140
141
143
144
146
147
150
IN08P
IN08N
IN09P
IN09N
IN10P
IN10N
IN11P
IN11N
IN12P
IN12N
IN13P
IN13N
IN14P
IN14N
IN15P
IN15N
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
R-Program
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
Connection Point for Output Logic Pull-Down
Programming Resistor (Must be Connected to VEE
V
EEREF
)
151
REF
R-Program
Connection Point for Output Logic Pull-Down
Programming Resistor
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
173
174
176
177
179
180
182
183
VSS
D6
D5
D4
D3
D2
D1
D0
A4
A3
A2
A1
A0
UPDATE
WE
Power Supply
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Most Negative Control Logic Supply
Enable/Disable Output
(32) MSB Input Select
(16)
(8)
(4)
(2)
(1) LSB Input Select
(16) MSB Output Select
(8)
(4)
(2)
(1) LSB Output Select
Second Rank Program
First Rank Program
Enable Readback
Enable Chip to Accept Programming
Disable All Outputs (Hi-Z)
Most Positive Control Logic Supply
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
RE
CS
RESET
VDD
TTL
Power Supply
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
IN16P
IN16N
IN17P
IN17N
IN18P
IN18N
IN19P
IN19N
REV. 0
–7–
AD8150–Typical Performance Characteristics
100
100
80
60
40
20
0
V
= –3.3V (V
OH
– V = 800mV)
OL
V
= –5V (V
– V = 800mV)
OL
EE
EE OH
80
60
40
20
0
PK-PK
PK-PK
RMS
RMS
0
0
–0.2
–0.4
–0.6
–0.8
– Volts
–1.0
–1.2
–1.4
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
V
V
– Volts
OH
OH
Figure 3. Jitter vs. VOH 1.5 Gbps, PRBS 23
Figure 6. Jitter vs. VOH 1.5 Gbps, PRBS 23
100
80
60
40
20
0
100
80
60
40
20
0
V
= –3.3V (V – V = 800mV)
V
= –5V (V – V = 800mV)
EE
IH
IL
EE
IH
IL
PK-PK
PK-PK
RMS
RMS
–2.0
–1.5
–1.0
–0.5
0.0
0.5
–2.0
–1.5
–1.0
–0.5
0.0
0.5
V
– Volts
V
– Volts
IH
IH
Figure 4. Jitter vs. VIH 1.5 Gbps, PRBS 23
Figure 7. Jitter vs. VIH 1.5 Gbps, PRBS 23
100
80
60
40
20
0
100
80
60
40
20
0
V
= –3.3V
V
= –5V
EE
EE
PK-PK
PK-PK
RMS
0.7
RMS
0.7
0.3
0.5
0.9
1.1
1.3
1.5
0.3
0.1
0.5
0.9
1.1
1.3
1.5
0.1
DATA RATE – Gbps
DATA RATE – Gbps
Figure 5. Jitter vs. Data Rate, PRBS 23
Figure 8. Jitter vs. Data Rate, PRBS 23
REV. 0
–8–
AD8150
100
80
60
40
20
0
100
80
60
40
20
0
V = –5V
EE
V
= –3.3V
EE
PK-PK
PK-PK
RMS
RMS
0
5
10
15
20
25
0
5
10
15
20
25
I
– mA
I
– mA
OUT
OUT
Figure 9. Jitter vs. IOUT 1.5 Gbps, PRBS 23
Figure 12. Jitter vs. IOUT 1.5 Gbps, PRBS 23
100
80
60
40
20
0
100
80
60
40
20
0
V
= –5V
V
= –3.3V
EE
EE
PK-PK
PK-PK
RMS
50
RMS
50
–25
0
25
75
100
125
–25
0
25
75
100
125
TEMPERATURE – ꢁC
TEMPERATURE – ꢁC
Figure 13. Jitter vs. Temperature 1.5 Gbps, PRBS 23
Figure 10. Jitter vs. Temperature 1.5 Gbps, PRBS 23
100
100
VOLTAGE (INNER EYE)
80
VOLTAGE (INNER EYE)
TIME DOMAIN
80
60
40
20
0
TIME DOMAIN
60
V
= –3.3V
EE
V
= –5V
EE
40
23
23
2
–1 PSEUDO-RANDOM BIT STREAM, ERROR-FREE AREA
2
–1 PSEUDO-RANDOM BIT STREAM, ERROR-FREE AREA
ERROR-FREE PERCENTAGE VALUE WAS COMPUTED
USING THE FOLLOWING FORMULA:
(DATA_PERIOD – PPJITTER) ꢀ 100 / DATA_PERIOD
TIME DOMAIN
ERROR-FREE PERCENTAGE VALUE WAS COMPUTED
USING THE FOLLOWING FORMULA:
(DATA_PERIOD – PPJITTER) ꢀ 100 / DATA_PERIOD
TIME DOMAIN
20
0
V
ꢀ 100 / V @500Mbps
V
ꢀ 100 / V
@500Mbps
INNER
INNER
INNER
INNER
VOLTAGE (INNER EYE)
500 1000
DATA RATE – Mbps
VOLTAGE (INNER EYE)
500 1000
DATA RATE – Mbps
0
1500
0
1500
Figure 14. AC Performance
Figure 11. AC Performance
REV. 0
–9–
AD8150
100
150
100
50
80
60
40
20
0
–50
0
–100
560
580
600
620
640
660
680
700
710
–25
0
25
50
75
100
DELAY – ps
TEMPERATURE – ꢁC
Figure 15. Variation in Channel-to-Channel Delay,
All 561 Points
Figure 18. Propagation Delay, Normalized at 25°C vs.
Temperature
17.0
16.5
16.0
15.5
15.0
14.5
100
80
60
PK-PK
40
20
RMS
0
3.5
4.0
3.0
4.5
CC EE
5.0
–3.3
–3.6
–3.9
V
–4.2
– Volts
–4.7
–5.0
SUPPLY VOLTAGE – V , V
EE
Figure 16. IOUT vs. Supply, VEE
Figure 19. Jitter vs. Supply, 1.5 Gbps, PRBS 23
+1V
+1V
95.55 RISE
96.32 FALL
87.11 RISE
87.36 FALL
20% PROXIMAL
80% DISTAL
20% PROXIMAL
80% DISTAL
–1V
–1V
200ps/DIV
200ps/DIV
Figure 17. Rise/Fall Times, VEE = –3.3 V
Figure 20. Rise/Fall Times, VEE = –5 V
REV. 0
–10–
AD8150
+500mV
+500mV
–500mV
–500mV
200ps/DIV
100ps/DIV
Figure 21. Eye Pattern, VEE = –3.3 V, 1.5 Gbps PRBS 23
Figure 23. Eye Pattern, VEE = –5 V, 1.5 Gbps PRBS 23
V
V
V
TT
CC
CC
R
= 50ꢂ
TEKTRONIX
11801B
L
1.65kꢂ
105ꢂ
AD8150
p
p
HP8133A
PRBS
GENERATOR
50ꢂ
IN
OUT
n
SD22
SAMPLING
HEAD
n
50ꢂ
R
= 50ꢂ
1.65kꢂ
L
V
EE
V
V
TT
EE
V
= 0V, V = –3.3V OR –5V, V = –1.6V
EE TT
CC
R
= 1.54kꢂ, I
= 16mA, V
= –0.8V, V = –1.8V
SET
OUT
OH OL
INTRINSIC JITTER OF HP8133A AND TEKTRONIX 11801B = 3ps RMS, 17ps PK-PK
Figure 22. Eye Pattern Test Circuit
REV. 0
–11–
AD8150
Control Interface Truth Tables
The following are truth tables for the control interface.
Table I. Basic Control Functions
Control Pins
Reset
CS
WE
RE
Update
Function
0
1
X
1
X
X
X
X
X
X
Global Reset. Reset all second rank enable bits to zero (disable all outputs).
Control Disable. Ignore all logic (but the signal matrix still functions as
programmed). D[6:0] are high-impedance.
1
1
1
1
0
0
0
0
0
X
0
X
X
0
Single Output Preprogram. Write input configuration data from data bus D[6:0].
into first rank of latches for the output selected by the output address bus A[4:0].
Single Output Readback. Readback input configuration data from second rank of latches
onto data bus D[6:0] for the single output selected by the output address bus A[4:0].
Global Update. Copy input configuration data from all 17 first rank latches into second
rank of latches, updating signal matrix connections for all outputs.
Transparent Write and Update. It is possible to write data directly onto rank two. This
simplifies logic when synchronous signal matrix updating is not necessary.
X
X
0
X
1
0
Table II. Address/Data Examples
Output Address Pins
MSB–LSB
Enable
Bit
Input Address Pins
MSB-LSB
A4 A3 A2 A1 A0 D6/E
D5 D4 D3 D2 D1 D0 Function
0
0
0
0
0
X
X
1
0
0
0
0
0
0
Lower Address/Data Range. Connect Output #00
(A[4:0] = 00000) to Input #00 (D[5:0] = 000000).
1
0
0
0
0
1
0
0
0
0
0
Upper Address/Data Range. Connect Output #16
(A[4:0] = 10000) to Input #32 (D[5:0] = 100000).
<Binary Output Number*>
<Binary Output Number*>
<Binary Input Number>
Enable Output. Connect Selected Output (A[4:0] = 0
to 16) to Designated Input (D[5:0] = 0 to 32) and
Enable Output (D6 = 1).
0
X
1
X
X
X
X
X
1
Disable Output. Disable Specified Output (D6 = 0).
1
0
0
0
1
X
<Binary Input Number>
Broadcast Connection. Connect all 17 outputs to
same designated input and set all 17 enable bits to
the value of D6. Readback is not possible with the
broadcast address.
1
0
0
1
0
X
0
0
0
0
Reserved. Any address or data code greater or equal
to these are reserved for future expansion or factory
testing.
*The binary output number may also be the broadcast connection designator, 10001X.
REV. 0
–12–
AD8150
Control Interface Timing Diagrams
CS INPUT
WE INPUT
A[4:0] INPUTS
D[6:0] INPUTS
tCSW
tCHW
tASW
tAHW
tWP
tDSW
tDHW
Figure 25. First Rank Write Cycle
Table III. First Rank Write Cycle
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tCSW
tASW
tDSW
Setup Time
Hold Time
Chip Select to Write Enable
Address to Write Enable
Data to Write Enable
TA = 25°C
VDD = 5 V
VCC = 5 V
0
0
15
ns
ns
ns
tCHW
tAHW
tDHW
Chip Select from Write Enable
Address from Write Enable
Data from Write Enable
0
0
0
ns
ns
ns
tWP
Width of Write Enable Pulse
15
ns
CS INPUT
UPDATE INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS
DATA FROM RANK 1
TOGGLE
OUT[0:16][N:P]
OUTPUTS
PREVIOUS RANK 2 DATA
DATA FROM RANK 1
DISABLING
OUT[0:16][N:P]
OUTPUTS
DATA FROM RANK 2
tCSU
tCHU
tUW
tUOE
tUOD
tUOT
Figure 26. Second Rank Update Cycle
Table IV. Second Rank Update Cycle
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
tCSU
tCHU
tUOE
tUOT
tUOD
Setup Time
Hold Time
Output Enable Times
Output Toggle Times Update to Output Reprogram
Output Disable Times Update to Output Disabled
Chip Select to Update
Chip Select from Update
Update to Output Enable
TA = 25°C
VDD = 5 V
VCC = 5 V
0
0
ns
ns
ns
ns
ns
25
25
25
40
40
30
tUW
Width of Update Pulse
15
ns
REV. 0
–13–
AD8150
CS INPUT
UPDATE INPUT
WE INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS
INPUT {DATA 1}
INPUT {DATA 1}
INPUT {DATA 2}
DISABLING
OUT[0:16][N:P]
OUTPUTS
INPUT {DATA 0}
tCSU
tCHU
tUW
tWOT
tUOT
tUOE
tWHU
tWOD
Figure 27. First Rank Write Cycle and Second Rank Update Cycle
Table V. First Rank Write Cycle and Second Rank Update Cycle
Symbol
Parameter
Chip Select to Update
Conditions
Min
Typ
Max
Unit
tCSU
tCHU
Setup Time
Hold Time
TA = 25°C
VDD = 5 V
0
0
ns
ns
Chip Select from Update
tUOE
tWOE
Output Enable Times
Update to Output Enable
Write Enable to Output Enable
VCC = 5 V
25
25
40
40
ns
ns
*
tUOT
Output Toggle Times
Output Disable Times
Update to Output Reprogram
Write Enable to Output Reprogram
25
25
30
30
ns
ns
tWOT
tUOD
tWOD
*
Update to Output Disabled
Write Enable to Output Disabled
25
25
30
30
ns
ns
tWHU
Setup Time
Write Enable to Update
10
15
ns
ns
tUW
Width of Update Pulse
*Not Shown.
CS INPUT
RE INPUT
A[4:0]
INPUTS
ADDR 1
ADDR 2
DATA
{ADDR1}
D[6:0]
OUTPUTS
DATA {ADDR2}
tCSR
tCHR
tAA
tRDE
tRHA
tRDD
Figure 28. Second Rank Readback Cycle
Table VI. Second Rank Readback Cycle
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
tCSR
tCHR
tRHA
Setup Time
Hold Time
Chip Select to Read Enable
Chip Select from Read Enable
Address from Read Enable
TA = 25°C
VDD = 5 V
VCC = 5 V
0
0
5
ns
ns
ns
tRDE
tAA
tRDD
Enable Time
Access Time
Release Time
Data from Read Enable
Data from Address
Data from Read Enable
10 kΩ
20 pF on D[6:0]
Bus
15
15
15
ns
ns
ns
30
REV. 0
–14–
AD8150
RESET INPUT
DISABLING
OUT[0:16][N:P]
OUTPUTS
tTOD
tTW
Figure 29. Asynchronous Reset
Table VII. Asynchronous Reset
Symbol
Parameter
Disable Time
Width of Reset Pulse
Conditions
Min
Typ
Max
Unit
tTOD
tTW
Output Disable from Reset
TA = 25°C
VDD = 5 V
VCC = 5 V
25
30
ns
ns
15
Control Interface Programming Example
The following conservative pattern connects all outputs to input number 7, except output 16 which is connected to input number 32.
The vector clock period, T0 is 15 ns. It is possible to accelerate the execution of this pattern by deleting vectors 1, 4, 7, and 9.
Table VIII. Basic Test Pattern
Vector No.
Reset
CS
WE
RE
Update
A[4:0]
D[6:0]
Comments
0
1
0
1
1
1
1
1
1
1
1
1
xxxxx
xxxxx
xxxxxxx
xxxxxxx
Disable All Outputs
2
3
4
1
1
1
0
0
0
1
0
1
1
1
1
1
1
1
10001
10001
10001
1000111
1000111
1000111
All Outputs to Input #07
Write to First Rank
5
6
7
1
1
1
0
0
0
1
0
1
1
1
1
1
1
1
10000
10000
10000
1100000
1100000
1100000
Output #16 to Input #32
Write to First Rank
8
9
10
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
xxxxx
xxxxx
xxxxx
xxxxxxx
xxxxxxx
xxxxxxx
Transfer to Second Rank
Disable Interface
REV. 0
–15–
AD8150
7
CONTROL PIN DESCRIPTION
A[4:0] Inputs
TO 17ꢀ33
SWITCH
MATRIX
UPDATE RESET
33
7
Output address pins. The binary encoded address applied to
these five input pins determines which one of the seventeen
outputs is being programmed (or being read back). The most
significant bit is A4.
7
7
7
7
7
0
1
2
0
1
2
33
33
7
7
7
7
7
D[0:6]
7
D[6:0] Inputs/Outputs
Input configuration data pins. In write mode, the binary encoded
data applied to pins D[6:0] determine which one of 33 inputs is
to be connected to the output specified with the A[4:0] pins.
The most significant bit is D5, and the least significant bit is
D0. Bit D6 is the enable bit, setting the specified output sig-
nal pair to an enabled state if D6 is logic HIGH, or disabled
to a high-impedance state if D6 is logic LOW.
33
7
7
7
7
16
16
RANK 1
RANK 2
1 OF 33
DECODERS
17 ROWS OF 7-BIT
LATCHES
WE
In readback mode, pins D[6:0] are low-impedance outputs indi-
cating the data word stored in the second rank for the output
specified with the A[4:0] pins. The readback drivers were designed
to drive high impedances only, so external drivers connected
to the D[6:0] should be disabled during readback mode.
1 OF 17 DECODERS
A[0:4]
RE
WE Input
First Rank Write Enable. Forcing this pin to logic LOW allows
the data on pins D[6:0] to be stored in the first rank latch for
the output specified by pins A[4:0]. The WE pin must be returned
to a logic HIGH state after a write cycle to avoid overwriting
the first rank data.
Figure 30. Control Interface (Simplified Schematic)
AD8150 CONTROL INTERFACE
The AD8150 control interface receives and stores the desired
connection matrix for the 33 input and 17 output signal pairs.
The interface consists of 17 rows of double-rank 7-bit latches,
one row for each output. The 7-bit data word stored in each
of these latches indicates to which (if any) of the 33 inputs the
output will be connected.
UPDATE Input
Second Rank Write Enable. Forcing this pin to logic LOW allows
the data stored in all 17 first rank latches to be transferred to the
second rank latches. The signal connection matrix will be repro-
grammed when the second rank data is changed. This is a global
pin, transferring all 17 rows of data at once. It is not necessary
to program the address pins. It should be noted that after initial
power-up of the device, the first rank data is undefined. It may
be desirable to preprogram all seventeen outputs before performing
the first update cycle.
One output at a time can be preprogrammed by addressing the
output and writing the desired connection data into the first
rank of latches. This process can be repeated until each of the
desired output changes has been preprogrammed. All output
connections can then be programmed at once by passing the
data from the first rank of latches into the second rank. The out-
put connections always reflect the data programmed into the
second rank of latches, and do not change until the first rank of
data is passed into the second rank.
RE Input
Second Rank Read-Enable. Forcing this pin to logic LOW enables
the output drivers on the bidirectional D[6:0] pins, entering the
readback mode of operation. By selecting an output address with
the A[4:0] pins and forcing RE to logic LOW, the 7-bit data
stored in the second rank latch for that output address will be
written to D[6:0] pins. Data should not be written to the D[6:0]
pins externally while in readback mode. The RE and WE pins
are not exclusive, and may be used at the same time, but data
should not be written to the D[6:0] pins from external sources
while in readback mode.
If necessary for system verification, the data in the second rank
of latches can be read back from the control interface.
At any time, a reset pulse can be applied to the control interface
to globally reset the appropriate second rank data bits, disabling
all 17 signal output pairs. This feature can be used to avoid out-
put bus contention on system start-up. The contents of the first
rank remain unchanged.
The control interface pins are connected via logic-level transla-
tors. These translators allow programming and readback of the
control interface using logic levels different from those in the
signal matrix.
CS Input
Chip-Select. This pin must be forced to logic LOW in order
to program or receive data from the logic interface, with the
exception of the RESET pin, described below. This pin has
no effect on the signal pairs and does not alter any of the stored
control data.
In order to facilitate multiple chip address decoding, there is a
chip-select pin. All logic signals except the reset pulse are ignored
unless the chip select pin is active. The chip select pin disables
only the control logic interface, and does not change the opera-
tion of the signal matrix. The chip select pin does not power
down any of the latches, so any data programmed in the latches
is preserved.
RESET Input
Global Output Disable Pin. Forcing the RESET pin to logic
LOW will reset the enable bit, D6, in all 17 second rank
latches, regardless of the state of any other pins. This has the
effect of immediately disabling the 17 output signal pairs in the
All control pins are level-sensitive, not edge-triggered.
REV. 0
–16–
AD8150
matrix. It is useful to momentarily hold RESET at a logic LOW
state when powering up the AD8150 in a system that has mul-
tiple output signal pairs connected together. Failure to do this
may result in several signal outputs contending after power-up.
The reset pin is not gated by the state of the chip-select pin, CS.
It should be noted that the RESET pin does not program the
first rank, which will contain undefined data after power-up.
In order to maintain signal fidelity at the high data rates supported
by the AD8150, the input transmission lines should be terminated
as close to the input pins as possible. The preferred input termi-
nation structure will depend primarily on the application and
the output circuit of the data source. Standard ECL compo-
nents have open emitter outputs that require pull-down resistors.
Three input termination networks suitable for this type of source
are shown in Figure 32. The characteristic impedance of the trans-
mission line is shown as ZO. The resistors, R1 and R2, in the
Thevenin termination are chosen to synthesize a VTT source
with an output resistance of ZO and an open-circuit output volt-
age equal to VCC – 2 V. The load resistors (RL) in the differential
termination scheme are needed to bias the emitter followers of
the ECL source.
CONTROL INTERFACE TRANSLATORS
The AD8150 control interface has two supply pins, VDD and
V
SS. The potential between the positive logic supply VDD and
the negative logic supply VSS must be at least 3 V and no more
than 5 V. Regardless of supply, the logic threshold is approxi-
mately 1.6 V above VSS, allowing the interface to be used with
most CMOS and TTL logic drivers.
V
V
CC
CC
V
– 2V
CC
The signal matrix supplies, VCC and VEE, can be set indepen-
dent of the voltage on VDD and VSS, with the constraints that
(VDD–VEE) ≤ 10 V. These constraints will allow operation of
the control interface on 3 V or 5 V while the signal matrix is
operated on 3.3 V or 5 V PECL, or –3.3 V or –5 V ECL.
R1
R1
Z
Z
Z
Z
O
O
INxxN
INxxN
O
O
INxxP
O
INxxP
Z
V
Z
R2
R2
O
ECL SOURCE
ECL SOURCE
CIRCUIT DESCRIPTION
V
= VCG2V
CC
EE
(a) TT
(b)
The AD8150 is a high-speed 33 × 17 differential crosspoint switch
designed for data rates up to 1.5 Gbps per channel. The AD8150
supports PECL-compatible input and output levels when operated
from a 5 V supply (VCC = 5 V, VEE = GND) or ECL-compatible
V
Z
O
INxxN
INxxP
levels when operated from a –5 V supply (VCC = GND, VEE
=
2Z
Z
O
O
–5 V). To save power, the AD8150 can run from a 3.3 V supply
to interface with low-voltage PECL circuits or a –3.3 V supply
to interface with low-voltage ECL circuits. The AD8150 utilizes
differential current mode outputs with individual disable control,
which facilitates busing together the outputs of multiple AD8150s
to assemble larger switch arrays. This feature also reduces sys-
tem crosstalk and can greatly reduce power dissipation in a large
switch array. A single external resistor programs the current for
all enabled output stages, allowing for user control over output
levels with different output termination schemes and transmis-
sion line characteristic impedances.
R
L
R
L
ECL SOURCE
V
EE
(c)
Figure 32. AD8150 Input Termination from ECL/PECL
Sources: a) Parallel Termination Using VTT Supply, b)
Thevenin Equivalent Termination, c) Differential Termination
If the AD8150 is driven from a current mode output stage such
as another AD8150, the input termination should be chosen
to accommodate that type of source, as explained in the fol-
lowing section.
High-Speed Data Inputs (INxxP, INxxN)
The AD8150 has 33 pairs of differential voltage-mode inputs.
The common-mode input range extends from the positive sup-
ply voltage (VCC) down to include standard ECL or PECL input
levels (VCC – 2 V). The minimum differential input voltage is
less than 300 mV. Unused inputs may be connected directly to
any level within the allowed common-mode input range. A sim-
plified schematic of the input circuit is shown in Figure 31.
High-Speed Data Outputs (OUTyyP, OUTyyN)
The AD8150 has 17 pairs of differential current-mode outputs.
The output circuit, shown in Figure 33, is an open-collector
NPN current switch with resistor-programmable tail current and
output compliance extending from the positive supply voltage
(VCC) down to standard ECL or PECL output levels (VCC – 2 V).
The outputs may be disabled individually to permit outputs
from multiple AD8150’s to be connected directly. Since the
output currents of multiple enabled output stages connected
in this way sum, care should be taken to ensure that the out-
put compliance limit is not exceeded at any time; this can be
achieved by disabling the active output driver before enabling
any inactive driver.
V
CC
INxxN
INxxP
V
EE
Figure 31. Simplified Input Circuit
REV. 0
–17–
AD8150
V
V
CC
CC
R
COM
V
COM
OUTyyP
OUTyyN
R
R
AD8150
OUTyyN
L
L
V
– 2V
CC
OUTyyP
Z
Z
O
O
AD8150
OUTyyN
OUTyyP
Z
Z
O
O
I
DISABLE
OUT
R
R
L
L
V
EE
V
EE
Figure 33. Simplified Output Circuit
RECEIVER
To ensure proper operation, all outputs (including unused output)
must be pulled high using external pull-up networks to a level
within the output compliance range. If outputs from multiple
AD8150s are wired together, a single pull-up network may be
used for each output bus. The pull-up network should be chosen
to keep the output voltage levels within the output compliance
range at all times. Recommended pull-up networks to produce
PECL/ECL 100K and 10K compatible outputs are shown in
Figure 34. Alternatively, a separate supply can be used to pro-
vide VCOM; making RCOM and DCOM unnecessary.
Figure 35. Double Termination of AD8150 Outputs
In this case, the output levels are:
V
OH = VCOM – (1/4) IOUTRL
OL = VCOM – (3/4) IOUTRL
SWING = VOH – VOL = (1/2) IOUTRL
V
V
Output Current Set Pin (REF)
A simplified schematic of the reference circuit is shown in Fig-
ure 36. A single external resistor connected between the REF
pin and VEE determines the output current for all output stages.
This feature allows a choice of pull-up networks and transmission
line characteristic impedances while still achieving a nominal
output swing of 800 mV. At low data rates, substantial power
savings can be achieved by using lower output swings and higher
load resistances.
V
CC
V
CC
R
D
COM
COM
V
V
COM
COM
R
R
L
R
R
L
L
L
OUTyyN
OUTyyN
OUTyyP
AD8150
OUTyyP
AD8150
I
/25
AD8150
OUT
V
CC
Figure 34. Output Pull-Up Networks: a) ECL 100K,
b) ECL 10K
REF
SET
1.25V
The output levels are simply:
R
V
OH = VCOM
OL = VCOM – IOUTRL
VSWING = VOH – VOL = IOUTRL
COM = VCC – IOUT COM (100K Mode)
COM = VCC – V (DCOM) (10K Mode)
V
EE
V
Figure 36. Simplified Reference Circuit
The resistor value current is given by the following expression:
V
R
25
V
RSET
=
IOUT
The common-mode adjustment element (RCOM or DCOM) may
be omitted if the input range of the receiver includes the positive
supply voltage. The bypass capacitors reduce common-mode
perturbations by providing an ac short from the common nodes
(VCOM) to ground.
Example:
R
SET = 1.54 kΩ for IOUT = 16.2 mA
The minimum set resistor is RSET,min = 1 kΩ resulting in IOUT,max
25 mA. The maximum set resistor is RSET,max = 5 kΩ result-
ing in IOUT,min = 5 mA. Nominal 800 mV output swings can be
achieved in a 50 Ω load using RSET = 1.56 kΩ (IOUT = 16.2 mA)
or in a doubly-terminated 75 Ω load using RSET = 1.17 kΩ (IOUT
= 21.3 mA).
=
When busing together the outputs of multiple AD8150s or when
running at high data rates, double termination of its outputs is
recommended to mitigate the impact of reflections due to open
transmission line stubs and the lumped capacitance of the
AD8150 output pins. A possible connection is shown in Figure
35; the bypass capacitors provide an ac short from the common
nodes of the termination resistors to ground. To maintain signal
fidelity at high data rates, the stubs connecting the output pins
to the output transmission lines or load resistors should be as
short as possible.
To minimize stray capacitance and avoid the pickup of unwanted
signals, the external set resistor should be located close to the
REF pin. Bypassing the set resistor is not recommended.
REV. 0
–18–
AD8150
Power Supplies
the part is to be ac coupled, it is not necessary to have the input/
output common mode at the same level as the other system cir-
cuits, but it will probably be more convenient to use the same
supply rails for all devices.
There are several options for the power supply voltages for the
AD8150, as there are two separate sections of the chip that require
power supplies. These are the control logic and the high-speed
data paths. Depending on the system architecture, the voltage
levels of these supplies can vary.
For PECL operation, VEE will be at ground potential and VCC
will be a positive voltage from 3.3 V to 5 V. Thus, the common
mode of the inputs and outputs will be at a positive voltage.
These can then be dc coupled to other PECL operated devices.
If the data paths are ac coupled, then the common-mode levels
do not matter, see Figure 38.
Logic Supplies
The control (programming) logic is CMOS and is designed to
interface with any of the various standard single-ended logic
families (CMOS or TTL). Its supply voltage pins are VDD (Pin
170, logic positive) and VSS (Pin 152, logic ground). In all cases
the logic ground should be connected to the system digital ground.
3V TO 5V
3V TO 5V
V
DD should be supplied at between 3.3 V to 5 V to match the
0.1ꢃF
(ONE FOR EACH V PIN, 4 REQ'D.)
0.1ꢃF
supply voltage of the logic family that is used to drive the logic
inputs. VDD should be bypassed to ground with a 0.1 µF ceramic
capacitor. The absolute maximum voltage from VDD to VSS
is 5.5 V.
CC
V
V
CC
DD
AD8150
DATA
PATHS
CONTROL
LOGIC
Data Path Supplies
The data path supplies have more options for their voltage lev-
els. The choices here will affect several other areas, like power
dissipation, bypassing, and common mode levels of the inputs
and outputs. The more positive voltage supply for the data paths
is VCC (Pins 41, 98, 149 and 171). The more negative supply is
VEE, which appears on many pins that will not be listed here.
The maximum allowable voltage across these supplies is 5.5 V.
V
V
EE
SS
GND
GND
Figure 38. Power Supplies and Bypassing for PECL
Operation
POWER DISSIPATION
The first choice in the data path power supplies is to decide
whether to run the device as ECL (Emitter-Coupled Logic) or
PECL (Positive ECL). For ECL operation, VCC will be at ground
potential, while VEE will be at a negative supply between –3.3 V
to –5 V. This will make the common-mode voltage of the inputs
and outputs at a negative voltage, see Figure 37.
For analysis, the power dissipation of the AD8150 can be divided
into three separate parts. These are the control logic, the data
path circuits and the (ECL or PECL) outputs, which are part of
the data path circuits, but can be dealt with separately. The first
of these, the control logic, is CMOS technology and does not
dissipate a significant amount of power. This power will, of
course, be greater when the logic supply is 5 V rather than 3 V,
but overall it is not a significant amount of power and can be
ignored for thermal analysis.
3V TO 5V
GND
V
0.1ꢃF
V
DD
CC
AD8150
V
V
CC
DD
R
OUT
AD8150
DATA
PATHS
CONTROL
LOGIC
I
OUT
DATA
PATHS
CONTROL
LOGIC
V
V
EE
SS
I, DATA PATH
LOGIC
V
LOW – V
EE
OUT
0.1ꢃF
(ONE FOR EVERY TWO V PINS)
GND
EE
V
V
EE
SS
3V TO 5V
GND
GND
Figure 37. Power Supplies and Bypassing for ECL
Operation
Figure 39. Major Power Consumption Paths
The data path circuits operate between the supplies VCC and
VEE. As described in the power supply section, this voltage can
range from 3.3 V to 5 V. The current consumed by this section
will be constant, so operating at a lower voltage can save about
40 percent in power dissipation.
If the data paths are to be dc-coupled to other ECL logic devices
that run with ground as the most positive supply and a negative
voltage for VEE, then this is the proper way to run. However, if
REV. 0
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AD8150
the pin leads can provide an even lower thermal resistive path. If
possible to use, 2 oz. copper foil will provide better heat removal
than 1 oz.
The power dissipated in the data path outputs is affected by several
factors. The first is whether the outputs are enabled or disabled.
The worst case occurs when all of the outputs are enabled.
The AD8150 package has a specified thermal impedance θJA of
30°C/W. This is the worst case, still-air value that can be expected
when the circuit board does not significantly enhance the heat
removal from the package. By using the concept described above
or by using forced-air circulation, the thermal impedance can be
lowered.
The current consumed by the data path logic can be approxi-
mated by:
I
CC = 30 mA + [4.5 mA + (IOUT/20 mA × 3 mA)]
× (# of outputs enabled)
This says that there will always be a minimum of 30 mA flow-
ing. ICC will increase by a factor that is proportional to both the
number of enabled outputs and the programmed output current.
For an extreme worst case analysis, the junction rise above the
ambient can be calculated assuming 2 W of power dissipation
and θJA of 30°C/W to yield a 60°C rise above the ambient. There
are many techniques described above that can mitigate this situa-
tion. Most actual circuits will not result in this high a rise of the
junction temperature above the ambient.
The power dissipated in this circuit section will simply be the
voltage of this section (VCC – VEE) times the current. For a worst
case, assume that VCC – VEE is 5.0 V, all outputs are enabled
and the programmed output current is 25 mA. The power dissi-
pated by the data path logic will be:
APPLICATIONS
AD8150 INPUT AND OUTPUT BUSING
P = 5.0 V {25 mA + [4.5 mA + (25 mA/20 mA × 3 mA)]
× 17} = 826 mW
Although the AD8150 is a digital part, in any application that
runs at high speed, analog design details will have to be given very
careful consideration. At high data rates, the design of the signal
channels will have a strong influence on the data integrity and
its associated jitter and ultimately bit error rate (BER).
The power dissipated by the output current depends on several
factors. These are the programmed output current, the voltage
drop from a logic low output to VEE and the number of enabled
outputs. A simplifying assumption is that one of each (enabled)
differential output pair will be low and draw the full output cur-
rent (and dissipate most of the power for that output), while the
complementary output of the pair will be high and draw insig-
nificant current. Thus, its power dissipation of the high output
can be ignored and the output power dissipation for each output
can be assumed to occur in a single static low output that sinks
the full output-programmed current.
While it might be considered very helpful to have a suggested cir-
cuit board layout for any particular system configuration, this is
not something that can be practically realized. Systems come in
all shapes, sizes, speeds, performance criteria and cost constraints.
Therefore, some general design guidelines will be presented
that can be used for all systems and judiciously modified where
appropriate.
The voltage across which this current flows can also vary, depend-
ing on the output circuit design and the supplies that are used
for the data path circuitry. In general, however, there will be a
voltage difference between a logic low signal and VEE. This is
the drop across which the output current flows. For a worst
case, this voltage can be as high as 3.5 V. Thus, for all outputs
enabled and the programmed output current set to 25 mA, the
power dissipated by the outputs:
High-speed signals travel best, i.e. maintain their integrity, when
they are carried by a uniform transmission line that is properly
terminated at either end. Any abrupt mismatches in impedance
or improper termination will create reflections that will add to
or subtract from parts of the desired signal. Small amounts of
this effect are unavoidable, but too much will distort the signal
to the point that the channel BER will increase. It is difficult to
fully quantify these effects, because they are influenced by many
factors in the overall system design.
P = 3.5 V (25 mA) × 17 = 1.49 W
A constant-impedance transmission line is characterized by
having a uniform cross-section profile over its entire length. In
particular, there should be no “stubs,” which are branches that
intersect the main run of the transmission line. These can have
an electrical “appearance” that is approximated by a lumped
element, such as a capacitor, or if long enough, as another trans-
mission line. To the extent that stubs are unavoidable in a design,
their effect can be minimized by making them as short as pos-
sible and as high an impedance as possible.
HEAT SINKING
Depending on several factors in its operation, the AD8150 can
dissipate upwards of 2 W or more. The part is designed to oper-
ate without the need for an explicit external heatsink. However,
the package design offers enhanced heat removal via some of the
package pins to the PC board traces.
The VEE pins on the input sides of the package (Pins 1 to 46 and
Pins 93 to 138) have “finger” extensions inside the package
that connect to the “paddle” upon which the IC chip is mounted.
These pins provide a lower thermal resistance from the IC to
the VEE pins than other pins that just have a bond wire. As a
result these pins can be used to enhance the heat removal pro-
cess from the IC to the circuit board and ultimately to the ambient.
Figure 35 shows a differential transmission line that connects
two differential outputs from AD8150s to a generic receiver. A
more generalized system can have more outputs bused, and
more receivers on the same bus, but all the same concepts apply.
The inputs of the AD8150 can also be considered as a receiver.
The transmission lines that bus all of the devices together are
shown with terminations at each end.
The VEE pins described above should be connected to a large area
of circuit board trace material in order to take most advantage
their lower thermal resistance. If there is a large area available
on an inner layer that is at VEE potential, then vias can be pro-
vided from the package pin traces to this layer. There should be
no thermal-relief pattern when connecting the vias to the inner
layers for these VEE pins. Additional vias in parallel and close to
The individual outputs of the AD8150 are stubs that intersect
the main transmission line. Ideally, their current-source outputs
would be infinite impedance, and they would have no effect on
signals that propagate along the transmission line. In reality, each
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AD8150
external pin of the AD8150 projects into the package, and has a
bond wire connected to the chip inside. On-chip wiring then
connects to the collectors of the output transistors and to ESD
protection diodes.
of the program signals can be a piece of test equipment, like the
Tektronix HFS-9000 digital test generator, or some other user-
supplied hardware that generates programming signals.
When using the PC interface, the jumper at W1 should be in-
stalled and no connections should be made to P3. When using
the P3 interface, no jumper is installed at W1. There are loca-
tions for termination resistors for the address and data signals if
these are necessary.
Unlike some other high-speed digital components, the AD8150
does not have on-chip terminations. While this location would
be closer to the actual end of the transmission line for some
architectures, this concept can limit system design options. In
particular, it is not possible to bus more than two inputs or
outputs on the same transmission line and it is also not possible
to change the value of these terminations to use for different
impedance transmission lines. The AD8150, with the added
ability to disable its outputs, is much more versatile in these
types of architectures.
Power Supplies
The AD8150 is designed to work with standard ECL logic levels.
This means that VCC is at ground and VEE is at a negative sup-
ply. The shells of the I/O SMB connectors are at VCC potential.
Thus, when operating in the standard ECL configuration, test
equipment can be directly connected to the board, as the test
equipment will have its connector “shells” at ground potential also.
If the external traces are kept to a bare minimum, then the out-
put will present a mostly lumped capacitive load of about 2 pF.
A single stub of 2 pF will not seriously adversely affect signal in-
tegrity for most transmission lines, but the more of these stubs,
the more adverse their influence will be.
Operating in PECL mode requires VCC to be at a positive volt-
age, while VEE is at ground. Since this would make the shells of
the I/O connectors at a positive voltage, it can cause problems
when directly connecting to test equipment. Some equipment,
such as battery operated oscilloscopes, can be “floated” from
ground, but care should be taken with line-powered equipment
such that a dangerous situation is not created. Refer to the manual
of the test equipment that is being used.
One way to mitigate this effect is to locally reduce the capacitance
of the main transmission line near the point of stub intersection.
Some practical means for doing this are to narrow the PC board
traces in the region of the stub and/or to remove some of the
ground plane(s) near this intersection. The effect of these tech-
niques will locally lower the capacitance of the main transmission
line at these points, while the added capacitance of the AD8150
outputs will “compensate” for this reduction in capacitance.
The overall intent is to create as uniform a transmission line as
possible.
The voltage difference from VCC to VEE can range from 3 V to 5 V.
Power savings can be realized by operating at a lower voltage
without any compromise in performance.
A separate connection is provided for VTT, the termination po-
tential of the outputs. This can be at a voltage as high as VCC
,
but power savings can be realized if VTT is at a voltage that is
somewhat lower. Please consult elsewhere in the data sheet for
the specification for the limits of the VTT supply.
In selecting the location of the termination resistors it is impor-
tant to keep in mind that, as their name implies, they should be
placed at either end of the line. There should be no or minimal
projection of the transmission line beyond the point where the
termination resistors connect to it.
As a practical matter, current on the evaluation board will flow
from the VTT supply, through the termination resistors and then
through the AD8150 from its outputs to the VEE supply. When
running in ECL mode, VTT will want to be at a negative supply.
EVALUATION BOARD
An evaluation board has been designed and is available to rapidly
test the main features of the AD8150. This board lets the user
analyze the analog performance of the AD8150 channels and
easily control the configuration of the board by a standard PC.
Most power supplies will not allow their ground to connect to
V
CC and then the negative supply to VTT. This will require them
to source current from their negative supply, which will not re-
turn to the ground terminal. Thus, VTT should be referenced to
V
EE when running in ECL mode or a true bipolar supply should
Differential inputs and outputs provide the interface for all chan-
nels with the connections made by a 50 Ω, SMB-type connector.
This type of connector was chosen for its rapid mating and
unmating action. The use of SMB-type connectors minimizes
the size and minimizes the effort of rearranging interconnects
that would be required by using connectors such as SMA-type.
be used.
The digital supply is provided to the AD8150 by the VDD and
VSS pins. VSS should always be at ground potential to make it com-
patible with standard CMOS or TTL logic. VDD can range from
3 V to 5 V and should be matched to the supply voltage of the
logic used to control the AD8150. However, since PCs use 5 V
logic on their parallel port, VDD should be at 5 V when using a
PC to program the AD8150.
Configuration Programming
The board is configurable by one of two methods. For ease of
use, custom software is provided that controls the AD8150
programming via the parallel port of a PC. This requires a user-
supplied standard printer cable that has a DB-25 connector at
one end (parallel- or printer-port interface) and a Centronix-
type connector at the other that connects to P2 of the AD8150
evaluation board. The programming with this scheme is done in
a serial fashion, so it is not the fastest way to configure the AD8150
matrix. However, the user interface makes it very convenient to
use this programming method.
Software Installation
The software to operate the AD8150 is provided on two 3.5"
floppy disks. The software is installed by inserting Disk 1 into
the floppy drive of a PC and running the “setup.exe” program.
This will routinely install the software and prompt the user when to
change to Disk 2. The setup program will also prompt the user
to select the directory location to store the program.
If a high-speed programming interface is desired, the AD8150
address and data buses are directly available on P3. The source
REV. 0
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AD8150
Software Operation
After running the software, the user will be prompted to identify
which (of three) software driver is used with the PC’s parallel
port. The default is LPT1, which is most commonly used. How-
ever, some laptops commonly use the PRN driver. It is also
possible that some systems are configured with the LPT2 driver.
Any button can be clicked in the matrix to program the input
to output connection. This will send the proper programming
sequence out the PC parallel port. Since only one input can be
programmed to a given output at one time, clicking a button in
a horizontal row will cancel the other selection that is already
selected in that row. However, any number of outputs can share
the same input. Refer to Figure 40.
If it is not known which driver is used, it is best to select LPT1
and proceed to the next screen. This will show a full array of
“buttons” that allows the connection of any input to output of
the AD8150. All of the outputs should be in the output “OFF”
state right after the program starts running. Any of the active
buttons can be selected with a mouse click which will send out
one burst of programming data.
A shortcut for programming all outputs to the same input is to
use the broadcast feature. After clicking on the Broadcast Con-
nection button, a window will appear that will prompt for the
user to select which input should be connected to all outputs.
The user should type in an integer from 0 to 32 and then click
on OK. This will send out the proper program data and return
to the main screen with a full column of buttons selected under
the chosen input.
After this, the PC keyboard’s left or right arrow keyboard key
can be held down to generate a steady stream of programming
signals out of the parallel port. The CLOCK test point on the
AD8150 evaluation board can be monitored with an oscilloscope
for any activity (user-supplied printer cable must be connected).
If there is a square-wave present, then the proper software driver
is selected for the PC’s parallel port.
The Off column can be used to disable to whichever output one
chooses. To disable all outputs, the Global Reset button can be
clicked. This will select the full column of OFF buttons.
Two scratchpad memories (Memory 1 and Memory 2) are pro-
vided to conveniently save a particular configuration. However,
these registers are erased when the program is terminated. For
long-term storage of configurations, the disk-storage memory
should be used. The Save and Load selections can be accessed
from the “File” pull-down menu under the title bar.
If there is no signal present, then another driver should be tried
by selecting the Parallel Port menu item under the “File” pull-
down menu selection just under the title bar. Select a different
software driver and carry out the above test until signal activity
is present at the CLOCK test point.
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AD8150
Figure 40.
–23–
REV. 0
AD8150
Figure 41. Component Side
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AD8150
Figure 42. Circuit Side
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AD8150
Figure 43. Silkscreen Top
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AD8150
Figure 44. Soldermask Top
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AD8150
Figure 45. Silkscreen Bottom
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AD8150
Figure 46. Soldermask Bottom
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AD8150
Figure 47. INT1 (VEE)
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AD8150
Figure 48. INT2 (VCC
)
REV. 0
–31–
AD8150
V
EE
C29
V
CC
0.01ꢃF
1
2
3
4
5
6
7
8
9
V
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
V
EE
EE
PIN 1
IDENTIFIER
IN20P
IN20N
IN12N
IN12P
V
EE
V
C31
EE
IN21P
IN21N
IN11N
IN11P
V
CC
0.01ꢃF
V
V
C32 EE
EE
IN22P
IN22N
IN10N
IN10P
V
CC
0.01ꢃF
10
V
V
EE
EE
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
IN23P
IN23N
IN09N
IN09P
V
V
EE
EE
IN24P
IN24N
IN08N
IN08P
V
V
EE
EE
IN25P
IN25N
IN07N
IN07P
V
V
EE
EE
IN26P
IN26N
IN06N
IN06P
V
V
AD8150
EE
EE
IN27P
IN27N
IN05N
IN05P
184L LQFP
TOP VIEW
(Not to Scale)
V
V
EE
EE
IN28P
IN28N
IN04N
IN04P
V
V
EE
EE
IN29P
IN29N
IN03N
IN03P
V
V
EE
EE
IN30P
IN30N
IN02N
IN02P
V
V
EE
EE
IN31P
IN31N
IN01N
IN01P
V
V
EE
EE
IN32P
IN32N
IN00N
IN00P
V
V
EE
EE
V
98
V
EE
C11
CC
V
V
97
V
EE
CC
0.01ꢃF
V
EE
EE
V
OUT16N
OUT16P
96
OUT00P
OUT00N
C60
0.01ꢃF
CC
C15
95
0.01ꢃF
V
94
V
EE
EE
93
V
V
EE
EE
Figure 49. Bypassing Schematic
REV. 0
–32–
AD8150
Figure 50.
–33–
REV. 0
AD8150
Figure 51.
–34–
REV. 0
AD8150
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
184-Lead Plastic LQFP
(ST-184)
0.063 (1.60)
MAX
0.866 (22.00) BSC SQ
0.787 (20.00) BSC SQ
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
186
1
139
138
PIN 1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.003 (0.08)
46
47
93
92
0.006 (0.15)
0.002 (0.05)
0.016 (0.40)
BSC
0.009 (0.23)
0.007 (0.18)
0.005 (0.13)
0.057 (1.45)
0.053 (1.40)
0.048 (1.35)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
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–35–
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