AD8152_技术文档

34

؋

34, 3.2 Gbps

a

Asynchronous Digital Crosspoint Switch

AD8152^*

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Low Cost

Low Power

VCC

2.0 W @ 2.5 V (Outputs Enabled)

<100 mW @ 2.5 V (Outputs Disabled)

34

؋

34, Fully Differential, Nonblocking Array

3.2 Gbps per Port NRZ Data Rate

Wide Power Supply Range: 2.5 V to 3.3 V

LVTTL or LVCMOS Level Control Inputs:

@ 2.5 V to 3.3 V

34

INP

OUTP

VTTO

34

؋

34

DIFFERENTIAL

SWITCH MATRIX

OUTPUT

LEVEL

DACs

VTTI

OUTN

INN

Low Jitter: 45 ps

MATRIX

CONNECTION

LATCHES

CONNECTION

DECODE

D[5:0]

Drives a Backplane Directly

Programmable Output Swing

100 mV to 1.6 V Differential

50 ⍀ On-Chip I/O Termination

User Controlled Voltage at the Load

Minimizes Power Dissipation

Dual Rank Latches

OUTPUT

LEVEL

LATCHES

RESET

CS

A[6:0]

RE

CONTROL

LOGIC

WE

Available in 256-Ball Grid Array

AD8152

UPDATE

APPLICATIONS

Fiber Optic Network Switching

High Speed Serial Backplane Routing to OC-48 with FEC

Gigabit Ethernet

VEE

Digital Video (HDTV)

Data Storage Networks

GENERAL DESCRIPTION

AD8152 is a member of the Xstream line of products and is a

breakthrough in digital switching, offering a large switch array

(34 × 34) on very little power, typically 2.0 W. Additionally, it

operates at data rates up to 3.2 Gbps per port, making it suitable

for Sonet/SDH OC-48 with Forward Error Correction (FEC).

The AD8152’s useful supply voltage range allows the user to

operate at LVPECL/CML data levels down to 2.5 V. The control

interface is LVTTL or LVCMOS compatible on 2.5 V to 3.3 V.

The AD8152’s fully differential signal path reduces jitter and

crosstalk while allowing the use of smaller single-ended voltage

swings. It is offered in a 256-ball SBGA package that operates

over the industrial temperature range of 0°C to 85°C.

80ps/DIV

Figure 1. Eye Pattern, 3.2 Gbps, PRBS 23

*Patent Pending

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

AD8152

ELECTRICAL CHARACTERISTICS ^{(@ 25؇C, VCC = 2.5 V to 3.3 V, VEE= 0 V, R = 50 ⍀, Differential Output Swing = 800 mV p-p,}

unless otherwise noted.)

L

Parameter

Condition

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Max Data Rate/Channel (NRZ)

Channel Jitter

RMS Channel Jitter

Propagation Delay

3.2

Gbps

ps p-p

ps

Data Rate £ 3.2 Gbps; PRBS 2²³– 1

Input to Output

45

<10

660

±50

100

800

±120

Propagation Delay Match

Output Rise/Fall Time

20% to 80%

ps

INPUT CHARACTERISTICS

Input Voltage Swing

Input Voltage Range

Input Bias Current

Single-Ended (See TPC 14)

Common-Mode (See TPC 15)

50

1000

VCC + 0.2

mV p-p

V

mA

pF

VEE + 0.8

2

Input Capacitance

OUTPUT CHARACTERISTICS

Output Voltage Swing

Output Voltage Range

Output Current

Differential (See TPC 18)

100

VCC – 1.2

2

800

2

1600

VCC + 0.2

32

mV p-p

V

mA

pF

Output Capacitance

TERMINATION CHARACTERISTICS

Resistance

Temperature Coefficient

43

50

0.05

57

W

W/∞C

POWER SUPPLY

Operating Range

VCC

Quiescent Current

VCC

VEE = 0 V

2.25

3.63

45

V

All Outputs Disabled

All Outputs Enabled

All Outputs Disabled

All Outputs Enabled

32

190

32

770

800

mA

VEE

45

T_MINto T_MAX,All Outputs Enabled

LOGIC INPUT CHARACTERISTICS

Input High (VIH)

Input Low (VIL)

Input High (VIH)

Input Low (VIL)

VCC = 3.3 V

VCC = 2.5 V

2

V

0.8

0.7

1.7

LOGIC OUTPUT CHARACTERISTICS

Output High (VOH)

Output Low (VOL)

Output High (VOH)

Output Low (VOL)

VCC = 3.3 V, IOH = –2 mA

VCC = 3.3 V, IOL = +2 mA

VCC = 2.5 V, IOH = –100 uA

VCC = 2.5 V, IOL = +100 uA

2.4

2.1

V

0.4

0.2

THERMAL CHARACTERISTICS

Operating Temperature Range

0

85

∞C

␪

Still Air

200 lfpm

400 lfpm

15

12

11

∞C/W

JA

Specifications subject to change without notice.

–2–

REV. A

AD8152

ABSOLUTE MAXIMUM RATINGS¹

16

14

12

10

8

Tj = 150؇C

VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 V

VTTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.6 V

VTTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.6 V

Internal Power Dissipation²

AD8152 256-Ball SBGA (BP) . . . . . . . . . . . . . . . . . . 8.33 W

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.6 V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 1.7 V

Logic Input Voltage . . . . . . VEE – 0.3 V < V_IN< VCC + 0.6 V

Storage Temperature Range . . . . . . . . . . . . . –65°C to +125°C

Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . 300°C

400 lfpm

200 lfpm

STILL AIR

6

4

NOTES

2

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

0

10

20

30

40

50

60

70

80

90

AMBIENTTEMPERATURE – ؇C

Figure 2. Maximum Power Dissipation vs. Temperature

²Specification is for the device in free air (T_A= 25°C): ␪_JA= 15°C/W @ still air.

a shift in parametric performance due to a change in the stresses

exerted on the die by the package. Exceeding a junction tem-

perature of 175°C for an extended period can result in device

failure. To ensure proper operation, it is necessary to observe the

maximum power derating curves shown in Figure 2.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD8152 is

limited by the associated rise in junction temperature. The maxi-

mum safe junction temperature for plastic encapsulated devices

is determined by the glass transition temperature of the plastic,

approximately 150°C. Temporarily exceeding this limit may cause

ORDERING GUIDE

Model

Temperature Range

Package Description

AD8152JBP

AD8152-EVAL

0°C to 85°C

256-Ball SBGA (27 mm × 27 mm)

Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD8152 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

REV. A

–3–

AD8152

BALL GRID ARRAY

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

VEE

VCC

VTTO

O14P

VTTO

O11P

VCC

O08P

VTTO

O05P

VTTO

O02P

VTTO

VCC

VEE

A

B

C

D

E

A

B

C

D

E

F

VEE

D4

VEE

D5

VCC

VTTO

O15P

O15N

O14N

O13N

O13P

VTTO

O12P

O12N

O11N

O10N

VCC

O09P

O09N

O08N

O07N

O07P

VTTO

O06P

O06N

O05N

O04N

O04P

VTTO

O03P

O03N

O02N

O01N

O01P

VTTO

O00P

O00N

VCC

A6

VEE

A5

VEE

O16N

O16P

O10P

A4

A3

D0

D1

RESET

RE

D2

N/C

D3

N/C

A2

A1

CS

N/C

UPDATE

WE

A0

I17P

I18N

I17N

I18P

I00N

I01P

I03N

I04P

I06N

I07P

I09N

I10P

I12N

I13P

I15N

I16P

VEE

VCC

I00P

I01N

I03P

I04N

I06P

I07N

I09P

I10N

I12P

I13N

I15P

I16N

VEE

VCC

I19P

VTTI

I22P

VTTI

I25P

F

G

H

J

VCC

I02P

VTTI

I05P

VTTI

I08P

VCC

I11P

VTTI

I14P

VTTI

VCC

VEE

I19N

VTTI

I22N

VTTI

I25N

VCC

I02N

VTTI

I05N

VTTI

I08N

VCC

I11N

VTTI

I14N

VTTI

VCC

VEE

G

H

J

I20P

I21N

I20N

I21P

K

L

I23P

I24N

I23N

I24P

K

L

M

N

P

R

T

VCC

I28P

VTTI

I26P

I27N

I26N

I27P

M

N

P

R

T

I28N

VTTI

I29P

I30N

I32P

I33N

VEE

I29N

I30P

I32N

I33P

VEE

I31P

VTTI

I31N

VTTI

O33P

O33N

VCC

O32N

O32P

VTTO

O30P

O30N

O31N

O29N

O29P

O27P

O27N

O26N

O26P

VCC

O24P

O24N

O25N

O23N

O23P

VTTO

O21P

O21N

O22N

O20N

O20P

VTTO

O18P

O18N

O19N

O17N

O17P

VTTO

U

V

W

Y

VCC

VEE

VCC

VEE

U

V

W

Y

VTTO O28N

VEE

20

VEE

19

VEE

18

VEE

17

VCC

16

VTTO

15

O31P

14

VTTO

13

O28P

12

VCC

11

O25P

10

VTTO

9

O22P

8

VTTO

7

O19P

6

VTTO

5

VCC

4

VEE

3

VEE

2

VEE

1

Ball Diagram, View from the Bottom

–4–

REV. A

AD8152

BALL GRID DESCRIPTIONS

Ball Mnemonic Type

Description

A1 VEE

A2 VEE

A3 VEE

Power

I/O

Power

I/O

Power

I/O

Negative Supply

Positive Supply

C12 OUT10N

C13 OUT12P

C14 OUT13N

C15 OUT15P

C16 OUT16N

C17 D5

C18 D4

C19 VEE

C20 VEE

D1 A1

I/O

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

A4 VCC

A5 VTTO

A6 OUT02P

A7 VTTO

A8 OUT05P

A9 VTTO

A10 OUT08P

A11 VCC

A12 OUT11P

A13 VTTO

A14 OUT14P

A15 VTTO

A16 VCC

A17 VEE

A18 VEE

A19 VEE

A20 VEE

B1 VEE

B2 VEE

B3 VEE

B4 VCC

B5 VTTO

B6 OUT02N I/O

B7 VTTO

B8 OUT05N I/O

B9 VTTO

B10 OUT08N I/O

B11 VCC

B12 OUT11N I/O

B13 VTTO

B14 OUT14N I/O

B15 VTTO

B16 VCC

B17 VEE

B18 VEE

B19 VEE

B20 VEE

C1 VEE

C2 VEE

C3 A5

Output Termination Supply

High Speed Output

Output Termination Supply

High Speed Output

Output Termination Supply

High Speed Output

Positive Supply

High Speed Output

Output Termination Supply

High Speed Output

Output Termination Supply

Positive Supply

Negative Supply

Positive Supply

Output Termination Supply

High Speed Output Complement

Output Termination Supply

High Speed Output Complement

Output Termination Supply

High Speed Output Complement

Positive Supply

High Speed Output Complement

Output Termination Supply

High Speed Output Complement

Output Termination Supply

Positive Supply

Negative Supply

High Speed Output Complement

Control Input Address Pin (MSB)

Control Input Address Pin

Power

Control Output Address Pin

I/O

Negative Supply

Power

I/O

Power

I/O

D2 A2

D3 A3

D4 A4

D5 OUT00N

D6 OUT01P

D7 OUT03N

D8 OUT04P

D9 OUT06N

D10 OUT07P

D11 OUT09N

D12 OUT10P

D13 OUT12N

D14 OUT13P

D15 OUT15N

D16 OUT16P

D17 D3

D18 D2

D19 D1

D20 D0

E1 A0

E2 UPDATE

E3 N/C Reserved

E4 N/C Reserved

E17 N/C Reserved

E18 N/C Reserved

E19 RESET

E20 CS

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

Power

Control Input Address Pin

Control Input Address Pin (LSB)

Control Output Address Pin (LSB)

Control Second Rank Write Enable

Do Not Connect

Power

Do Not Connect

Power

Control Reset/Disable Outputs

Control Chip Select Enable

Power

F1 VCC

F2 WE

Positive Supply

Control First Rank Write Enable

F3 IN00P

F4 IN00N

F17 IN17N

F18 IN17P

F19 RE

I/O

High Speed Input

High Speed Input Complement

High Speed Input

Control Output Address Pin (MSB)

Control Output Address Pin (Bank Des.)

C4 A6

Control Readback Enable

C5 OUT00P

I/O

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

F20 VCC

Power

I/O

Positive Supply

High Speed Input

High Speed Input Complement

High Speed Input

C6 OUT01N I/O

C7 OUT03P I/O

C8 OUT04N I/O

C9 OUT06P I/O

C10 OUT07N I/O

G1 IN02P

G2 IN02N

G3 IN01N

G4 IN01P

G17 IN18P

G18 IN18N

I/O

High Speed Input

High Speed Input Complement

C11 OUT09P

I/O

REV. A

–5–

AD8152

BALL GRID DESCRIPTIONS (continued)

Ball Mnemonic Type

Description

G19 IN19N

G20 IN19P

H1 VTTI

H2 VTTI

H3 IN03P

H4 IN03N

H17 IN20N

H18 IN20P

H19 VTTI

H20 VTTI

I/O

Power

I/O

Power

I/O

High Speed Input Complement

High Speed Input

Input Termination Supply

High Speed Input

High Speed Input Complement

High Speed Input

Input Termination Supply

High Speed Input

P2

P3

P4

VTTI

IN12P

IN12N

Power

I/O

Power

I/O

Input Termination Supply

High Speed Input

High Speed Input Complement

High Speed Input

Input Termination Supply

High Speed Input

High Speed Input Complement

High Speed Input

P17 IN29N

P18 IN29P

P19 VTTI

P20 VTTI

R1 IN14P

R2 IN14N

R3 IN13N

R4 IN13P

R17 IN30P

R18 IN30N

R19 IN31N

R20 IN31P

T1 VTTI

I/O

J1

J2

J3

J4

IN05P

IN05N

IN04N

IN04P

High Speed Input

High Speed Input Complement

High Speed Input

High Speed Input Complement

High Speed Input

Input Termination Supply

High Speed Input

High Speed Input Complement

High Speed Input

Input Termination Supply

Positive Supply

High Speed Input Complement

High Speed Input

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Input

High Speed Input Complement

Positive Supply

I/O

J17 IN21P

J18 IN21N

J19 IN22N

J20 IN22P

K1 VTTI

K2 VTTI

K3 IN06P

K4 IN06N

K17 IN23N

K18 IN23P

K19 VTTI

K20 VTTI

L1 IN08P

L2 IN08N

L3 IN07N

L4 IN07P

L17 IN24P

L18 IN24N

L19 IN25N

L20 IN25P

M1 VCC

High Speed Input

Power

I/O

High Speed Input Complement

High Speed Input

Input Termination Supply

High Speed Input Complement

High Speed Input

High Speed Input Complement

High Speed Input

Input Termination Supply

High Speed Input

T2 VTTI

T3 IN15P

T4 IN15N

T17 IN32N

T18 IN32P

T19 VTTI

T20 VTTI

U1 VCC

U2 VCC

U3 IN16N

U4 IN16P

U5 OUT17N

U6 OUT18P

U7 OUT20N

U8 OUT21P

U9 OUT23N

U10 OUT24P

U11 OUT26N

U12 OUT27P

U13 OUT29N

U14 OUT30P

U15 OUT32N

U16 OUT33P

U17 IN33P

U18 IN33N

U19 VCC

I/O

Power

I/O

Power

I/O

Power

I/O

Power

I/O

High Speed Input Complement

High Speed Input

High Speed Input Complement

High Speed Input

Positive Supply

I/O

Power

I/O

M2 VCC

M3 IN09P

M4 IN09N

M17 IN26N

M18 IN26P

M19 VCC

High Speed Input

High Speed Input Complement

High Speed Input

Positive Supply

I/O

Power

I/O

M20 VCC

U20 VCC

V1 VEE

V2 VEE

V3 VEE

N1 IN11P

N2 IN11N

N3 IN10N

N4 IN10P

N17 IN27P

N18 IN27N

N19 IN28N

N20 IN28P

High Speed Input

Negative Supply

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Input Complement

High Speed Input

V4 VEE

High Speed Input

V5 OUT17P

V6 OUT18N

V7 OUT20P

V8 OUT21N

High Speed Input Complement

High Speed Input

I/O

Power

High Speed Output Complement

P1

VTTI

Input Termination Supply

–6–

REV. A

AD8152

BALL GRID DESCRIPTIONS (continued)

Ball Mnemonic Type

Description

V9 OUT23P

V10 OUT24N

V11 OUT26P

V12 OUT27N

V13 OUT29P

V14 OUT30N

V15 OUT32P

V16 OUT33N

V17 VEE

V18 VEE

V19 VEE

V20 VEE

W1 VEE

I/O

Power

I/O

Power

I/O

Power

I/O

Power

I/O

Power

I/O

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Output Complement

High Speed Output

High Speed Output Complement

Negative Supply

W15 VTTO

W16 VCC

W17 VEE

W18 VEE

W19 VEE

W20 VEE

Y1 VEE

Y2 VEE

Y3 VEE

Y4 VCC

Y5 VTTO

Y6 OUT19P

Y7 VTTO

Y8 OUT22P

Y9 VTTO

Y10 OUT25P

Y11 VCC

Y12 OUT28P

Y13 VTTO

Y14 OUT31P

Y15 VTTO

Y16 VCC

Y17 VEE

Power

I/O

Power

I/O

Power

I/O

Power

I/O

Power

I/O

Output Termination Supply

Positive Supply

Negative Supply

Positive Supply

Output Termination Supply

High Speed Output

Output Termination Supply

High Speed Output

Output Termination Supply

High Speed Output

Positive Supply

High Speed Output

Output Termination Supply

High Speed Output

Output Termination Supply

Positive Supply

Negative Supply

Positive Supply

W2 VEE

W3 VEE

W4 VCC

W5 VTTO

W6 OUT19N

W7 VTTO

W8 OUT22N

W9 VTTO

W10 OUT25N

W11 VCC

W12 OUT28N

W13 VTTO

W14 OUT31N

Output Termination Supply

High Speed Output Complement

Output Termination Supply

High Speed Output Complement

Output Termination Supply

High Speed Output Complement

Positive Supply

High Speed Output Complement

Output Termination Supply

High Speed Output Complement

Power

Negative Supply

Y18 VEE

Y19 VEE

Y20 VEE

REV. A

–7–

AD8152–Typical Performance Characteristics _{(2.5 V Supply, VCC = VTTI = VTTO, Data Rate = 3.2 Gbps;}

PRBS 2²³–1; Differential Output Swing = 800 mV p-p; R_L= 50 ⍀; Input Amplitude = 0.4 V p-p Single-Ended; unless otherwise noted.)

80ps/DIV

200ps/DIV

TPC 1. Eye Pattern 3.2 Gbps

TPC 4. Eye Pattern 1.5 Gbps

PEAK-PEAK JITTER = 35ps STD DEV = 5.2ps

20ps/DIV

PEAK-PEAK JITTER = 35ps STD DEV = 5.1ps

20ps/DIV

TPC 5. Jitter @ 1.5 Gbps

TPC 2. Jitter @ 3.2 Gbps

1.2ns/DIV

2.5ns/DIV

TPC 3. Response, 3.2 Gbps, 32-Bit Pattern

1111 1111 0000 0000 1010 1010 1100 1100

TPC 6. Response, 1.5 Gbps, 32-Bit Pattern

1111 1111 0000 0000 1010 1010 1100 1100

–8–

REV. A

AD8152

1.E+00

1.E–01

1.E–02

1.E–03

1.E–04

1.E–05

1.E–06

1.E–07

1.E–08

1.E–09

1.E–10

1.E–11

1.E–12

1400

1200

1000

800

BINWIDTH = 5ps

600

400

200

0

–0.5

–0.3 –0.2 –0.1

0

0.1

0.2

0.3

0.4 0.5

–0.4

–50 –40 –30 –20 –10

0

10

20

30

40

50

UNIT INTERVAL

DUTY CYCLE DISTORTION – ps

TPC 7. Duty Cycle Distortion Distribution

TPC 10. Bit Error Rate vs. Unit Interval

100

90

80

70

60

50

40

30

20

10

0

V

@ DATA RATE

@ 0.5Gbps

OUT

؋

100

%EYE HEIGHT =

V

OUT

1.0

2.0

2.5

3.0

3.5

4.0

0.5

1.5

DATA RATE – Gbps

PEAK-PEAK JITTER = 35ps STD DEV = 5.6ps

80ps/DIV

TPC 8. Eye Height vs. Data Rate

TPC 11. Crosstalk, 3.2 Gbps, Attack Signal OFF

(See TPC 25)

50

45

40

PEAK-PEAK JITTER

35

30

25

20

15

10

STANDARD DEVIATION

5

0

1.0

2.0

2.5

3.0

3.5

4.0

1.5

DATA RATE – Gbps

PEAK-PEAK JITTER = 46ps STD DEV = 6.5ps

80ps/DIV

TPC 9. Jitter vs. Data Rate

TPC 12. Crosstalk, 3.2 Gbps, Attack Signal ON

(See TPC 25)

REV. A

–9–

AD8152

55

80

70

50

45

40

35

30

60

50

1.5 Gbps

PEAK-PEAK JITTER

40

30

20

10

0

3.2 Gbps

STANDARD DEVIATION

25

0

1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

SUPPLY VOLTAGE – V

10

20

30

40

50

60

70

80

90

TEMPERATURE – ؇C

TPC 16. Jitter vs. Supply

TPC 13. Single Point Jitter vs. Temperature

120

100

80

160

140

120

100

80

I

= 16mA

OUT

I

= 24mA

I

OUT

60

PEAK–PEAK JITTER

= 32mA

OUT

60

40

20

STANDARD DEVIATION

0

–1.4

–1.2

–1.0

–0.8

–0.6

– V

–0.4

–0.2

0

10

100

1000

INPUT AMPLITUDE – mV

V

OL

TPC 14. Jitter vs. Single-Ended Input Amplitude

TPC 17. Jitter vs. V_OL(Relative to VCC)

180

50

45

40

35

30

25

20

15

10

5

INPUT AMPLITUDE = 50mV p-p

160

140

PEAK–PEAK JITTER

120

100

@3.3V

@2.5V

80

60

STANDARD DEVIATION

40

20

0

0.5 0.8 1.1 1.4 1.7 2.0 2.3 2.6 2.9 3.2 3.5 3.8

INPUT CML – V

0

5

10

15

I

20

– mA

25

30

35

OUT

TPC 18. Jitter vs. Programmed I_OUT

TPC 15. Jitter vs. Input Common-Mode Level

–10–

REV. A

AD8152

750

725

700

675

650

160

140

120

100

80

BINWIDTH = 5ps

60

40

625

600

20

0

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

600

625

650

675

700

725

750

SUPPLYVOLTAGE –V

PROPAGATION DELAY – ps

TPC 21. Propagation Delay vs. Supply

TPC 19. Variation in Propagation Delay

800

34

32

30

28

26

24

780

760

740

720

700

680

660

640

620

600

MEASURED

22

20

18

IDEAL

16

14

12

10

8

6

4

2

0

10

20

30

40

50

60

70

80

90

0

1

2

3

4

5

6

7

8

10 11 12 13 14 15 16

9

TEMPERATURE – ؇C

I

CODE

OUT

TPC 20. Propagation Delay vs. Temperature

TPC 22. I_OUTvs. I_OUTCode

REV. A

–11–

AD8152

VCC

VTTI

VTTO

PATTERN

GENERATOR

HIGH SPEED

SAMPLING

OSCILLOSCOPE

DATA OUT

–6dB

IN##P

–6dB

OUT##P

50⍀

AD8152

DATA OUT

IN##N

OUT##N

50⍀

TRIGGER OUT

VEE = –2.5V

TRIGGER IN

I

= 16mA, V

HI = 0V,V

OUT OUT

LO = –0.4V

OUT

23

V

AMPLITUDE = 400mV p-p SINGLE-ENDED, V HI = –0.2V PRBS 2 – 1

IN

TPC 23. Negative Supply Test Circuit

2.5V

VCC

HIGH SPEED

SAMPLING

OSCILLOSCOPE

VTTI

PATTERN

GENERATOR

VTTO

0.1␮F

DATA OUT

OUT##P

–6dB

IN##P

50⍀

AD8152

–6dB

OUT##N

DATA OUT

IN##N

50⍀

0.1␮F

TRIGGER OUT

VEE

TRIGGER IN

I

= 16mA, V

HI = 2.5V,V

LO = 2.1V

OUT

V

AMPLITUDE = 400mV p-p SINGLE-ENDED, V HI = 2.7V

IN

23

PRBS 2 – 1, INPUTS AND OUTPUTS ARE AC-COUPLED

TPC 24. Positive Supply Test Circuit

VCC

PATTERN

GENERATOR #1

ATTACK SIGNAL

VTTI

VTTO

IN25P

OUT00P...OUT26P

OUT28P...OUT33P

DATA OUT

–6dB

50⍀

OUT00N...OUT26N

OUT28N...OUT33N

–6dB

IN25N

DATA OUT

HIGH SPEED

SAMPLING

OSCILLOSCOPE

AD8152

PATTERN

GENERATOR #2

DATA OUT

–6dB

IN24P

IN24N

–6dB

OUT27P

50⍀

DATA OUT

OUT27N

50⍀

TRIGGER OUT

VEE = –2.5V

TRIGGER IN

ATTACK SIGNAL APPLIED TO IN25. IN25 BROADCAST TO ALL OUTPUTS EXCEPT OUT27.

TWO SEPARATE PATTERN GENERATORS USED TO PROVIDE INPUT PATTERN TO AD8152.

OUTPUTS NOT CONNECTED TO OSCILLOSCOPE ARE TERMINATED WITH EXTERNAL 50⍀ TO GND.

TPC 25. Crosstalk Test Circuit

–12–

REV. A

AD8152

Table I. Address and Data Buses

Output Address Pins

Connection/Current Bit

Data Pins

A6

A5 A4

A3

A2

A1

A0

D5

D4

D3

D2

D1

D0

0 = CONNECTION LATCHES

1 = OUTPUT CURRENT LEVEL

MSB

LSB

MSB

LSB

Table II. Connection Data and Address Programming Examples

Data Pins

Connection/

Current Bit

Output Address Pins

(Used to Select Inputs)

Comments

0 = CONNECTION

MSB

LSB

MSB

LSB

A6

0

A5 A4 A3 A2 A1 A0

D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Program IN00 to OUT00

Program IN33 to OUT00

Program IN31 to OUT33

Broadcast IN00 to All Outputs

Disable OUT00

Disable OUT33

Disable All Outputs (Broadcast)

Table III. Output-Current Level Data and Address Programming Examples

Data Pins

Connection/

Current Bit

Output Address Pins

(Used to Select Inputs)

LSB MSB

A5 A4 A3 A2 A1 A0 D5 D4 D3 D2 D1 D0

Comments

1 = CURRENT LEVEL MSB

LSB

A6

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

Program OUT00 to Current—Code 00 (2 mA)

Program OUT00 to Current—Code 15 (32 mA)

Program OUT33 to Current—Code 07 (16 mA)

Broadcast Current—Code 08 to All

Outputs (18 mA)

Table IV. Basic Control Strobe Functions

RESET CS WE RE UPD Function

0

1

X

1

0

X

0

X

0

X

1

0

X

1

X

0

Global Reset. Disables all outputs and resets all output current to code 0111 (16 mA).

Disable All Control Signals. Signal matrix/currents remain the same. D5:D0 are high impedance.

Write Enable. Write D5:D0 data into first rank register addressed by A6:A0.

Single-Output Readback. Second rank register data for output A6:A0 appears on D5:D0.

Global Update. Copy all first rank data into second rank registers.

0

Transparent Write and Update. D5:D0 immediately control programming. Use RE as gating signal.

REV. A

–13–

AD8152

CS

WE

A[6:0]INPUTS

D[5:0]INPUTS

t

CSW

ACHW

t

AHW

ASW

t

WP

t

DSW

t

DHW

Figure 3a. First Rank Write Cycle

Table V. First Rank Write Cycle

Conditions

Symbol

Parameter

Min

Typ

Max

Unit

t_CSW

t_ASW

t_DSW

Setup Time

Hold Time

Chip Select to Write Enable

Address to Write Enable

Data to Write Enable

T_A= 25؇C

0

1

ns

VCC = 3.3 V

t_CHW

t_AHW

t_DHW

Chip Select from Write Enable

Address from Write Enable

Data from Write Enable

0

ns

t_WP

Width of Write Enable Pulse

10

ns

CS

UPDATE

ENABLING

OUT[0:33][N:P]

OUTPUTS

DATA FROM RANK 1

TOGGLE

OUT[0:33][N:P]

OUTPUTS

PREVIOUS RANK 2 DATA

DATA FROM RANK 1

DISABLING

OUT[0:33][N:P]

OUTPUTS

DATA FROM RANK 2

t_CSU

t_CHU

t_UW

t_UOE

t_UOD

t_UOT

Figure 3b. Second Rank Update Cycle

Table VI. Second Rank Update Cycle

Conditions

Symbol

Parameter

Min

Typ

Max

Unit

t_CSU

t_CHU

t_UOE

t_UOT

t_UOD

Setup Time

Hold Time

Output Enable Times

Output Toggle Times

Output Disable Times

Chip Select to Update

T_A= 25؇C

0

ns

Chip Select from Update

Update to Output Enable

Update to Output Reprogram

Update to Output Disabled

VCC = 3.3 V

25

45

t_UW

Width of Update Pulse

10

ns

–14–

REV. A

AD8152

CS

UPDATE

WE

ENABLING

OUT[0:33][N:P]

OUTPUTS

INPUT {DATA 1}

INPUT {DATA 2}

DISABLING

OUT[0:33][N:P]

OUTPUTS

INPUT {DATA 0}

t_CSU

t_CHU

t_UW

t_WOT

t_UOT

t_UOE

t_WHU

t_WOD

Figure 4a. Transparent Write and Update Cycle

Table VII. Transparent Update Cycle

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_CSU

t_CHU

Setup Time

Hold Time

Chip Select to Update

Chip Select from Update

T_A= 25؇C

VCC = 3.3 V

0

ns

t_UOE

Output Enable Times

Output Toggle Times

Output Disable Times

Update to Output Enable

Write Enable to Output Enable

35

50

ns

t_WOE

t_UOT

t_WOT

t_UOD

t_WOD

*

Update to Output Reprogram

Write Enable to Output Reprogram

25

45

ns

*

Update to Output Disabled

Write Enable to Output Disabled

25

45

ns

t_WHU

Setup Time

Write Enable to Update

0

ns

t_UW

Width of Update Pulse

10

*Not shown

CS

RE

D[5:0]

INPUT

ADDR 1

ADDR 2

A[5:0]

OUTPUTS

DATA

DATA {ADDR 2}

{ADDR 1}

t_CSR

t_CHR

t_RDE

t_AA

t_RHA

t_RDD

Figure 4b. Second Rank Readback Cycle

Table VIII. Second Rank Readback Cycle

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_CSR

t_CHR

t_RHA

Setup Time

Hold Time

Chip Select to Read Enable

Chip Select from Read Enable

Address from Read Enable

T_A= 25؇C

VCC = 3.3 V

0

5

ns

t_RDE

t_AA

Enable Time

Access Time

Data from Read Enable

Data from Address

15

ns

30

REV. A

–15–

AD8152

RESET

DISABLING

OUT[0:33][N:P]

OUTPUTS

t_TOD

t_TW

Figure 5. Asynchronous Reset

Table IX. Asynchronous Reset

Conditions

Symbol

t_TOD

Parameter

Min

Typ

Max

Unit

ns

Disable Time

Output Disable from Reset

T_A= 25؇C

10

25

t_TW

Width of Reset Pulse

VCC = 3.3 V

10

ns

CONTROL INTERFACE

connected to the output specified with the A[5:0] pins. The most

significant bit is D5, and the least significant bit is D0. To disable

an output completely, the input address D[5:0] = “111111”

should be written into the input configuration bank at the desired

output address.

The AD8152 control interface receives and stores the desired

connection matrix and output levels for the 34 input and 34 output

signal pairs. The interface consists of 34 rows of double-rank

6-bit latches, one for each output. The 6-bit data-word stored

in these latches indicates to which (if any) of the 34 inputs the

output will be connected, as well as the full-scale output current.

In write mode, when the bank selection bit A6 is HIGH, the

binary encoded data applied to pins D[3:0] indicate the output

current level to be used for the output specified with the A[5:0]

pins. The reset default is “0111” for 16 mA. Each LSB is 2 mA.

One output at a time can be preprogrammed by addressing the

output and writing the desired connection data or output cur-

rent into the first rank of latches. This process can be repeated

until each of the desired output changes has been preprogrammed.

All output connections can then be programmed at once by passing

the data from the first rank of latches into the second rank. The

output connections always reflect the data programmed into the

second rank of latches and do not change until the first rank of

data is passed into the second rank.

In readback mode, pins D[5:0] are low impedance outputs

indicating the data-word stored in the second rank for the out-

put specified with the A[5:0] pins and the bank specified with

the A6 bit. The readback drivers were designed to drive high

impedances only, so external drivers connected to the D[5:0]

should be disabled during readback mode.

WE Input

If necessary for system verification, the data in the second rank

of latches can be read back from the control interface.

First rank write enable. Forcing this pin to logic low allows the

data on pins D[5:0] to be stored in the first rank latch for the

output specified by pins A[6:0]. The WE pin must be returned to a

logic high state after a write cycle to avoid overwriting the first

rank data.

At any time, a reset pulse can be applied to the control interface to

globally reset the appropriate second rank data bits, disabling all 34

signal output pairs and resetting the output currents. To facilitate

multiple chip address decoding, there is a chip select pin. All logic

signals except the reset pulse are ignored unless the chip select

pin is active. The chip select pin disables only the control logic

interface and does not change the operation of the signal matrix.

The chip select pin does not power down any of the latches, so any

data programmed in the latches is preserved.

UPDATE Input

Second rank write enable. Forcing this pin to logic low allows the

data stored in all 34 first rank latches (in both banks) to be trans-

ferred to the second rank latches. The signal connection matrix

will be reprogrammed when the second rank data and levels are

changed. This is a global pin, transferring all 34 rows of data at

once. It is not necessary to program the address pins. It should

be noted that after initial power-up of the device, the first rank

data is undefined. It is desirable to preprogram all 17 outputs

before performing the first update cycle.

All control pins are level-sensitive, not edge-triggered.

CONTROL PIN DESCRIPTION

A[6:0] Inputs

Output address pins. The binary encoded address applied to the

lower A[5:0] input pins determines which of the 34 outputs is

being programmed (or being read back). The most significant bit,

A6, determines whether the data pins contain information for

the connection register bank or the output level register bank.

Using the broadcast address, A[5:0] = “111111” will simulta-

neously program data into all outputs at once.

RE Input

Second rank read enable. Forcing this pin to logic low enables the

output drivers on the bidirectional D[5:0] pins, entering the read-

back mode of operation. By selecting an output address with the

A[6:0] pins and forcing RE to logic low, the 6-bit data stored in

the second rank latch for that output address will be written to

D[5:0] pins. Data should not be written to the D[5:0] pins

externally while in readback mode. The RE is a higher priority

pin than the WE pin, so first rank programming is not possible

while in readback mode.

D[5:0] Inputs/Outputs

Input configuration or output level data pins. In write mode,

when the bank selection bit A6 is LOW, the binary encoded data

applied to pins D[5:0] determine which of the 34 inputs is to be

–16–

REV. A

AD8152

CS Input

If it is desired to program all outputs to the same current level,

then the broadcast Code 63 can be placed on the address bus

(A5:A0), along with A6 = 1. (D3:D0) will then program all output

currents to the same level.

Chip select. This pin must be forced to logic low to program or

receive data from the logic interface, with the exception of the

RESET pin, described below. This pin has no effect on the signal

pairs and does not alter any of the stored control data.

When the current code is set to 0000, a minimum current level

of 2 mA is obtained. For any other code, the current can be

calculated by (current code) ¥ 2 mA + 2 mA. Refer to Table III.

For example, 16 mA can be programmed by Code 0111. This is

7 ¥ 2 mA + 2 mA = 16 mA.

RESET Input

Global output disable pin. Forcing the RESET pin to logic low

will disable all outputs, setting both ranks of all 34 input connec-

tion latches, regardless of the state of any other pins. This has the

effect of immediately disabling the 34 output signal pairs in the

matrix. The output level information is also changed. It is necessary

to momentarily hold RESET at a logic low state when powering

up the AD8152 in order to avoid random internal contention

where multiple inputs may be connected to one output. The

RESET pin is not gated by the state of the chip select pin, CS.

Register-Control Signals

Several single-ended logic input pins control the register loading

associated with the address and data buses described in the previ-

ous section. The control functions are tabulated in Table IV.

There are dual ranks of registers for the data that programs the

AD8152. The first rank registers accumulate the data for the

various outputs as they are being programmed one by one. The

second rank registers actually control the functions of the device.

Control Interface Levels

The AD8152 control interface shares the data path supply pins,

VCC and VEE. The potential between the positive logic supply

VCC and the negative supply VEEmust be at least 2.25 V and no

more than 3.63 V. Regardless of supply, the logic threshold is

approximately one-half the supply range, allowing the interface

to be used with most LVCMOS and LVTTL logic drivers.

The RESET signal is used to reset the connection matrix, disable

all outputs, and set all of the output currents to a default condition

at Code 0111. This action sets the output current to a nominal

value of 16 mA. The data in the first rank latches is also reset by

the assertion of RESET.

Output Addressing

The CS signal is used to enable the control interface. If several

devices are used in a system with the other control signals

bussed, the CS signal can be used to select an individual device

to change its programming.

The AD8152 is programmed using a memory interface module,

with parallel address and data buses. Six bits (A5:A0) are used to

address the outputs. By setting the decimal value of these address

bits to a value from 0 to 33 inclusive, then one of the 34 outputs

is uniquely addressed.

The WE signal is used to enable writing data to the first rank

registers. This data will not immediately affect the features of

the AD8152.

One additional code, 63 (all 1s), is used for the broadcast mode.

If this address is selected, then all outputs will receive the same

programming. The remaining addresses in the space are not

valid and are reserved, Codes 34 to 66 inclusive. (See Table I.)

The UPDATE signal transfers the data from the first rank registers

to the second rank registers. After assertion of UPDATE, the

data actively controls the AD8152 functions.

Connection and Output Current Programming

A seventh address bit (A6) determines which of two types of

programming is selected. If A6 = 0, connection matrix program-

ming is selected. If A6 = 1, output current programming is selected.

The second rank registers can be read back through the data bus.

The output is addressed on A5:A0 and the connection/current is

selected via A6. Asserting RE will cause the second rank data to

appear on the data bus. The RE function will dominate over

WE if both are asserted at the same time. Broadcast readback is

not permitted.

Using the Data Bus

Once it is determined which output is to be programmed (or broad-

cast to all outputs) and which type of programming (connection/

output-current), then the data bits (D5:D0) further define the

programming action.

Some typical programming waveforms for the control signals are

provided in Figure 6.

If the selection is connection programming (A6 = 0), then the data

bits select the input that is to be connected to the addressed

output. If the broadcast address is selected, then the data bits select

the input that will be connected to all 34 outputs. (See Table II.)

A[6:0

]

VALID ADDRESS INPUT

VALID DATA INPUT

VALID ADDRESS INPUT

VALID DATA INPUT

D[5:0

]

A disable code (D5:D0 = 63, or all 1s) is used to disable (and

power down) the particular output that is addressed. A broadcast

disable can be effected by setting Code 63 on both the address

bus and the data bus along with A6 = 0.

WE

UPDATE

Figure 6. Programming Waveforms

Output-Current Programming

A current source in each output can be digitally programmed to

any one of 16 different current levels. Changing these current

levels will change the amplitude of the output swing that is

developed across the internal 50 W termination resistors.

Input/Output Coupling

The AD8152 has internal 50 W termination resistors for each

single-ended input and output. This can also provide a 100 W

termination for a 100 W differential transmission line. All of the

input termination resistors connect to one common point called

VTTI. Similarly, each of the output termination resistors connects

to one common point called VTTO. The voltage can be set

independently at VTTI and VTTO to accommodate various

interface architectures.

To program the current for a particular output, its address is set on

A5:A0 (00–33), while A6 is set to 1. The four LSBs of the data

address (D3:D0) are then used to select one of the 16 output

current levels. D4 and D5 are “don’t cares” for output current

programming. (See Table III.)

REV. A

–17–

AD8152

Input Coupling

If VTTI is set equal to VCC, then the single-ended signal will

just meet the specifications where its highest excursion will be

0.2 V higher than VCC. The lowest level to set VTTI is 0.8 V

above VEE. This will cause the negative signal excursions to stay

within the operating range.

One way to simplify the input circuit and make it compatible with

a wide variety of driving devices is to use ac coupling. This has

the effect of isolating the dc common-mode levels of the driver

and the AD8152 input circuitry. For example, the XAUI inter-

connect specification for 10 Gbps Ethernet requires ac coupling

in order to ensure that there are no interactions of dc levels

between the transmitting and receiving devices.

With ac-coupled inputs, there is no power consumption advan-

tage associated with varying VTTI. As a practical matter, it

might be desirable to set VTTI at the same voltage as VTTO so

that only one supply is necessary. Refer to the VTTO section for

more information.

AC coupling requires that the signal patterns have no long-term

dc component, which may occur in any random data stream.

Codes such as 8b/10b, called for in the XAUI specification, are

used in many data communications systems to ensure that the

data pattern is benign in an ac-coupled link. This is accomplished

by run-length limiting (RLL), which sets a maximum for the

number of 1s or 0s that can occur consecutively. In addition,

residual dc components are monitored and modified by keeping

track of the running disparity, excess of 1s versus 0s or vice versa.

Output Coupling

Each single-ended output of the AD8152 has a termination

resistor that ties to a common point called VTTO. When VTTO

is varied, it will change the common-mode levels of the outputs

and the power dissipation of the output stages when they are

enabled.

The individual output currents are programmable. Varying this

current will change the lower level of the output voltage (and thus

the peak-to-peak swing) and also change the power dissipation in

the output stages. To obtain a standard 800 mV p-p differential

output (single-ended = 400 mV p-p), the output current should

be programmed to 16 mA. With an effective termination resis-

tance of 25 W, this will generate the proper differential voltage.

For the AD8152 inputs, ac coupling requires a capacitor in series

with each single-ended input signal, as shown in Figure 7. This

should be done in a manner that does not interfere with the high

speed signal integrity of the PC board. The details of this are

covered in the section on board layout guidelines. The two critical

variables are setting the proper voltage for VTTI and selecting

the correct value of coupling capacitors.

If the AD8152 drives another device that is ac-coupled, there is no

interaction of the dc levels on each side of the coupling capacitors

(see Figure 8). The dc levels for the AD8152 can be calculated

independent of the levels of the device that is driven.

VTTI

VCC

The upper allowable setting for VTTO is 0.2 V higher than VCC.

The signals will be pulled up to this level at their highest excursion.

However at this setting, the power dissipation will be a maximum.

50⍀

C

INP

INXXP

INXXN

To save power, VTTO can be lowered. The lowest level for

VTTO will be determined by the lowest output level allowable

(V_OL) by the AD8152 output when it is logically low. The output

at any time should not go lower than 1.0 V below VCC. If the

single-ended swing of an output is 400 mV p-p, then the lowest

that VTTO can go is 0.6 V below VCC. For more information

on V_OL, see TPC 17.

C

INN

VEE

Figure 7. AC-Coupling Input Signal from AD8152

On the AD8152 side of the input coupling capacitor, the average

value of the single-ended input voltage will be at the voltage set at

VTTI. The range of allowable voltages is a function of the accept-

able input voltages of the active circuitry of the AD8152 inputs

and the amplitude of the input signal. The operating input range

of the AD8152 extends from VCC + 0.2 V to 0.8 V above VEE.

VCC

VTTO

VTT

VCC

AD8152

50⍀

OUTXXP

OUTXXN

The total range that will be occupied by the input signal will be

its average value (as established by the voltage applied to VTTI)

plus or minus one half the single-ended swing of the signal. For a

standard 800 mV p-p differential signal, the single-ended swing is

400 mV p-p. Thus, the signal will swing ±200 mV about the

average value equal to VTTI.

DRIVEN DEVICE

VEE

I = 2mA

؋

(CODE) + 2mA

VEE

Figure 8. AC-Coupling Output Signal from AD8152

–18–

REV. A

AD8152

AD8152 POWER CONSUMPTION

is powered down. Thus, the total number of active inputs will

affect the total power consumption.

There are several sections of the AD8152 that draw varying

power depending on the supply voltages, the type of I/O coupling

used, and the status of the AD8152 operation. Figure 9 shows a

block diagram of these sections. These are described briefly below

and then in detail later in the data sheet. Table X summarizes the

power consumption of each section and is a useful guide as the

following sections are reviewed.

The core of the device performs the crosspoint switching function.

It draws a fixed quiescent current whenever the AD8152 is

powered from VCC to VEE.

An output predriver section draws a current that is proportional

to the programmed output current, I_OUT. This current always

flows from VCC to VEE. It is treated separately from the output

current, which flows from VTTO, and might not be the same

voltage as VCC.

The first section is the input termination resistors. The power

dissipated in the termination resistors is the result of their being

driven by the respective driving stage. Also, there might be dc power

dissipated in the input termination resistors if the inputs are

dc-coupled and the driving source reference is a dc voltage that is

not equal to VTTI.

The final section is the outputs. For an individual output, the

programmed output current will flow through two separate paths.

One is the on-chip termination resistor, and the other is the

transmission line and the destination termination resistor. The

nominal parallel impedance of these two paths is 25 W. The sum

In the next section, the active part of the input stages, each input

is powered only when it is selected. If an input is not selected, it

VCC

VTT

VTTO

VTTI

OUTPUT TERMINATIONS

I

OUT

50⍀

P =

50⍀

DRIVEN DEVICE

TERMINATIONS

2

50⍀

OUTP

OUTN

INP

INN

INPUT

OUTPUT

PRE-

SWITCH

MATRIX

OPTIONAL COUPLING CAPACITORS

)

TERMINATIONS

INPUTS

DRIVER

(V ) (I

P =

OL OUT

I = 2mA

PER

ACTIVE

INPUT

V

= V

– (I

؋

25⍀)

OUT

OUT-

PUTS

OL

TTO

2

(V

)

indiffrms

P =

I = .25 I

I = 32mA

OUT

100⍀

I

OUT

VEE

Figure 9. Power Consumption Block Diagram

Table X. Power Consumption

Output

Switch +

Current

Source

Input

Termination

Resistors

Output

Termination

Resistors

Input

Stage

Output

Predriver

Total

Power

Core

Quiescent Current

32 mA

Current per Active Channel

V_IN

/

(R_TERMINATION

)

2 mA

0.25 ¥ I_OUT0.5 ¥ I_OUT

I_OUT

Current per Active Channel

for Differential

V_IN= 800 mV p-p Sine

V_OUT= 800 mV p-p

566 mV rms/100

= 5.66 mA

2 mA

4 mA

8 mA

16 mA

2.5 V Operation (VCC – VEE = 2.5 V, VTTO = 2.5 V, I_OUT= 16 mA)

Per Channel Power

Power for All Channels Active 108.8 mW

Percentage of Total Power 5%

3.3 V Operation (VCC – VEE = 3.3 V, VTTO = 3.3 V, I_OUT= 16 mA)

Per Channel Power 3.2 mW 6.6 mW

Power for All Channels Active 108.8 mW

3.2 mW

5 mW

170 mW 80 mW

8%

10 mW

340 mW

17%

8 mW

272 mW

13.6%

33.6 mW

1.03 W

51%

2.0 W

4%

13.2 mW

8 mW

272 mW

10%

46.4 mW

1.47 W

56%

224 mW 106 mW 449 mW

2.63 W

Percentage of Total Power

4%

9%

4%

17%

REV. A

–19–

AD8152

of these two currents will flow through the switches and the current

source of the AD8152 output circuit and out through VEE.

OUTPUTS

The output current is forced by a current source that is pro-

grammed to a variable amount of current from 2 mA to 32 mA

in 2 mA steps. For the two logic switch states, this current flows

through an on-chip termination resistor and a parallel path to the

destination device and its termination resistor. The power in this

parallel path is not dissipated by the AD8152.

The power dissipated in the transmission line and the destination

resistor will not be dissipated in the AD8152, but will have to be

supplied from the power supply, and is a factor in the overall system

power. The current in the on-chip termination resistors and the

output current source will dissipate power in the AD8152 itself.

The nominal programmed output current is 16 mA. With the two

parallel 50 W resistors at each collector (25 W equivalent), this

current will create a 400 mV p-p swing in each half of the circuit.

The differential output voltage will be 800 mV p-p.

Input Termination Resistors

The power dissipated in the input termination resistors is

delivered by the driving source. First, assume the driving wave-

form for an individual input is a differential square wave with an

amplitude of Vinpp. Then the power dissipated in this input is

(Vinpp)²/2Rterm.

Under steady state conditions and with a data pattern that is

run-length limited so that its low frequency content is significantly

higher than the RC pole formed by the coupling capacitor and the

termination resistors, the common-mode level at the AD8152

outputs will be 400 mV lower than VTTO. Each output will then

swing ±200 mV from this level, which is a 400 mV p-p single-

ended output swing.

However, this result is quite pessimistic, because at high fre-

quencies, the wave shape is usually more sinusoidal than square.

If instead, a differential sine wave of amplitude Vinpp is assumed,

then its rms amplitude is 0.7 times that of a square wave. This will

yield a power that is one half of the square wave case. The assumed

wave shape is not too critical because the fraction of the power

dissipated in the input termination resistors is not very large.

At the high level, there will be 200 mV across the termination

resistor. This will dissipate a power of 0.8 mW. At the low level, the

600 mV across the termination resistor will dissipate a power of

7.2 mW. Since the output signal is basically 50% duty cycle, the

average power dissipated will be the average of these two values

or 4 mW. By symmetry, the other differential output will dissipate

the same power. This yields an on-chip termination-resistor

power dissipation of 8 mW per channel for each output, or 272 mW

for all 34 outputs.

A further effect is that the input signal might travel over a path

that attenuates the signal. This will usually be a function of

frequency. Thus, for such a case, some of the signal power will

be dissipated in the signal path. This will reduce the amount of

power dissipated in the AD8152 input terminations.

If dc coupling is used, a dc current will flow from VTTIthrough

the termination resistors if the dc voltage of the drive circuit is not

equal to VTTI. The additional power in each input termination

resistor will be the current that flows multiplied by the 50 W

value of the input terminations.

The full output current (from both on- and off-chip termination

resistors) will flow in the lower part of each output. This current

flows only in the side that is “on,” or in its low state (V_OL). This

voltage is 600 mV below the dc level at VTTO.

For a point of reference, assume a channel has a sinusoidal input of

800 mV p-p differential. The power dissipated for a single input

will be 3.2 mW. If all 34 input channels are driven the same, then

the power in the input terminations will be 109 mW.

Thus, for VTTO = 2.5 V, V_OL= 1.9 V, and the power dissipa-

tion for I_OUT= 16 mA is 30.4 mA. For all 34 channels, the

power is 1.03 W.

If VTTO = 3.3 V, then V_OL= 2.7 V. The single power is 43.2 mW

and the power for all 34 channels is 1.47 W.

Input Stage

The input stages are powered down when not in use. There is

about 2 mA that flows through an enabled input from VCC to VEE.

Thus, the power dissipated by an enabled input is 5 mW for a

supply of 2.5 V and 6.6 mW for a 3.3 V supply. For all 34 inputs

enabled, the respective figures are 170 mW for a 2.5 V supply

and 224 mW for a 3.3 V supply.

If VTTO = 2.5 V, then the additional power is given by 16 mA

¥ [(2.5 V – (16 mA ¥ 25 W)] = 33.6 mW. Thus, the total AD8152

power dissipation for this output is 37.6 mW.

If all 34 outputs are enabled with the same I_OUT, the total power

dissipation is 1.28 W. Thus it can be seen that the outputs are

the major contributor to the power dissipation.

Switch Matrix

The switch matrix draws a fixed 32 mA when the AD8152 is

powered. This current flows from VCC to VEE. The power dissi-

pation from this current is 80 mW at 2.5 V and 106 mW at 3.3 V.

Power Saving Considerations

While the AD8152 power consumption is very low compared to

similar devices, careful control of its operating conditions can yield

further power savings. Significant power reduction can be realized

by operating the part at a lower voltage. Compared to 3.3 V

operation, a supply voltage of 2.5 V can result in power savings of

about 25 percent. There is virtually no performance penalty when

operating at lower voltage.

Output Predrivers

The output predrivers draw additional current when each of the

outputs is enabled. This extra current is proportional to the

programmed output current. The extra predriver current for a

channel will be 25 percent of the programmed output current

for that channel. This current will also flow from VCC to VEE.

A second measure is to disable outputs when they are not being

used. This can be done on a static basis if the output is not used,

or on a dynamic basis if the output does not have a constant

stream of traffic.

When an output is enabled and programmed to 16 mA, an addi-

tional 4 mA will flow in the predriver section. This will dissipate

10 mW at 2.5 V or 13.2 mW at 3.3 V for an individual output.

For all 34 outputs enabled and programmed to 16 mA, the

predriver power will be 340 mW at 2.5 V or 449 mW at 3.3 V.

Since the majority of the power dissipated is in the output stage,

some of its flexibility can be used to lower the power consumption.

–20–

REV. A

AD8152

ALLTOP-MOUNT SMAs SIT ON PCB TOP LEVEL

First, the output current can be programmed to the smallest amount

required to maintain BER performance. If an output circuit

always has a short length and the receiver has good sensitivity,

then a lower output current can be used.

SMA CENTER PIN

PLANE RELIEF

MICROSTRIP

DRILL HOLES

(7 EACH)

It is also possible to lower the voltage on VTTO to lower the

power dissipation. The amount that VTTO can be lowered is

dependent on the lowest of all the output’s V_OL. This will be

determined by the output that is operating at the highest pro-

grammed output current since V_OL= VTTO – (I_OUT¥ 25 W).

TOP VIEW OF TOP LEVEL TRACE

BOTTOM VIEW OF BOTTOM LEVEL TRACE

Figure 10. Top-Mount SMA PCB Layout, Two Views

EVALUATION BOARD AND PCB LAYOUT HINTS

The AD8152 evaluation board was designed to allow the user to

analyze signal integrity in many configurations, as controlled by

a standard PC.

The FR4 PC board is eight layers with a thickness of 62 mils

(1.57 mm). The two outer most metal layers hold the high speed

microstrip routing lines. The two outer most dielectric layers are

5 mils thick and must be controlled impedance (50 W) layers. These

are the only two layers that require controlled impedance. The

next two inner metal layers are ground (reference) planes for the

microstrip and are the shell for the SMA connectors. The remain-

ing four inner metal layers are for the four AD8152 supply and

digital control signal routing. From top to bottom the four supply

layers are VTTO, VCC, VEE, and VTTI. Because all four supply

PCB metal layers float, positive, negative, and even dual-supply

configurations are possible. The variety of supply configurations

ease the connection of test equipment. The four inner supply

layers also provide an interlayer capacitance, which has better

impedance versus frequency than standard chip capacitors.

The FR4 board comes equipped with a full complement of

136 SMA connectors to support the complete 34 ϫ 34 matrix of

points. Each differential pair of microstrip is connected to either

top mount or side-launch SMA connectors. The mounting area of

the short center pin top-mount SMA connectors are drilled (seven

holes) and stubbed for greatly improved performance. In the

area surrounding SMA top-mount center pin and drill holes, all

internal planes are relieved or cleared out (see Figure 10 for layout).

DIELECTRIC

THICKNESS

COPPER

LAYER

THICKNESS/DESIGNATION

(IN OUNCES)

NUMBER

0.5mils

5.0mils

4.0mils

SILKSCREEN

1.

2.

3.

4.

5.

6.

1.50/TOP MICROSTRIPWIDTH = 8.0mils

0.50/GND

0.50/VTTO

0.50/VCC

0.50/VEE

0.50/VTTI

16.0mils

4.0mils

16.0mils

4.0mils

5.0mils

7.

8.

0.50/GND

1.50/BOTTOM MICROSTRIPWIDTH = 8.0mils

SILKSCREEN

0.5mils

Figure 11. Evaluation Board Stack-Up

–21–

REV. A

AD8152

Figure 12. Cross-Sectional Layout and Dimensioning (To Scale) of Differential

The variety of supply configurations cause the need for a supply

agile digital control circuitry. This is done by a programmable

logic device (PLD), which provides instructions to the AD8152.

The PLD supply is typically tied with jumpers across the AD8152’s

VCC and VEE supplies (Jumpers J3 and J4). The PLD is addressed

from the PC by way of digital isolators. These couplers isolate

PC levels from the PLD and allow for any level shifting. If

desired, the user can drive the PLD supply separately as long as

the VEE of the AD8152 and the PLD are tied together (remove

Jumper J3 and leave J4 installed). This allows one to measure

the AD8152 only supply current, for example.

During the layout of the differential microstrip, a software tool

snaps the distance between the two traces to be a constant. If

the distance is not kept constant, impedance variations will

result. These fluctuations can be measured by time domain

reflectometry (TDR).

EXTRA ADDED INDUCTANCE

Board Construction or Stack-Up

Figure 11 is a picture of AD8152 evaluation board stack-up from

top to bottom. The layer stack-up has been made symmetrical

to avoid board warpage during manufacture. The microstrip

layout and dimensions are shown in Figure 12. The microstrip

trace width was chosen to be 8 mils. This allows relative ease in

routing through the BGA rows that are 50 mils (1.27 mm) apart.

The outer two out of four rows of high speed signals are routed on

top of the PCB, while the inner two rows are via holed to the

board’s opposite side and then routed outward. Wider microstrip

is desirable for reducing eye height loss versus long traces; how-

ever, the routing will be more difficult as the AD8152 is approached.

The wide microstrip would have to be necked down in width in

order to be routed into the BGA. The necking will increase trace

impedance and therefore induce more signal reflection problems.

Figure 14. Poor Capacitor Layout

Bypass Capacitor Layout

The AD8152 8-layer PCB takes advantage of buried interlayer

capacitance. The VEE to VCC planes are placed in the very middle

of the board to make the highest value capacitor. The 4 mil

(0.102 mm) dielectric spacing between VCC/VEE yields 26 nF

of capacitance. Each AD8152 supply pin is directly connected to

its supply plane through a via hole beneath the BGA ball. The

via hole size for a BGA supply pin is slightly bigger than a signal

via. This is to reduce the inductance of the connection, and it

also happens to be a compact layout.

For the chip capacitors, the via holes are placed directly in the

middle of the mounting area and made as large as possible, i.e.,

greater than or equal to 35 mils (0.89 mm). This is to minimize

inductance as much as possible. By minimizing inductance, the

performance of the capacitor or impedance versus frequency

response is not greatly diminished. Note that chip capacitors

will work up to only about 300 MHz.

BGA CORNER OUTLINE

VIA HOLE

(GRAY)

Figure 14 is an example of a bypass capacitor layout that should

be avoided in any high speed printed circuit board. This layout

connects the chip capacitor mounting pads to small via holes

through a skinny PCB trace. This amounts to four extra inductors

added to the capacitor, two largely from the skinny surface traces

and two from small via holes. Inductance is also variable with

copper thickness and attachment method to power plane. Thermal

relief for soldering purposes also adds unwanted inductance and

should be avoided.

CHIP CAPACITOR

(805) SIZE

MICROSTRIPTRACES

Figure 13. BGA Corner Capacitor Layout

–22–

REV. A

AD8152

This would require VTTI to be attached to ground, causing

excessive power to be dissipated in the internal 50 W input

termination resistors. Secondly, when the AD8152 output tries

to drive its own input with VTTI = 0 V and VTTO = 2.5 V, the

input will pull the output stage levels down enough to shut off

any signal toggling.

VCC

VTTO

AD8152

All ac coupling shown is actually done with a set of bias tees. If

desired, the bias tee can be used to monitor average dc voltage

levels at an input or output (depending on direction installed),

and it can also serve to change input dc levels. Make sure the

bias tees used in the setup have enough low frequency bandwidth

to pass long patterns and keep edge rates intact. The longer the

pattern, the more low frequency bandwidth is needed.

P

OUT

TO 50⍀

SCOPE

INPUTS

ECL

DRIVER

IN

N

VEE = –2.5V

VTTI = –2V

If ac coupling is desired on a user board, 0402 or 0603 sized

capacitors can be installed on microstrip lines. The biggest 0402

size, XR7 type usable is 0.01 mF, which will work fine for short

patterns (PRBS 2⁷–1) and data rates down to 1.0 Gbps. For

long patterns a 0603 sized, XR7 type, 0.1 mF should be used. To

decrease capacitive loading from the mounting area, clear out

planes underneath the coupling capacitor.

Figure 15. Evaluation Board ECL Driver Test Setup

Connections for Testing

The AD8152 evaluation board can be used under a variety of posi-

tive or negative supply configurations. Negative supply configurations,

as shown in Figure 15, allow the easiest hookup to test equip-

ment because inputs and outputs can be direct coupled. In a real

world application however, the negative supply configuration would

be difficult because control logic levels must be shifted negative.

In Figure 16, 6 dB attenuators are placed before the AD8152

input ac-coupling or bias tees. This is because many generators

won’t go below 500 mV single-ended. The output pair of 6 dB

attenuators is present to protect the scope inputs and allow for

higher scale voltages per division. The eye diagram is usually

viewed differentially by using a simple P – N math function.

Figure 16 is an example of a loop-through test setup using a posi-

tive supply. In this case, the test signal goes through the AD8152

twice. It is possible to loop through multiple times if desired, but

jitter will increase with number of loop-throughs. The first

input from the generator and the last output to a scope must be

ac-coupled. However, an AD8152 output driving its own input can

be direct-coupled. Direct coupling to the first AD8152 input is not

effective since generators usually want to see 50 W to ground.

Cabling used in this setup must be matched. Mismatched cables

cause either a P or N signal to be falsely delayed. This delay can

show up as a change in the crossing point, from 50 percent in the

eye diagram. To accurately check cable matches, a TDR setup

is recommended.

2.5V

VCC

VTTI

VTTO

HIGH SPEED

SAMPLING

OSCILLOSCOPE

PATTERN

GENERATOR

AD8152

P

DATA OUT

P

–6dB

50⍀

IN01

N

OUT01

N

DATA OUT

P

OUT02

N

TRIGGER OUT

TRIGGER IN

IN02

N

VEE

VCC = VTTI = VTTO = 2.5V, VEE = 0V,I

SET = 16mA

OUT

RTI (REFERRED TO INPUT)A MPLITUDE = 400mV SINGLE–ENDED,

23

V

HI = 2.7V (IN01), PRBS 2 –1, V = 2.5V,

OH

IN

V

= 2.1V,

OL

AC-COUPLED IS FROM BIAS TEES,

PROGRAMMING: IN01 TO OUT02, IN02 TO OUT01.

Figure 16. Positive Supply Loop-Through Test Setup

REV. A

–23–

AD8152

EVALUATION BOARD CONTROL SOFTWARE

Next, select the desired output from the Output Select box by double-

clicking the appropriate output channel number.

The AD8152 evaluation board can be controlled by using a PC

and a custom software program. The hardware interface uses a

PC parallel (or printer) port. A standard printer cable is used to

connect from the PC DB-25 connector to the Centronics-type

connector on the evaluation board. Figure 17 shows an evaluation

board control panel from a PC display.

Finally, the Program button is clicked and the data is immediately

sent to the evaluation board for programming the part to the

selected I/O combination.

If an additional output(s) is desired to be programmed to the same

input, double-click the desired output channel number and click

the Program button.

A single screen allows control of all the programmable functions

of the AD8152. The programming modes are listed in the Mode

box. Select either I/O Programming or Current Programming by

selecting the appropriate radio button. These will allow either

programming the switch matrix or the output currents one at a time.

The Programmed Output table indicates which outputs are

programmed to the input that is indicated in the Active Input

Selection window. If it is desired to disable an individual output,

its radio button in the Programmed Output table can be clicked,

and it will change from black to white to indicate that it is not

enabled. Note: It is not possible to program outputs by selecting

their radio buttons.

An alternative is to use the Broadcast mode. This will either

simultaneously program all of the outputs to one selected input

or program all outputs to the same current.

To observe the set of outputs that are connected to any input,

double-click the desired input channel number from the Input

Select box. The selected channel number will show up in the Active

Input Selection window and the programmed outputs will have a

black dot in their radio button in the Programmed Output table.

To program an output current, select the Current Programming

button in the Mode box. Then double-click the desired output

channel number from the Output Select table. Next double-click

the desired entry for the Output Current. Finally, click the

Program button.

If the Broadcast button is selected from the Mode box, all outputs

will be treated the same. If I/O Programming is selected, double-

click the input channel number from the Input Select table

and click the Program button. This will cause all outputs to be

programmed to the selected output, and all of the buttons will

have a black dot in the Programmed Output table.

Figure 17. Evaluation Board Control Panel

In the I/O Programming mode (nonbroadcast), the desired input

is selected from the Input Select box by double-clicking on the

appropriate input channel number. This will cause the same

channel to appear in the Active Input Selection indicator window.

For broadcast current programming, double-click the desired

Output Current. Then click the Program button. All of the outputs

will be programmed to the selected output current.

The Reset button will disable all outputs. In addition, all output

currents will be programmed to the nominal value of 16 mA.

–24–

REV. A

AD8152

Figure 18. Evaluation Board Top Side Signals

REV. A

–25–

AD8152

Figure 19. Evaluation Board Bottom Side Signals, View from Top

–26–

REV. A

AD8152

Figure 20. Evaluation Board VCC Layer, View from Top

REV. A

–27–

AD8152

Figure 21. Evaluation Board VEE Layer, View from Top

–28–

REV. A

AD8152

Figure 22. Evaluation Board VTTI Layer, View from Top

REV. A

–29–

AD8152

Figure 23. Evaluation Board VTTO Layer, View from Top

–30–

REV. A

AD8152

OUTLINE DIMENSIONS

256-Ball Grid Array [SBGA]

(BP-256)

Dimensions shown in millimeters

A1 CORNER

27.00 BSC

20

18 16 14 12 10

19 17 15 13 11

8

6

4

2

9

7

5

3

1

A

B

C

D

E

F

1.27

A1

G

H

J

K

L

24.13 REF

27.00 BSC

M

N

P

R

T

U

V

W

Y

TOP

24.13 REF

BOTTOM

1.27

1.00

0.80

0.60

0.70

0.60

0.50

0.20 MIN

0.90

0.75

0.60

SEATING PLANE

0.25 MIN

SEATING

PLANE

0.20

COPLANARITY

BALL DIAMETER

COMPLIANTTO JEDEC STANDARDS MO-192-BAL-2

REV. A

–31–

AD8152

Revision History

Location

Page

1/03—Data Sheet changed from REV. 0 to REV. A.

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

–32–

REV. A


型号：	AD8152
厂家：	ADI
描述：	34 x 34, 3.2 Gbps Asynchronous Digital Crosspoint Switch 34 x 34英寸， 3.2 Gbps的异步数字交叉点开关开关
文件：	总32页 (文件大小：1210K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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