AD8158-EVALZ [ADI]
6.5 Gbps Quad Buffer Mux/Demux; 6.5 Gbps的四路缓冲复用器/解复用器
| 型号： | AD8158-EVALZ |
| 厂家： | 
ADI |
| 描述： | 6.5 Gbps Quad Buffer Mux/Demux |
| 文件： | 总36页 (文件大小：709K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6.5 Gbps
Quad Buffer Mux/Demux
AD8158
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Quad 2:1 mux/1:2 demux
TRANSMIT
RECEIVE
PRE-
Optimized for dc to 6.5 Gbps NRZ data
Per-lane P/N pair inversion for routing ease
Programmable input equalization
Compensates up to 40 inches of FR4
Loss-of-signal detection
EQUALIZATION
EMPHASIS
EQ
EQ
Ix_A[3:0]
Ix_B[3:0]
2:1
Ox_C[3:0]
Programmable output pre-emphasis up to 12 dB
Programmable output levels with squelch and disable
Accepts ac-coupled or dc-coupled differential CML inputs
50 Ω on-chip termination
Ox_A[3:0]
Ox_B[3:0]
1:2
EQ
Ix_C[3:0]
1:2 demux supports unicast or bicast operation
Port-level loopback
Port or single lane switching
TRANSMIT
PRE-
EMPHASIS
QUAD
2:1
RECEIVE
EQUALIZATION
MULTIPLEXER/
1:2
DEMULTIPLEXER
1.8 V to 3.3 V flexible core supply
LB_A
User-settable I/O supply from VCC to 1.2 V
Low power, typically 2.0 W in basic configuration
100-lead LFCSP
LB_B
LB_C
PE_A
PE_B
SCL
SDA
PE_C
2
I C
−40°C to +85°C operating temperature range
EQ_A[1:0]
EQ_B[1:0]
EQ_C[1:0]
SEL[3:0]
BICAST
SEL4G
RESETb
LOS_INT
TOGGLE
CONTROL
LOGIC
I2C_A0
I2C_A1
I2C_A2
CONTROL
LOGIC
APPLICATIONS
Low cost redundancy switch
SONET OC48/SDH16 and lower data rates
XAUI/GbE/FC/Infiniband over backplane
OIF CEI 6.25 Gbps over backplane
Serial data-level shift
AD8158
Figure 1.
4-/8-/12-lane equalizers or redrivers
GENERAL DESCRIPTION
The AD8158 is an asynchronous, protocol-agnostic, quad-lane
2:1 switch with a total of 12 differential CML inputs and
12 differential CML outputs. The signal path supports NRZ
signaling with data rates up to 6.5 Gbps per lane. Each lane
offers programmable receive equalization, programmable
output pre-emphasis, programmable output levels, and loss-of-
signal detection.
capability, allowing the part to support either 1 + 1 or 1:1
redundancy.
The AD8158 is also suited for testing high speed serial links
because of its ability to duplicate incoming data. In a port-
monitoring application, the AD8158 can maintain link-
connectivity with a pass-through connection from Port C to
Port A while sending a duplicate copy of the data to test
equipment on Port B.
The nonblocking switch-core of the AD8158 implements a
2:1 multiplexer and 1:2 demultiplexer per lane and supports
independent lane switching through the four select pins,
SEL[3:0]. Each port is a four-lane link. Every lane implements
an asynchronous path supporting dc to 6.5 Gbps NRZ data,
fully independent of other lanes. The AD8158 has low latency
and very low lane-to-lane skew.
The rich feature set of the AD8158 can be controlled either
through external toggle pins or by setting on-chip control
registers through the I2C® interface.
The main application of the AD8158 is to support redundancy
on both the backplane and the line interface sides of a serial
link. The demultiplexing path implements unicast and bicast
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD8158
TABLE OF CONTENTS
Features .............................................................................................. 1
Pre-Emphasis .............................................................................. 21
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
I2C Timing Specifications............................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 15
The Switch (Mux/Demux/Unicast/Bicast/Loopback)........... 16
Receivers...................................................................................... 18
Lane Disables .............................................................................. 19
Equalizer Settings ....................................................................... 19
Loss of Signal (LOS)................................................................... 19
Lane Inversion: P/N Swap ......................................................... 21
Transmitters ................................................................................ 21
Output Level Programming and Output Structure ............... 21
Output Compliance, AC vs. DC Coupling, Minimum Supply
Voltage, and the TX_HEADROOM Bit.................................. 23
Signal Levels and Common-Mode Shift for AC-Coupled and
DC-Coupled Outputs ................................................................ 24
Squelch and Disable................................................................... 26
Speed Select................................................................................. 26
AD8158 Power Consumption .................................................. 26
Outputs ........................................................................................ 28
Power Saving Considerations ................................................... 28
I2C Control Interface...................................................................... 29
Serial Interface General Functionality..................................... 29
I2C Interface Data Transfers: Data Write ................................ 29
I2C Interface Data Transfers: Data Read ................................. 30
Applications Information.............................................................. 31
Supply Sequencing ..................................................................... 31
Single Supply vs. Multiple Supply Operation ......................... 31
Register Map ................................................................................... 32
Outline Dimensions....................................................................... 34
Ordering Guide .......................................................................... 34
REVISION HISTORY
6/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD8158
SPECIFICATIONS
VCC = VTTI = VTTO= 1.8 V, DVCC = 3.3 V, VEE = 0 V, RL = 50 Ω, basic configuration1, data rate = 6.5 Gbps, ac-coupled differential input
swing = 800 mV p-p, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Data Rate/Channel (NRZ)
DC
6.5
Gbps
ps p-p
ps
Deterministic Jitter (No Channel) Data rate = 6.5 Gbps, EQ enabled
Random Jitter (No Channel)
20
1
RMS, data rate = 6.5 Gbps
30
40
35
42
700
90
ps p-p
ps p-p
ps p-p
ps p-p
ps
Residual Deterministic Jitter
with Receive Equalization
Data rate 6.5 Gbps, 20 inch FR4
Data rate 6.5 Gbps, 40 inch FR4
Data rate 6.5 Gbps, 10 inch FR4
Data rate 6.5 Gbps, 30 inch FR4
50% input to 50% output (maximum EQ)
Residual Deterministic Jitter
with Transmit Pre-Emphasis
Propagation Delay
Lane-to-Lane Skew
Signal path and switch architecture is balanced and
symmetric (maximum EQ)
ps
Switching Time
Output Rise/Fall Time
50% logic switching to 50% output data
20% to 80% (PE = lowest setting)
150
62
ns
ps
INPUT CHARACTERISTICS
Differential Input Voltage Swing
VICM2 = VCC − 0.6 V, VCC = VMIN to VMAX, TA = TMIN to TMAX, LOS
threshold register = 0x10, LOS control register = 0x05
200
590
2000
mV p-p
mV p-p
Differential Sensitivity with
Default LOS Setting
Input Voltage Range
300
Single-ended absolute voltage level, VL minimum
Single-ended absolute voltage level, VH maximum
VEE + 0.6
VCC + 0.3
V
V
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Range
Differential, PE = 0, default output level, @ dc
Single-ended absolute voltage level, TX_HEADROOM = 0;
VL minimum
Single-ended absolute voltage level, TX_HEADROOM = 0;
VH maximum
Single-ended absolute voltage level, TX_HEADROOM = 1;
VL minimum
725
820
mV p-p
V
VCC − 1.1
VCC + 0.6
VCC − 1.3
VCC + 0.6
V
V
V
Single-ended absolute voltage level, TX_HEADROOM = 1;
VH maximum
Output Current
Output Current
Port A/B/C, PE_A/B/C = minimum
Port A/B/C, PE_A/B/C = 6 dB, VOD = 800 mV p-p
16
32
mA
mA
TERMINATION CHARACTERISTICS
Resistance
Differential, VCC = VMIN to VMAX, TA = TMIN to TMAX
LOS threshold = 0x10
LOS_GSEL = 0, @ dc
LOS_GSEL = 0, @ dc
LOS control = 0, VID = 0 to 50% OP/ON settling, VCC = 1.8 V
90
100
110
Ω
LOS CHARACTERISTICS
Assert Level
Deassert Level
LOS to Output Squelch
LOS to Output Enable
25
150
21
mV diff
mV diff
ns
LOS control = 0, data present to first valid transition,
VCC = 1.8 V
67
ns
POWER SUPPLY
Operating Range
VCC
VCC
DVCC
VTTI
VTTO
VEE = 0 V, TX_HEADROOM = 0
VEE = 0 V, TX_HEADROOM = 1
DVCC ≥ VCC, VEE = 0 V
1.6
2.2
1.6
1.2
1.2
1.8 to 3.3
3.3
1.8 to 3.3
3.6
3.6
3.6
VCC + 0.3
VCC + 0.3
V
V
V
V
V
Rev. 0 | Page 3 of 36
AD8158
Parameter
Conditions
Min
Typ
Max
Unit
Supply Current
DC-coupled inputs/outputs, 400 mV I/O swings (800 mV
p-p differential), 50 Ω far-end terminations
ICC
ITTO
ITTI
IDVCC
354
128
94
450
150
107
4
mA
mA
mA
mA
2
Supply Current
ICC
ITTO
LB_x = 1, PE = 6 dB on all ports, dc-coupled
inputs/outputs, 400 mV I/O swings (800 mV p-p
differential), 50 Ω far-end terminations
730
367
95
850
420
107
4
mA
mA
mA
mA
ITTI
IDVCC
2
THERMAL CHARACTERISTICS
Operating Temperature Range
θJA
−40
+85
125
°C
Still air; JEDEC four-layer test board, ePAD soldered
Still air; thermal resistance through exposed pad
22.2
1.4
°C/W
°C/W
°C
θJC
Maximum Junction Temperature
LOGIC INPUT CHARACTERISTICS3
Input High (VIH)
Input Low (VIL)
Input High (VIH)
I2C, SDA, SCL, control pins
DVCC = 3.3 V
DVCC = 3.3 V
DVCC = 1.8 V
0.7 × DVCC
VEE
DVCC
0.3 × DVCC
0.8 × DVCC DVCC
0.2 × DVCC
V
V
V
V
Input Low (VIL)
DVCC = 1.8 V
VEE
1 Bicast is off, loopback is off on all ports, pre-emphasis is set to minimum on all ports, and equalization is set to minimum on all ports.
2 VICM is the input common-mode voltage.
3 EQ control pins (EQ_A0, EQ_A1, EQ_B0, EQ_B1, EQ_C0, EQ_C1) require 5 kΩ in series when DVCC > VCC
.
I2C TIMING SPECIFICATIONS
SDA
tF
tR
tBUF
tR
tSU;DAT
tHD;STA
tF
tLOW
SCL
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tHIGH
S
Sr
P
S
Figure 2. I2C Timing Diagram
Table 2. I2C Timing Parameters
Parameter
SCL Clock Frequency
Hold Time for a Start Condition
Setup Time for a Repeated Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Data Hold Time
Symbol
Min
0
Max
Unit
fSCL
400+
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
ns
pF
tHD;STA
tSU;STA
tLOW
tHIGH
tHD;DAT
tSU;DAT
tR
tF
tSU;STO
tBUF
0.6
0.6
1.3
0.6
0
10
1
1
Data Setup Time
Rise Time for Both SDA and SCL
Fall Time for Both SDA and SCL
Setup Time for Stop Condition
Bus Free Time Between a Stop and a Start Condition
Capacitance for Each I/O Pin
300
300
0.6
1
5
Ci
7
Rev. 0 | Page 4 of 36
AD8158
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VCC to VEE
3.7 V
DVCC to VEE
3.7 V
VTTI
Lower of (VCC + 0.6 V) or 3.6V
VTTO
Lower of (VCC + 0.6 V) or 3.6V
VCC to DVCC
0.6 V
Internal Power Dissipation
Differential Input Voltage
Logic Input Voltage
Storage Temperature Range
Lead Temperature
4.26 W
2.0 V
ESD CAUTION
VEE − 0.3 V < VIN < VCC + 0.6 V
−65°C to +125°C
300°C
Rev. 0 | Page 5 of 36
AD8158
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CONTROL
PORT C INPUTS
CONTROL
V
1
2
3
75 V
EE
74 OP_C0
73 ON_C0
EE
ON_A3
OP_A3
PIN 1
INDICATOR
V
4
5
6
72 V
71 OP_C1
70 ON_C1
CC
CC
ON_A2
OP_A2
V
7
8
9
69 V
68 OP_C2
67 ON_C2
TTO
TTO
ON_A1
OP_A1
V
10
66 V
CC
CC
ON_A0 11
OP_A0 12
65 OP_C3
64 ON_C3
AD8158
TOP VIEW
V
13
63
V
EE
CC
(Not to Scale)
IN_A3 14
62 IP_B0
61 IN_B0
IP_A3 15
DIE IS PACKAGED DIE UP
V
16
60
V
CC
CC
IN_A2 17
IP_A2 18
59 IP_B1
58 IN_B1
V
19
57
V
TTI
TTI
IN_A1 20
IP_A1 21
56 IP_B2
55 IN_B2
V
22
54 V
CC
CC
IN_A0 23
IP_A0 24
53 IP_B3
52 IN_B3
V
25
51 V
I2C
PORT B OUTPUTS
CONTROL
EE
EE
NOTES
1. THE ePAD ON THE BOTTOM OF THE PACKAGE MUST BE ELECTRICALLY CONNECTED TO V
.
EE
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
VEE
Type
Description
1, 13, 25, 44, 51, 75, 94, ePAD
Power
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Input
Negative Supply
2
ON_A3
OP_A3
VCC
High Speed Output Complement
High Speed Output
3
4, 10, 16, 22, 35, 41, 54, 60, 63, 66, 72, 85, 91
Positive Supply
5
ON_A2
OP_A2
VTTO
High Speed Output Complement
High Speed Output
6
7, 38, 69
Port A, Port B, and Port C Output Termination Supply
High Speed Output Complement
High Speed Output
8
ON_A1
OP_A1
ON_A0
OP_A0
IN_A3
IP_A3
IN_A2
IP_A2
VTTI
9
11
High Speed Output Complement
High Speed Output
12
14
High Speed Input Complement
High Speed Input
15
Input
17
Input
High Speed Input Complement
High Speed Input
18
Input
19, 57, 88
20
Power
Input
Port A, Port B, and Port C Input Termination Supply
High Speed Input Complement
High Speed Input
IN_A1
IP_A1
IN_A0
IP_A0
DVCC
21
Input
23
Input
High Speed Input Complement
High Speed Input
24
Input
26
Power
Digital Power Supply
Rev. 0 | Page 6 of 36
AD8158
Pin No.
27
28
29
30
31
32
33
34
36
37
39
40
42
43
45
46
47
48
49
50
52
53
55
56
58
59
61
62
64
65
67
68
70
71
73
74
76
77
78
79
80
81
82
83
84
86
87
89
90
92
93
Mnemonic
SCL
Type
I2C
I2C
I2C
I2C
I2C
Description
I2C Clock Pin
I2C Data Pin
I2C Address Pin (LSB)
I2C Address Pin
I2C Address Pin (MSB)
SDA
I2C_A0
I2C_A1
I2C_A2
RESETb
ON_B3
OP_B3
ON_B2
OP_B2
ON_B1
OP_B1
ON_B0
OP_B0
EQ_A02
EQ_A12
EQ_B02
EQ_B12
EQ_C02
EQ_C12
IN_B3
IP_B3
Control1
Output
Output
Output
Output
Output
Output
Output
Output
Control1
Control1
Control1
Control1
Control1
Control1
Input
Chip Reset. Active Low
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
Port A Equalizer Control Bit 0 (LSB)
Port A Equalizer Control Bit 1 (MSB)
Port B Equalizer Control Bit 0 (LSB)
Port B Equalizer Control Bit 1 (MSB)
Port C Equalizer Control Bit 0 (LSB)
Port C Equalizer Control Bit 1 (MSB)
High Speed Input Complement
High Speed Input
Input
IN_B2
IP_B2
Input
High Speed Input Complement
High Speed Input
Input
IN_B1
IP_B1
Input
High Speed Input Complement
High Speed Input
Input
IN_B0
IP_B0
Input
High Speed Input Complement
High Speed Input
Input
ON_C3
OP_C3
ON_C2
OP_C2
ON_C1
OP_C1
ON_C0
OP_C0
LB_C
Output
Output
Output
Output
Output
Output
Output
Output
Control1
Control1
Control1
Interrupt
Control1
Control1
Control1
Input
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
Loopback Enable for Port C
Loopback Enable for Port B
Loopback Enable for Port A
Loss of Signal Interrupt, Active High
Pre-Emphasis Control for Port C
Pre-Emphasis Control for Port B
Pre-Emphasis Control for Port A
High Speed Input Complement
High Speed Input
LB_B
LB_A
LOS_INT
PE_C
PE_B
PE_A
IN_C3
IP_C3
Input
IN_C2
IP_C2
Input
High Speed Input Complement
High Speed Input
Input
IN_C1
IP_C1
Input
High Speed Input Complement
High Speed Input
Input
IN_C0
IP_C0
Input
High Speed Input Complement
High Speed Input
Input
Rev. 0 | Page 7 of 36
AD8158
Pin No.
95
Mnemonic
SEL3
Type
Description
Control1
Control1
Control1
Control1
Control1
Control1
Lane 3 A/B Switch Control
Lane 2 A/B Switch Control
Lane 1 A/B Switch Control
Lane 0 A/B Switch Control
Enable Bicast Mode for Port A and Port B Outputs
Set Transmitter for Low Speed PE
96
SEL2
97
SEL1
98
SEL0
99
BICAST
SEL4G
100
1 Logic level of control pins referred to DVCC
.
2 EQ control pins (EQ_A0, EQ_A1, EQ_B0, EQ_B1, EQ_C0, EQ_C1) require 5 kΩ in series when DVCC > VCC
.
Rev. 0 | Page 8 of 36
AD8158
TYPICAL PERFORMANCE CHARACTERISTICS
50Ω CABLES
50Ω CABLES
2
2
2
2
INPUT
PIN
OUTPUT
PIN
DATA OUT
50Ω
HIGH SPEED
SAMPLING
AD8158
AC-COUPLED
EVALUATION
BOARD
PATTERN
GENERATOR
TP1
TP2
OSCILLOSCOPE
Figure 4. Standard Test Circuit (No Channel)
25ps/DIV
25ps/DIV
Figure 5. 6.5 Gbps Input Eye (TP1 from Figure 4)
Figure 6. 6.5 Gbps Output Eye, No Channel (TP2 from Figure 4)
Rev. 0 | Page 9 of 36
AD8158
50Ω CABLES
50Ω CABLES
50Ω CABLES
2
2
2
2
2
2
INPUT OUTPUT
PIN PIN
DATA OUT
FR4 TEST BACKPLANE
50Ω
HIGH
SPEED
SAMPLING
OSCILLOSCOPE
DIFFERENTIAL
STRIPLINE TRACES
8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
TRACE LENGTHS = 20 INCHES,
40 INCHES
AD8158
AC-COUPLED
EVALUATION
BOARD
PATTERN
GENERATOR
TP1
TP2
TP3
25ps/DIV
REFERENCE EYE DIAGRAM AT TP1
Figure 7. Input Equalization Test Circuit
25ps/DIV
25ps/DIV
Figure 8. 6.5 Gbps Input Eye, 20 Inch FR4 Input Channel (TP2 from Figure 7)
Figure 10. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel (TP3 from Figure 7)
25ps/DIV
25ps/DIV
Figure 9. 6.5 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 7)
Figure 11. 6.5 Gbps Output Eye, 40 Inch FR4 Input Channel (TP3 from Figure 7)
Rev. 0 | Page 10 of 36
AD8158
50Ω CABLES
50Ω CABLES
50Ω CABLES
2
2
2
2
2
2
INPUT OUTPUT
PIN PIN
DATA OUT
FR4 TEST BACKPLANE
50Ω
HIGH
SPEED
SAMPLING
OSCILLOSCOPE
DIFFERENTIAL
STRIPLINE TRACES
8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
TRACE LENGTHS = 20 INCHES,
30 INCHES
AD8158
AC-COUPLED
EVALUATION
BOARD
PATTERN
GENERATOR
TP1
TP2
TP3
25ps/DIV
REFERENCE EYE DIAGRAM AT TP1
Figure 12. Output Pre-emphasis Test Circuit
25ps/DIV
25ps/DIV
Figure 13. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel, PE = 0
(TP3 from Figure 12)
Figure 15. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel, PE = Best Setting,
Default Output Level (TP3 from Figure 12)
25ps/DIV
25ps/DIV
Figure 14. 6.5 Gbps Output Eye, 30 Inch FR4 Input Channel, PE = 0
(TP3 from Figure 12)
Figure 16. 6.5 Gbps Output Eye, 30 Inch FR4 Input Channel, PE = Best Setting,
200 mV Output Level (TP3 from Figure 12)
Rev. 0 | Page 11 of 36
AD8158
100
80
60
40
20
80
70
60
50
40
30
20
10
0
V
V
= 3.3V
CC
= 1.8V
2.0
CC
0
0
2
4
6
8
0
0.5
1.0
1.5
2.5
3.0
3.5
4.0
4.5
DATA RATE (GHz)
INPUT COMMON-MODE (V)
Figure 17. Deterministic Jitter vs. Data Rate
Figure 20. Deterministic Jitter vs. Input Common Mode
100
80
60
40
20
100
80
60
40
20
0
0
0
0.5
1.0
1.5
2.0
2.5
1.0
1.5
2.0
2.5
(V)
3.0
3.5
4.0
DIFFERENTIAL INPUT SWING (V p-p)
V
CC
Figure 18. Deterministic Jitter vs. Input Swing
Figure 21. Deterministic Jitter vs. VCC
100
80
60
40
20
100
90
80
70
60
50
40
30
20
10
0
(V = 3.3V)
CC
MIN OUTPUT SWING
(V = 3.3V)
CC
DEFAULT OUTPUT SWING
(V = 1.8V)
CC
MIN OUTPUT SWING
(V = 1.8V)
CC
DEFAULT OUTPUT SWING
0
–60
–40
–20
0
20
40
60
80
100
1.0
1.5
2.0
2.5
3.0
3.5
4.0
TEMPERATURE (°C)
V
VOLTAGE (V)
TTO
Figure 19. Deterministic Jitter vs. Temperature
Figure 22. Deterministic Jitter vs. Output Termination Voltage (VTTO
)
Rev. 0 | Page 12 of 36
AD8158
100
90
80
70
60
50
40
30
20
10
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
(V = 3.3V)
CC
DEFAULT OUTPUT SWING
(V = 1.8V)
CC
DEFAULT OUTPUT SWING
(V = 1.8V)
CC
200mV OUTPUT VOLTAGE
(V
= 3.3V)
CC
200mV OUTPUT VOLTAGE
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.4
1.9
2.4
2.9
3.4
V
VOLTAGE (V)
CORE VOLTAGE (V)
OCM
Figure 23. Deterministic Jitter vs. Output VOCM
Figure 26. Output Amplitude (Default Setting) vs. Core Voltage
1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
–1
–2
–3
–4
–5
–9
–7
–5
–3
0
2
4
6
0
1
2
3
4
5
6
7
JITTER (ps)
RATE (Gbps)
Figure 27. Output Amplitude vs. Rate
Figure 24. Random Jitter/Periodic Jitter Histogram
1000
950
900
850
800
750
700
650
600
550
500
100
90
80
70
60
50
1.6
2.1
2.6
3.1
3.6
–60
–40
–20
0
20
40
60
80
100
CORE SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 28. Propagation Delay vs. Core Supply
Figure 25. tR/tF vs. Temperature
Rev. 0 | Page 13 of 36
AD8158
1000
950
900
850
800
750
700
650
600
550
90
80
70
60
50
40
30
20
10
0
0" DEFAULT OUTPUT SWING
10" DEFAULT OUTPUT SWING
20" DEFAULT OUTPUT SWING
30" DEFAULT OUTPUT SWING
30" 200mV OUTPUT LEVEL
500
–60
0
1
2
3
4
5
6
7
–40
–20
0
20
40
60
80
100
PE SETTING
TEMPERATURE (°C)
Figure 29. Propagation Delay vs. Temperature
Figure 32. Deterministic Jitter vs. PE Setting
0"
140
120
100
80
10"
20"
30"
40"
10
9
8
7
6
5
4
3
2
1
0
0" DEFAULT OUTPUT SWING
10" DEFAULT OUTPUT SWING
20" DEFAULT OUTPUT SWING
30" DEFAULT OUTPUT SWING
30" MINIMUM OUTPUT SWING
60
40
20
0
NO
DUT
0
1
2
3
4
5
6
7
8
9
EQ SETTING
0
1
2
3
4
5
6
7
8
PE SETTING
Figure 30. Deterministic Jitter vs. EQ Setting
Figure 33. Random Jitter vs. PE Setting
10
9
8
7
6
5
4
3
2
1
0
0"
0
–2
10"
20"
30"
40"
–4
–6
–8
–10
–12
–14
–16
–18
–20
6"
10"
20"
30"
40"
0
1
2
3
4
5
6
7
8
9
10
EQ SETTING
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 31. Random Jitter vs. EQ Setting vs. Trace
Figure 34. S21 Test Traces
Rev. 0 | Page 14 of 36
AD8158
THEORY OF OPERATION
The AD8158 is a buffered, asynchronous, three-port transceiver
that allows 2:1 multiplexing and 1:2 demultiplexing among its
ports. The 1:2 demux path supports bicast operation, allowing
the AD8158 to operate as a port replicator as well as a redundancy
switch. The AD8158 offers loopback on each lane, allowing the
part to be configured as a 12-lane equalizer or redriver with FFE.
MUX
Table 5. Control Modes
Mode
Description
Toggle Pin
Control
Asynchronous control through toggle pins only
Mixed Control Switch configuration via toggle pins, register-
based control through the I2C serial interface
Serial Control
Register-based control through the I2C serial
interface
RXA
RXB
TXC
The pin control mode offers access to a subset of the total
feature list but allows for a much simplified control scheme.
Table 6 compares the available features in all control modes.
DEMUX
The primary advantage of using the serial control interface is
that it allows finer resolution in setting receive equalization,
transmitter pre-emphasis, loss-of-signal (LOS) behavior, and
output levels.
TXA
TXB
RXC
Figure 35. Mux/Demux Paths, Port A to Port C
By default, the AD8158 starts in the pin control mode. Strobing
the RESETb pin sets all on-chip registers to their default values
and uses pins to configure switch connectivity, PE, and EQ
levels. In mixed mode, switch connectivity is still controlled
through the SEL[3:0], LB_[A:C], and BICAST pins. The user
can override PE and EQ settings in mixed mode. In serial
mode, all functions are accessed through registers and the
control pin inputs are ignored, except RESETb. Register 0x0F
selects the control mode (see Table 7).
The AD8158 register set is controlled through a 2-wire I2C
interface. The AD8158 acts only as an I2C slave device. The
7-bit slave address for the AD8158 I2C interface contains the
static value b1010 for the upper four bits. The lower three bits
are controlled by the input pins I2C_A[2:0].
The part offers extensively programmable transmit output levels
and pre-emphasis settings as well as squelch or full-disable. The
receivers integrate a programmable, multizero transfer function
for aggressive equalization and a programmable loss-of-signal
feature. The AD8158 provides a balanced, high speed switch
core that maintains low lane-to-lane skew while preserving
edge rates.
The I/O on-chip termination resistors are tied to user-settable
supplies for increased flexibility. The AD8158 supports a wide
primary supply range; VCC can be set from 1.8 V to 3.3 V. These
features, together with programmable transmitter output levels,
allow for a wide range of dc- and ac-coupled I/O configurations.
The AD8158 supports several control and configuration modes,
shown in Table 5.
Table 6. Features Available Through Toggle Pin or Serial Control
Feature
Pin Control
Serial Control
Switch Features
BICAST
One pin
One bit
A/B Lane Select
Loopback
Four pins
Three pins
Four bits
Three bits
Rx Features
EQ Levels
N/P Swap
Four settings
Not available
Enabled
10 settings
Available
Three bits
Squelch
Tx Features
Programmable Output Levels
PE Levels
400 mV diff fixed1
Two settings
200 mV diff/ 300 mV diff/ 400 mV diff/ 600 mV diff
>7 settings
1
400 mV diff indicates a 400 mV amplitude signal measured between two differential nodes. The voltage swing at differential I/O pins is described in this data sheet
both in terms of the differentially measured voltage range ( 400 mV diff, for example) and in terms of peak-to-peak differential swing, denoted mV p-p diff. An output
level setting of 400 mV diff delivers a differential peak-to-peak output voltage of 800 mV p-p diff.
Rev. 0 | Page 15 of 36
AD8158
Table 7. Register Address 0x0F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
MODE[1]
MODE[0]
Mode
When the device is in unicast mode, the output lanes on either
Port A or Port B are in an idle state. In the idle state, the output
tail current is set to 0, and the P and N sides of the lane are
pulled up to the output termination voltage through the on-chip
termination resistors. To save power, the unused receiver
automatically disables.
Table 8. Setting the Control Interface Mode
Mode 1
Mode 0
Control Mode
0
0
1
0
1
1
Pin control
Mixed control
Serial control
THE SWITCH
(MUX/DEMUX/UNICAST/BICAST/LOOPBACK)
The AD8158 supports port-level loopback, illustrated in Figure 36.
The loopback control pins override the lane select (SEL[3:0])
and bicast control (BICAST) pin settings at the port level. In serial
control mode, Bits [6:4] of Register 0x01 control loopback and
are equivalent to asserting Pin LB_A, Pin LB_B, and Pin LB_C.
Table 10 summarizes the different loopback configurations.
The mux and demux functions of the AD8158 can be controlled
either with the toggle pins or through the register map. The
multiplexer path switches received data from Input Port A or
Input Port B to Output Port C. The SEL[3:0] pins allow switching
lanes independently. The demultiplexer path switches received
data from Input Port C to Output Port A, Output Port B, or (if
bicast mode is enabled) to both Output Port A and Output Port B.
The loopback feature is useful for system debug, self test, and
initialization, allowing system ASICs to compare Tx and Rx
data sent over a single bidirectional link. Loopback can also be
used to configure the device as a 4- to 12-lane receive equalizer
or backplane redriver.
Table 9. Port Selection and Configuration with All
Loopbacks Disabled
Output
Port A
Output
Port B
Output
Port C
BICAST
SELx
0
0
1
1
0
1
0
1
Ix_C[3:0]
Idle
Ix_C[3:0]
Ix_C[3:0]
Idle
Ix_A[3:0]
Ix_B[3:0]
Ix_A[3:0]
Ix_B[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
X4
Ox_A[3:0]
X4
Ix_C[3:0]
1:2 DEMUX
X4
Ox_B[3:0]
PORT A LOOPBACK
PORT B LOOPBACK
PORT C LOOPBACK
X4
Ix_A[3:0]
X4
2:1 MUX
Ox_C[3:0]
X4
Ix_B[3:0]
Figure 36. Port Level Loopback
Rev. 0 | Page 16 of 36
AD8158
Table 10. Switch Connectivity vs. Loopback, BICAST, and Port Select Settings
LBA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LBB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
LBC
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BICAST
SELAb/B
Output Port A Output Port B Output Port C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ix_C[3:0]
Idle
Idle
Ix_A[3:0]
Ix_B[3:0]
Ix_A[3:0]
Ix_B[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_A[3:0]
Ix_B[3:0]
Ix_A[3:0]
Ix_B[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_A[3:0]
Ix_B[3:0]
Ix_A[3:0]
Ix_B[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_A[3:0]
Ix_B[3:0]
Ix_A[3:0]
Ix_B[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Idle
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Idle
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Idle
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Idle
Ix_C[3:0]
Ix_C[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_A[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_B[3:0]
Ix_B[3:0]
Ix_B[3:0]
Ix_B[3:0]
Ix_B[3:0]
Ix_B[3:0]
Ix_B[3:0]
Ix_B[3:0]
Idle
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Idle
Ix_C[3:0]
Ix_C[3:0]
Ix_C[3:0]
Ix_B[3:0]
Ix_B[3:0]
Ix_B[3:0]
Ix_B[3:0]
Ix_B[3:0]
Ix_B[3:0]
Ix_B[3:0]
Ix_B[3:0]
Rev. 0 | Page 17 of 36
AD8158
Input Structure and Allowed Input Levels
RECEIVERS
The AD8158 tolerates an input common-mode range (meas-
ured with zero differential input) of
The AD8158 receivers incorporate 50 ꢀ on-chip termination,
ESD protection, and a multizero equalization function capable
of delivering up to 18 dB of boost at 4.25 GHz. The AD8158 can
compensate signal degradation at 6.5 Gbps from over 40 inches
of FR-4 backplane trace. The receive path also incorporates a
loss-of-signal (LOS) function with user programmable thresh-
old and hysteresis, which squelches the associated transmitter
when the midband differential voltage falls below a specified
threshold value. Finally, the receivers implement a sign-swapping
option (P/N swap), which allows the user to invert the sign of
the input signal path and eliminates the need for board-level
crossovers in the receive channels.
V
EE + 0.6 V < VIN_CM < VCC + 0.3 V
Typical supply configurations include, but are not limited to,
those listed in Table 11.
Table 11. Typical Input Supply Configurations
Configuration
DVCC
VCC
VTTI
Low VTTI, AC-Coupled Input
Single 1.8 V Supply
3.3 V Core
3.3 V − 1.8 V
3.3 V − 1.8 V
3.3 V
1.8 V
1.8 V
3.3 V
3.3 V
1.6 V
1.8 V
1.8 V
3.3 V
Single 3.3 V Supply
3.3 V
When dc-coupling with LVDS, CML, or ECL signals, it can be
advantageous to operate with split or negative supplies (see the
Applications Information section). In these applications, it is
necessary to observe the maximum voltage ratings between VCC
and VEE and generally to select supply voltages for VTTO and VTTI
in the range of VCC to VEE to avoid activating the ESD protection
devices.
V
CC
ESD
ON-CHIP TERMINATION
V
TTI
V
THRESH
SIG
RP
TERM
RN
TERM
LOSS
R
R
OF
SIGNAL
DETECT
IP_xx
IN_xx
EQ OUT
EQUALIZER
V
EE
Figure 37. Functional Diagram of the AD8158 Receiver
V
CC
V
TTI
RLN
RL
RLP
RL
RP
52Ω
RN
52Ω
R1
750Ω
Q1
IP_xx
IN_xx
R3
1kΩ
R2
750Ω
Q2
I1
V
EE
Figure 38. Simplified Receiver Input Structure
Rev. 0 | Page 18 of 36
AD8158
the equalized waveform over a selectable interval of either 2 ns
or 10 ns. The detectors are enabled on a per-port basis with Bit 0 of
the RXA/B/C LOS control registers (0x51, 0x91, 0xD1).
LANE DISABLES
By default, the receivers and transmitters enable in an on-demand
fashion according to the state of the SEL[3:0], LB_[A:C], and
BICAST pins or to the state of the equivalent registers in serial
control mode. Register 0x40, Register 0x80, and Register 0xC0
implement per-lane disables for the receivers and Register 0x48,
Register 0x88, and Register 0xC8 implement per-lane transmit-
ter disables. These disables override the default settings. Each
bit in the register is named for the lane and function it disables.
For example, RXDIS B2 disables the receiver on Lane 2 of Port B
while TXDIS C3 disables the Lane 3 transmitter of Port C (see
Table 12).
By default, when the receiver detects an LOS event, it squelches
its associated transmitter, lowering the output current to
submicroamps. This prevents the high gain, wide bandwidth
signal path from turning low-level system noise on an undriven
input pair into a source of hostile crosstalk at the transmitter.
The squelch feature can be disabled with Bit 3 of the global
squelch control register (0x04).
Register 0x50, Register 0x90, and Register 0xD0 set values for
the LOS signal detection threshold for Port A, Port B, and Port C,
respectively. The recommended setting is Rx LOS threshold
register = 0x10 with Rx LOS control register = 0x05. This is an
optimum setting that all parts are factory tested to comply with
(see Table 1).
EQUALIZER SETTINGS
Every input lane offers a low power, asynchronous, programma-
ble receive equalizer for NRZ data up to 6.5 Gbps. The pin
control interface makes four levels of receive equalization
available: 6 dB, 12 dB, 15 dB, and 18 dB. Register-based control
allows the user 10 equalizer settings within this range. High
frequency boost increases monotonically (and approximately
linearly) with EQ control setting in ~2 dB steps.
LOS Recommended Settings
Rx LOS threshold register: 0x10
Rx LOS control register: 0x05
Register 0x51, Register 0x91, and Register 0xD1 set the integration
interval, LOS gain, and the enable state for the LOS feature for
Port A, Port B, and Port C, respectively (see Table 14 through
Table 16)
The four LSBs of Register 0x41, Register 0x81, and Register 0xC1
allow programming of all the equalizers in a port simultane-
ously (see Table 12). The 0x42, 0x43, 0x82, 0x83, 0xC2, and
0xC3 registers allow per-lane programming of the equalizers
(see Table 23). Be aware that writing to the port-level equalizer
registers updates and overwrites per-lane settings.
Bit 0, LOS_ENB, enables and disables the LOS detectors. (The
default setting is enabled, LOS_ENB = 1).
Bit 1, LOS_GSEL, adjusts the detector gain (1 = high gain, 0 =
low gain). A value of 0 is recommended.
LOSS OF SIGNAL (LOS)
The serial control interface allows access to the AD8158 loss of
signal features. (LOS is not available in pin control mode.) Each
receiver includes a low power, loss-of-signal detector. The loss-
of-signal circuit monitors the received data stream and
Bit 2, LOS_FILT, adjusts the interval over which incoming data
is averaged. LOS_FILT = 0 gives a 2 ns interval and LOS_FILT = 1
sets a 10 ns interval.
generates a system interrupt when the received signal power
falls below a programmed threshold. The default threshold is
25 mV diff, referred to the input pins. The LOS circuit monitors
the equalized receive waveform and integrates the rms power of
Bit 7 through Bit 3 should be set to 0.
Rev. 0 | Page 19 of 36
AD8158
Table 12. Per Lane Disables
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
RXA disable
RXB disable
RXC disable
TXA disable
TXB disable
TXC disable
RXDIS A3
RXDIS B3
RXDIS C3
TXDIS A3
TXDIS B3
TXDIS C3
RXDIS A2
RXDIS B2
RXDIS C2
TXDIS A2
TXDIS B2
TXDIS C2
RXDIS A1
RXDIS B1
RXDIS C1
TXDIS A1
TXDIS B1
TXDIS C1
RXDIS A0
RXDIS B0
RXDIS C0
TXDIS A0
TXDIS B0
TXDIS C0
0x40
0x80
0xC0
0x48
0x88
0xC8
Table 13. Port-Level EQ Setting
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
0x41
0x81
0xC1
AEQ[3]
BEQ[3]
CEQ[3]
AEQ[2]
BEQ[2]
CEQ[2]
AEQ[1]
BEQ[1]
CEQ[1]
AEQ[0]
BEQ[0]
CEQ[0]
Port A equalizer
Port B equalizer
Port C equalizer
Table 14. Global Loss-of-Signal Squelch Control Register
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
GSQLCH_ENB
Global squelch control
0x04
Table 15. Port-Level Loss-of-Signal Control Registers
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
0x50
0x51
0x90
0x91
0xD0
0xD1
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
THRBIT[5]
Set to 0
THRBIT[5]
Set to 0
THRBIT[5]
Set to 0
THRBIT[4]
Set to 0
THRBIT[4]
Set to 0
THRBIT[4]
Set to 0
THRBIT[3]
Set to 0
THRBIT[3]
Set to 0
THRBIT[3]
Set to 0
THRBIT[2]
LOS_FILT
THRBIT[2]
LOS_FILT
THRBIT[2]
LOS_FILT
THRBIT[1]
LOS_GSEL
THRBIT[1]
LOS_GSEL
THRBIT[1]
LOS_GSEL
THRBIT[0]
LOS_ENB
THRBIT[0]
LOS_ENB
THRBIT[0]
LOS_ENB
RXA LOS threshold
RXA LOS control
RXB LOS threshold
RXB LOS control
RXC LOS threshold
RXC LOS control
Table 16. Loss-of-Signal Configuration Bits
Bit(s)
Function
Description
Default
THRBIT[5:0]
LOS threshold
Binary coded value between 0 and 31. Covers ranges of 10 mV to 60 mV and 60 mV
to 250 mV for LOS_GSEL = 0 and LOS_GSEL = 1, respectively.
Recommended setting = 0x10.
0x1C
VIN_DC < 50 mV
LOS_FILT
LOS filter
Loss-of-signal filter.
1
1
0: LOS integrates 2 ns of data.
1: LOS integrates 10 ns of data.
LOS gain select.
LOS_GSEL
LOS sensitivity
Recommended setting = 0.
0: LOS covers an input range of 60 mV to 250 mV.
1: LOS covers an input range of 10 mV to 60 mV.
LOS enable.
LOS_ENB
LOS enable
1
0: LOS function disabled
1: LOS function enabled
Rev. 0 | Page 20 of 36
AD8158
The LOS_INT pin evaluates a logical OR of all LOS status
register bits for all enabled receivers. (LOS status registers are
located at 0x45, 0x85, and 0xC5.) The upper four bits in the
RXA, RXB, and RXC LOS status registers are sticky while the
four LSBs are continuously updated to indicate the instantaneous
status of LOS for an enabled receiver. The sticky bits are cleared
by writing 0 to the RXA, RXB, and RXC LOS status registers.
The LOS_INT pin remains high after an LOS event until all
sticky registers are cleared and all active status registers (for
example, Bits [3:0]) read 0.
allowing the AD8158 to offer exceptional transmit channel
compensation for legacy applications (4.5 Gbps and slower).
OUTPUT LEVEL PROGRAMMING AND OUTPUT
STRUCTURE
The output level of the transmitter of each lane is independently
programmable. In pin control mode, a default output amplitude
of 800 mV p-p diff ( 400 mV diff) is delivered (see Table 17).
Register-based control allows the user to set the transmitter
output levels on a per-port or per-lane basis to four predefined
levels. Port-level programming overwrites lane-level configuration.
The ALEV, BLEV, and CLEV bits in Register 0x49, Register 0x89,
and Register 0xC9, respectively, are used to set the output levels
for all transmitters. The A[3:0]OLEV[1:0], B[3:0]OLEV[1:0],
and C[3:0]OLEV[1:0] bits in Register 0x4C, Register 0x8C, and
Register 0xCC allow per-lane settings (see Table 23).
The LOS_INT pin can be used to generate an interrupt for the
system control software. In a standard implementation, when
LOS_INT goes high, the system software registers the interrupt
and polls the RXA, RXB, and RXC LOS status registers to
determine which input lost signal and if the signal has been
restored.
Table 17. Predefined Output Levels
LANE INVERSION: P/N SWAP
[A/B/C]OLEV1
[A/B/C]OLEV0
Output Level
200 mV diff
300 mV diff
400 mV diff (default)
600 mV diff
The receiver P/N swap function is a convenience intended to
allow the user to implement the equivalent of a board-level
routing crossover in a much smaller area while eliminating vias
(impedance discontinuities) that compromise the high frequency
integrity of the signal path.
0
0
1
1
0
1
0
1
Note that the choice of output level influences the output
common-mode level. A 600 mV diff output level with a full PE
range requires a supply and output termination voltage of 2.5 V
or higher (VTTO, VCC ≥ 2.5 V).
A Note of Caution
Using this feature to correct an inversion downstream of the
receiver may require the user to be aware of the sign of the data
when switching connectivity (the mux/demux path). The
feature is available on a per-lane setting through Register 0x44,
Register 0x84, and Register 0xC4. Setting the bit true flips the
sign sense of the P and N inputs for the associated lane. The
default setting is 0 (no inversion).
PRE-EMPHASIS
Transmitter pre-emphasis levels can be set by pin control or
through the control registers. Pin control allows two settings of
PE, 0 dB, and 6 dB. The control registers provide seven levels of
PE. Note that a larger range of boost settings is available for
lower output levels.
TRANSMITTERS
The AD8158 transmitter offers programmable pre-emphasis,
programmable output levels, output disable, and transmit
squelch. The SEL4G pin lets the user lower the transmitter
frequency of maximum boost from 3.25 GHz to 2.0 GHz,
Pre-emphasis can be programmed per-port or per-lane.
Register 0x49, Register 0x89, and Register 0xC9 set all outputs
in a port at once. Registers 0x4A, 0x4B, 0x8A, 0x8B, 0xCA, and
0xCB allow setting PE on a per-lane basis.
Table 18. Lane Inversion Bits
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
0x44
0x84
0xC4
PNA3
PNB3
PNC3
PNA2
PNB2
PNC2
PNA1
PNB1
PNC1
PNA0
PNB0
PNC0
P/N Swap A
P/N Swap B
P/N Swap C
Rev. 0 | Page 21 of 36
AD8158
V
V
CC
ON-CHIP TERMINATION
ESD
V3
VC
TTO
RP
TERM
RN
TERM
R
R
V2
VP
OP_xx
ON_xx
V1
VN
Q1
Q2
IT
PE
I
+ I
DC
V
EE
Figure 39. Simplified Transmitter Structure
Table 19. Setting Transmitter Pre-Emphasis (Note that Toggle Pin Control of PE Is Limited to the 400 mV diff Output Level Settings.)
Output Level
(mV diff)
Pin PE_[A/B/C] Bit [A/B/C][3:0]PE[2] Bit [A/B/C][3:0]PE[1] Bit [A/B/C][3:0]PE[0] PE Boost (%) PE Boost (dB)
200
200
200
200
200
200
200
300
300
300
300
300
300
300
400
400
400
400
400
400
400
600
600
600
600
600
600
600
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
0
50
100
150
200
250
300
0
3.52
6.02
7.96
9.54
10.88
12.04
0
33
2.5
67
4.44
6.02
7.36
8.52
9.54
0
100
133
167
200
0
25
1.94
3.52
4.86
6.02
7.04
7.96
0
N/A
N/A
N/A
1
50
75
100
125
150
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
17
1.34
2.5
33
50
3.52
4.44
5.26
6.02
67
83
100
Rev. 0 | Page 22 of 36
AD8158
Examples
OUTPUT COMPLIANCE, AC vs. DC COUPLING,
MINIMUM SUPPLY VOLTAGE, AND THE
TX_HEADROOM BIT
Consider a typical application using pin control mode. In this
case, the default output level of 400 mV diff (800 mV p-p diff)
is selected and the user can choose pre-emphasis settings of
0 dB or 6 dB. Table 19 shows that with pre-emphasis disabled, a
dc-coupled transmitter causes a 200 mV common-mode shift
across the termination resistors whereas an ac-coupled transmitter
causes twice the common-mode shift. Notice that with VCC and
VTTO powered from a 1.8 V supply, the single-ended output
voltage swings between 1.8 V and 1.4 V when dc-coupled and
between 1.6 V and 1.2 V when ac-coupled. (Note also that VH =
VH peak and VL = VL peak because transmitter pre-emphasis is
disabled.) In both cases, these levels are greater than the minimum
VL limit of 725 mV, and VCC satisfies the minimum VCC limit of
1.8 V with the TX_HEADROOM bit set to 0. Note that setting
TX_HEADROOM = 1 violates the minimum VCC limit of 2.5 V.
In low voltage applications, users must pay careful attention
to both the differential and common-mode signal level. The
choice of output voltage swing, pre-emphasis setting, supply
voltages (VCC and VTTO), and output coupling (ac or dc) affect
peak and settled single-ended voltage swings and the common-
mode shift measured across the output termination resistors.
These choices also affect output current and, consequently,
power consumption.
Table 20 shows the change in output common-mode (dVOCM
=
VCC − VOCM) with output level (VOD) and pre-emphasis setting.
Table 20 also shows the minimum and maximum dc and peak
single-ended output levels (VL, VH, VL peak, and VH peak,
respectively). The single-ended output levels are calculated for
With a PE setting of 6.02 dB, the ac-coupled transmitter has
single-ended swings from 1.4 V to 0.6 V while the dc-coupled
transmitter outputs swing between 1.8 V and 1 V. The peak
minimum single-ended swing (VL peak) of the ac-coupled
transmitter, in this case, exceeds the minimum VL limit of
725 mV by 125 mV. While objectionable in theory, in practice,
this setting works quite well. The transmitter theoretical peak
voltage is rarely achieved in practice because the high frequency
characteristic of the pre-emphasis is attenuated at the output
pins by the low-pass nature of the PC board environment and
the channel. For 6.5 Gbps PE (SEL4G = 0), a 30% reduction of
overshoot is not unexpected. For an output level of 400 mV diff
and a PE setting of 6 dB, the user can calculate a maximum
overshoot of 400 mV diff but can measure only a 270 mV
overshoot.
V
TTO supplies of 3.3 V and 1.8 V to illustrate practical challenges
of reducing the supply voltage. Table 20 shows the voltage
margins required for proper transmitter operation. Minimum
VL (min VL) is the lowest single-ended voltage allowed given the
user’s choice of VCC voltage.
For output levels greater than 400 mV diff (800 mV p-p diff), or
when enabling the TX_HEADROOM bit, operating the part
from core supply voltage, VCC ≥ 2.5 V, is suggested. In this high
current case, setting the TX_HEADROOM bit to 1 allows the
transmitter an extra 200 mV of output compliance range.
Additional transmitter headroom is enabled on a per-port basis
through Bits [6:4] in Register 0x05. A value of 0 disables the
headroom generating circuitry; a value of 1 enables it.
Theory (maximum)
V_overshoot_max = VOD × (PE [V/V] − 1)
Measured
V_overshoot_measured = VOD × (PE [V/V] − 1) × (1 − 0.3)
With the pre-emphasis configured for 4.25 Gbps operation
(SEL4G = 1), the overshoot can only be reduced 5% from the
theoretic maximum. In this case, the peak minimum voltage
limit should be more closely observed.
Rev. 0 | Page 23 of 36
AD8158
SIGNAL LEVELS AND COMMON-MODE SHIFT FOR AC-COUPLED AND DC-COUPLED OUTPUTS
Table 20. Output Voltage Range and Output Common-Mode Shift vs. Output Level and PE Setting
Output Levels and Output Compliance
AC-Coupled Transmitter
DC-Coupled Transmitter
TX_HEADROOM = 0 TX_HEADROOM = 1
VH
VL
VH
VL
VOD ITOT IPRED VD_PEAK PE
PE
dVOCM VH
VL
Peak Peak dVOCM VH
VL
Peak Peak
(mV) (mA) (mA) (mV)
Boost (dB) (mV) (V)
(V)
(V)
(V)
(mV) (V) (V) (V)
(V)
Min VL (V)
Min VL (V)
VTTO and VCC = 3.3 V
200
8
29
48
48
48
48
51
51
29
48
48
48
48
51
51
29
48
48
48
48
51
51
32
51
51
51
51
54
54
200
300
400
500
600
700
800
300
400
500
600
700
800
900
400
500
600
700
800
900
1000
600
700
800
900
1000
1100
1200
1.00 0.00 200
1.50 3.52 300
2.00 6.02 400
2.50 7.96 500
3.00 9.54 600
3.50 10.88 700
4.00 12.04 800
1.00 0.00 300
1.33 2.50 400
1.67 4.44 500
2.00 6.02 600
2.33 7.36 700
3.2
3.1
3
3
3.2
3
100
3.3 3.1 3.3
3.25 3.05 3.3
3.1
3
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
200 12
200 16
200 20
200 24
200 28
200 32
300 12
300 16
300 20
300 24
300 28
300 32
300 36
400 16
400 20
400 24
400 28
400 32
400 36
400 40
600 24
600 28
600 32
600 36
600 40
600 44
600 48
2.9
2.8
2.7
2.6
2.5
2.4
3.15 2.85 150
3.1 2.7 200
3.05 2.55 250
2.4 300
2.95 2.25 350
2.9 2.1 400
3.2
3
3.3
2.9
2.8
2.7
2.6
2.5
3
2.9
2.8
2.7
2.6
3.15 2.95 3.3
3.1 2.9 3.3
3.05 2.85 3.3
3
3
2.8 3.3
3 3.3
3.15 2.85 3.15 2.85 150
3.05 2.75 3.1 2.7 200
2.95 2.65 3.05 2.55 250
2.85 2.55 2.4 300
2.75 2.45 2.95 2.25 350
3.3
3.25 2.95 3.3
3.2 2.9 3.3
3.15 2.85 3.3
3.1 2.8 3.3
3.05 2.75 3.3
2.9
2.8
2.7
2.6
2.5
2.4
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.7
2.6
2.5
2.4
2.3
2.2
3
2.67 8.52 8001 2.651 2.351 2.91 2.11 400
3.00 9.54 9001 2.551 2.251 2.851 1.951 450
3
2.7 3.3
1.00 0.00 400
1.25 1.94 500
1.50 3.52 600
1.75 4.86 700
2.00 6.02 8001 2.71 2.31 2.91 2.11 400
2.25 7.04 9001 2.61 2.21 2.851 1.951 450
3.1
3
2.7
2.6
2.5
2.4
3.1
3.05 2.55 250
2.4 300
2.95 2.25 350
2.7
200
3.3 2.9 3.3
3.25 2.85 3.3
3.2 2.8 3.3
3.15 2.75 3.3
3.1 2.7 3.3
3.05 2.65 3.3
2.9
3
2.8
2.50 7.96
500
300
3
2.6 3.3
1.00 0.00 600
1.17 1.34 700
1.33 2.50 8001 2.81 2.21 2.91 2.11 400
1.50 3.52 9001 2.71 2.11 2.851 1.951 450
3
2.4
2.3
3
2.4
3.3 2.7 3.3
3.25 2.65 3.3
3.2 2.6 3.3
3.15 2.55 3.3
3.1 2.5 3.3
3.05 2.45 3.3
2.9
2.95 2.25 350
1.67 4.44
1.83 5.26
2.00 6.02
500
550
6001 31
2.41 3.31 2.11 2.2
VCC and VTTO = 1.8 V, TX_HEADROOM = 1 requires VCC > 2.5 V
200
8
29
48
48
48
48
51
51
29
48
48
48
48
51
51
29
48
48
48
48
51
51
200
300
400
500
600
700
800
300
400
500
600
700
800
900
400
500
600
700
800
900
1000
1.00 0.00 200
1.50 3.52 300
2.00 6.02 400
2.50 7.96 500
3.00 9.54 600
3.50 10.88 700
4.00 12.04
1.7
1.6
1.5
1.4
1.3
1.2
1.5
1.4
1.3
1.2
1.1
1
1.7
1.65 1.35 150
1.6 1.2 200
1.55 1.05 250
1.5 0.9 300
1.5
100
1.8 1.6 1.8
1.6
1.5
1.4
1.3
1.2
1.1
1
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
200 12
200 16
200 20
200 24
200 28
200 32
300 12
300 16
300 20
300 24
300 28
300 32
300 36
400 16
400 20
400 24
400 28
400 32
400 36
400 40
1.75 1.55 1.8
1.7 1.5 1.8
1.65 1.45 1.8
1.6 1.4 1.8
1.55 1.35 1.8
1.5 1.3 1.8
1.8 1.5 1.8
1.75 1.45 1.8
1.7 1.4 1.8
1.65 1.35 1.8
1.6 1.3 1.8
1.55 1.25 1.8
1.5 1.2 1.8
1.8 1.4 1.8
1.75 1.35 1.8
1.7 1.3 1.8
1.65 1.25 1.8
1.6 1.2 1.8
1.55 1.15 1.8
1.5 1.1 1.8
1.45 0.75 350
400
1.00 0.00 300
1.33 2.50 400
1.67 4.44 500
2.00 6.02 600
2.33 7.36 700
2.67 8.52
1.65 1.35 1.65 1.35 150
1.55 1.25 1.6 1.2 200
1.45 1.15 1.55 1.05 250
1.35 1.05 1.5 0.9 300
1.5
1.4
1.3
1.2
1.1
1
1.25 0.95 1.45 0.75 350
400
450
3.00 9.54
0.9
1.4
1.3
1.2
1.1
1
1.00 0.00 400
1.25 1.94 500
1.50 3.52 600
1.75 4.86 700
2.00 6.02
1.6
1.5
1.4
1.3
1.2
1.1
1
1.6
1.55 1.05 250
1.5 0.9 300
1.2
200
0.9
1.45 0.75 350
400
450
500
2.25 7.04
0.9
0.8
2.50 7.96
Rev. 0 | Page 24 of 36
AD8158
Output Levels and Output Compliance
AC-Coupled Transmitter
DC-Coupled Transmitter
TX_HEADROOM = 0 TX_HEADROOM = 1
VH
VL
VH
VL
VOD ITOT IPRED VD_PEAK PE
(mV) (mA) (mA) (mV) Boost (dB) (mV) (V)
PE
dVOCM VH
VL
(V)
Peak Peak dVOCM VH
VL
Peak Peak
(V)
(V)
(mV) (V) (V) (V)
(V)
1.2
1.1
1
Min VL (V)
0.7
Min VL (V)
0.5
600 24
600 28
600 32
600 36
600 40
600 44
600 48
32
51
51
51
51
54
54
600
1.00 0.00 600
1.17 1.34 700
1.33 2.50
1.5
1.4
0.9
0.8
1.5
0.9
300
1.8 1.2 1.8
1.75 1.15 1.8
1.7 1.1 1.8
1.65 1.05 1.8
700
1.45 0.75 350
0.7
0.5
800
400
450
500
550
0.7
0.5
900
1.50 3.52
0.9
0.8
0.7
0.7
0.5
1000
1100
1200
1.67 4.44
1.6
1
1.8
0.7
0.5
1.83 5.26
1.55 0.95 1.8
0.7
0.5
2.00 6.02
0.7
0.5
1 Requires TX_HEADROOM = 1.
Table 21. Symbol Definitions
Symbol
Formula
25 Ω × IDC
25 Ω × IDC × 2 = 2 × VOD
25 Ω × ITX/2 = VODPP/4 + (IPE/2 × 25)
50 Ω × ITX/2 = VODPP/2 + (IPE/2 × 50)
VOD/RTERM
N/A
IDC + IPE
VTTO − ∆VOCM + VOD/2
VTTO − ∆VOCM − VOD/2
Definition
VOD
VOD p-p
∆VOCM_DC-COUPLED
∆VOCM_AC-COUPLED
IDC
IPE
ITX
VH
VL
Peak differential output voltage
Peak-to-peak differential output voltage
Output common-mode shift
Output common-mode shift
Output current that sets output level
Output current used for PE
Total transmitter output current
Maximum single-ended output voltage
Minimum single-ended output voltage
V
TTO
DV
OCM
V
V
V
H
V
OD
OCM
L
V
p-p = 2 × V
OD
OD
V
EE
Figure 40. VH, VL, VOCM
Rev. 0 | Page 25 of 36
AD8158
AD8158 POWER CONSUMPTION
SQUELCH AND DISABLE
There are several sections of the AD8158 that draw varying
power depending on the supply voltages, the type of I/O
coupling used, and the status of the AD8158 operation. Figure 41
shows a block diagram of these sections. Figure 42 summarizes
the power consumption of each section and is a useful guide as
the following sections are reviewed.
Each transmitter is equipped with disable and squelch controls.
Disable is a full power-down state: the transmitter current is
reduced to zero and the output pins pull up to VTTO, but there
is a delay of approximately 1 μs associated with re-enabling
the transmitter. Squelch simply reduces the output current to
submicroamp levels, again allowing both output pins to pull up
to VTTO through the output termination resistors. The transmit-
ter recovers from squelch in less than 100 ns.
A power budget calculator is available on the AD8158 product
page at www.analog.com.
SPEED SELECT
The SEL4G pin lets the user lower the transmitter frequency of
maximum boost from 3.25 GHz to 2.0 GHz, allowing the
AD8158 to offer exceptional transmit channel compensation for
legacy applications (4.5 Gbps and slower). SEL4G = 1 lowers the
frequency of maximum boost without sacrificing the amount of
boost delivered.
V
DV
CC
V
V
TTO
CC
VTT
TTI
OUTPUT
TERMINATIONS
I
OUT
2
P =
× 50Ω
50Ω
50Ω
50Ω
50Ω
EQUALIZER
IP_xx
IN_xx
OPTIONAL COUPLING
CAPACITORS
LOSS OF
INPUT
SIGNAL
TERMINATION
P = (V ) (I
)
OL OUT
2
)
AC-COUPLING CAPS
(OPTIONAL)
(V
IN_DIFF_RMS
I
OUT
V
= V
– (I
× 25Ω)
P =
RECEIVER
SWITCH
OL
TTO OUT
100Ω
V
EE
Figure 41. AD8158 Power Distribution Block Diagram
Rev. 0 | Page 26 of 36
AD8158
0 3 3 4 6 - 6 6 0
Figure 42. Power Budget Calculator
Rev. 0 | Page 27 of 36
AD8158
The first section is the input termination resistors. The power
dissipated in the termination resistors is due to the input
differential swing and any common-mode current resulting
from dc-coupling the input.
This pre-emphasis current gives rise to an output common-
mode shift, which varies with ac-coupling or dc-coupling and
which is calculated for both cases in Table 20.
Perhaps the most direct method for calculating power dissi-
pated in the output is to calculate the power that would be
dissipated if all of ITOT were to flow on-die from VTTO to VEE
and to subtract from this the power dissipated off-die in the
destination device termination resistors and the channel.
For this purpose, the destination device and channel can be
modeled as 50 ꢀ load resistors, RL, in parallel with the AD8158
termination resistors.
In the next section, the receiver, each input is powered only
when it is selected and the disable bits are set to 0. If a receiver
is not selected, it is powered down. Thus, the total number of
active inputs affects the total power consumption. Furthermore,
the loss-of-signal detection circuits can be disabled independent
of the receiver for even greater power savings.
The core of the device performs the multiplexer and demulti-
plexer switching functions. It draws a fixed quiescent current of
2 mA whenever the AD8158 is powered from VCC to VEE. The
switch draws an additional 8 × 4.6 mA in normal mux/demux
operation and an additional 12 × 4.6 mA with all ports in
loopback or with bicast selected. The switch core can be
disabled to save power.
POWER SAVING CONSIDERATIONS
While the AD8158 power consumption is very low compared to
similar devices, careful control of its operating conditions can
yield further power savings. Significant power reduction can be
realized by operating the part at a lower voltage. Compared to
3.3 V operation, a supply voltage of 1.8 V can result in power
savings of ~45%. There is no performance penalty when
operating at lower voltage.
An output predriver section draws a current, IPRED, that is
related to the programmed output current, ITOT. Table 20 lists
values for ITOT and IPRED for all settings of output level and pre-
emphasis. The predriver current always flows from VCC to VEE.
It is treated separately from the output current, which flows
A second measure is to disable transmitters when they are not
being used. This can be done on a static basis if the output is
not used or on a dynamic basis if the output does not have a
constant stream of traffic. On transmit disable (Register 0x48,
Register 0x88, Register 0xC8), both the predriver and output
switch currents are disabled. The LOS-activated squelch
disables only the output switch current, ITOT. Superior power
saving is achieved by using the TX and RX disable registers to
turn off an unused lane as opposed to relying on the AD8158
transmit squelch feature.
from VTTO, and may not be the same voltage as VCC
.
The final section is the outputs. For an individual output, the
programmed output current flows through two separate paths.
One is the on-chip termination resistor, and the other is the
transmission line and the destination termination resistor. The
nominal parallel impedance of these two paths is 25 ꢀ. The
sum of these two currents flows through the switches and the
current source of the AD8158 output circuit and out through VEE.
The power dissipated in the transmission line and the destination
resistor is not dissipated in the AD8158 but has to be supplied
from the power supply and is a factor in the overall system
power. The current in the on-chip termination resistors and
the output current source dissipate power in the AD8158 itself.
Because the majority of the power dissipated is in the output
stage, some of its flexibility can be used to lower the power
consumption. First, the output current and output pre-emphasis
settings can be programmed to the smallest amount required to
maintain BER performance. If an output circuit always has a
short length and the receiver has good sensitivity, then a lower
output current can be used.
OUTPUTS
The output current is set by a combination of output level and
pre-emphasis setting (see Table 20). For the two logic switch
states, this current flows through an on-chip termination
resistor and a parallel path to the destination device and its
termination resistor. The power in this parallel path is not
dissipated by the AD8158. With pre-emphasis enabled, some
current always flows in both the P and N termination resistors.
It is also possible to lower the voltage on VTTO to lower the
power dissipation. The amount that VTTO can be lowered is
dependent on the lowest of all the output’s VOL and VCC. This
is determined by the output that is operating at the highest
programmed output current. Table 1 and Table 20 list minimum
output levels.
Rev. 0 | Page 28 of 36
AD8158
I2C CONTROL INTERFACE
5. Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
SERIAL INTERFACE GENERAL FUNCTIONALITY
The AD8158 register set is controlled through a 2-wire I2C
interface. The AD8158 acts only as an I2C slave device. The
7-bit slave address for the AD8158 I2C interface contains the
static value b1010 for the upper four bits. The lower three bits
are controlled by the input pins I2C_A[2:0].
Therefore, the I2C bus in the system needs to include an I2C
master to configure the AD8158 and other I2C devices that may
be on the bus. Data transfers are controlled through the use of
the two I2C wires: the SCL input clock pin and the SDA bidirec-
tional data pin.
The AD8158 I2C interface can be run in the standard (100 kHz)
and fast (400 kHz) modes. The SDA line only changes value
when the SCL pin is low with two exceptions. To indicate the
beginning or continuation of a transfer, the SDA pin is driven
low while the SCL pin is high, and to indicate the end of a
transfer, the SDA line is driven high while the SCL line is high.
Therefore, it is important to control the SCL clock to toggle
only when the SDA line is stable unless indicating a start,
repeated start, or stop condition.
6. Wait for the AD8158 to acknowledge the request.
7. Send the data (eight bits) to be written to the register whose
address was set in Step 5. This transfer should be MSB first.
8. Wait for the AD8158 to acknowledge the request.
9a. Send a stop condition (while holding the SCL line high,
pull the SDA line high) and release control of the bus.
9b. Send a repeated start condition (while holding the SCL
line high, pull the SDA line low) and continue with Step 2
in this procedure to perform another write.
9c. Send a repeated start condition (while holding the SCL
line high, pull the SDA line low) and continue with Step 2
of the read procedure (in the I2C Interface Data Transfers:
Data Read section) to perform a read from another
address.
9d. Send a repeated start condition (while holding the SCL
line high, pull the SDA line low) and continue with Step 8
of the read procedure (in the I2C Interface Data Transfers:
Data Read section) to perform a read from the same
address set in Step 5.
I2C INTERFACE DATA TRANSFERS: DATA WRITE
In Figure 43, the AD8158 write process is shown. The SCL
signal is shown along with a general write operation and a
specific example. In this example, the value 0x92 is written to
Address 0x6D of an AD8158 device with a part address of 0x53.
The part address is seven bits wide and is composed of the
AD8158 static upper four bits (b1010) and the pin-programmable
lower three bits (I2C_A[2:0]). The address pins are set to b011.
In Figure 43, the corresponding step number is visible in the
circle under the waveform. The SCL line is driven by the I2C
master and never by the AD8158 slave. As for the SDA line, the
data in the shaded polygons is driven by the AD8158, whereas
the data in the nonshaded polygons is driven by the I2C master.
The end phase case shown is that of Step 9A.
To write data to the AD8158 register set, a microcontroller or
any other I2C master needs to send the appropriate control
signals to the AD8158 slave device. The following steps need to
be taken, where the signals are controlled by the I2C master,
unless otherwise specified. For a diagram of the procedure, see
Figure 43.
1. Send a start condition (while holding the SCL line high,
pull the SDA line low).
2. Send the AD8158 part address (seven bits) whose upper
four bits are the static value b1010 and whose lower three
bits are controlled by the I2C_A[2:0] input pins. This
transfer should be MSB first.
It is important to note that the SDA line only changes when the
SCL line is low, except for the case of sending a start, stop, or
repeated start condition (Step 1 and Step 9 in this case).
3. Send the write indicator bit (0).
4. Wait for the AD8158 to acknowledge the request.
SCL
ADDR
[1:0]
START
FIXED PART ADDR
R/W ACK
REGISTER ADDR
ACK
DATA
ACK
STOP
SDA
SDA
1
2
2
3
4
5
6
7
8
9a
Figure 43. I2C Write Diagram
Rev. 0 | Page 29 of 36
AD8158
13a. Send a stop condition (while holding the SCL line high,
pull the SDA line high) and release control of the bus.
13b. Send a repeated start condition (while holding the SCL
line high, pull the SDA line low) and continue with Step 2
of the write procedure (see the I2C Interface Data
I2C INTERFACE DATA TRANSFERS: DATA READ
To read data from the AD8158 register set, a microcontroller
or any other I2C master needs to send the appropriate control
signals to the AD8158 slave device. The following steps need
to be taken, where the signals are controlled by the I2C master,
unless otherwise specified. For a diagram of the procedure, see
Figure 44.
Transfers: Data Write section) to perform a write.
13c. Send a repeated start condition (while holding the SCL
line high, pull the SDA line low) and continue with Step 2
of this procedure to perform a read from another address.
13d. Send a repeated start condition (while holding the SCL
line high, pull the SDA line low) and continue with Step 8
of this procedure to perform a read from the same address.
1. Send a start condition (while holding the SCL line high,
pull the SDA line low).
2. Send the AD8158 part address (seven bits) whose upper
four bits are the static value b1010 and whose lower three
bits are controlled by the I2C_A[2:0] input pins. This
transfer should be MSB first.
In Figure 44, the AD8158 read process is shown. The SCL signal is
shown along with a general read operation and a specific example.
In this example, the value 0x49 is read from Address 0x6D of
an AD8158 device with a 0x53 part address. The part address
is seven bits wide and is composed of the AD8158 static upper
four bits (b1010) and the pin-programmable lower three bits
(I2C_A[2:0]). The address pins are set to b011. In Figure 44, the
corresponding step number is visible in the circle under the
waveform. The SCL line is driven by the I2C master and never
by the AD8158 slave. As for the SDA line, the data in the shaded
polygons is driven by the AD8158, whereas the data in the
nonshaded polygons is driven by the I2C master. The end phase
case shown is that of Step 13A.
3. Send the write indicator bit (0).
4. Wait for the AD8158 to acknowledge the request.
5. Send the register address (eight bits) from which data is to
be read. This transfer should be MSB first. The register
address is kept in memory in the AD8158 until the part is
reset or the register address is written over with the same
procedure (Step 1 to Step 6).
6. Wait for the AD8158 to acknowledge the request.
7. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low).
8. Send the AD8158 part address (seven bits) whose upper
four bits are the static value b1010 and whose lower three
bits are controlled by the I2C_A[2:0] input pins. This
transfer should be MSB first.
It is important to note that the SDA line only changes when
the SCL line is low, except for the case of sending a start, stop,
or repeated start condition, as in Step 1, Step 7, and Step 13.
In Figure 44, A is the same as ACK. Equally, Sr represents a
repeated start where the SDA line is brought high before SCL
is raised. SDA is then dropped while SCL is still high.
9. Send the read indicator bit (1).
10. Wait for the AD8158 to acknowledge the request.
11. The AD8158 then serially transfers the data (eight bits)
held in the register indicated by the address set in Step 5.
12. Acknowledge the data.
SCL
ADDR R/
FIXED PART
ADDR
ADDR R/
A
START
b11110
A
REGISTER ADDR
A
6
Sr
DATA
A
STOP
SDA
SDA
[1:0]
W
[1:0]
W
1
2
2
3
4
5
7
8
8
9
10
11
12
13a
Figure 44. I2C Read Diagram
Rev. 0 | Page 30 of 36
AD8158
APPLICATIONS INFORMATION
SUPPLY SEQUENCING
Table 22. Alternate Supply Configuration Examples
Signal Level
VCC, VTTI, VTTO
VEE
Ideally, all power supplies should be brought up to the appropri-
ate levels simultaneously (power supply requirements are set by
the supply limits in Table 1 and the absolute maximum ratings
listed in Table 3). In the event that the power supplies to the
AD8158 are brought up separately, the supply power-up sequence
is as follows: DVCC powered first, followed by VCC, and lastly
1.2 V CML
GND − 400 mV diff
1.2 V
GND
−2.1 V ≤VEE ≤ −0.6 V
−3.3 V ≤VEE ≤ +1.8 V
The AD8158 control signals are always referenced between
DVCC and VEE and, when using a split supply configuration,
logic level-shift circuits should be used. The evaluation board
design shows the use of the Analog Devices, Inc., ADUM1250
I2C isolator and a level shifter to level-shift the SCL and SDA
signals.
VTTI and VTTO. The power-down sequence is reversed with VTTI
and VTTO being powered off first.
VTTI and VTTO contain ESD protection diodes to the VCC power
domain (see Figure 38 and Figure 39). To avoid a sustained high
current condition in these devices (ISUSTAINED < 100 mA), the
Evaluation of DC-Coupled Links
When evaluating the AD8158 dc-coupled, remember that most
lab equipment is ground referenced while the AD8158 high
speed I/O are connected by 50 ꢀ on-die termination resistors to
VTTI and VTTO supplies should be powered on after VCC and
should be powered off before VCC
.
If the system power supplies have a high impedance in the
powered off state, then supply sequencing is not required
provided the following limits are observed:
V
TTI and VTTO. To interface the AD8158 to ground-referenced,
high speed instrumentation (for example, the 50 ꢀ inputs of a
high speed oscilloscope), it is necessary to level-shift the outputs by
either using a dc-blocking network or by powering the AD8158
between ground and a negative supply.
•
•
Peak current from VTTI or VTTO to VCC < 200 mA
Sustained current from VTTI or VTTO to VCC < 100 mA
For example, to evaluate 1.8 V dc-coupled transmitter perfor-
mance with a 50 ꢀ ground-referenced oscilloscope, use the
following supply configuration:
SINGLE SUPPLY vs. MULTIPLE SUPPLY
OPERATION
The AD8158 supports a flexible supply voltage of 1.8 V to 3.3 V.
For some dc-coupled links, 1.2 V or ground-referenced signaling
may be desired. In these cases, the AD8158 can be run with a
split supply configuration.
V
V
CC = VTTO = VTTI = Ground
EE = −1.8 V
Ground < DVCC < 1.5 V
Rev. 0 | Page 31 of 36
AD8158
REGISTER MAP
All registers are port-level and global registers, unless otherwise noted.
Table 23. Register Definitions
Mnemonic
Addr. Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Reset
0x00
RESET
Switch
Control 1
0x01
LBC
LBB
LBA
SELAb/B[3]
SELAb/B[2]
SELAb/B[1]
SELAb/B[0]
0x00
0x00
0x0F
Switch
Control 2
0x02
0x04
0x05
SEL4G
BICAST
Global
Squelch Ctrl
GSQLCH_ENB
Switch Core/
Headroom
TX_HEAD
ROOM_C
TX_HEAD
ROOM_B
TX_HEAD
ROOM_A
XCORE_ENB 0x01
Mode
0x0F
0x40
0x41
MODE[1]
RXDIS A1
AEQ[1]
MODE[0]
RXDIS A0
AEQ[0]
0x00
0x00
0x00
0x1C
RXA Disable
RXA Setting
RXDIS A3
AEQ[3]
RXDIS A2
AEQ[2]
RXA LOS
Threshold
0x50
0x51
0x421
Set to 0
Set to 0
Set to 0
A1EQ[2]
THRBIT[5]
Set to 0
THRBIT[4]
Set to 0
THRBIT[3]
THRBIT[2]
THRBIT[1]
THRBIT[0]
RXA LOS
Control
Set to 0
A1EQ[3]
Set to 0
A0EQ[3]
LOS_FILT
A0EQ[2]
LOS_GSEL
A0EQ[1]
LOS_ENB
A0EQ[0]
0x07
0x00
RXA Lane 1/
RXA Lane 0
Setting
A1EQ[1]
A1EQ[0]
RXA Lane 3/
RXA Lane 2
Setting
0x431
A3EQ[3]
A3EQ[2]
A3EQ[1]
A3EQ[0]
A2EQ[3]
PNA3
A2EQ[2]
PNA2
A2EQ[1]
PNA1
A2EQ[0]
PNA0
0x00
0x00
RXA P/N
Swap
0x441
0x451
RXA LOS
Status
LOSA3
Sticky
LOSA2
Sticky
LOSA1
Sticky
LOSA0
Sticky
LOSA3 Active LOSA2
Active
LOSA1
Active
LOSA0
Active
TXA Disable
0x48
0x49
TXDIS A3
TXDIS A2
TXDIS A1
APE[1]
TXDIS A0
APE[0]
0x00
0x20
TXA Level/PE
Control
ALEV[1]
A1PE[1]
ALEV[0]
A1PE[0]
APE[2]
TXA Lane1/
TXA Lane 0
PE Setting
0x4A1
A1PE[2]
A0PE[2]
A0PE[1]
A0PE[0]
0x00
TXA Lane2/3
PE Setting
0x4B1
A3PE[2]
A3PE[1]
A3PE[0]
A2PE[2]
A2PE[1]
A2PE[0]
0x00
0xAA
TXA Per-Lane
Level Setting
0x4C1 A3OLEV[1]
A3OLEV[0]
A2OLEV[1]
A2OLEV[0]
A1OLEV[1]
A1OLEV[0]
A0OLEV[1]
A0OLEV[0]
RXB Disable
RXB Setting
0x80
0x81
RXDIS B3
BEQ[3]
RXDIS B2
BEQ[2]
RXDIS B1
BEQ[1]
RXDIS B0
BEQ[0]
0x00
0x00
0x1C
RXB LOS
0x90
Set to 0
Set to 0
THRBIT[5]
THRBIT[4]
THRBIT[3]
THRBIT[2]
THRBIT[1]
THRBIT[0]
Threshold
RXB LOS Ctrl
0x91
Set to 0
B1EQ[3]
Set to 0
B1EQ[2]
Set to 0
B1EQ[1]
Set to 0
B1EQ[0]
Set to 0
B0EQ[3]
LOS_FILT
B0EQ[2]
LOS_GSEL
B0EQ[1]
LOS_ENB
B0EQ[0]
0x07
0x00
RXB Lane 1/
RXB Lane 0
Setting
0x821
RXB Lane 3/
RXB Lane 2
Setting
0x831
B3EQ[3]
B3EQ[2]
B3EQ[1]
B3EQ[0]
B2EQ[3]
B2EQ[2]
PNB2
B2EQ[1]
PNB1
B2EQ[0]
PNB0
0x00
0x00
RXB P/N
Swap
0x841
0x851
PNB3
RXB LOS
Status
LOSB3
Sticky
LOSB2
Sticky
LOSB1
Sticky
LOSB0
Sticky
LOSB3 Active
TXDIS B3
LOSB2
Active
LOSB1
Active
LOSB0
Active
TXB Disable
0x88
0x89
TXDIS B2
BPE[2]
TXDIS B1
BPE[1]
TXDIS B0
BPE[0]
0x00
0x20
TXB Level/PE
Control
BLEV[1]
B1PE[1]
BLEV[0]
B1PE[0]
TXB Lane1/
TXB Lane 0
PE Setting
0x8A1
B1PE[2]
B0PE[2]
B0PE[1]
B0PE[0]
0x00
Rev. 0 | Page 32 of 36
AD8158
Mnemonic
Addr. Bit 7
0x8B1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
TXB Lane2/
TXB Lane 3
PE Setting
B3PE[2]
B3PE[1]
B3PE[0]
B2PE[2]
B2PE[1]
B2PE[0]
0x00
TXB Per-Lane
Level Setting
0x8C1 B3OLEV[1]
B3OLEV[0]
B2OLEV[1]
B2OLEV[0]
B1OLEV[1]
B1OLEV[0]
B0OLEV[1]
B0OLEV[0]
0xAA
RXC Disable
RXC Setting
0xC0
0xC1
RXDIS C3
CEQ[3]
RXDIS C2
CEQ[2]
RXDIS C1
CEQ[1]
RXDIS C0
CEQ[0]
0x00
0x00
0x1C
RXC LOS
Threshold
0xD0
Set to 0
Set to 0
Set to 0
THRBIT[5]
THRBIT[4]
THRBIT[3]
THRBIT[2]
THRBIT[1]
THRBIT[0]
RXC LOS Ctrl
0xD1
Set to 0
C1EQ[2]
Set to 0
C1EQ[1]
Set to 0
C1EQ[0]
Set to 0
C0EQ[3]
LOS_FILT
C0EQ[2]
LOS_GSEL
C0EQ[1]
LOS_ENB
C0EQ[0]
0x07
0x00
RXC Lane 1/
RXC Lane 0
Setting
0xC21 C1EQ[3]
0xC31 C3EQ[3]
0xC41
RXC Lane 3/
RXC Lane 2
Setting
C3EQ[2]
C3EQ[1]
C3EQ[0]
C2EQ[3]
C2EQ[2]
PNC2
C2EQ[1]
PNC1
C2EQ[0]
PNC0
0x00
0x00
RXC P/N
Swap
PNC3
RXC LOS
Status
0xC51 LOSC3
Sticky
LOSC2
Sticky
LOSC1
Sticky
LOSC0
Sticky
LOSC3 Active
TXDIS C3
LOSC2
Active
LOSC1
Active
LOSC0
Active
TXC Disable
0xC8
0xC9
TXDIS C2
CPE[2]
TXDIS C1
CPE[1]
TXDIS C0
CPE[0]
0x00
0x20
TXC Level/PE
Control
CLEV[1]
C1PE[1]
CLEV[0]
C1PE[0]
TXC Lane1/
TXC Lane 0
PE Setting
0xCA1
C1PE[2]
C0PE[2]
C0PE[1]
C0PE[0]
0x00
0x00
0xAA
TXC Lane2/
TXC Lane 3
PE Setting
0xCB1
C3PE[2]
C3PE[1]
C3PE[0]
C2PE[2]
C2PE[1]
C2PE[0]
TXC Per-Lane
Level Setting
0xCC1 C3OLEV[1]
C3OLEV[0]
C2OLEV[1]
C2OLEV[0]
C1OLEV[1]
C1OLEV[0]
C0OLEV[1]
C0OLEV[0]
1 Per-lane registers.
Rev. 0 | Page 33 of 36
AD8158
OUTLINE DIMENSIONS
0.25
0.20
0.15
0.60 MAX
12.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
75
76
1
100
PIN 1
INDICATOR
0.40
BSC
11.75
BSC SQ
7.00
6.90 SQ
6.80
EXPOSEDPAD
(BOTTOM VIEW)
26
50
51
25
0.20 MIN
0.50
0.40
0.30
TOP VIEW
0.70
0.65
0.60
9.60 REF
12° MAX
0.90
0.85
0.80
THE EXPOSED METAL PADDLE ON THE
BOTTOM OF THE LFCSP PACKAGE
MUST BE SOLDERED TO PCB GROUND
FOR PROPER HEAT DISSIPATION AND
ALSO FOR NOISE AND MECHANICAL
STRENGTH BENEFITS.
0.05 MAX
0.01 NOM
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VRRE.
Figure 45. 100-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
12 mm × 12 mm Body, Very Thin Quad
(CP-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8158ACPZ1
AD8158-EVALZ1
−40°C to +85°C
100-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
CP-100-1
1 Z = RoHS Compliant Part.
Rev. 0 | Page 34 of 36
AD8158
NOTES
Rev. 0 | Page 35 of 36
AD8158
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06646-0-6/08(0)
Rev. 0 | Page 36 of 36
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