AD8159ASVZ [ADI]
3.2 Gbps Quad Buffer Mux/Demux; 3.2 Gbps的四路缓冲复用器/解复用器
| 型号： | AD8159ASVZ |
| 厂家： | 
ADI |
| 描述： | 3.2 Gbps Quad Buffer Mux/Demux |
| 文件： | 总24页 (文件大小：591K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.2 Gbps
Quad Buffer Mux/Demux
AD8159
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Port level 2:1 mux/1:2 demux
Each port consists of 4 lanes
Each lane runs from dc to 3.2 Gbps, independent
of the other lanes
Compensates over 40 inches of FR4 at 3.2 Gbps through
two levels of input equalization, or four levels of output
pre-emphasis
RECEIVE
EQUALIZATION
TRANSMIT
PRE-
EMPHASIS
I/O
CROSS-
OVER
SWITCH
EQ
EQ
IN_A[3:0]
IN_B[3:0]
OUT_C[3:0]/
IN_C[3:0]
2:1
Accepts ac- or dc-coupled differential CML inputs
Low deterministic jitter, typically 20 ps p-p
Low random jitter, typically 1 ps rms
BER < 10-16
OUT_A[3:0]
OUT_B[3:0]
IN_C[3:0]/
OUT_C[3:0]
1:2
EQ
QUAD
2:1
MULTIPLEXER/
1:2
RECEIVE
EQUALIZATION
TRANSMIT
PRE-
EMPHASIS
LB_A
LB_B
LB_C
PE_A[1:0]
PE_B[1:0]
PE_C[1:0]
EQ_A
EQ_B
EQ_C
On-chip termination
DEMULTIPLEXER
Reversible inputs and outputs on one port
Unicast or bicast on 1:2 demux function
Port level loopback capability
Single lane switching capability
3.3 V core supply
CONTROL
LOGIC
SEL[3:0]
BICAST
REVERSE_C
AD8159
Flexible I/O supply down to 2.5 V
Low power, typically 1 W in basic configuration
100-pin TQFP_EP
Figure 1.
−40°C to +85°C operating temperature range
APPLICATIONS
Low cost redundancy switch
SONET OC48/SDH16 and lower data rates
XAUI (10 Gigabit Ethernet) over backplane
Gigabit Ethernet over backplane
Fibre channel 1.06 Gbps and 2.125 Gbps over backplane
Infiniband over backplane
PCI-Express over backplane
GENERAL DESCRIPTION
The main application of the AD8159 is to support redundancy
on both the backplane side and the line interface side of a serial
link. The device has unicast and bicast capability, so it is
configurable to support either 1 + 1 or 1:1 redundancy.
The AD8159 is an asynchronous, protocol agnostic, quad-lane
2:1 switch with a total of 12 differential PECL/CML-compatible
inputs and 12 differential CML outputs. The operation of this
product is optimized for NRZ signaling with data rates up to
3.2 Gbps per lane. Each lane offers two levels of input
The AD8159 supports reversing the output and input pins on
one of its ports, which helps to connect two ASICs with
opposite pinouts.
equalization and four levels of output pre-emphasis.
The AD8159 consists of four multiplexers and four demulti-
plexers, one per lane. Each port is a 4-lane link, and each lane
runs up to a 3.2 Gbps data rate independent of the other lanes.
The lanes are switched independently using the four select pins,
SEL[3:0]; each select pin controls one lane of the port. The
AD8159 has low latency and very low lane-to-lane skew.
The AD8159 is also used for testing high speed serial links by
duplicating incoming data and sending it to the destination port
and to test equipment simultaneously.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD8159
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 15
Input Equalization (EQ) and Output Pre-Emphasis (PE) .... 15
Loopback ..................................................................................... 16
Port C Reverse (Crossover) Capability.................................... 17
Applications..................................................................................... 18
Interfacing to the AD8159............................................................. 19
Termination Structures.............................................................. 19
Input Compliance....................................................................... 19
Output Compliance ................................................................... 20
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 7
Evaluation Board Simplified Block Diagrams ............................ 12
Test Circuits..................................................................................... 13
REVISION HISTORY
4/06—Rev. 0 to Rev. A
Changes to Applications Section .................................................... 1
Changes to Table 5.......................................................................... 15
Updates to Outline Dimensions ................................................... 22
Changes to Ordering Guide .......................................................... 22
9/05—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD8159
SPECIFICATIONS
VCC = +3.3 V, VEE = 0 V, RL = 50 Ω, basic configuration,1 data rate= 3.2 Gbps, input common-mode voltage = 2.7 V, differential input
swing = 800 mV p-p, @ TA = +25°C, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
DC
Typ
Max
3.2
Unit
DYNAMIC PERFORMANCE
Data Rate/Channel (NRZ)
Deterministic Jitter
Random Jitter
Gbps
ps p-p
ps
Data rate = 3.2 Gbps; see Figure 21
RMS; see Figure 24
20
1
Propagation Delay
Lane-to-Lane Skew
Switching Time
Input to output
600
100
5
ps
ps
ns
Output Rise/Fall Time
INPUT CHARACTERISTICS
Input Voltage Swing
Input Voltage Range
Input Bias Current
Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Range
Output Current
20% to 80%
100
ps
Differential, VICM = VCC − 0.6 V;2 see Figure 22
Common mode, VID = 800 mV p-p;3 see Figure 25
200
VEE + 1.8
2000
VCC + 0.3
mV p-p
V
μA
pF
4
2
Differential, PE = 0
Single-ended absolute voltage level; see Figure 26
Port A/B, PE_A/B = 0
Port C, PE_C = 0
Port A/B, PE_A/B = 3
800
mV p-p
V
VCC − 1.6
VCC + 0.6
16
20
28
32
2
mA
mA
mA
mA
pF
Port C, PE_C = 3
Output Capacitance
TERMINATION CHARACTERISTICS
Resistance
Temperature Coefficient
POWER SUPPLY
Operating Range
VCC
Differential
VEE = 0 V
90
100 110
0.15
Ω
Ω/°C
3.0
3.3
3.6
V
Supply Current
ICC
II/O = ITTO + ITTOI + ITTI + ITTIO
Supply Current
ICC
II/O = ITTO + ITTOI + ITTI + ITTIO
THERMAL CHARACTERISTICS
Operating Temperature Range
θJA
Basic configuration1, dc-coupled inputs/outputs, 400 mV I/O
swings (800 mV p-p differential), 50 Ω far end terminations
175
144
mA
mA
BICAST = 1, PE = 3 on all ports, dc-coupled inputs/outputs,
400 mV I/O swings (800 mV p-p differential), 50 Ω far end
terminations
255
352
mA
mA
−40
+85
°C
Still air
Still air
Still air
29
16
13
°C/W
°C/W
°C/W
θJB
θJC
LOGIC INPUT CHARACTERISTICS
Input High (VIH)
Input Low (VIL)
2.4
VEE
VCC
0.8
V
V
1 Bicast off, loopback off on all ports, pre-emphasis off on all ports, equalization set to minimum on all ports.
2 VICM = input common-mode voltage.
3 VID = input differential peak-to-peak voltage swing.
Rev. A | Page 3 of 24
AD8159
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VCC to VEE
3.7 V
VTTI
VTTIO
VTTO
VTTOI
VCC + 0.6 V
VCC + 0.6 V
VCC + 0.6 V
VCC + 0.6 V
4.26 W
Internal Power Dissipation
Differential Input Voltage
Logic Input Voltage
Storage Temperature Range
Lead Temperature
2.0 V
VEE − 0.3 V < VIN < VCC + 0.6 V
−65°C to +125°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 4 of 24
AD8159
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
CC
V
CC
PIN 1
2
V
EQ_A
EQ_B
EQ_C
SEL3
SEL2
SEL1
SEL0
LB_C
LB_B
LB_A
BICAST
3
V
V
V
EE
EE
EE
4
5
6
PE_A0
PE_A1
7
8
PE_B0
9
PE_B1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PE_C0
AD8159
PE_C1
REVERSE_C
TOP VIEW
(Not to Scale)
V
V
CC
CC
ON_A3
OP_A3
IP_B0
IN_B0
V
V
EE
EE
ON_A2
OP_A2
IP_B1
IN_B1
V
V
TTI
TTO
ON_A1
OP_A1
IP_B2
IN_B2
V
V
EE
EE
ON_A0
OP_A0
IP_B3
IN_B3
V
V
CC
CC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC = NO CONNECT
NOTES
1. THE AD8159 TQFP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE OF THE PACKAGE WHICH AIDS
IN HEAT DISSIPATION. THE ePAD MUST BE ELECTRICALLY CONNECTED TO THE V SUPPLY PLANE IN ORDER
EE
TO MEET THERMAL SPECIFICATIONS.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
NC
Type
N/A
Description
1
No connect
2, 13, 25, 26, 38, 50, 51, 63, 75, 76, 88, 100
3 to 5, 16, 22, 29, 35, 41, 47, 54, 60, 79, 85, 91, 97
6
7
8
9
10
11
12
14
15
17
18
19, 44
20
21
23
24
27
VCC
VEE
Power
Power
Control
Control
Control
Control
Control
Control
Control
I/O
I/O
I/O
I/O
Power
I/O
Positive supply
Negative supply
Pre-emphasis control for Port A (LSB)
PE_A0
PE_A1
PE_B0
PE_B1
PE_C0
PE_C1
REVERSE_C
ON_A3
OP_A3
ON_A2
OP_A2
VTTO
ON_A1
OP_A1
ON_A0
OP_A0
IN_A3
Pre-emphasis control for Port A (MSB)
Pre-emphasis control for Port B (LSB)
Pre-emphasis control for Port B (MSB)
Pre-emphasis control for Port C (LSB)
Pre-emphasis control for Port C (MSB)
Reverse inputs and outputs on Port C
High speed output complement
High speed output
High speed output complement
High speed output
Port A and Port B output termination supply
High speed output complement
High speed output
I/O
I/O
I/O
I/O
High speed output complement
High speed output
High speed input complement
Rev. A | Page 5 of 24
AD8159
Pin No.
28
30
31
32, 57
33
34
36
37
39
40
42
43
45
46
48
49
52
53
55
56
58
59
61
62
64
65
66
67
68
69
70
71
72
73
74
77
78
80
81
82
83
84
86
87
89
90
92
93
94
95
96
98
99
Mnemonic
IP_A3
IN_A2
IP_A2
VTTI
Type
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
Description
High speed input
High speed input complement
High speed input
Port A and Port B input termination supply
High speed input complement
High speed input
High speed input complement
High speed input
High speed output complement
High speed output
High speed output complement
High speed output
High speed output complement
High speed output
High speed output complement
High speed output
High speed input complement
High speed input
High speed input complement
High speed input
High speed input complement
High speed input
High speed input complement
High speed input
IN_A1
IP_A1
IN_A0
IP_A0
ON_B3
OP_B3
ON_B2
OP_B2
ON_B1
OP_B1
ON_B0
OP_B0
IN_B3
IP_B3
IN_B2
IP_B2
IN_B1
IP_B1
IN_B0
IP_B0
BICAST
LB_A
Bicast enable
Loopback enable for Port A
Loopback enable for Port B
Loopback enable for Port C
A/B select for Lane 0
LB_B
LB_C
SEL0
SEL1
A/B select for Lane 1
SEL2
A/B select for Lane 2
SEL3
A/B select for Lane 3
EQ_C
EQ_B
EQ_A
Equalization control for Port C
Equalization control for Port B
Equalization control for Port A
High speed input/output complement
High speed input/output
High speed input/output complement
High speed input/output
Port C input/output termination supply
High speed input/output complement
High speed input/output
High speed input/output complement
High speed input/output
High speed output/input complement
High speed output/input
High speed output/input complement
High speed output/input
Port C output/input termination supply
High speed output/input complement
High speed output/input
High speed output/input complement
High speed output/input
ION_C3
IOP_C3
ION_C2
IOP_C2
VTTIO
ION_C1
IOP_C1
ION_C0
IOP_C0
OIN_C3
OIP_C3
OIN_C2
OIP_C2
VTTOI
OIN_C1
OIP_C1
OIN_C0
OIP_C0
Rev. A | Page 6 of 24
AD8159
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = +3.3 V, VEE = 0 V, RL = 50 Ω, basic configuration, data rate = 3.2 Gbps, input common-mode voltage = 2.7 V, differential input
swing = 800 mV p-p, TA = 25°C, unless otherwise noted.
Note: All graphs were generated using the setup shown in Figure 32, unless otherwise specified.
0
–2
–4
–6
–8
–10
–12
–14
–16
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.9
0.9
1.0
1.0
1.0
39.0625ps/DIV
TIME (Unit Interval)
Figure 3. Output Port A Eye Diagram 3.2 Gbps
Input Port A or Input Port C
Figure 6. Output Port A Bathtub Curve 3.2 Gbps
0
–2
–4
–6
–8
–10
–12
–14
–16
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
39.0625ps/DIV
TIME (Unit Interval)
Figure 7. Output Port B Bathtub Curve 3.2 Gbps
Figure 4. Output Port B Eye Diagram
Input Port B or Input Port C
0
–2
–4
–6
–8
–10
–12
–14
–16
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
39.0625ps/DIV
TIME (Unit Interval)
Figure 5. Output Port C Eye Diagram 3.2 Gbps
Input Port A or Input Port B
Figure 8. Output Port C Bathtub Curve 3.2 Gbps
Rev. A | Page 7 of 24
AD8159
39.0625ps/DIV
39.0625ps/DIV
Figure 9. Eye Diagram over Backplane
(18” FR4 + 2 GbX Connectors), PE = 0
Figure 12. Eye Diagram over Backplane
(18” FR4 + 2 GbX Connectors), PE = 1
39.0625ps/DIV
39.0625ps/DIV
Figure 10. Eye Diagram over Backplane
(30” FR4 + 2 GbX Connectors), PE = 0
Figure 13. Eye Diagram over Backplane
(30” FR4 + 2 GbX Connectors), PE = 2
39.0625ps/DIV
39.0625ps/DIV
Figure 11. Eye Diagram over Backplane
(36” FR4 + 2 GbX Connectors), PE = 0
Figure 14. Eye Diagram over Backplane
(36” FR4 + 2 GbX Connectors), PE = 3
Rev. A | Page 8 of 24
AD8159
39.0625ps/DIV
39.0625ps/DIV
Figure 15. Eye Diagram over Backplane
(42” FR4 + 2 GbX Connectors), PE = 0
Figure 18. Eye Diagram over Backplane
(42” FR4 + 2 GbX Connectors), PE = 3
39.0625ps/DIV
39.0625ps/DIV
Figure 16. Reference Eye Diagram for Figure 19
Figure 19. Eye Diagram with Equalization
(10” FR4), EQ = 0
Note: See Figure 34 for Test Circuit Used
39.0625ps/DIV
39.0625ps/DIV
Figure 17. Reference Eye Diagram for Figure 20
Figure 20. Eye Diagram with Equalization
(34” FR4 + 2 GbX Connectors), EQ = 1
Note: See Figure 34 for Test Circuit Used
Rev. A | Page 9 of 24
AD8159
100
90
80
70
60
50
40
30
20
10
0
–3ps
–2ps
–1ps
0s
1ps
2ps
3ps
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
DATA RATE (Gbps)
Figure 21. Deterministic Jitter vs. Data Rate
Figure 24. Random Jitter Histogram
Note: See Figure 35 for Test Circuit Used
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VICM = 2.7V
DIFFERENTIAL INPUT SWING = 800mV p-p
INPUT A/B
INPUT C
INPUT C
INPUT A/B
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
200 400 600 800 1000 1200 1400 1600 1800 2000
DIFFERENTIAL INPUT SWING (mV p-p)
INPUT COMMON-MODE VOLTAGE (V)
Figure 22. Deterministic Jitter vs. Differential Input Swing
Figure 25. Deterministic Jitter vs. Input Common-Mode Voltage
100
100
90
90
80
70
60
50
40
30
20
10
0
80
OUTPUT C
70
60
50
40
30
INPUT C
INPUT A/B
20
OUTPUT A/B
10
0
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
V
(V)
CC
OUTPUT TERMINATION VOLTAGE (V)
Figure 23. Deterministic Jitter vs. Core Supply Voltage
Figure 26. Deterministic Jitter vs. Output Termination Voltage
Rev. A | Page 10 of 24
AD8159
100
90
80
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
–60
–40
–20
0
20
40
60
80
100
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27. Deterministic Jitter vs. Temperature
Figure 28. Transition Time vs. Temperature
Note: See Figure 33 for Test Circuit Used
Rev. A | Page 11 of 24
AD8159
EVALUATION BOARD SIMPLIFIED BLOCK DIAGRAMS
AD8159-EVAL-AC
AC-COUPLED
EVALUATION BOARD
3.3V
V
TTIO
/
V
V
V
/
TTI
CC
TTO
TTOI
V
AD8159
100Ω DIFF.
TRACE
INPUT A
100Ω DIFF.
0.1µF
TRACE
A
B
OUTPUT C
100Ω DIFF.
TRACE
C
0.1µF
INPUT B
INPUT C
AD8159
0.1µF
100Ω DIFF.
TRACE
AC-COUPLED
EVALUATION BOARD
A
B
OUTPUT A
OUTPUT B
C
100Ω DIFF.
TRACE
0.1µF
100Ω DIFF.
TRACE
0.1µF
0.1µF
V
EE
5"
5"
Figure 29. AC-Coupled Evaluation Board Simplified Block Diagram
AD8159-EVAL-DC
DC-COUPLED
EVALUATION BOARD
V
TTIO
/
V
V
V
/
TTI
CC
TTO
TTOI
V
AD8159
100Ω DIFF.
TRACE
INPUT A
100Ω DIFF.
TRACE
A
B
OUTPUT C
100Ω DIFF.
TRACE
C
INPUT B
INPUT C
AD8159
100Ω DIFF.
TRACE
DC-COUPLED
EVALUATION BOARD
A
B
OUTPUT A
OUTPUT B
C
100Ω DIFF.
TRACE
100Ω DIFF.
TRACE
V
EE
5"
5"
–3.3V
Figure 30. DC-Coupled Evaluation Board Simplified Block Diagram
Rev. A | Page 12 of 24
AD8159
TEST CIRCUITS
All graphs were generated using the setup shown in Figure 32, unless otherwise specified.
TERADYNE FR4 TEST BACKPLANE
GBX4 TO SMA DAUGHTER CARDS
0.25"
DIFFERENTIAL STRIPLINE TRACES
8mm WIDE, 8mm SPACE, 8mm HEIGHT
TRACE LENGTHS = 6", 18", 24", 30" + 3" × 2 DAUGHTER CARDS
Figure 31. Test Backplane
HIGH SPEED
REAL-TIME
50Ω CABLE
OSCILLOSCOPE
A
B
DATA OUT
50Ω CABLE
50Ω CABLE
TEST BACKPLANE
C
50Ω
PATTERN
GENERATOR
AD8159
AC-COUPLED
EVALUATION BOARD
A
B
C
50Ω
50Ω
NOTES
1. SINGLE-ENDED REPRESENTATION
Figure 32. AC-Coupled Test Circuit
HIGH SPEED
REAL-TIME
50Ω CABLE
OSCILLOSCOPE
A
B
DATA OUT
50Ω CABLE
50Ω CABLE
TEST BACKPLANE
C
PATTERN
GENERATOR
50Ω
AD8159
DC-COUPLED
EVALUATION BOARD
A
B
C
50Ω
50Ω
NOTES
1. SINGLE-ENDED REPRESENTATION
Figure 33. DC-Coupled Test Circuit
Note: Test Circuit Used for Figure 28
Rev. A | Page 13 of 24
AD8159
DEVICE UNDER TEST
A
B
C
HIGH SPEED
REAL-TIME
OSCILLOSCOPE
50Ω
50Ω CABLE
AD8159
A
B
DATA OUT
50Ω CABLE
50Ω CABLE
DC-COUPLED
EVALUATION BOARD
A
B
TEST BACKPLANE
C
C
50Ω CABLE
50Ω
50Ω
PATTERN
GENERATOR
AD8159
DC-COUPLED
EVALUATION BOARD
A
B
C
50Ω
50Ω
NOTES
1. SINGLE-ENDED REPRESENTATION
Figure 34. Equalization Test Circuit
Note: Test Circuit Used for Figure 19 and Figure 20
HIGH SPEED
SAMPLING
50Ω CABLE
OSCILLOSCOPE
A
B
DATA OUT
50Ω CABLE
C
PATTERN
GENERATOR
50Ω
AD8159
AC-COUPLED
EVALUATION BOARD
A
B
50Ω
50Ω
C
NOTES
1. SINGLE-ENDED REPRESENTATION
Figure 35. Random Jitter Test Circuit
Note: Test Circuit Used for Figure 24
Rev. A | Page 14 of 24
AD8159
THEORY OF OPERATION
The AD8159 relays received data on the demultiplexer Input
Port C to Output Port A and/or Output Port B, depending on
the mode selected by the BICAST control pin. On the
multiplexer side, the AD8159 relays received data on either
Input Port A or Input Port B to Output Port C, based on the
SEL[3:0] pin states.
INPUT EQUALIZATION (EQ) AND OUTPUT
PRE-EMPHASIS (PE)
In backplane applications, the AD8159 needs to compensate
for signal degradation over potentially long traces. The device
supports two levels of input equalization, configured on a per-
port basis. Table 6 to Table 8 summarize the high-frequency
gain (EQ) for each control setting as well as the typical length
of backplane trace that can be compensated for each setting.
The AD8159 is configured by toggling control pins. On the demul-
tiplexer side, when the device is configured in the unicast mode,
it sends the received data on Input Port C to Output Port A or
Output Port B. When the device is configured in the bicast mode,
received data on Input Port C is sent to both Output Port A and
Output Port B.
The AD8159 also has four levels of output pre-emphasis,
configured for each port. The pre-emphasis circuitry adds
a controlled amount of overshoot to the output waveform
to compensate for the loss in a backplane trace.
Table 9 to Table 11 summarize the high-frequency gain, amount
of overshoot, and the typical backplane channel length (including
two connectors) that can be compensated using each setting. A
typical backplane is made of FR4 material with 8 mil wide trace
and 8 mil spacing loosely coupled differential traces. Each
backplane channel consists of two connectors. The total length
of the channel includes three inches of traces on each card.
On the multiplexer side, only received data on Input Port A or
Input Port B is sent to Output Port C, depending on the state of
the SEL[3:0] pins. Table 4 summarizes port selection and
configuration when loopback is disabled (LB_A = LB_B = LB_C
= 0).
When the device is in unicast mode, the output lanes on either
Port A or Port B are in an idle state. In the idle state, the output
tail current is set to 0, and the P and N sides of the lane are
pulled up to the output termination voltage through the on-chip
termination resistors.
Table 4. Port Selection and Configuration Table
SEL
BICAST
OUT_A
IN_C
IN_C
Idle
OUT_B
OUT_C
IN_A
IN_A
IN_B
0
0
1
1
0
1
0
1
Idle
IN_C
IN_C
IN_C
IN_C
IN_B
Table 5. Port C I/O Selection
Port C Pin List on
100-Lead TQFP
Port C when REVERSE_C = 0
Input/Output
Port C when REVERSE_C = 1
Pin Name
Pin Name
Input/Output
Output pin
Output pin
Output pin
Output pin
Output pin
Output pin
Output pin
Output pin
Input pin
77
78
80
81
83
84
86
87
89
90
92
93
95
96
98
99
ION_C3 = INN_C3
IOP_C3 = INP_C3
ION_C2 = INN_C2
IOP_C2 = INP_C2
ION_C1 = INN_C1
IOP_C1 = INP_C1
ION_C0 = INN_C0
IOP_C0 = INP_C0
OIN_C3 = OUTN_C3
OIP_C3 = OUTP_C3
OIN_C2 = OUTN_C2
OIP_C2 = OUTP_C2
OIN_C1 = OUTN_C1
OIP_C1 = OUTP_C1
OIN_C0 = OUTN_C0
OIP_C0 = OUTP_C0
Input pin
Input pin
Input pin
Input pin
Input pin
Input pin
Input pin
Input pin
Output pin
Output pin
Output pin
Output pin
Output pin
Output pin
Output pin
Output pin
ION_C3 = OUTN_C3
IOP_C3 = OUTP_C3
ION_C2 = OUTN_C2
IOP_C2 = OUTP_C2
ION_C1 = OUTN_C1
IOP_C1 = OUTP_C1
ION_C0 = OUTN_C0
IOP_C0 = OUTP_C0
OIN_C3 = INN_C3
OIP_C3 = INP_C3
OIN_C2 = INN_C2
OIP_C2 = INP_C2
OIN_C1 = INN_C1
OIP_C1 = INP_C1
OIN_C0 = INN_C0
OIP_C0 = INP_C0
Input pin
Input pin
Input pin
Input pin
Input pin
Input pin
Input pin
Rev. A | Page 15 of 24
AD8159
Table 6. IN_C Port Input Equalization Settings
Table 10. OUT_A Port Output Pre-Emphasis Settings
EQ_C
EQ
Typical Backplane Length
Typical
Backplane
Overshoot Length
0
1
6 dB
12 dB
0 to 20 inches
20 to 40+ inches
PE_A[1] PE_A[0] PE
0
0
1
1
0
1
0
1
0 dB
0% 0 to 10 inches
1.9 dB 15%
3.5 dB 35%
4.9 dB 60%
10 to 20 inches
20 to 30 inches
30 to 40+ inches
Table 7. IN_A Port Input Equalization Settings
EQ_A
0
1
EQ
Typical Backplane Length
6 dB
12 dB
0 to 20 inches
20 to 40+ inches
Table 11. OUT_B Port Output Pre-Emphasis Settings
Typical
Backplane
Overshoot Length
Table 8. IN_B Port Input Equalization Settings
EQ_B
EQ
Typical Backplane Length
PE_B[1] PE_B[0] PE
0
1
6 dB
12 dB
0 to 20 inches
20 to 40+ inches
0
0
1
1
0
1
0
1
0 dB
0% 0 to 10 inches
1.9 dB 15%
3.5 dB 35%
4.9 dB 60%
10 to 20 inches
20 to 30 inches
30 to 40+ inches
Table 9. OUT_C Port Output Pre-Emphasis Settings
Typical
Backplane
Length
LOOPBACK
PE_C[1] PE_C[0] PE
Overshoot
0
0
1
1
0
1
0
1
0 dB
0%
0 to 10 inches
10 to 20 inches
20 to 30 inches
30 to 40+ inches
The AD8159 also supports port level loopback, illustrated in
Figure 36. The loopback control pins override the lane select
(SEL[3:0]) and bicast control (BICAST) pins. Table 12 summa-
rizes the different loopback configurations.
1.9 dB 15%
3.5 dB 35%
4.9 dB 60%
X4
OUT_A[3:0]
X4
IN_C[3:0]
1:2 DEMUX
X4
OUT_B[3:0]
PORT A LOOPBACK
PORT B LOOPBACK
PORT C LOOPBACK
X4
IN_A[3:0]
X4
2:1 MUX
OUT_C[3:0]
X4
IN_B[3:0]
Figure 36. Port-Based Loopback Capability
Rev. A | Page 16 of 24
AD8159
Table 12. Loopback, Bicast, and Port Select Settings1
LB_A
LB_B
LB_C
SEL
BICAST
OUT_A
IN_C
IN_C
Idle
IN_C
IN_C
IN_C
Idle
IN_C
Idle
IN_C
IN_C
Idle
IN_C
IN_A
IN_A
IN_A
IN_A
IN_A
IN_A
IN_A
IN_A
IN_A
OUT_B
Idle
IN_C
IN_C
IN_C
Idle
IN_C
IN_C
IN_B
IN_B
IN_B
IN_B
IN_B
IN_B
Idle
IN_C
IN_C
Idle
IN_C
IN_C
IN_B
IN_B
IN_B
OUT_C
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
0
X
1
0
1
1
0
1
X
0
0
1
0
X
1
0
1
0
1
0
1
0
X
0
1
X
0
1
0
1
X
0
1
X
X
X
X
IN_A
IN_A
IN_B
IN_B
IN_C
IN_C
IN_C
IN_A
IN_B
IN_B
IN_C
IN_C
IN_C
IN_A
IN_A
IN_B
IN_C
IN_C
IN_C
IN_A
IN_B
IN_C
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
0
1
X
1 Switching is done on a lane-by-lane basis, but input equalization, output pre-emphasis, and loopback are set for each port.
PORT C REVERSE (CROSSOVER) CAPABILITY
X4
Port C has a reversible I/O capability. The sense (input vs.
output) of the Port C pins can be swapped by toggling the
REVERSE_C control pin. This feature has been added to
facilitate the connection to different ASICs that may have
the opposite pinouts.
OUT_A[3:0]
OUT_B[3:0]
X4
I/O
SWITCH
1:2 DEMUX
IN_C [3:0]/OUT_C[3:0]
X4
REVERSE_C
X4
X4
X4
Figure 37 illustrates the reversible I/O function of Port C, and
Table 5 describes this function in a selection table that
corresponds to a TQFP-100 package. Please note that the
reverse capability is supported only on Port C.
X4
X4
IN_A[3:0]
IN_B[3:0]
I/O
SWITCH
2:1 MUX
OUT_C [3:0]/IN_C[3:0]
Figure 37. Port C Reverse I/O Capability
Rev. A | Page 17 of 24
AD8159
APPLICATIONS
The main application of the AD8159 is to support redundancy
on both the backplane side and the line interface side of a serial
link. Each port consists of four lanes to support standards such
as XAUI. Figure 38 illustrates redundancy in an XAUI backplane
system. Each line card is connected to two switch fabrics
(primary and redundant). The device can be configured to
support either 1 + 1 or 1:1 redundancy.
Another application for the AD8159 is test equipment for
evaluating high speed serial I/Os running at data rates at or
lower than 3.2 Gbps. Figure 40 illustrates a possible application
of the AD8159 in a simple XAUI link tester.
FABRIC INTERFACE
TRAFFIC MANAGERS
NETWORK PROCESSOR
PRIMARY
SWITCH
FABRIC
PHYSICAL
INTERFACE
MACs
FRAMERS
AD8159
LINE CARDS
REDUNDANT
SWITCH
FABRIC
FABRIC INTERFACE
TRAFFIC MANAGERS
NETWORK PROCESSOR
PHYSICAL
INTERFACE
MACs
FRAMERS
AD8159
BACKPLANE
FABRIC CARDS
Figure 38. Using the AD8159 for Switch Redundancy
PRIMARY
MODULE
FABRIC INTERFACE
TRAFFIC MANAGERS
NETWORK PROCESSOR
MACs
FRAMERS
REDUNDANT
MODULE
LINE CARD
Figure 39. Using the AD8159 for Line Interface Redundancy
CONNECT TO DEVICE UNDER TEST
CONNECTOR
PORT B
CONNECT TO PROTOCOL
ANALYZER
PORT A
PORT C
FPGA
TEST CARD
GENERATES SIMPLE
PATTERNS
Figure 40. Using the AD8159 in Test Equipment
Rev. A | Page 18 of 24
AD8159
INTERFACING TO THE AD8159
For output ports, there are two 50 Ω resistors connected to the
termination supply. Note that the differential input resistance
for both structures is the same, 100 Ω.
TERMINATION STRUCTURES
To determine the best strategy for connecting to the high speed
pins of the AD8159, the user must first be familiar with the on-
chip termination structures. The AD8159 contains two types of
these structures (see Figure 41 and Figure 42): one type for input
and bidirectional ports and one type for output ports.
INPUT COMPLIANCE
The range of allowable input voltages is determined by the
fundamental limitations of the active input circuitry. This range
of signals is normally a function of the common-mode level of
the input signal, the signal swing, and the supply voltage. For a
given input signal swing, there is a range of common-mode
voltages that keeps the high and low voltage excursions within
acceptable limits. Similarly, for a given common-mode input
voltage there is a maximum acceptable input signal swing.
There is also a minimum signal swing that the active input
circuitry can resolve reliably.
V
/V
/V
TTI TTIO TTOI
54.5Ω
54.5Ω
P
N
1173Ω
Figure 41. Termination Structure: Input and Bidirectional Ports
V
TTO
Figure 22 and Figure 25 summarize the input voltage ranges for
all ports. Note that the input range is different when comparing
bidirectional ports to strictly input ports. This is a consequence
of the additional circuitry required to support the bidirectional
feature on Port C.
50Ω
50Ω
P
N
Figure 42. Output Ports
For input and bidirectional ports, the termination structure
consists of two 54.5 Ω resistors connected to a termination
supply and an 1173 Ω resistor connected across the differential
inputs, the latter being a result of the finite differential input
impedance of the equalizer.
AC Coupling
One way to simplify the input circuit and make it compatible
with a wide variety of driving devices is to use ac coupling. This
has the effect of isolating the dc common-mode levels of the
driver and the AD8159 input circuitry. AC coupling requires a
capacitor in series with each single-ended input signal, as shown
in Figure 43. This should be done in a manner that does not
interfere with the high speed signal integrity of the PCB.
V
V
/V
V
CC
CC
TTI TTIO
50Ω
50Ω
54.5Ω
54.5Ω
C
P
IP
IN
C
N
1173Ω
VEE
AD8159
DRIVER
Figure 43. AC-Coupling Input Signal of AD8159
Rev. A | Page 19 of 24
AD8159
DC Coupling
When ac coupling is used, the common-mode level at the input
of the device is equal to VTTI. The single-ended input signal
swings above and below VTTI equally. The user can then use
Figure 22 and Figure 25 to determine the acceptable range of
common-mode levels and signal swing levels that satisfy the
input range of the AD8159.
First, consider the dc-coupled case (see Figure 44). A lane on
Output Port A or Output Port B on the AD8159 is dc-coupled
to a receiving device. In this example, the output termination
voltage (VTTO) on the AD8159 is set to the same level as the
input termination voltage (VTTIR) on the receiving device, and
this level sets the high value (VHI) of the single-ended output
voltage. With pre-emphasis low (PE = 0), the maximum single-
ended current is 16 mA1, which flows through the parallel
combination of the 50 ꢀ on-chip resistor and the 50 Ω far end
termination. Therefore, the low value (VLO) of the output
voltage is equal to
If dc coupling is required, determining the input common-
mode level is less straightforward because the configuration of
the driver must be also be considered. In most cases, the user
would set VTTI on the AD8159 to the same level as the driver
output termination voltage, VTTOD. This prevents a continuous
dc current from flowing between the two supply nets. As a
practical matter, both devices can be terminated to the same
physical supply net.
V
TTO − 16 mA × (50 Ω || 50 Ω) = VTTO − 400 mV
Because the minimum allowed voltage at the output is
Consider the following example: A driver is dc-coupled to the
input of the AD8159. The AD8159 input termination voltage
(VTTI) and the driver output termination voltage (VTTOD) are both
set to the same level; that is, VTTI = VTTOD = 3.3 V. If an 800 mV
differential p-p swing is desired, the total output current of the
driver is 16 mA. At balance, the output current is divided evenly
between the two sides of the differential signal path, 8 mA to each
side. This 8 mA of current flows through the parallel combina-
tion of the 54.5 Ω input termination resistor on the AD8159
and the 50 Ω output termination resistor on the driver, resulting
in a common-mode level of
V
CC − 1.6 V, the lowest acceptable value for VTTO is
V
CC − 1.6 V + 0.4 V = VCC − 1.2 V
Increasing pre-emphasis to its highest level (PE = 3) results in
a maximum, single-ended current of 28 mA.2 In this case
V
LO = VTTO − 28 mA × (50 Ω || 50 Ω) = VTTO − 700 mV
As a result, the lowest acceptable value for VTTO is
CC − 1.6 V + 0.7 V = VCC − 0.9 V
V
It is expected that the minimum VTTO is 300 mV higher than the
case when PE = 0, because increasing the pre-emphasis level
results in a 300 mV lower voltage excursion at the output.
V
TTI − 8 mA × (50 Ω || 54.5 Ω) = VTTI − 209 mV
The user can then use Figure 25 to determine the allowable
range of values for VTTI that meets the input compliance range
based on an 800 mV p-p differential swing.
1 The output current for Port C when PE_C = 0 is slightly higher, 20 mA. The
extra 4 mA of current (compared to Port A/Port B) is needed to support the
bidirectional feature.
OUTPUT COMPLIANCE
2 The output current for Port C when PE_C = 3 is 32 mA, for the same reason
as stated in Endnote 1.
Not surprisingly, there is also a range of voltages that satisfies
the requirements of the output devices. This range is specified
as the minimum and maximum voltage (with respect to VCC
)
allowed at an output pin.
V
V
TTO
TTIR
AD8159
50Ω
50Ω
OP
ON
RECEIVING DEVICE
PORT A/B: (16 + 4 × PE) mA
PORT C: (20 + 4 × PE) mA
V
EE
Figure 44. DC-Coupling Output Signal from AD8159
Rev. A | Page 20 of 24
AD8159
AC Coupling
The lowest acceptable value for VTTO is
CC − 1.6 V + 0.6 V = VCC − 1.0 V
In general, more VTTO supply headroom is required with ac-
coupled outputs. When the outputs are ac-coupled, the average
single-ended current does not see the far end 50 Ω termination
because the capacitor acts as a dc block. For example, with
PE = 0, the single-ended output current alternates from 0 mA
to 16 mA, or 8 mA on average. This 8 mA current flows entirely
through the on-chip 50 Ω termination resistor due to the dc
block.
V
The same exercise can be repeated for other pre-emphasis
settings.
Output Compliance Table
To simplify the task of interfacing to the AD8159 output,
Table 13 is useful as a quick-reference. It provides the minimum
and maximum values for output termination voltage for both
ac and dc coupling. The values in the table are valid for any pre-
emphasis setting.
The single-ended output voltage has an average value of
V
TTO − 8 mA × 50 Ω = VTTO − 400 mV
Table 13. Output Compliance
For appropriate data patterns,1 the capacitor acts as a short and
the voltage swing is 400 mV p-p, identical to the dc-coupled case.
The low output voltage is, therefore,
AC-Coupled
DC-Coupled
Minimum Maximum
Minimum Maximum
(V)
(V)
(V)
(V)
VTTO VCC – 0.5
VTTOI VCC – 0.4
VCC + 0.6
VCC + 0.6
VCC – 0.9
VCC – 0.8
VCC + 0.6
VCC + 0.6
V
TTO − 400 mV − 200 mV = VTTO − 600 mV
1AC coupling requires that the signal pattern have no long term dc
component. Codes such as 8b/10b, for example, ensure that the data
pattern is benign in an ac-coupled link.
Rev. A | Page 21 of 24
AD8159
OUTLINE DIMENSIONS
16.00 BSC SQ
1.20
MAX
0.75
0.60
0.45
14.00 BSC SQ
100
1
76
75
76
75
100
1
PIN 1
EXPOSED
PAD
5.00 SQ
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
BOTTOM VIEW
(PINS UP)
51
51
25
25
26
50
50
26
3.5°
0°
0.08 MAX
COPLANARITY
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
VIEW A
0.15
0.05
SEATING
PLANE
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
NOTES
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE AD8159 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO V . IT IS RECOMMENDED THAT NO PCB SIGNAL
EE
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A V PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
EE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 45. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
AD8159ASVZ1
100-Lead TQFP_EP
DC-Coupled Evaluation Board
AC-Coupled Evaluation Board
SV-100-4
AD8159-EVAL-DC
AD8159-EVAL-AC
1 Z = Pb-free part.
Rev. A | Page 22 of 24
AD8159
NOTES
Rev. A | Page 23 of 24
AD8159
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05611-0-4/06(A)
Rev. A | Page 24 of 24
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