AD8231-EVALZ [ADI]
Zero Drift, Digitally Programmable Instrumentation Amplifier; 零漂移，数字可编程仪表放大器
| 型号： | AD8231-EVALZ |
| 厂家： | 
ADI |
| 描述： | Zero Drift, Digitally Programmable Instrumentation Amplifier |
| 文件： | 总24页 (文件大小：675K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Zero Drift, Digitally Programmable
Instrumentation Amplifier
AD8231
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Digitally/pin-programmable gain
G = 1, 2, 4, 8, 16, 32, 64, or 128
Specified from −40°C to +125°C
50 nV/°C maximum input offset drift
10 ppm/°C maximum gain drift
Excellent dc performance
80 dB minimum CMR, G = 1
15 μV maximum input offset voltage
500 pA maximum bias current
0.7 μV p-p noise (0.1 Hz to 10 Hz)
Good ac performance
1
2
3
4
12
11
10
9
NC
–INA
+INA
NC
+V
–V
S
LOGIC
S
IN-AMP
OUTA
REF
OP
AMP
AD8231
2.7 MHz bandwidth, G = 1
1.1 V/ꢀs slew rate
Rail-to-rail output
Shutdown/multiplex
Figure 1.
Extra op amp
Single-supply range: 3 V to 6 V
Dual-supply range: 1.5 V to 3 V
Table 1. Instrumentation and Difference Amplifiers by
Category
High
Low
Cost
High
Voltage
Mil
Grade
Low
Power
Digital
Gain
Performance
AD8221
AD82201
AD8222
AD82241
AD6231
AD85531
AD628
AD629
AD620
AD621
AD524
AD526
AD624
AD6271
AD82311
AD8250
AD8251
AD85551
AD85561
AD85571
APPLICATIONS
Pressure and strain transducers
Thermocouples and RTDs
Programmable instrumentation
Industrial controls
Weigh scales
1 Rail-to-rail output.
GENERAL DESCRIPTION
The AD8231 also includes an uncommitted op amp that can be
used for additional gain, differential signal driving, or filtering.
Like the in-amp, the op amp has an auto-zero architecture, rail-
to-rail input, and rail-to-rail output.
The AD8231 is a low drift, rail-to-rail, instrumentation amplifier
with software-programmable gains of 1, 2, 4, 8, 16, 32, 64, or 128.
The gains are programmed via digital logic or pin strapping.
The AD8231 is ideal for applications that require precision
performance over a wide temperature range, such as industrial
temperature sensing and data logging. Because the gain setting
resistors are internal, maximum gain drift is only 10 ppm/°C for
gains of 1 to 32. Because of the auto-zero input stage, maximum
input offset is 15 μV and maximum input offset drift is just
50 nV/°C. CMRR is 80 dB for G = 1, increasing to 110 dB at
higher gains.
The AD8231 includes a shutdown feature that reduces current
to a maximum of 1 μA. In shutdown, both amplifiers also have
a high output impedance, which allows easy multiplexing of
multiple amplifiers without additional switches.
The AD8231 is specified over the extended industrial tempera-
ture range of −40°C to +125°C. It is available in a 4 mm × 4 mm
16-lead LFCSP.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD8231
TABLE OF CONTENTS
Features .............................................................................................. 1
Amplifier Architecture .............................................................. 18
Gain Selection............................................................................. 18
Reference Terminal .................................................................... 18
Layout .......................................................................................... 19
Input Bias Current Return Path ............................................... 19
Input Protection ......................................................................... 19
RF Interference ........................................................................... 20
Common-Mode Input Voltage Range..................................... 20
Reducing Noise........................................................................... 20
Applications Information.............................................................. 21
Differential Output .................................................................... 21
Multiplexing................................................................................ 21
Using the AD8231 with Bipolar Supplies................................ 21
Sallen Key Filter.......................................................................... 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Instrumentation Amplifier Performance Curves..................... 9
Operational Amplifier Performance Curves .......................... 15
Performance Curves Valid for Both Amplifiers ..................... 17
Theory of Operation ...................................................................... 18
REVISION HISTORY
9/07—Rev. 0to Rev. A
5/07—Revision 0: Initial Version
Changes to Features and General Description ............................. 1
Changes to Table 2............................................................................ 3
Changes to Table 3............................................................................ 5
Changes to Typical Performance Characteristics Layout............ 9
Inserted Figure 3 to Figure 8; Renumbered Sequentially............ 9
Inserted Figure 9; Renumbered Sequentially.............................. 10
Inserted Figure 16, and Figure 18 to Figure 20; Renumbered
Sequentially ..................................................................................... 11
Inserted Figure 24; Renumbered Sequentially............................ 12
Deleted Figure 28 and Figure 29; Renumbered Sequentially ... 13
Inserted Figure 33 and Figure 34; Renumbered Sequentially... 14
Inserted Figure 41 to Figure 46; Renumbered Sequentially...... 16
Inserted Figure 48; Renumbered Sequentially............................ 17
Changes to Gain Selection Section and Figure 50 ..................... 18
Added Input Protection Section................................................... 19
Added Reducing Noise Section .................................................... 20
Changes to Multiplexing Section.................................................. 21
Added Using the AD8231 with Bipolar Supplies Section ......... 21
Added Sallen Key Filter Section ................................................... 22
Changes to Ordering Guide .......................................................... 23
Rev. A | Page 2 of 24
AD8231
SPECIFICATIONS
VS = 5 V, VREF = 2.5 V, G = 1, RL = 10 kΩ, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
INSTRUMENTATION AMPLIFIER
Offset Voltage
VOS RTI = VOSI + VOSO/G
TA = −40°C to +125°C
TA = −40°C to +125°C
Input Offset, VOSI
4
15
μV
Average Temperature Drift
Output Offset, VOSO
Average Temperature Drift
Input Currents
0.01
15
0.05
30
μV/°C
μV
0.05
0.5
μV/°C
Input Bias Current
250
20
500
5
100
0.5
pA
nA
pA
nA
TA = −40°C to +125°C
Input Offset Current
TA = −40°C to +125°C
Gains
1, 2, 4, 8, 16, 32, 64, or 128
Gain Error
G = 1
G = 2 to 128
Gain Drift
G = 1 to 32
G = 64
0.05
0.8
%
%
TA = −40°C to +125°C
3
4
10
3
5
10
20
30
ppm/°C
ppm/°C
ppm/°C
ppm
G = 128
Linearity
0.2 V to 4.8 V, 10 kΩ load
0.2 V to 4.8 V, 2 kΩ load
ppm
CMRR
G = 1
G = 2
G = 4
G = 8
G = 16
G = 32
G = 64
G = 128
Noise
Input Voltage Noise, eni
80
86
92
98
104
110
110
110
dB
dB
dB
dB
dB
dB
dB
dB
en = √(eni2 + (eno/G)2), VIN+, VIN− = 2.5 V
f = 1 kHz
f = 1 kHz, TA = −40°C
f = 1 kHz, TA = 125°C
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz, TA = −40°C
f = 1 kHz, TA = 125°C
f = 0.1 Hz to 10 Hz
f = 10 Hz
32
27
39
0.7
58
50
70
1.1
20
nV/√Hz
nV/√Hz
nV/√Hz
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
μV p-p
fA/√Hz
Output Voltage Noise, eno
Current Noise
Other Input Characteristics
Common-Mode Input Impedance
Power Supply Rejection Ratio
Input Operating Voltage Range
Reference Input
10||5
115
GΩ||pF
dB
V
100
0.05
4.95
+5.2
Input Impedance
Voltage Range
28
kΩ
V
−0.2
Rev. A | Page 3 of 24
AD8231
Parameter
Conditions
Min
Typ
Max
Unit
Dynamic Performance
Bandwidth
G = 1
G = 2
2.7
2.5
MHz
MHz
Gain Bandwidth Product
G = 4 to 128
Slew Rate
7
1.1
MHz
V/μs
Output Characteristics
Output Voltage High
RL = 100 kΩ to ground
RL = 10 kΩ to ground
RL = 100 kΩ to 5 V
RL = 10 kΩ to 5 V
4.9
4.8
4.94
4.88
60
80
70
V
V
mV
mV
mA
Output Voltage Low
100
200
Short-Circuit Current
Digital Interface
Input Voltage Low
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
1.0
V
V
ns
ns
Input Voltage High
Setup Time to CS High
Hold Time after CS High
4.0
50
20
OPERATIONAL AMPLIFIER
Input Characteristics
Offset Voltage, VOS
5
15
μV
Temperature Drift
Input Bias Current
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
0.01
250
0.06
500
5
100
0.5
4.95
μV/°C
pA
nA
pA
nA
Input Offset Current
20
Input Voltage Range
Open-Loop Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Voltage Noise Density
Voltage Noise
0.05
100
100
100
V
120
120
110
20
V/mV
dB
dB
nV/√Hz
μV p-p
f = 0.1 Hz to 10 Hz
0.4
Dynamic Performance
Gain Bandwidth Product
Slew Rate
1
0.5
MHz
V/μs
Output Characteristics
Output Voltage High
RL = 100 kΩ to ground
RL = 10 kΩ to ground
RL = 100 kΩ to 5 V
RL = 10 kΩ to 5 V
4.9
4.8
4.96
4.92
60
80
70
V
V
mV
mV
mA
Output Voltage Low
100
200
Short-Circuit Current
BOTH AMPLIFIERS
Power Supply
Quiescent Current
Quiescent Current (Shutdown)
4
0.01
5
1
mA
μA
Rev. A | Page 4 of 24
AD8231
VS = 3.0 V, VREF = 1.5 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
INSTRUMENTATION AMPLIFIER
Offset Voltage
VOS RTI = VOSI + VOSO/G
Input Offset, VOSI
4
15
μV
Average Temperature Drift
Output Offset, VOSO
Average Temperature Drift
Input Currents
0.01
15
0.05
0.05
30
0.5
μV/°C
μV
μV/°C
Input Bias Current
250
20
500
5
100
0.5
pA
nA
pA
nA
TA = −40°C to +125°C
Input Offset Current
TA = −40°C to +125°C
Gains
1, 2, 4, 8, 16, 32, 64, or 128
Gain Error
G = 1
0.05
0.8
%
%
G = 2 to 128
Gain Drift
G = 1 to 32
G = 64
G = 128
CMRR
TA = −40°C to +125°C
3
4
10
10
20
30
ppm/°C
ppm/°C
ppm/°C
G = 1
G = 2
G = 4
G = 8
G = 16
G = 32
G = 64
G = 128
Noise
80
86
92
98
104
110
110
110
dB
dB
dB
dB
dB
dB
dB
dB
en = √(eni2 + (eno/G)2)
VIN+, VIN− = 2.5 V, TA = 25°C
Input Voltage Noise, eni
f = 1 kHz
40
35
48
0.8
72
62
83
1.4
20
nV/√Hz
nV/√Hz
nV/√Hz
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
μV p-p
fA/√Hz
f = 1 kHz, TA = −40°C
f = 1 kHz, TA = 125°C
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz, TA = −40°C
f = 1 kHz, TA = 125°C
f = 0.1 Hz to 10 Hz
f = 10 Hz
Output Voltage Noise, eno
Current Noise
Other Input Characteristics
Common-Mode Input Impedance
Power Supply Rejection Ratio
Input Operating Voltage Range
Reference Input
10||5
115
GΩ||pF
dB
V
100
0.05
2.95
+3.2
Input Impedance
Voltage Range
28
kΩ||pF
V
−0.2
Rev. A | Page 5 of 24
AD8231
Parameter
Conditions
Min
Typ
Max
Unit
Dynamic Performance
Bandwidth
G = 1
G = 2
2.7
2.5
MHz
MHz
Gain Bandwidth Product
G = 4 to 128
Slew Rate
7
1.1
MHz
V/μs
Output Characteristics
Output Voltage High
RL = 100 kΩ to ground
RL = 10 kΩ to ground
RL = 100 kΩ to 3 V
RL = 10 kΩ to 3 V
2.9
2.8
2.94
2.88
60
80
40
V
V
mV
mV
mA
Output Voltage Low
100
200
Short-Circuit Current
Digital Interface
Input Voltage Low
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
0.7
V
V
ns
ns
Input Voltage High
Setup Time to CS High
Hold Time after CS High
2.3
60
20
OPERATIONAL AMPLIFIERS
Input Characteristics
Offset Voltage, VOS
5
15
μV
Temperature Drift
Input Bias Current
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
0.01
250
0.06
500
5
100
0.5
2.95
μV/°C
pA
nA
pA
nA
Input Offset Current
20
Input Voltage Range
Open-Loop Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Voltage Noise Density
Voltage Noise
0.05
100
100
100
V
120
120
110
27
V/mV
dB
dB
nV/√Hz
μV p-p
f = 0.1 Hz to 10 Hz
0.6
Dynamic Performance
Gain Bandwidth Product
Slew Rate
1
0.5
MHz
V/μs
Output Characteristics
Output Voltage High
RL = 100 kΩ to ground
RL = 10 kΩ to ground
RL = 100 kΩ to 3 V
RL = 10 kΩ to 3 V
2.9
2.8
2.96
2.82
60
80
40
V
V
mV
mV
mA
Output Voltage Low
100
200
Short-Circuit Current
BOTH AMPLIFIERS
Power Supply
Quiescent Current
Quiescent Current (Shutdown)
3.5
0.01
4.5
1
mA
μA
Rev. A | Page 6 of 24
AD8231
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
Rating
Table 5.
Thermal Pad
Soldered to Board
Not Soldered to Board
Supply Voltage
6 V
Indefinite1
−VS − 0.3 V to +VS + 0.3 V
−VS − 0.3 V to +VS + 0.3 V
–65°C to +150°C
–40°C to +125°C
θJA
54
96
Unit
°C/W
°C/W
Output Short-Circuit Current
Input Voltage (Common-Mode)
Differential Input Voltage
Storage Temperature Range
Operational Temperature Range
The θJA values in Table 5 assume a 4-layer JEDEC standard
board. If the thermal pad is soldered to the board, it is
also assumed it is connected to a plane. θJC at the exposed pad
is 6.3°C/W.
Package Glass Transition Temperature 130°C
ESD (Human Body Model)
ESD (Charged Device Model)
ESD (Machine Model)
1 For junction temperatures between 105°C and 130°C, short-circuit operation
beyond 1000 hours can impact part reliability.
1.5 kV
1.5 kV
0.2 kV
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the AD8231 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 130°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric perform-
ance of the amplifiers. Exceeding a temperature of 130°C for an
extended period can result in a loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 7 of 24
AD8231
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
12 +V
11 –V
NC
(IN-AMP –IN) –INA
(IN-AMP +IN) +INA
NC
1
2
3
4
S
S
AD8231
TOP VIEW
(Not to Scale)
10 OUTA (IN-AMP OUT)
REF
9
NC = NO CONNECT
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin Number
Mnemonic
Description
1
2
3
4
5
6
7
8
9
NC
No Connect.
−INA (IN-AMP −IN)
+INA (IN-AMP +IN)
NC
SDN
Instrumentation Amplifier Negative Input.
Instrumentation Amplifier Positive Input.
No Connect.
Shutdown.
+INB
−INB
Operational Amplifier Positive Input.
Operational Amplifier Negative Input.
Operational Amplifier Output.
Instrumentation Amplifier Reference Pin. It should be driven with a low impedance. Output is
referred to this pin.
OUTB (OP AMP OUT)
REF
10
11
12
13
14
15
16
OUTA (IN-AMP OUT)
Instrumentation Amplifier Output.
Negative Power Supply. Connect to ground in single-supply applications.
Positive Power Supply.
Chip Select. Enables digital logic interface.
Gain Setting Bit (LSB).
−VS
+VS
CS
A0
A1
A2
Gain Setting Bit.
Gain Setting Bit (MSB).
Rev. A | Page 8 of 24
AD8231
TYPICAL PERFORMANCE CHARACTERISTICS
INSTRUMENTATION AMPLIFIER PERFORMANCE CURVES
1000
1400
1200
1000
800
600
400
200
0
N: 5956
MEAN: 0.977167
SD: 11.8177
N: 5956
MEAN: –48.0779
SD: 21.0433
800
600
400
200
0
–100 –80 –60 –40 –20
0
20
40
60
80
100
–500 –400 –300 –200 –100
0
100 200 300 400 500
CMRR (µV/V)
GAIN ERROR (µV/V)
Figure 3. Instrumentation Amplifier CMR Distribution, G = 1
Figure 6. Instrumentation Amplifier Gain Distribution, G = 1
800
9
N: 5956
N: 40
MEAN: 2.06788
SD: 1.07546
MEAN: –8.31
SD: 6
8
700
600
500
400
300
200
100
0
7
6
5
4
3
2
1
0
–15
–10
–5
0
5
10
15
–50 –40 –30 –20 –10
0
10
20
30
40
50
V
(µV)
INPUT OFFSET DRIFT (nV/°C)
OSI
Figure 7. Instrumentation Amplifier Input Offset Voltage Drift,
−40°C to +125°C
Figure 4. Instrumentation Amplifier Input Offset Voltage Distribution
16
800
N: 40
MEAN: –0.003
SD: 0.061
N: 5956
MEAN: 10.3901
SD: 3.9553
14
700
12
10
8
600
500
400
300
200
100
0
6
4
2
0
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
–30
–20
–10
0
10
20
30
OUTPUT OFFSET DRIFT (µV/°C)
V
(µV)
OSO
Figure 8. Instrumentation Amplifier Output Offset Drift, −40°C to +125°C
Figure 5. Instrumentation Amplifier Output Offset Voltage Distribution
Rev. A | Page 9 of 24
AD8231
2000
V
6
5
4
3
2
1
0
= MIDSUPPLY
= MIDSUPPLY
REF
CM
0V, 4.96V
V
1500
1000
500
0
5V SINGLE SUPPLY
4.92V, 2.5V
0V, 2.96V
3V SINGLE SUPPLY
3V
5V
2.92V, 1.5V
4
0V, 0.04V
–500
–40
–20
0
20
40
60
80
100
120
0
1
2
3
5
6
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
Figure 9. Instrumentation Amplifier Bias Current vs. Temperature
Figure 12. Instrumentation Amplifier Input Common-Mode Range vs.
Output Voltage, VREF = 0 V
2.0
1.5
1.0
0.5
0
6
1.5V, 4.96V
5
0.02V, 4.22V
4
5V SINGLE SUPPLY
1.5V, 2.96V
4.98V, 3.22V
4.98V, 1.78V
3
2
1
0
–0.5
–1.0
0.02V, 2.22V
0.02V, 0.78V
2.98V, 2.22V
3V SINGLE SUPPLY
2.98V, 0.78V
1.5V, 0.04V
+V = +2.5V
S
–1.5
–2.0
–V = –2.5V
S
V
= 0V
REF
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
(V)
OUTPUT VOLTAGE (V)
CM
Figure 13. Instrumentation Amplifier Input Common-Mode Range vs.
Output Voltage, VREF = 1.5 V
Figure 10. Instrumentation Amplifier Bias Current vs.
Common-Mode Voltage, 5 V
6
1.0
0.8
2.5V, 4.96V
5
0.6
5V SINGLE SUPPLY
4
0.4
4.98V, 3.72V
0.2
0.02V, 3.72V
3
2
1
0
0
2.98V, 2.72V
2.5V, 2.96V
–0.2
–0.4
–0.6
–0.8
–1.0
0.02V, 1.72V
0.02V, 1.28V
3V SINGLE
SUPPLY
4.98V,1.28V
+V = +1.5V
S
–V = –1.5V
2.5V, 0.04V
S
V
= 0V
REF
2.98V, 0.28V
3.0 3.5 4.0
OUTPUT VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
4.5
5.0
–1.5 –1.2 –0.9 –0.6 –0.3
0
0.3
0.6
0.9
1.2
1.5
V
(V)
CM
Figure 14. Instrumentation Amplifier Input Common-Mode Range vs.
Output Voltage, VREF = 2.5 V
Figure 11. Instrumentation Amplifier Bias Current vs.
Common-Mode Voltage, 3 V
Rev. A | Page 10 of 24
AD8231
50
40
20
15
G = 128
G = 1
G = 1
G = 8
G = 8
G = 128
G = 128
G = 64
G = 32
G = 16
G = 8
G = 4
G = 2
G = 1
30
10
20
5
10
0
0
–5
–10
–20
–30
–40
–10
–15
–20
REPRESENTATIVE SAMPLES
100
1k
10k
100k
1M
10M
–40
–20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 15. Instrumentation Amplifier Gain vs. Frequency
Figure 18. Instrumentation Amplifier CMRR vs. Temperature
1000
800
140
G = 1
G = 1
G = 8
G = 2
G = 4
G = 8
G = 16
G = 32
G = 64
G = 128
120
100
80
60
40
20
0
600
400
G = 128
200
0
–200
–400
–600
–800
–1000
–40
–20
0
20
40
60
80
100
120
1
10
100
1k
10k
100k
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 16. Instrumentation Amplifier Gain Drift vs. Temperature
Figure 19. Instrumentation Amplifier Positive PSRR vs. Frequency
140
140
G = 128
G = 1
G = 8
120
120
100
G = 8
100
80
G = 128
G = 1
60
40
20
0
80
60
40
10
100
1k
10k
100k
1
10
100
1k
100k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Instrumentation Amplifier CMRR vs. Frequency
Figure 20. Instrumentation Amplifier Negative PSRR vs. Frequency
Rev. A | Page 11 of 24
AD8231
100
10
G = +128, 0.4µV/DIV
G = +1, 1µV/DIV
1
0.1
0.01
1
10
100
1k
10k
100k
1s/DIV
FREQUENCY (Hz)
Figure 21. Instrumentation Amplifier 0.1 Hz to 10 Hz Noise
Figure 24. Instrumentation Amplifier Current Noise Spectral Density
100
G = +1
G = +8
G = +128
90
80
70
60
50
40
30
20
10
0
1
10
100
FREQUENCY (Hz)
1k
20mV/DIV
5µs/DIV
Figure 25. Instrumentation Amplifier Small Signal Pulse Response, G = 1,
RL = 2 kΩ, CL = 500 pF
Figure 22. Instrumentation Amplifier Voltage Noise Spectral Density vs.
Frequency, 5 V, 1 Hz to 1000 Hz
1000
G = +1
G = +8
G = +128
900
500pF
800pF
800
700
600
500
400
300
200
100
0
300pF
NO
LOAD
1
10
100
1k
10k
100k
20mV/DIV
4µs/DIV
FREQUENCY (Hz)
Figure 26. Instrumentation Amplifier Small Signal Pulse Response for Various
Capacitive Loads, G = 1
Figure 23. Instrumentation Amplifier Voltage Noise Spectral Density vs.
Frequency, 5 V, 1 Hz to 1 MHz
Rev. A | Page 12 of 24
AD8231
G = +8
G = +32
G = +128
2V/DIV
17.6µs TO 0.01%
21.4µs TO 0.001%
0.001%/DIV
100µs/DIV
20mV/DIV
10µs/DIV
Figure 27. Instrumentation Amplifier Small Signal Pulse Response, G = 4, 16,
and 128, RL = 2 kΩ, CL = 500 pF
Figure 30. Instrumentation Amplifier Large Signal Pulse Response,
G = 128, VS = 5 V
25
20
0.001%
15
0.01%
2V/DIV
10
5
3.95µs TO 0.01%
4µs TO 0.001%
0
1
10
100
1k
0.001%/DIV
10µs/DIV
GAIN (V/V)
Figure 28. Instrumentation Amplifier Large Signal Pulse Response,
G = 1, VS = 5 V
Figure 31. Instrumentation Amplifier Settling Time vs.
Gain for a 4 V p-p Step, VS = 5 V
25
20
15
10
5
0.001%
0.01%
2V/DIV
3.75µs TO 0.01%
3.8µs TO 0.001%
0
1
10
100
1k
0.001%/DIV
10µs/DIV
GAIN (V/V)
Figure 29. Instrumentation Amplifier Large Signal Pulse Response,
G = 8, VS = 5 V
Figure 32. Instrumentation Amplifier Settling Time vs.
Gain for a 2 V p-p Step, VS = 3 V
Rev. A | Page 13 of 24
AD8231
+V
+V
S
S
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
–0.2
–0.4
–0.6
–0.8
–0.2
–0.4
–0.6
–0.8
–1.0
1.0
–1.0
1.0
0.8
0.6
0.4
0.2
0.8
0.6
0.4
0.2
–V
–V
S
0.1
S
0.1
1
10
100
1
10
100
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 33. Instrumentation Amplifier Output Voltage Swing vs.
Output Current, VS = 3 V
Figure 34. Instrumentation Amplifier Output Voltage Swing vs.
Output Current, VS = 5 V
Rev. A | Page 14 of 24
AD8231
OPERATIONAL AMPLIFIER PERFORMANCE CURVES
100
80
60
40
20
0
–90
–100
–110
–120
–130
–140
–150
NO
LOAD
76° PHASE
MARGIN
300pF
800pF
1nF
R
C
= 10kΩ
= 200pF
L
L
–20
1.5nF
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
20mV/DIV
5µs/DIV
Figure 35. Operational Amplifier Open-Loop Gain and Phase vs.
Frequency, VS = 5 V
Figure 38. Operational Amplifier Small Signal Response for
Various Capacitive Loads, VS = 3 V
100
–90
80
60
40
20
0
–100
–110
–120
–130
–140
–150
NO
LOAD
1nF║2kΩ
1.5nF║2kΩ
72° PHASE
MARGIN
R
C
= 10kΩ
= 200pF
L
L
–20
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
TIME (5µs/DIV)
Figure 36. Operational Amplifier Open-Loop Gain and Phase vs.
Frequency, VS = 3 V
Figure 39. Operational Amplifier Large Signal Transient Response, VS = 5 V
NO
LOAD
1nF
2nF
800pF
NO
LOAD
1nF║2kΩ
1.5nF║2kΩ
1.5nF
20mV/DIV
5µs/DIV
TIME (5µs/DIV)
Figure 40. Operational Amplifier Large Signal Transient Response, VS = 3 V
Figure 37. Operational Amplifier Small Signal Response for
Various Capacitive Loads, VS = 5 V
Rev. A | Page 15 of 24
AD8231
1000
900
800
700
600
500
400
300
200
100
+V
S
–40°C
+25°C
+85°C
+125°C
–0.2
–0.4
–0.6
–0.8
–1.0
1.0
0.8
0.6
0.4
0.2
0
1
–V
S
0.1
1
10
100
10
100
1k
10k
100k
OUTPUT CURRENT (mA)
FREQUENCY (Hz)
Figure 41. Operational Amplifier Voltage Spectral Noise Density vs. Frequency
Figure 44. Operational Amplifier Output Voltage Swing vs.
Output Current, VS = 3 V
+V
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
S
–0.2
–0.4
–0.6
–0.8
–40°C
+25°C
+85°C
+125°C
–1.0
1.0
0.8
0.6
0.4
0.2
0.2
3V
0
5V
–0.2
–V
S
0.1
1
10
100
–40 –25 –10
5
20
35
50
65
80
95 110 125
OUTPUT CURRENT (mA)
TEMPERATURE (°C)
Figure 45. Operational Amplifier Output Voltage Swing vs.
Output Current, VS = 5 V
Figure 42. Operational Amplifier Bias Current vs. Temperature
140
400
300
200
100
+PSRR
120
100
80
60
40
20
0
V
= ±2.5V
S
–PSRR
0
–100
–200
–300
–400
V
= ±1.5V
S
–3
–2
–1
0
1
2
3
1
10
100
1k
10k
100k
V
(V)
FREQUENCY (Hz)
CM
Figure 46. Operational Amplifier Power Supply Rejection Ratio
Figure 43. Operational Amplifier Bias Current vs. Common Mode
Rev. A | Page 16 of 24
AD8231
PERFORMANCE CURVES VALID FOR BOTH AMPLIFIERS
7
160
140
120
100
80
G = 8
G = 128
+125°C
+85°C
6
5
G = 1
+25°C
–40°C
4
3
60
2
1
0
40
20
SOURCE CHANNEL: OP AMP AT G = 1
0
2.7
3.1
3.5
3.9
4.3
4.7
(V)
5.1
5.5
5.9
10
100
1k
FREQUENCY (Hz)
10k
100k
V
SUPPLY
Figure 47. Supply Current vs. Supply Voltage
Figure 48. Channel Separation vs. Frequency
Rev. A | Page 17 of 24
AD8231
THEORY OF OPERATION
CS A0 A1 A2
SDN
A4
OUTB
–INA
14kΩ
14kΩ
14kΩ
–INB
+INB
OUTA
A1
A2
A3
14kΩ
+INA
AD8231
+V
–V
REF
S
S
Figure 49. Simplified Schematic
Table 7. Truth Table for AD8231 Gain Settings
AMPLIFIER ARCHITECTURE
CS
A2
A1
A0
Gain
The AD8231 is based on the classic 3-op amp topology. This
topology has two stages: a preamplifier to provide amplification,
followed by a difference amplifier to remove the common-mode
voltage. Figure 49 shows a simplified schematic of the AD8231.
The preamp stage is composed of Amplifier A1, Amplifier A2,
and a digitally controlled resistor network. The second stage is a
gain of 1 difference amplifier composed of Amplifier A3 and
four 14 kꢀ resistors. A1, A2, and A3 are all zero drift, rail-to-
rail input, rail-to rail-output amplifiers.
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
High
High
High
High
X
Low
Low
High
High
Low
Low
High
High
X
Low
High
Low
High
Low
High
Low
High
X
1
2
4
8
16
32
64
128
No change
The AD8231 design makes it extremely robust over temperature.
The AD8231 uses an internal thin film resistor to set the gain.
Because all of the resistors are on the same die, gain temperature
drift performance and CMRR drift performance are better than
can be achieved with topologies using external resistors. The
AD8231 also uses an auto-zero topology to null the offsets of all its
internal amplifiers. Because this topology continually corrects for
any offset errors, offset temperature drift is nearly nonexistent.
REFERENCE TERMINAL
The output voltage of the AD8231 is developed with respect to
the potential on the reference terminal, which is useful when
the output signal needs to be offset to a midsupply level. For
example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8231 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
The AD8231 also includes a free operational amplifier. Like
the other amplifiers in the AD8231, it is a zero drift, rail-to-rail
input, rail-to-rail output architecture.
For best performance, source impedance to the REF terminal
should be kept below 1 Ω. As shown in Figure 49, the reference
terminal, REF, is at one end of a 14 kꢀ resistor. Additional
impedance at the REF terminal adds to this 14 kꢀ resistor
and results in amplification of the signal connected to the
positive input, causing a CMRR error.
GAIN SELECTION
The gain of the AD8231 is set by voltages applied to the A0, A1,
CS
and A2 pins. To change the gain, the
pin must be driven
pin is driven high, the gain is latched, and
CS
CS
low. When the
voltages at the A0 to A2 pins have no effect. Because the
pin
INCORRECT
CORRECT
is level sensitive rather than edge sensitive, it can also be tied
permanently low. Table 7 shows the different gain settings.
+
+
AD8231
AD8231
The time required for a gain change is dominated by the settling
time of the amplifier. The AD8231 takes about 200 ns to switch
gains, after which the amplifier begins to settle. Refer to Figure 28
through Figure 32 to determine the settling time for different gains.
IN-AMP
IN-AMP
V
REF
–
–
REF
REF
V
REF
+
AD8231
OP AMP
–
Figure 50. Driving the Reference (REF)
Rev. A | Page 18 of 24
AD8231
INCORRECT
+V
CORRECT
+V
LAYOUT
S
S
The AD8231 is a high precision device. To ensure optimum
performance at the PCB level, care must be taken in the design
of the board layout. The AD8231 pinout is arranged in a logical
manner to aid in this task.
AD8231
AD8231
REF
REF
REF
REF
Power Supplies
The AD8231 should be decoupled with a 0.1 μF bypass capacitor
between the two supplies. This capacitor should be placed as close
as possible to Pin 11 and Pin 12, either directly next to the pins or
beneath the pins on the backside of the board. The auto-zero
architecture of the AD8231 requires a low ac impedance between
the supplies. Long trace lengths to the bypass capacitor increase
this impedance, which results in a larger input offset voltage.
–V
S
–V
S
TRANSFORMER
TRANSFORMER
+V
+V
S
S
AD8231
AD8231
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect
performance.
REF
10MΩ
–V
S
–V
S
Package Considerations
THERMOCOUPLE
THERMOCOUPLE
The AD8231 comes in a 4 mm × 4 mm LFCSP. Beware of
blindly copying the footprint from another 4 mm × 4 mm
LFCSP part; it cannot have the same thermal pad size and leads.
Refer to the Outline Dimensions section to verify that
the PCB symbol has the correct dimensions. Space between
the leads and thermal pad should be kept as wide as possible
for the best bias current performance.
+V
+V
S
S
C
C
C
R
R
1
fHIGH-PASS
=
AD8231
2πRC
AD8231
C
REF
Thermal Pad
–V
–V
S
S
The AD8231 4 mm × 4 mm LFCSP comes with a thermal pad.
This pad is connected internally to −VS. The pad can either be
left unconnected or connected to the negative supply rail. For
high vibration applications, a landing is recommended.
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 51. Creating an IBIAS Path
INPUT PROTECTION
Because the AD8231 dissipates little power, heat dissipation
is rarely an issue. If improved heat dissipation is desired (for
example, when ambient temperatures are near 125°C or when
driving heavy loads), connect the thermal pad to the negative
supply rail. For the best heat dissipation performance, the
negative supply rail should be a plane in the board. See the
Thermal Resistance section for thermal coefficients with and
without the pad soldered.
All terminals of the AD8231 are protected against ESD. In
addition, the input structure allows for dc overload conditions
a diode drop above the positive supply and a diode drop below
the negative supply. Voltages beyond these limits cause the ESD
diodes to conduct and current to flow. If overvoltage events are
anticipated, an external resistor should be used in series with
each of the inputs to limit the current to below 10 mA. Currents
up to 100 mA can be sustained for a few seconds.
INPUT BIAS CURRENT RETURN PATH
Note that if either input is brought below the negative supply
to the point where the ESD diode turns on, the AD8231 output
can phase-reverse.
The input bias current of the AD8231 must have a return path
to common. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 51.
Rev. A | Page 19 of 24
AD8231
If more common-mode range is required, the simplest solution is
to apply less gain in the instrumentation amplifier. The extra op
amp can be used to provide another gain stage after the in-amp.
Because the AD8231 has good offset and noise performance at low
gains, applying less gain in the instrumentation amplifier generally
has a limited impact on the overall system performance.
RF INTERFERENCE
RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass, RC network placed at the
input of the instrumentation amplifier, as shown in Figure 52.
The filter limits the input signal bandwidth according to the
following relationship
REDUCING NOISE
Because the AD8231 has no 1/f noise, reducing the bandwidth
corresponds directly to less noise. Table 8 shows the AD8231
performance at a gain of 1 at different bandwidths, assuming a
2-pole Butterworth filter roll off.
1
FilterFreqDiff =
2π R(2CD + CC)
1
FilterFreqCM =
Table 8. AD8231 noise at various bandwidths
2π RCC
SNR
SNR Differential
where CD ≥ 10CC.
Single-Ended1
Output2
Bandwidth
(Hz)
Noise
(μV rms)
+V
S
dB
Bits
24.3
23.5
22.7
21.8
21.0
20.2
19.3
18.5
17.7
16.9
dB
Bits
25.3
24.5
23.7
22.8
22.0
21.2
20.3
19.5
18.7
17.9
1
3.2
10
0.07
0.12
0.21
0.37
0.66
1.17
2.07
3.71
6.55
11.73
148.3
143.2
138.3
133.2
128.3
123.2
118.3
113.2
108.3
103.2
154.3
149.2
144.3
139.2
137.63
129.2
124.3
119.2
117.3
109.2
0.1µF
+INA
10µF
C
1nF
C
R
32
4.02kΩ
100
320
1 k
3.2 k
10 k
32 k
V
C
D
10nF
OUT
AD8231
R
REF
–INA
4.02kΩ
C
C
1nF
0.1µF
10µF
1 SNR for single-ended output configuration calculated with output signal of
4.8 V p-p, which corresponds to 1.697 V rms.
–V
S
2 SNR for differential output configuration calculated with output signal of
9.6 V p-p, which corresponds to 3.397 V rms.
Figure 52. RFI Suppression
Figure 52 shows an example where the differential filter frequency
is approximately 2 kHz, and the common-mode filter frequency
is approximately 40 kHz.
The AD8231 has two clocks: an auto-zero clock at 3.4 kHz and
a commutating clock at 54 kHz. While the auto-zero clock has
negligible energy and can generally be ignored, the commutating
clock has enough energy to significantly affect the noise of the
part. Therefore, in applications where low noise is critical, limiting
the bandwidth of the system below 54 kHz is recommended.
Values of R and CC should be chosen to minimize RFI. Mismatch
between the R × CC at the positive input and the R × CC at the
negative input degrades the CMRR of the AD8231. By using a
value of CD that is ten times larger than the value of CC, the
effect of the mismatch is reduced and performance is improved.
COMMON-MODE INPUT VOLTAGE RANGE
The 3-op amp architecture of the AD8231 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8231 experience a combination of both the gained
signal and the common-mode signal. This combined signal can
be limited by the voltage supplies even when the individual input
and output signals are not. To determine whether the signal could
be limited, refer to Figure 12 through Figure 14 or use the
following formula
VDIFF ×Gain
−VS + 0.04 V <VCM
±
<+VS − 0.04 V
2
Rev. A | Page 20 of 24
AD8231
APPLICATIONS INFORMATION
The outputs of both the AD8231 in-amp and op amp are high
impedance in the shutdown state. This feature allows several
AD8231s to be multiplexed together without any external
switches. Figure 54 shows an example of such a configuration.
All the outputs are connected together and only one amplifier is
turned on at a time. This feature is analogous to the high-Z
mode of the digital tristate logic.
DIFFERENTIAL OUTPUT
Figure 53 shows how to create a differential output in-amp
using the AD8231 uncommitted op amp. Because this
configuration makes use of the reference terminal of the
in-amp, errors from the op amp and resistor mismatch result in
common-mode errors, rather than differential errors. Because
common-mode errors are typically rejected by the next device
in the signal chain, this circuit configuration adds almost no
extra error.
The resistors in the AD8231 instrumentation amplifier create a
resistive path from the output to the reference pin of about
100 kꢀ. If a higher output impedance in shutdown mode is
desired, the reference pin can be driven with the op amp of
the AD8231. In this configuration, the output impedance in
shutdown is several GΩ, and many thousand AD8231s can
theoretically be multiplexed in such a way.
3
+IN
10
IN-AMP
+OUT
REF
9
2
–IN
4.99kΩ
4.99kΩ
V
REF
The AD8231 can enter and leave shutdown mode very quickly.
However, when the amplifier wakes up and reconnects its input
circuitry, the voltage at its internal input nodes changes dramati-
cally. It takes time for the output of the amplifier to settle. Refer
to Figure 28 through Figure 32 to determine the settling time
for different gains. This settling time limits how quickly the
7
6
–
+
OP AMP
8
–OUT
Figure 53. Differential Output Using Operational Amplifier
AD8231 can be multiplexed with the
pin.
SDN
MULTIPLEXING
USING THE AD8231 WITH BIPOLAR SUPPLIES
SDN0
SDN1
SDN2
The AD8231 can be used with bipolar supplies as long as the
maximum voltage drop between the supply rails is kept below
6 V and all input voltages are kept within the supply rails.
With bipolar supplies, the acceptable levels for the digital inputs
A0, A1, A2, , and
shift. Table 9 shows acceptable values
CS
SDN
for low and high signals for both single and dual supplies.
Table 9. Digital Pin Thresholds
Low
High
Supply Voltage (V)
0 to 5
0 to 3
−2.5 to +2.5
−1.5 to +1.5
Min (V) Max (V) Min (V) Max (V)
0
+1
4
5
SDN3
0
−2.5
−1.5
+0.8
−1.5
−0.7
2.2
1.5
0.7
3
2.5
1.5
Figure 54. Four AD8231s in Multiplexing Configuration
Rev. A | Page 21 of 24
AD8231
When operating the AD8231 on dual supplies, a level-shift is
typically needed from standard single-supply control logic. One
easy way to accomplish the level-shift is through a single-pole,
double-throw switch, such as the ADG633. Figure 55 shows an
application schematic for 2.5 V operation.
Note that in addition to setting the peaking of the filter, the
ratio R3/R4 also sets the dc gain: G = 1 + R3/R4. If lower dc
gain is required, replace R1 with a voltage divider, where the
output resistance of the divider is equal to the required value of R1.
Figure 56 shows a bias point connected to R4 and the in-amp
reference. The filter stage amplifies the signal around this bias
point. The bias point is typically midsupply and should be low
impedance.
V
DIGITAL
V
DD
+2.5V
Table 10. Recommended Component Values for Butterworth
Low-Pass Filter in Figure 56
–2.5V
+2.5V
Optional Poles
Sallen Key
R1, R2 C1, C2 R6, R7
Before In-Amp
After Op Amp
–2.5V
+2.5V
3 dB
Freq
C4
(nF)
R5
(kΩ)
C3
(nF)
(kΩ)
(nF)
10
10
10
1
(kΩ)
499
158
49.9
158
49.9
15.8
4.99
V
DIGITAL
32 Hz
499
4.7
4.7
4.7
0.47
0.47
0.47
0.47
49.9
16
4.99
1.6
0.499
0.16
0.049
100
100
100
100
100
100
100
–2.5V
100 Hz 158
320 Hz 49.9
V
DD
A0 A1 A2
A0
+V
+2.5V
–2.5V
S
DIGITAL
CONTROL
A1
A2
EN
SDN
–V
1 kHz
158
S
(FPGA,
3.2 kHz 49.9
10 kHz 15.8
32 kHz 4.99
1
1
1
MICROCONTROLLER,
ETC.)
CS
ADG633
GND
AD8231
V
GND
SS
OPTIONAL POLE
R6
SALLEN KEY
(TWO POLE)
OPTIONAL POLE
–2.5V
IS THE DIGITAL SUPPLY VOLTAGE. IT CAN BE
V
DIGITAL
ANY VOLTAGE BETWEEN 2.5V AND 9.5V.
R1
R2
C2
C1
OP AMP
IN-AMP
REF
C4
R7
R5
Figure 55. Converting Single-Supply Control Signals to Dual Supply.
C3
R3
SALLEN KEY FILTER
BIAS
POINT
The extra op amp in the AD8231 can be used to create a 2-pole
Sallen Key filter. Such a filter can remove excess noise or
perform antialiasing before an analog-to-digital converter.
R4
BIAS
POINT
Figure 56. Butterworth Low-Pass Filter (Dotted Sections Indicate Optional Poles)
Figure 56 shows how to create a 2-pole low-pass Butterworth
filter. Components R1, R2, C1, and C2 set the frequency of the
filter. The ratio of R3 and R4 sets the peaking of the filter. If R4
equals 10 kΩ, R3 should equal 5.9 kΩ for an optimum 2-pole
response.
Depending on the circuitry before and after the AD8231,
a 3-pole filter can be possible. If the previous stage has a small
output impedance, an additional pole can be added before the
in amp (R6, R7, and C4). If the following stage has a high input
impedance, an additional pole can be added after the op amp
(R5 and C3). Peaking from the Sallen Key stage should be
higher to compensate for the extra attenuation of the third pole;
both R3 and R4 should be 10 kΩ for optimum response.
Rev. A | Page 22 of 24
AD8231
OUTLINE DIMENSIONS
4.00
0.60 MAX
(BOTTOM VIEW)
BSC SQ
0.60 MAX
0.65 BSC
PIN 1
INDICATOR
13
16
1
12
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
TOP
VIEW
3.75
BSC SQ
0.75
0.60
0.50
9
4
8
5
0.25 MIN
1.95 BSC
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.35
0.30
0.25
0.20 REF
COPLANARITY
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8231ACPZ-R71
AD8231ACPZ-RL1
AD8231ACPZ-WP1
AD8231-EVALZ1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
16-Lead LFCSP_VQ, 7”Tape and Reel
16-Lead LFCSP_VQ, 13”Tape and Reel
16-Lead LFCSP_VQ, Waffle Pack
Evaluation Board
CP-16-4
CP-16-4
CP-16-4
1 Z = RoHS Compliant Part.
Rev. A | Page 23 of 24
AD8231
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06586-0-9/07(A)
Rev. A | Page 24 of 24
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