AD8331ARQZ-RL_技术文档

Ultralow Noise VGAs with

Preamplifier and Programmable R_IN

AD8331/AD8332/AD8334

FEATURES

FUNCTIONAL BLOCK DIAGRAM

LON LOP VIP VIN

VCM

HILO

Ultralow noise preamplifier

Voltage noise = 0.74 nV/√Hz

Current noise = 2.5 pA/√Hz

3 dB bandwidth

AD8331: 120 MHz

3.5dB/15.5dB

V

MID

LNA

INH

–

ATTENUATOR

VOH

VOL

+

48dB

19dB

21dB

PA

–

LMD

+

AD8332, AD8334: 100 MHz

Low power

AD8331: 125 mW/channel

CLAMP

GAIN

LNA VCM

BIAS

VGA BIAS AND

INTERPOLATOR

RCLMP

CONTROL

INTERFACE

AD8331/AD8332/AD8334

AD8332, AD8334: 145 mW/channel

Wide gain range with programmable postamp

−4.5 dB to +43.5 dB

ENB

GAIN

Figure 1. Signal Path Block Diagram

+7.5 dB to +55.5 dB

60

50

40

30

20

10

0

Low output-referred noise: 48 nV/√Hz typical

Active input impedance matching

Optimized for 10-bit/12-bit ADCs

Selectable output clamping level

Single 5 V supply operation

AD8332 and AD8334 available in lead frame chip scale package

V

= 1V

GAIN

HIGH GAIN

MODE

V

= 0.8V

= 0.6V

= 0.4V

GAIN

V

= 0.2V

= 0V

APPLICATIONS

V

GAIN

Ultrasound and sonar time-gain controls

High performance AGC systems

I/Q signal processing

–10

100k

High speed, dual ADC drivers

1M

10M

FREQUENCY (Hz)

100M

1G

GENERAL DESCRIPTION

Figure 2. Frequency Response vs. Gain

The AD8331/AD8332/AD8334 are single-, dual-, and quad-

channel ultralow noise, linear-in-dB, variable gain amplifiers

(VGAs). Optimized for ultrasound systems, they are usable as a

low noise variable gain element at frequencies up to 120 MHz.

Differential signal paths result in superb second- and third-

order distortion performance and low crosstalk.

The VGA’s low output-referred noise is advantageous in driving

high speed differential ADCs. The gain of the postamplifier can

be pin selected to 3.5 dB or 15.5 dB to optimize gain range and

output noise for 12-bit or 10-bit converter applications. The

output can be limited to a user-selected clamping level,

preventing input overload to a subsequent ADC. An external

resistor adjusts the clamping level.

Included in each channel are an ultralow noise preamplifier

(LNA), an X-AMP® VGA with 48 dB of gain range, and a

selectable gain postamplifier with adjustable output limiting.

The LNA gain is 19 dB with a single-ended input and

differential outputs. Using a single resistor, the LNA input

impedance can be adjusted to match a signal source without

compromising noise performance.

The operating temperature range is −40°C to +85°C. The

AD8331 is available in a 20-lead QSOP package, the AD8332 is

available in 28-lead TSSOP and 32-lead LFCSP packages, and

the AD8334 is available in a 64-lead LFCSP package.

The 48 dB gain range of the VGA makes these devices suitable

for a variety of applications. Excellent bandwidth uniformity is

maintained across the entire range. The gain control interface

provides precise linear-in-dB scaling of 50 dB/V for control

voltages between 40 mV and 1 V. Factory trim ensures excellent

part-to-part and channel-to-channel gain matching.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD8331/AD8332/AD8334

TABLE OF CONTENTS

Features .............................................................................................. 1

Variable Gain Amplifier ............................................................ 27

Postamplifier............................................................................... 28

Applications..................................................................................... 30

LNA—External Components.................................................... 30

Driving ADCs............................................................................. 32

Overload...................................................................................... 32

Optional Input Overload Protection. ...................................... 33

Layout, Grounding, and Bypassing.......................................... 33

Multiple Input Matching ........................................................... 33

Disabling the LNA...................................................................... 33

Ultrasound TGC Application ................................................... 34

High Density Quad Layout ....................................................... 34

Outline Dimensions....................................................................... 39

Ordering Guide .......................................................................... 40

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 12

Test Circuits ..................................................................................... 20

Measurement Considerations................................................... 20

Theory of Operation ...................................................................... 24

Overview...................................................................................... 24

Low Noise Amplifier (LNA) ..................................................... 25

Rev. E | Page 2 of 40

AD8331/AD8332/AD8334

REVISION HISTORY

4/06—Rev. D to Rev. E

3/06—Rev. C to Rev. D

Added AD8334................................................................... Universal

Changes to Figure 1 and Figure 2....................................................1

Changes to Table 1 ............................................................................4

Changes to Table 2 ............................................................................7

Changes to Figure 7 through Figure 9 and Figure 12.................12

Changes to Figure 13, Figure 14, Figure 16, and Figure 18 .......13

Changes to Figure 23 and Figure 24 .............................................14

Changes to Figure 25 through Figure 27......................................15

Changes to Figure 31 and Figure 33 through Figure 36.............16

Changes to Figure 37 through Figure 42......................................17

Changes to Figure 43, Figure 44, and Figure 48..........................18

Changes to Figure 49, Figure 50, and Figure 54..........................19

Inserted Figure 56 and Figure 57 ..................................................20

Inserted Figure 58, Figure 59, and Figure 61...............................21

Changes to Figure 60 ......................................................................21

Inserted Figure 63 and Figure 65 ..................................................22

Changes to Figure 64 ......................................................................22

Moved Measurement Considerations Section ............................20

Inserted Figure 67 and Figure 68 ..................................................23

Inserted Figure 70 and Figure 71 ..................................................24

Change to Figure 72........................................................................24

Changes to Figure 73 and Low Noise Amplifier Section...........25

Changes to Postamplifier Section .................................................28

Changes to Figure 80 ......................................................................29

Changes to LNA—External Components Section......................30

Changes to Logic Inputs—ENB, MODE, and HILO Section....31

Changes to Output Decoupling and Overload Sections............32

Changes to Layout, Grounding, and Bypassing Section............33

Changes to Ultrasound TGC Application Section......................34

Added High Density Quad Layout Section .................................34

Inserted Figure 94............................................................................38

Updated Outline Dimensions........................................................39

Changes to Ordering Guide...........................................................40

Updated Format ................................................................. Universal

Changes to Features and General Description..............................1

Changes to Table 1 ............................................................................3

Changes to Table 2 ............................................................................6

Changes to Ordering Guide...........................................................34

11/03—Rev. B to Rev. C

Addition of New Part......................................................... Universal

Changes to Figures............................................................. Universal

Updated Outline Dimensions........................................................32

5/03—Rev. A to Rev. B

Edits to Ordering Guide.................................................................32

Edits to Ultrasound TGC Application Section ...........................25

Added Figure 71, Figure 72, and Figure 73..................................26

Updated Outline Dimensions........................................................31

2/03—Rev. 0 to Rev. A

Edits to Ordering Guide.................................................................32

Rev. E | Page 3 of 40

AD8331/AD8332/AD8334

SPECIFICATIONS

T_A= 25°C, V_S= 5 V, R_L= 500 Ω, R_S= R_IN= 50 Ω, R_FB= 280 Ω, C_SH= 22 pF, f = 10 MHz, R_CLMP= ∞, C_L= 1 pF, VCM pin floating,

−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.

Table 1.

Parameter

Conditions

Min

Typ

Max Unit

LNA CHARACTERISTICS

Gain

Single-ended input to differential output

Input to output (single ended)

AC-coupled

19

13

2ꢀ7

dB

mV

Ω

Input Voltage Range

Input Resistance

R_FB= 280 Ω

70

R_FB= 412 Ω

ꢀ7

Ω

R_FB= 762 Ω

R_FB= 1.13 kΩ

R_FB= ∞

100

200

6

13

7

130

670

0.ꢀ4

2.7

Ω

kΩ

pF

Ω

MHz

V/μs

Input Capacitance

Output Impedance

−3 dB Small Signal Bandwidth

Slew Rate

Input Voltage Noise

Input Current Noise

Noise Figure

Single-ended, either output

V_OUT= 0.2 V p-p

R_S= 0 Ω, HI or LO gain, R_FB= ∞, f = 7 MHz

R_FB= ∞, HI or LO gain, f = 7 MHz

f = 10 MHz, LOP output

nV/√Hz

pA/√Hz

Active Termination Match

Unterminated

R_S= R_IN= 70 Ω

R_S= 70 Ω, R_FB= ∞

3.ꢀ

2.7

dB

Harmonic Distortion @ LOP1 or LOP2

HD2

HD3

Output Short-Circuit Current

LNA + VGA CHARACTERISTICS

−3 dB Small Signal Bandwidth

AD8331

AD8332, AD8334

−3 dB Large Signal Bandwidth

AD8331

V_OUT= 0.7 V p-p, single-ended, f = 10 MHz

−76

−ꢀ0

167

dBc

mA

Pin LON, Pin LOP

V_OUT= 0.2 V p-p

120

100

MHz

V_OUT= 2 V p-p

110

90

MHz

AD8332, AD8334

Slew Rate

AD8331

LO gain

300

V/μs

HI gain

LO gain

1200

2ꢀ7

V/μs

AD8332, AD8334

HI gain

1100

0.82

V/μs

nV/√Hz

Input Voltage Noise

Noise Figure

R_S= 0 Ω, HI or LO gain, R_FB= ∞, f = 7 MHz

V_GAIN= 1.0 V

Active Termination Match

R_S= R_IN= 70 Ω, f = 10 MHz, measured

R_S= R_IN= 200 Ω, f = 7 MHz, simulated

R_S= 70 Ω, R_FB= ∞, f = 10 MHz, measured

R_S= 200 Ω, R_FB= ∞, f = 7 MHz, simulated

4.17

2.0

2.7

dB

Unterminated

1.0

Output-Referred Noise

AD8331

V_GAIN= 0.7 V, LO gain

V_GAIN= 0.7 V, HI gain

V_GAIN= 0.7 V, LO gain

V_GAIN= 0.7 V, HI gain

DC to 1 MHz

48

1ꢀ8

40

170

1

nV/√Hz

Ω

AD8332, AD8334

Output Impedance, Postamplifier

Rev. E | Page 4 of 40

AD8331/AD8332/AD8334

Parameter

Conditions

Min

Typ

Max Unit

Output Signal Range, Postamplifier

Differential

R_L≥ 700 Ω, unclamped, either pin

V_CM1.127

4.7

V

V p-p

Output Offset Voltage

AD8331

V_GAIN= 0.7 V

Differential

Common mode

Differential

−70

−127 −27

−20

7

+70

+100 mV

+20 mV

mV

AD8332, AD8334

7

Common mode

−127 –27

47

+100 mV

mA

Output Short-Circuit Current

Harmonic Distortion

AD8331

V_GAIN= 0.7 V, V_OUT= 1 V p-p, HI gain

f = 1 MHz

HD2

−88

−87

−68

−67

dBc

HD3

HD2

HD3

f = 10 MHz

AD8332, AD8334

HD2

HD3

HD2

HD3

f = 1 MHz

−82

−87

−62

−66

1

dBc

f = 10 MHz

Input 1 dB Compression Point

Two-Tone Intermodulation Distortion (IMD3)

AD8331

V_GAIN= 0.27 V, V_OUT= 1 V p-p, f = 1 MHz to 10 MHz

dBm¹

V_GAIN= 0.ꢀ2 V, V_OUT= 1 V p-p, f = 1 MHz

V_GAIN= 0.7 V, V_OUT= 1 V p-p, f = 10 MHz

V_GAIN= 0.ꢀ2 V, V_OUT= 1 V p-p, f = 1 MHz

V_GAIN= 0.7 V, V_OUT= 1 V p-p, f = 10 MHz

−80

−ꢀ2

−ꢀ8

−ꢀ4

dBc

AD8332, AD8334

Output Third-Order Intercept

AD8331

V_GAIN= 0.7 V, V_OUT= 1 V p-p, f = 1 MHz

V_GAIN= 0.7 V, V_OUT= 1 V p-p, f = 10 MHz

V_GAIN= 0.7 V, V_OUT= 1 V p-p, f = 1 MHz

V_GAIN= 0.7 V, V_OUT= 1 V p-p, f = 10 MHz

38

33

37

32

−98

7

dBm

dB

AD8332, AD8334

Channel-to-Channel Crosstalk (AD8332, AD8334) V_GAIN= 0.7 V, V_OUT= 1 V p-p, f = 1 MHz

Overload Recovery

Group Delay Variation

ACCURACY

V_GAIN= 1.0 V, V_IN= 70 mV p-p/1 V p-p, f = 10 MHz

7 MHz < f < 70 MHz, full gain range

ns

2

Absolute Gain Error²

0.07 V < V_GAIN< 0.10 V

0.10 V < V_GAIN< 0.97 V

0.97 V < V_GAIN< 1.0 V

0.1 V < V_GAIN< 0.97 V

−1

−2

+0.7

0.3

−1

0.2

0.1

+2

+1

dB

Gain Law Conformance³

Channel-to-Channel Gain Matching

GAIN CONTROL INTERFACE (Pin GAIN)

Gain Scaling Factor

0.10 V < V_GAIN< 0.97 V

LO gain

HI gain

48.7

70

71.7

dB/V

dB

V

MΩ

ns

Gain Range

−4.7 to +43.7

ꢀ.7 to 77.7

0 to 1.0

10

Input Voltage (V_GAIN) Range

Input Impedance

Response Time

48 dB gain change to 90% full scale

700

COMMON-MODE INTERFACE (PIN VCMn)

Input Resistance⁴

Output CM Offset Voltage

Voltage Range

Current limited to 1 mA

V_CM= 2.7 V

V_OUT= 2.0 V p-p

30

Ω

−127 −27

1.7 to 3.7

+100 mV

V

Rev. E | Page 7 of 40

AD8331/AD8332/AD8334

Parameter

Conditions

Min

Typ

Max Unit

ENABLE INTERFACE

(PIN ENB, PIN ENBL, PIN ENBV)

Logic Level to Enable Power

Logic Level to Disable Power

Input Resistance

2.27

0

7

1.0

V

Pin ENB

Pin ENBL

Pin ENBV

V_INH= 30 mV p-p

V_INH= 170 mV p-p

27

40

ꢀ0

300

4

kΩ

μs

ms

Power-Up Response Time

HILO GAIN RANGE INTERFACE (PIN HILO)

Logic Level to Select HI Gain Range

Logic Level to Select LO Gain Range

Input Resistance

2.27

0

7

1.0

V

kΩ

70

OUTPUT CLAMP INTERFACE

(PIN RCLMP; HI OR LO GAIN)

Accuracy

HILO = LO

HILO = HI

R_CLMP= 2.ꢀ4 kΩ, V_OUT= 1 V p-p (clamped)

R_CLMP= 2.21 kΩ, V_OUT= 1 V p-p (clamped)

70

ꢀ7

mV

MODE INTERFACE (PIN MODE)

Logic Level for Positive Gain Slope

Logic Level for Negative Gain Slope

Input Resistance

0

2.27

1.0

7

V

kΩ

200

7.0

POWER SUPPLY (PIN VPS1, PIN VPS2,

PIN VPSV, PIN VPSL, PIN VPOS)

Supply Voltage

4.7

7.7

V

Quiescent Current per Channel

AD8331

AD8332, AD8334

20

27

29

mA

Power Dissipation per channel

AD8331

AD8332, AD8334

No signal

127

147

mW

Power-Down Current

AD8332 (VGA and LNA Disabled)

AD8331 (VGA and LNA Disabled)

LNA Current

70

300

240

600

400

μA

AD8331 (ENBL)

AD8332, AD8334 (ENBL)

VGA Current

Each channel

ꢀ.7

11

12

17

mA

AD8331 (ENBV)

AD8332, AD8334 (ENBV)

PSRR

ꢀ.7

14

1ꢀ

−68

20

mA

dB

V_GAIN= 0 V, f = 100 kHz

¹All dBm values are referred to 70 Ω.

²The absolute gain refers to the theoretical gain expression in Equation 1.

³Best-fit to linear-in-dB curve.

⁴The current is limited to 1 mA typical.

Rev. E | Page 6 of 40

AD8331/AD8332/AD8334

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

Voltage

Supply Voltage (VPSn, VPSV, VPSL, VPOS)

Input Voltage (INHn)

ENB, ENBL, ENBV, HILO Voltage

GAIN Voltage

7.7 V

V_S+ 200 mV

2.7 V

Power Dissipation

AR Package¹

CP-20 Package (AD8331)

CP-32 Package (AD8332)

RQ Package¹

0.96 W

1.63 W

1.9ꢀ W

0.ꢀ8 W

0.91 W

CP-64 Package (AD8334)

Temperature

Operating Temperature Range

Storage Temperature Range

Lead Temperature (Soldering 60 sec)

θ_JA

−40°C to +87°C

−67°C to +170°C

300°C

AR Package¹

68°C/W

40°C/W

33°C/W

83°C/W

24.2°C/W

CP-20 Package²

CP-32 Package²

RQ Package¹

CP-64 Package³

¹Four-layer JEDEC board (2S2P).

²Exposed pad soldered to board, nine thermal vias in pad—JEDEC, 4-layer

board J-STD-71-9.

³Exposed pad soldered to board, 27 thermal vias in pad—JEDEC, 4-layer

board J-STD-71-9.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. E | Page ꢀ of 40

AD8331/AD8332/AD8334

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

20 COMM

LMD

INH

PIN 1

INDICATOR

19

18

ENBL

ENBV

3

VPSL

LON

LOP

4

17 COMM

AD8331

TOP VIEW

(Not to Scale)

5

16

15

14

VOL

6

VOH

VPOS

COML

VIP

7

8

13 HILO

VIN

9

12

11

RCLMP

VCM

MODE

GAIN

10

Figure 3. 20-Lead QSOP Pin Configuration (AD8331)

Table 3. 20-Lead QSOP Pin Function Description (AD8331)

Pin No.

Mnemonic

Description

1

2

LMD

INH

LNA Signal Ground

LNA Input

3

4

7

6

ꢀ

8

9

10

11

12

13

14

17

16

1ꢀ

18

19

20

VPSL

LON

LOP

COML

VIP

VIN

MODE

GAIN

VCM

RCLMP

HILO

VPOS

VOH

VOL

LNA 7 V Supply

LNA Inverting Output

LNA Noninverting Output

LNA Ground

VGA Noninverting Input

VGA Inverting Input

Gain Slope Logic Input

Gain Control Voltage

Common Mode Voltage

Output Clamping Level

Gain Range Select (HI or LO)

VGA 7 V Supply

Noninverting VGA Output

Inverting VGA Output

VGA Ground

VGA Enable

LNA Enable

COMM

ENBV

ENBL

COMM

VGA Ground

Rev. E | Page 8 of 40

AD8331/AD8332/AD8334

1

2

28

27

26

25

24

23

LMD2

INH2

LMD1

INH1

PIN 1

INDICATOR

32

31

30

29

28

27

26

25

3

VPS2

LON2

LOP2

COM2

VIP2

VPS1

LON1

LOP1

COM1

VIP1

LON1

VPS1

INH1

1

2

3

4

5

6

7

8

COMM

VOH1

VOL1

VPSV

NC

24

23

22

21

20

19

18

17

4

PIN 1

INDICATOR

5

AD8332

TOP VIEW

6

7

(Not to Scale) 22

LMD1

LMD2

INH2

AD8332

TOP VIEW

(Not to Scale)

8

21

20

19

VIN2

VIN1

9

VCM2

GAIN

RCLMP

VOH2

VOL2

COMM

VCM1

HILO

VOL2

VOH2

COMM

10

11

12

13

14

18 ENB

VPS2

LON2

17 VOH1

16 VOL1

15 VPSV

9

10

11

12

13

14

15

16

NC = NO CONNECT

Figure 4. 28-Lead TSSOP Pin Configuration (AD8332)

Figure 5. 32-Lead LFCSP Pin Configuration (AD8332)

Table 4. 28-Lead TSSOP Pin Function Description (AD8332)

Table 5. 32-Lead LFCSP Pin Function Description (AD8332)

Pin No.

Mnemonic

LMD2

INH2

Description

Pin No.

Mnemonic

LON1

VPS1

Description

1

2

CH2 LNA Signal Ground

CH2 LNA Input

1

2

CH1 LNA Inverting Output

CH1 LNA Supply 7 V

3

VPS2

CH2 Supply LNA 7 V

3

INH1

CH1 LNA Input

4

7

6

ꢀ

8

9

LON2

LOP2

COM2

VIP2

CH2 LNA Inverting Output

CH2 LNA Noninverting Output

CH2 LNA Ground

CH2 VGA Noninverting Input

CH2 VGA Inverting Input

CH2 Common-Mode Voltage

Gain Control Voltage

Output Clamping Resistor

CH2 Noninverting VGA Output

CH2 Inverting VGA Output

VGA Ground (Both Channels)

VGA Supply 7 V (Both Channels)

CH1 Inverting VGA Output

CH1 Noninverting VGA Output

Enable—VGA/LNA

VGA Gain Range Select (HI or LO)

CH1 Common-Mode Voltage

CH1 VGA Inverting Input

CH1 VGA Noninverting Input

CH1 LNA Ground

4

7

6

ꢀ

8

9

LMD1

LMD2

INH2

CH1 LNA Signal Ground

CH2 LNA Signal Ground

CH2 LNA Input

VPS2

CH2 LNA Supply 7 V

VIN2

LON2

LOP2

COM2

VIP2

CH2 LNA Inverting Output

CH2 LNA Noninverting Output

CH2 LNA Ground

CH2 VGA Noninverting Input

CH2 VGA Inverting Input

CH2 Common-Mode Voltage

Gain Slope Logic Input

Gain Control Voltage

Output Clamping Level Input

VGA Ground

VCM2

GAIN

RCLMP

VOH2

VOL2

COMM

VPSV

VOL1

VOH1

ENB

10

11

12

13

14

17

16

1ꢀ

18

19

20

21

22

23

24

27

26

2ꢀ

28

10

11

12

13

14

17

16

1ꢀ

18

19

20

21

22

23

24

27

26

2ꢀ

28

29

30

31

32

VIN2

VCM2

MODE

GAIN

RCLMP

COMM

VOH2

VOL2

NC

VPSV

VOL1

VOH1

COMM

ENBV

ENBL

HILO

CH2 Noninverting VGA Output

CH2 Inverting VGA Output

No Connect

HILO

VCM1

VIN1

VGA Supply 7 V

VIP1

CH1 Inverting VGA Output

CH1 Noninverting VGA Output

VGA Ground

VGA Enable

LNA Enable

VGA Gain Range Select (HI or LO)

CH1 Common-Mode Voltage

CH1 VGA Inverting Input

CH1 VGA Noninverting Input

CH1 LNA Ground

COM1

LOP1

LON1

VPS1

INH1

LMD1

CH1 LNA Noninverting Output

CH1 LNA Inverting Output

CH1 LNA Supply 7 V

CH1 LNA Input

CH1 LNA Signal Ground

VCM1

VIN1

VIP1

COM1

LOP1

CH1 LNA Noninverting Output

Rev. E | Page 9 of 40

AD8331/AD8332/AD8334

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

INH2

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

COM12

VOH1

VOL1

VPS12

VOL2

VOH2

COM12

MODE

NC

PIN 1

INDICATOR

LMD2

2

COM2X

LON2

LOP2

VIP2

3

4

5

6

VIN2

7

AD8334

8

VPS2

VPS3

VIN3

TOP VIEW

9

(Not to Scale)

10

11

12

13

14

15

16

COM34

VOH3

VOL3

VPS34

VOL4

VOH4

COM34

VIP3

LOP3

LON3

COM3X

LMD3

INH3

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

NC = NO CONNECT

Figure 6. 64-Lead LFCSP Pin Configuration (AD8334)

Table 6. 64-Lead LFCSP Pin Function Description (AD8334)

Pin No.

Mnemonic

Description

1

INH2

CH2 LNA Input

2

3

4

7

LMD2

COM2X

LON2

LOP2

CH2 LNA V_MIDBypass (AC-Coupled to GND)

CH2 LNA Ground Shield

CH2 LNA Feedback Output (for R_FBK

)

CH2 LNA Output

6

ꢀ

8

VIP2

VIN2

VPS2

CH2 VGA Positive Input

CH2VGA Negative Input

CH2 LNA Supply 7 V

9

VPS3

CH3 LNA Supply 7 V

10

11

12

13

14

17

16

1ꢀ

18

19

20

21

22

23

24

27

26

2ꢀ

28

VIN3

VIP3

LOP3

CH3VGA Negative Input

CH3 VGA Positive Input

CH3 LNA Positive Output

CH3 LNA Feedback Output (for R_FBK

CH3 LNA Ground Shield

CH3 LNA V_MIDBypass (AC-Coupled to GND)

CH3 LNA Input

CH3 LNA Ground

CH4 LNA Ground

CH4 LNA Input

CH4 LNA V_MIDBypass (AC-Coupled to GND)

CH4 LNA Ground Shield

LON3

COM3X

LMD3

INH3

COM3

COM4

INH4

LMD4

COM4X

LON4

LOP4

VIP4

VIN4

VPS4

GAIN34

CLMP34

)

CH4 LNA Feedback Output (for R_FBK

CH4 LNA Positive Output

CH4 VGA Positive Input

CH4VGA Negative Input

CH4 LNA Supply 7 V

)

Gain Control Voltage for CH3 and CH4

Output Clamping Level Input for CH3 and CH4

Rev. E | Page 10 of 40

AD8331/AD8332/AD8334

Pin No.

29

30

31

32

33

34

37

36

3ꢀ

38

39

40

41

42

43

44

47

46

4ꢀ

48

49

70

71

72

73

74

77

76

7ꢀ

78

79

60

61

62

63

64

Mnemonic

HILO

VCM4

VCM3

NC

COM34

VOH4

VOL4

VPS34

VOL3

VOH3

COM34

NC

MODE

COM12

VOH2

VOL2

Description

Gain Select for Postamp 0 dB or 12 dB

CH4 Common-Mode Voltage—AC Bypass

CH3 Common-Mode Voltage—AC Bypass

No Connect

VGA Ground, CH3 and CH4

CH4 Positive VGA Output

CH4 Negative VGA Output

VGA Supply 7V CH3 and CH4

CH3 Negative VGA Output

CH3 Positive VGA Output

VGA ground CH3 and CH4

No Connect

Gain Control SLOPE, Logic Input, 0 = Positive

VGA Ground CH1 and CH2

CH2 Positive VGA Output

CH2 Negative VGA Output

CH2 VGA Supply 7 V CH1 and CH2

CH1 Negative VGA Output

CH1 Positive VGA Output

VPS12

VOL1

VOH1

COM12

VCM2

VCM1

EN34

VGA Ground CH1 and CH2

CH2 Common-Mode Voltage—AC Bypass

CH1 Common-Mode Voltage—AC Bypass

Shared LNA/VGA Enable, CH3 and CH4

Shared LNA/VGA Enable, CH1 and CH2

Output Clamping Level Input, CH1 and CH2

Gain Control Voltage CH1 and CH2

CH1 LNA Supply 7 V

CH1 VGA Negative Input

CH1 VGA Positive Input

CH1 LNA Positive Output

CH1 LNA Feedback Output (for R_FBK

CH1 LNA Ground Shield

CH1 LNA V_MIDBypass (AC-Coupled to GND)

CH1 LNA Input

CH1 LNA Ground

CH2 LNA Ground

EN12

CLMP12

GAIN12

VPS1

VIN1

VIP1

LOP1

LON1

COM1X

LMD1

INH1

COM1

COM2

)

Rev. E | Page 11 of 40

AD8331/AD8332/AD8334

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_S= 5 V, R_L= 500 Ω, R_S= R_IN= 50 Ω, R_FB= 280 Ω, C_SH= 22 pF, f = 10 MHz, R_CLMP= ∞, C_L= 1 pF, VCM pin floating,

−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.

60

50

40

30

20

10

0

50

40

30

20

10

0

SAMPLE SIZE = 80 UNITS

= 0.5V

V

GAIN

HILO = HI

HILO = LO

ASCENDING GAIN MODE

DESCENDING GAIN MODE

(WHERE AVAILABLE)

–10

0

0.2

0.4

0.6

(V)

0.8

1.0 1.1

–0.5 –0.4 –0.3 –0.2 –0.1

0

0.1

0.2

0.3

0.4

0.5

V

GAIN ERROR (dB)

GAIN

Figure 10. Gain Error Histogram

Figure 7. Gain vs. V_GAINand MODE (MODE Available on AC Package)

25

20

15

10

5

2.0

1.5

1.0

SAMPLE SIZE = 50 UNITS

V = 0.2V

GAIN

–40°C

+25°C

0.5

0

25

V

= 0.7V

GAIN

20

15

10

5

–0.5

+85°C

–1.0

–1.5

–2.0

0

0.2

0.4

0.6

(V)

0.8

1.0 1.1

V

GAIN

CHANNEL TO CHANNEL GAIN MATCH (dB)

Figure 8. Absolute Gain Error vs. V_GAINat Three Temperatures

Figure 11. Gain Match Histogram for V_GAIN= 0.2 V and 0.7 V

2.0

50

V

= 1V

GAIN

1.5

1.0

40

30

= 0.8V

V

= 0.6V

= 0.4V

= 0.2V

GAIN

0.5

20

1MHz

0

10

10MHz

30MHz

–0.5

0

–1.0

50MHz

V

= 0V

GAIN

–10

–1.5

70MHz

–20

100k

–2.0

1M

10M

FREQUENCY (Hz)

100M

500M

0

0.2

0.4

0.6

(V)

0.8

1.0 1.1

V

GAIN

Figure 12. Frequency Response for Various Values of V_GAIN

Figure 9. Absolute Gain Error vs. V_GAINat Various Frequencies

Rev. E | Page 12 of 40

AD8331/AD8332/AD8334

60

50

40

30

20

10

0

–20

V

= 1V

GAIN

V

= 1V p-p

OUT

= 0.8V

V

= 1.0V

= 0.7V

= 0.4V

GAIN

V

= 0.6V

= 0.4V

= 0.2V

AD8332

AD8334

GAIN

V

–40

V

–60

–80

V

= 0V

GAIN

–100

–10

100k

–120

100k

1M

10M

FREQUENCY (Hz)

100M

500M

1M

10M

FREQUENCY (Hz)

100M

Figure 13. Frequency Response for Various Values of V_GAIN, HILO = HI

Figure 16. Channel-to-Channel Crosstalk vs.

Frequency for Various Values of V_GAIN

30

50

45

40

35

30

25

20

15

10

5

V

= 0.5V

GAIN

R

= R = 75Ω

S

IN

R

= R = 50Ω

S

IN

20

10

0.1µF

COUPLING

R

= R = 100Ω

S

IN

R

= R = 200Ω

S

IN

1µF

COUPLING

0

R

= R = 500Ω

S

IN

–10

–20

–30

R

= R = 1kΩ

S

IN

0

100k

1M

10M

FREQUENCY (Hz)

100M

500M

1M

10M

FREQUENCY (Hz)

100M

Figure 14. Frequency Response for Various Matched Source Impedances

Figure 17. Group Delay vs. Frequency for Two Values of AC Coupling

20

30

T = +85°C

T = +25°C

T = –40°C

HI GAIN

V

R

= 0.5V

∞

GAIN

=

FB

10

0

20

10

–10

–20

20

0

LO GAIN

10

0

–10

–20

–30

T = +85°C

T = +25°C

T = –40°C

–10

–20

100k

1M

10M

100M

500M

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

(V)

FREQUENCY (Hz)

V

GAIN

Figure 15. Frequency Response, Unterminated LNA, R_S= 50 Ω

Figure 18. Representative Differential Output Offset Voltage vs.

V_GAINat Three Temperatures

Rev. E | Page 13 of 40

AD8331/AD8332/AD8334

50j

100j

25j

35

SAMPLE SIZE = 100

R

= 50Ω,

= 270Ω

IN

0.2V < V

< 0.7V

GAIN

FB

30

25

20

15

10

5

R

= 6kΩ,

f

= 100kHz

IN

=

∞

FB

0Ω

17Ω

R

= 75Ω,

IN

= 412Ω

FB

R

= 100Ω,

= 549Ω

IN

FB

R

= 200Ω,

= 1.1kΩ

IN

0

FB

49.6 49.7 49.8 49.9 50.0 50.1 50.2 50.3 50.4 50.5

GAIN SCALING FACTOR

–25j

–100j

–50j

Figure 19. Gain Scaling Factor Histogram

Figure 22. Smith Chart, S11 vs. Frequency,

0.1 MHz to 200 MHz for Various Values of R_FB

100

10

1

20

15

10

5

SINGLE ENDED, PIN VOH OR VOL

V

= 10mV p-p

R

= 50Ω

IN

R

= ∞

L

R

= 100Ω

IN

R

= 200Ω

IN

R

= 500Ω

IN

0

R

= 1kΩ

IN

–5

–10

–15

R

= 75Ω

IN

0.1

100k

1M

10M

FREQUENCY (Hz)

100M

100k

1M

10M

FREQUENCY (Hz)

100M

500M

Figure 20. Output Impedance vs. Frequency

Figure 23. LNA Frequency Response, Single Ended, for Various Values of R_IN

10k

20

15

R

= ∞, C = 0pF

SH

FB

R

= ∞

R

= 6.65kΩ, C = 0pF

SH

FB

R

= 3.01kΩ, C = 0pF

SH

FB

10

5

1k

100

10

R

= 1.1kΩ, C = 1.2pF

SH

FB

0

R

= 549Ω, C = 8.2pF

SH

FB

–5

–10

–15

R

= 412Ω, C = 12pF

FB

SH

R

= 270Ω, C = 22pF

FB

SH

100k

1M

10M

100M

100k

1M

10M

100M

500M

FREQUENCY (Hz)

Figure 21. LNA Input Impedance vs.

Figure 24. Frequency Response for Unterminated LNA, Single Ended

Frequency for Various Values of R_FBand C_SH

Rev. E | Page 14 of 40

AD8331/AD8332/AD8334

500

400

300

200

100

0

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

R

V

= 0, R = ∞,

FB

S

= 1V, f = 10MHz

f

= 10MHz

GAIN

AD8332

AD8334

LO GAIN

HI GAIN

AD8331

0

0.2

0.4

0.6

0.8

1.0

–50

–30

–10

10

30

50

70

90

V

(V)

TEMPERATURE (°C)

GAIN

Figure 25. Output-Referred Noise vs. V_GAIN

Figure 28. Short-Circuit, Input-Referred Noise vs. Temperature

2.5

2.0

1.5

1.0

0.5

R

= 0, R

FB

=

∞

, V = 1V,

S

GAIN

10

HILO = LO OR HI

f = 5MHz, R

FB

= ∞,

V

= 1V

GAIN

1

R

THERMAL NOISE

ALONE

S

100k

1M

10M

FREQUENCY (Hz)

100M

0.1

1

10

100

1k

SOURCE RESISTANCE (Ω)

Figure 26. Short-Circuit, Input-Referred Noise vs. Frequency

Figure 29. Input-Referred Noise vs. R_S

100

7

6

5

4

3

2

1

0

R

= 0, R = ∞,

FB

S

INCLUDES NOISE OF VGA

HILO = LO OR HI, f = 10MHz

R

= 50Ω

10

IN

R

= 75Ω

IN

R

= 100Ω

IN

1

R

= 200Ω

IN

R

= ∞

FB

SIMULATION

50 100

0.1

0

0.2

0.4

0.6

0.8

1.0

1k

V

(V)

SOURCE RESISTANCE (Ω)

GAIN

Figure 30. Noise Figure vs. R_Sfor Various Values of R_IN

Figure 27. Short-Circuit, Input-Referred Noise vs. V_GAIN

Rev. E | Page 17 of 40

AD8331/AD8332/AD8334

35

–30

–40

–50

–60

–70

–80

–90

PREAMP LIMITED

f = 10MHz, R = 50Ω

S

f = 10MHz,

= 1V p-p

V

OUT

30

HILO = LO, R = 50Ω

IN

25

20

15

10

5

HILO = HI, R = 50Ω

IN

HILO = LO, HD2

HILO = HI, HD2

HILO = HI, HD3

HILO = LO, R

FB

= ∞

HILO = LO, HD3

HILO = HI, R = ∞

IN

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

(V)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

(Ω)

V

R

LOAD

GAIN

Figure 31. Noise Figure vs. V_GAIN

Figure 34. Harmonic Distortion vs. R_LOAD

30

25

20

15

10

5

–40

–50

–60

–70

–80

–90

f = 10MHz,

= 1V p-p

f = 10MHz, R = 50Ω

S

V

OUT

HILO = HI, R = 50Ω

IN

HILO = HI, R

=

∞

HILO = LO, HD2

HILO = LO, HD3

FB

HILO = HI, HD2

HILO = HI, HD3

HILO = LO, R = 50Ω

IN

HILO = LO, R

FB

= ∞

0

10

15

20

25

30

35

40

45

50

55

60

10

20

30

(pF)

40

50

GAIN (dB)

C

LOAD

Figure 35. Harmonic Distortion vs. C_LOAD

Figure 32. Noise Figure vs. Gain

–20

–40

f = 10MHz,

GAIN = 30dB

0

G = 30dB,

= 1V p-p

V

OUT

–10

–20

–30

–40

–50

–60

–70

–80

–90

HILO = LO, HD3

HILO = LO, HD2

HILO = LO, HD3

–60

HILO = HI, HD2

HILO = HI, HD3

–80

HILO = HI, HD2

HILO = HI, HD3

–100

1

2

3

4

1M

10M

100

V

(V p-p)

OUT

FREQUENCY (Hz)

Figure 36. Harmonic Distortion vs. Differential Output Voltage

Figure 33. Harmonic Distortion vs. Frequency

Rev. E | Page 16 of 40

AD8331/AD8332/AD8334

0

–20

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

V

= 1V p-p COMPOSITE (f₁

+

f₂)

OUT

G = 30dB

V

= 1V p-p

OUT

INPUT RANGE

LIMITED WHEN

HILO = LO

–40

HILO = LO, HD3

HILO = LO

HILO = LO, HD2

–60

–80

HILO = HI, HD3

–100

–120

HILO = HI, HD2

HILO = HI

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1M

10M

100M

V

(V)

FREQUENCY (Hz)

GAIN

Figure 40. IMD3 vs. Frequency

Figure 37. Harmonic Distortion vs. V_GAIN, f = 1 MHz

0

–20

40

35

30

25

20

15

10

5

10MHz HILO = HI

V

= 1V p-p

OUT

1MHz HILO = LO

10MHz HILO = LO

1MHz HILO = HI

HILO = LO, HD2

INPUT RANGE

LIMITED WHEN

HILO = LO

–40

HILO = LO, HD3

–60

–80

HILO = HI, HD3

HILO = HI, HD2

–100

–120

V

= 1V p-p COMPOSITE (f₁+ f₂)

OUT

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

V

(V)

V

(V)

GAIN

Figure 41. Output Third-Order Intercept vs. V_GAIN

Figure 38. Harmonic Distortion vs. V_GAIN, f = 10 MHz

10

0

2mV

f = 10MHz

100

90

HILO = LO

–10

–20

–30

–40

HILO = HI

10

0

50mV

10ns

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

V

(V)

GAIN

Figure 42. Small Signal Pulse Response, G = 30 dB,

Top: Input, Bottom: Output Voltage, HILO = HI or LO

Figure 39. Input 1 dB Compression vs. V_GAIN

Rev. E | Page 1ꢀ of 40

AD8331/AD8332/AD8334

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

20mV

100

90

HILO = HI

HILO = LO

10

0

500mV

10ns

0

5

10

15

20

25

30

(kΩ)

35

40

45

50

R

CLMP

Figure 43. Large Signal Pulse Response, G = 30 dB,

HILO = HI or LO, Top: Input, Bottom: Output Voltage

Figure 46. Clamp Level vs. R_CLMP

4

3

2

1

G = 40dB

C

= 0pF

L

R

= 48.1kΩ

G = 30dB

CLMP

R

= 10pF

= 22pF

= 47pF

= 16.5kΩ

CLMP

2

INPUT

1

INPUT

0

R

= 7.15kΩ

0

CLMP

R

= 2.67kΩ

–1

–2

–3

–4

CLMP

–1

INPUT IS NOT TO SCALE

–30 –20 –10

0

10

20

30

40

50

60

70

80

–2

–50 –40 –30 –20 –10

0

10

20

30

40

50

TIME (ns)

Figure 47. Clamp Level Pulse Response for 4 Values of R_CLMP

Figure 44. Large Signal Pulse Response for Various Capacitive Loads,

C_L= 0 pF, 10 pF, 20 pF, 50 pF

200mV

100

90

500mV

10

0

100ns

200mV

400ns

Figure 48. LNA Overdrive Recovery, V_INH0.05 V p-p to 1 V p-p Burst,

V_GAIN= 0.27 V VGA Output Shown

Figure 45. Pin GAIN Transient Response,

Top: V_GAIN, Bottom: Output Voltage

Rev. E | Page 18 of 40

AD8331/AD8332/AD8334

1V

2V

100

90

10

0

100ns

1V

1ms

Figure 52. Enable Response, Large Signal,

Top: V_ENB, Bottom: V_OUT, V_INH= 150 mV p-p

Figure 49. VGA Overdrive Recovery, V_INH4 mV p-p to 70 mV p-p Burst,

V_GAIN= 1 V VGA Output Shown Attenuated by 24 dB

0

–10

–20

–30

–40

–50

–60

–70

–80

VPS1, V

GAIN

= 0.5V

1V

100

90

VPSV, V

GAIN

= 0.5V

VPS1, V

GAIN

= 0V

10

0

100ns

100k

1M

10M

FREQUENCY (Hz)

100M

Figure 50. VGA Overdrive Recovery, V_INH4 mV p-p to 275 mV p-p Burst,

V_GAIN= 1 V VGA Output Shown Attenuated by 24 dB

Figure 53. PSRR vs. Frequency (No Bypass Capacitor)

140

130

120

110

100

90

V

= 0.5V

GAIN

2V

AD8334

80

70

AD8332

60

50

40

AD8331

40

200mV

1ms

30

20

–40

–20

0

20

60

80

100

TEMPERATURE (°C)

Figure 51. Enable Response, Top: V_ENB, Bottom: V_OUT, V_INH= 30 mV p-p

Figure 54. Quiescent Supply Current vs. Temperature

Rev. E | Page 19 of 40

AD8331/AD8332/AD8334

TEST CIRCUITS

Short-circuit input noise measurements are made using Figure 62.

The input-referred noise level is determined by dividing the

output noise by the numerical gain between Point A and Point B

and accounting for the noise floor of the spectrum analyzer.

The gain should be measured at each frequency of interest and

with low signal levels because a 50 Ω load is driven directly. The

generator is removed when noise measurements are made.

MEASUREMENT CONSIDERATIONS

Figure 55 through Figure 68 show typical measurement

configurations and proper interface values for measurements

with 50 Ω conditions.

NETWORK ANALYZER

50Ω

OUT

IN

18nF

270Ω

FERRITE

BEAD

120nH

237Ω

28Ω

0.1µF

INH

LMD

DUT

1:1

22pF

237Ω

28Ω

0.1µF

Figure 55. Gain and Bandwidth Measurements

NETWORK ANALYZER

50Ω

OUT

IN

10kΩ

18nF

FERRITE

BEAD

120nH

237Ω

28Ω

0.1µF

10kΩ

INH

LMD

DUT

1:1

22pF

237Ω

28Ω

0.1µF

Figure 56. Frequency Response for Various Matched Source Impedances

NETWORK ANALYZER

50Ω

OUT

IN

FERRITE

BEAD

120nH

237Ω

28Ω

0.1µF

INH

LMD

DUT

1:1

22pF

237Ω

28Ω

0.1µF

Figure 57. Frequency Response for Unterminated LNA, R_S= 50 Ω

Rev. E | Page 20 of 40

AD8331/AD8332/AD8334

NETWORK ANALYZER

50Ω

OUT

IN

10kΩ

18nF

0.1µF

AND

10µF

FERRITE

BEAD

0.1µF

AND

10µF

237Ω

28Ω

120nH

INH

LMD

LNA

VGA

1:1

22pF

237Ω

28Ω

0.1µF

AND

10µF

Figure 58. Group Delay vs. Frequency for Two Values of AC Coupling

NETWORK

ANALYZER

18nF

270Ω

FERRITE

BEAD

237Ω

28Ω

0.1µF

120nH

50Ω

OUT

INH

LMD

DUT

22pF

1:1

50Ω

237Ω

28Ω

0.1µF

Figure 59. LNA Input Impedance vs. Frequency in Standard and Smith Chart (S11) Formats

NETWORK ANALYZER

50Ω

OUT

IN

0.1µF

FERRITE

BEAD

120nH

237Ω

28Ω

0.1µF

INH

LNA

VGA

1:1

22pF

LMD

237Ω

28Ω

0.1µF

Figure 60. Frequency Response for Unterminated LNA, Single Ended

NETWORK

ANALYZER

18nF

270Ω

FERRITE

BEAD

237Ω

28Ω

50Ω

IN

1:1

0.1µF

120nH

INH

LMD

DUT

22pF

237Ω

28Ω

0.1µF

Figure 61. Short-Circuit, Input-Referred Noise

Rev. E | Page 21 of 40

AD8331/AD8332/AD8334

SPECTRUM

ANALYZER

A

B

GAIN

FERRITE

BEAD

50Ω

IN

0.1µF

120nH

49.9Ω

50Ω

INH

LMD

22pF

1:1

1Ω

0.1µF

SIGNAL GENERATOR

TO MEASURE GAIN

DISCONNECT FOR

NOISE MEASUREMENT

Figure 62. Noise Figure

SPECTRUM

ANALYZER

18nF

270Ω

AD8332

50Ω

IN

1kΩ

0.1µF

22pF

–6dB

INH

–6dB

28Ω

LPF

1:1

LMD

50Ω

0.1µF

SIGNAL

GENERATOR

Figure 63. Harmonic Distortion vs. Load Resistance

SPECTRUM

ANALYZER

18nF

270Ω

AD8332

50Ω

IN

0.1µF

22pF

–6dB

237Ω

INH

–6dB

28Ω

237Ω

LPF

1:1

LMD

50Ω

0.1µF

28Ω

SIGNAL

GENERATOR

Figure 64. Harmonic Distortion vs. Load Capacitance

–6dB

SPECTRUM

ANALYZER

+22dB

18nF

270Ω

INPUT

FERRITE

BEAD

50Ω

0.1µF

–6dB

237Ω

120nH

INH

28Ω

237Ω

–6dB

+22dB

1:1

DUT

22pF

LMD

COMBINER

–6dB

0.1µF

28Ω

50Ω

SIGNAL

GENERATORS

Figure 65. IMD3 vs. Frequency

Rev. E | Page 22 of 40

AD8331/AD8332/AD8334

OSCILLOSCOPE

18nF

270Ω

FERRITE

BEAD

50Ω

0.1µF

237Ω

120nH

INH

IN

28Ω

237Ω

1:1

DUT

22pF

LMD

50Ω

0.1µF

28Ω

Figure 66. Pulse Response Measurements

OSCILLOSCOPE

CH1 CH2

18nF

270Ω

FERRITE

BEAD

120nH

0.1µF

DIFF

PROBE

INH

255Ω

DUT

22pF

LMD

50Ω

RF

0.1µF

SIGNAL

0.1µF 255Ω

GENERATOR

9.5dB

TO PIN GAIN

OR ENxx

50Ω

PULSE

GENERATOR

Figure 67. GAIN and Enable Transient Response

NETWORK

ANALYZER

50Ω

OUT

IN

18nF

TO POWER

PIN(S)

270Ω

FERRITE

BEAD

120nH

0.1µF

DIFF PROBE

PROBE POWER

INH

255Ω

DUT

22pF

LMD

50Ω

RF

0.1µF

SIGNAL

0.1µF 255Ω

GENERATOR

Figure 68. PSRR vs. Frequency

Rev. E | Page 23 of 40

AD8331/AD8332/AD8334

THEORY OF OPERATION

OVERVIEW

LON1 LOP1 VIP1 VIN1 EN12

VCM1

INH1

CLMP12

V

CLAMP

PA1

The following discussion applies to all part numbers. Figure 69,

Figure 70, and Figure 71 are functional block diagrams of the

AD8331, AD8332, and AD8334, respectively.

MID1

LNA 1

LMD1

VOH1

VOL1

–

+

ATTENUATOR

–48dB

21dB

LNA

BIAS

LON LOP VIP VIN

VCM

HILO

VGA BIAS AND

GAIN

INT

GAIN12

HILO

LMD2

INTERPOLATOR

3.5dB/

LNA 2

V

15.5dB

PA

MID

INH2

LON2

LOP2

VIP2

VOL2

+

ATTENUATOR

–48dB

21dB

PA2

INH

–

VOH

VOL

+

–

VOH2

ATTENUATOR

–48dB

LNA

21dB

–

LMD

+

V

VCM2

VCM3

MID2

VIN2

GAIN UP/

DOWN

LNA

BIAS

VGA BIAS AND

INTERPOLATOR

GAIN

INT

MODE

CLAMP

RCLMP

MODE

MID3

VIN3

VIP3

AD8331

VOH3

VOL3

–

+

LOP3

LON3

ATTENUATOR

–48dB

21dB

PA3

ENBL

ENBV

GAIN

Figure 69. AD8331 Functional Block Diagram

INH3

VGA BIAS AND

INTERPOLATOR

GAIN

INT

GAIN34

LNA 3

LMD3

VOL4

VOH4

+

ATTENUATOR

–48dB

21dB

PA4

LNA

BIAS

LON1 LOP1 VIP1 VIN1

VCM1

HILO

–

3.5dB/

V

LMD4

INH4

MID

+19dB

15.5dB

CLAMP34

LNA 4

CLMP34

AD8334

INH1

V

MID4

VOH1

VOL1

–

LNA 1

ATTENUATOR

–48dB

21dB

PA1

+

LMD1

LON4 LOP4 VIP4 VIN4

EN34

VCM4

BIAS

(V

VGA BIAS AND

INTERPOLATOR

GAIN

INT

GAIN

)

MID

Figure 71. AD8334 Functional Block Diagram

LMD2

INH2

VOL2

VOH2

+

ATTENUATOR

–48dB

Each channel contains an LNA that provides user-adjustable

input impedance termination, a differential X-AMP VGA, and a

programmable gain postamplifier with adjustable output voltage

limiting. Figure 72 shows a simplified block diagram with

external components.

21dB

PA2

LNA 2

–

AD8332

V

CLAMP

MID

RCLMP

LON2 LOP2 VIP2 VIN2

ENB

VCM2

Figure 70. AD8332 Functional Block Diagram

HILO

LON

VIN

SIGNAL PATH

3.5dB/15.5dB

PRE-AMPLIFIER

19dB

VOH

VOL

INH

+

48dB

ATTENUATOR

POST-

AMP

21dB

LNA

–

LMD

V

MID

LOP

VIP

VCM

CLAMP

BIAS

(V

BIAS AND

INTERPOLATOR

GAIN

INTERFACE

)

MID

RCLMP

GAIN

Figure 72. Simplified Block Diagram

Rev. E | Page 24 of 40

AD8331/AD8332/AD8334

LOW NOISE AMPLIFIER (LNA)

The linear-in-dB gain-control interface is trimmed for slope

and absolute accuracy. The gain range is 48 dB, extending from

−4.5 dB to +43.5 dB in HI gain and +7.5 dB to +55.5 dB in LO

gain mode. The slope of the gain control interface is 50 dB/V,

and the gain control range is 40 mV to 1 V. Equation 1 and

Equation 2 are the expressions for gain.

Good noise performance relies on a proprietary ultralow noise

preamplifier at the beginning of the signal chain, which minimizes

the noise contribution in the following VGA. Active impedance

control optimizes noise performance for applications that benefit

from input matching.

GAIN (dB) = 50 (dB/V) × V_GAIN− 6.5 dB, (HILO = LO)

(1)

A simplified schematic of the LNA is shown in Figure 74. INH

is capacitively coupled to the source. An on-chip bias generator

establishes dc input bias voltages of 3.25 V and centers the

output common-mode levels at 2.5 V. A Capacitor C_LMDof the

same value as the Input Coupling Capacitor C_INHis connected

from the LMD pin to ground.

or

GAIN (dB) = 50 (dB/V) × V_GAIN+ 5.5 dB, (HILO = LO)

(2)

The ideal gain characteristics are shown in Figure 73.

60

C

R

FB

50

LOP

VPOS

LON

HILO = HI

40

30

20

10

0

I

0

C

INH

LMD

Q1

Q2

C

LMD

HILO = LO

C

SH

R

S

I

0

ASCENDING GAIN MODE

DESCENDING GAIN MODE

(WHERE AVAILABLE)

–10

0

0.2

0.4

0.6

(V)

0.8

1.0 1.1

Figure 74. Simplified LNA Schematic

V

GAIN

The LNA supports differential output voltages as high as 5 V p-p

with positive and negative excursions of 1.25 V, about a

common-mode voltage of 2.5 V. Because the differential gain

magnitude is 9, the maximum input signal before saturation is

275 mV or +550 mV p-p. Overload protection ensures quick

recovery time from large input voltages. Because the inputs are

capacitively coupled to a bias voltage near midsupply, very large

inputs can be handled without interacting with the ESD protection.

Figure 73. Ideal Gain Control Characteristics

The gain slope is negative with the MODE pulled high (where

available):

GAIN (dB) = −50 (dB/V) × V_GAIN+ 45.5 dB, (HILO = LO)

(3)

or

GAIN (dB) = −50 (dB/V) × V_GAIN+ 57.5 dB, (HILO = HI)

(4)

Low value feedback resistors and the current-driving capability

of the output stage allow the LNA to achieve a low input-referred

voltage noise of 0.74 nV/√Hz. This is achieved with a current

consumption of only 11 mA per channel (55 mW). On-chip

resistor matching results in precise single-ended gains of 4.5×

(9× differential), critical for accurate impedance control. The

use of a fully differential topology and negative feedback

minimizes distortion. Low HD2 is particularly important in

second harmonic ultrasound imaging applications. Differential

signaling enables smaller swings at each output, further

reducing third-order distortion.

The LNA converts a single-ended input to a differential output

with a voltage gain of 19 dB. If only one output is used, the gain

is 13 dB. The inverting output is used for active input impedance

termination. Each of the LNA outputs is capacitively coupled to

a VGA input. The VGA consists of an attenuator with a range of

48 dB followed by an amplifier with 21 dB of gain for a net gain

range of −27 dB to +21 dB. The X-AMP gain-interpolation

technique results in low gain error and uniform bandwidth, and

differential signal paths minimize distortion.

The final stage is a logic programmable amplifier with gains of

3.5 dB or 15.5 dB. The LO and HI gain modes are optimized for

12-bit and 10-bit ADC applications, in terms of output-referred

noise and absolute gain range. Output voltage limiting can be

programmed by the user.

Rev. E | Page 27 of 40

AD8331/AD8332/AD8334

UNTERMINATED

Active Impedance Matching

R

IN

R

S

The LNA supports active impedance matching through an external

shunt feedback resistor from Pin LON to Pin INH. The input

resistance, R_IN, is given by Equation 5, where A is the single-

ended gain of 4.5, and 6 kΩ is the unterminated input impedance.

+

–

V

OUT

V

IN

RESISTIVE TERMINATION

6 kꢀ × R_FB

33 kꢀ + R_FB

R

R_FB

1 + A

IN

R_IN

=

6 kꢀ =

(5)

R

S

+

–

R

V

S

OUT

V

IN

C

_FBis needed in series with R_FBbecause the dc levels at Pin LON

and Pin INH are unequal. Expressions for choosing R_FBin terms

of R_INand for choosing C_FBare found in the Applications section.

ACTIVE IMPEDANCE MATCH

R

FB

R

IN

C_SHand the ferrite bead enhance stability at higher frequencies

R

S

where the loop gain is diminished and prevent peaking. Frequency

response plots of the LNA are shown in Figure 23 and Figure 24.

The bandwidth is approximately 130 MHz for matched input

impedances of 50 Ω to 200 Ω and declines at higher source

impedances. The unterminated bandwidth (when R_FB= ∞) is

approximately 80 MHz.

+

–

V

OUT

V

IN

R

FB

R

=

IN

1 + 4.5

Figure 75. Input Configurations

7

6

5

4

3

2

1

0

Each output can drive external loads as low as 100 Ω in addition

to the 100 Ω input impedance of the VGA (200 Ω differential).

Capacitive loading up to 10 pF is permissible. All loads should

be ac-coupled. Typically, Pin LOP output is used as a single-

ended driver for auxiliary circuits, such as those used for

Doppler ultrasound imaging, and Pin LON drives R_FB.

Alternatively, a differential external circuit can be driven from

the two outputs in addition to the active feedback termination.

In both cases, important stability considerations discussed in

the Applications section should be carefully observed.

INCLUDES NOISE OF VGA

RESISTIVE TERMINATION

(R = R

)

S

IN

ACTIVE IMPEDANCE MATCH

UNTERMINATED

The impedance at each LNA output is 5 Ω. A 0.4 dB reduction

in open-circuit gain results when driving the VGA, and 0.8 dB

with an additional 100 Ω load at the output. The differential

gain of the LNA is 6 dB higher. If the load is less than 200 Ω on

either side, a compensating load is recommended on the

opposite output.

SIMULATION

50 100

1k

R

(Ω)

S

Figure 76. Noise Figure vs. R_Sfor Resistive,

Active Matched and Unterminated Inputs

7

6

5

4

3

2

1

0

INCLUDES NOISE OF VGA

LNA Noise

The input-referred voltage noise sets an important limit on

system performance. The short-circuit input voltage noise of

the LNA is 0.74 nV/√Hz or 0.82 nV/√Hz (at maximum gain),

including the VGA noise. The open-circuit current noise is

2.5 pA/√Hz. These measurements, taken without a feedback

resistor, provide the basis for calculating the input noise and

noise figure performance of the configurations in Figure 75.

Figure 76 and Figure 77 are simulations extracted from these

results, and the 4.1 dB NF measurement with the input actively

matched to a 50 Ω source. Unterminated (R_FB= ∞) operation

exhibits the lowest equivalent input noise and noise figure.

Figure 76 shows the noise figure vs. source resistance, rising at

low R_S, where the LNA voltage noise is large compared to the

source noise, and again at high R_Sdue to current noise. The

VGA’s input-referred voltage noise of 2.7 nV/√Hz is included in

all of the curves.

R

= 50Ω

= 75Ω

IN

R

IN

R

= 100Ω

IN

R

= 200Ω

IN

R

= ∞

FB

SIMULATION

50 100

1k

R

(Ω)

S

Figure 77. Noise Figure vs. R_Sfor Various Fixed Values of R_IN, Actively Matched

Rev. E | Page 26 of 40

AD8331/AD8332/AD8334

The primary purpose of input impedance matching is to

improve the system transient response. With resistive termination,

the input noise increases due to the thermal noise of the

matching resistor and the increased contribution of the LNA’s

input voltage noise generator. With active impedance matching,

however, the contributions of both are smaller than they would

be for resistive termination by a factor of 1/(1 + LNA Gain).

Figure 76 shows their relative noise figure (NF) performance. In

this graph, the input impedance was swept with R_Sto preserve

the match at each point. The noise figures for a source impedance

of 50 ꢀ are 7.1 dB, 4.1 dB, and 2.5 dB, respectively, for the

resistive, active, and unterminated configurations. The noise

figures for 200 ꢀ are 4.6 dB, 2.0 dB, and 1.0 dB, respectively.

X-AMP VGA

The input of the VGA is a differential R-2R ladder attenuator

network with 6 dB steps per stage and a net input impedance of

200 Ω differential. The ladder is driven by a fully differential

input signal from the LNA and is not intended for single-ended

operation. LNA outputs are ac-coupled to reduce offset and

isolate their common-mode voltage. The VGA inputs are biased

through the ladder’s center tap connection to VCM, which is

typically set to 2.5 V and is bypassed externally to provide a

clean ac ground.

The signal level at successive stages in the input attenuator

falls from 0 dB to −48 dB in 6 dB steps. The input stages of the

X-AMP are distributed along the ladder, and a biasing interpolator,

controlled by the gain interface, determines the input tap point.

With overlapping bias currents, signals from successive taps

merge to provide a smooth attenuation range from 0 dB to

−48 dB. This circuit technique results in excellent, linear-in-dB

gain law conformance and low distortion levels and deviates

0.2 dB or less from the ideal. The gain slope is monotonic with

respect to the control voltage and is stable with variations in

process, temperature, and supply.

Figure 77 is a plot of the NF vs. R_Sfor various values of R_IN,

which is helpful for design purposes. The plateau in the NF for

actively matched inputs mitigates source impedance variations.

For comparison purposes, a preamp with a gain of 19 dB and

noise spectral density of 1.0 nV/√Hz, combined with a VGA

with 3.75 nV/√Hz, yields a noise figure degradation of

approximately 1.5 dB (for most input impedances), significantly

worse than the AD8332 performance.

The equivalent input noise of the LNA is the same for single-

ended and differential output applications. The LNA noise figure

improves to 3.5 dB at 50 Ω without VGA noise, but this is

exclusive of noise contributions from other external circuits

connected to LOP. A series output resistor is usually

recommended for stability purposes when driving external

circuits on a separate board (see the Applications section). In

low noise applications, a ferrite bead is even more desirable.

The X-AMP inputs are part of a gain-of-12 feedback amplifier

that completes the VGA. Its bandwidth is 150 MHz. The input

stage is designed to reduce feedthrough to the output and to

ensure excellent frequency response uniformity across gain

setting (see Figure 12 and Figure 13).

Gain Control

Position along the VGA attenuator is controlled by a single-

ended analog control voltage, V_GAIN, with an input range of

40 mV to 1.0 V. The gain control scaling is trimmed to a slope

of 50 dB/V (20 mV/dB). Values of V_GAINbeyond the control

range saturate to minimum or maximum gain values. Both

channels of the AD8332 are controlled from a single gain

interface to preserve matching. Gain can be calculated using

Equation 1 and Equation 2.

VARIABLE GAIN AMPLIFIER

The differential X-AMP VGA provides precise input

attenuation and interpolation. It has a low input-referred noise

of 2.7 nV/√Hz and excellent gain linearity. A simplified block

diagram is shown in Figure 78.

GAIN

GAIN INTERPOLATOR

(BOTH CHANNELS)

POSTAMP

+

Gain accuracy is very good because both the scaling factor and

absolute gain are factory trimmed. The overall accuracy relative

to the theoretical gain expression is 1 dB for variations in

temperature, process, supply voltage, interpolator gain ripple,

trim errors, and tester limits. The gain error relative to a best-fit

line for a given set of conditions is typically 0.2 dB. Gain

matching between channels is better than 0.1 dB (Figure 11

shows gain errors in the center of the control range). When

g

m

6dB

R

VIP

VIN

48dB

2R

V_GAIN< 0.1 or > 0.95, gain errors are slightly greater.

–

POSTAMP

Figure 78. Simplified VGA Schematic

Rev. E | Page 2ꢀ of 40

AD8331/AD8332/AD8334

signal. A transformer can be used with single-ended applications

when low noise is desired.

The gain slope can be inverted, as shown in Figure 73 (available

in most versions). The gain drops with a slope of −50 dB/V

across the gain control range from maximum to minimum gain.

This slope is useful in applications, such as automatic gain

control, where the control voltage is proportional to the

measured output signal amplitude. The inverse gain mode is

selected by setting the MODE pin HI.

Gain control noise is a concern in very low noise applications.

Thermal noise in the gain control interface can modulate the

channel gain. The resultant noise is proportional to the output

signal level and usually only evident when a large signal is

present. Its effect is observable only in LO gain mode, where the

noise floor is substantially lower. The gain interface includes an

on-chip noise filter, which reduces this effect significantly at

frequencies above 5 MHz. Care should be taken to minimize

noise impinging at the GAIN input. An external RC filter can be

used to remove V_GAINsource noise. The filter bandwidth should be

sufficient to accommodate the desired control bandwidth.

Gain control response time is less than 750 ns to settle within 10%

of the final value for a change from minimum to maximum gain.

VGA Noise

In a typical application, a VGA compresses a wide dynamic

range input signal to within the input span of an ADC. While

the input-referred noise of the LNA limits the minimum

resolvable input signal, the output-referred noise, which

depends primarily on the VGA, limits the maximum

instantaneous dynamic range that can be processed at any one

particular gain control voltage. This limit is set in accordance

with the quantization noise floor of the ADC.

Common-Mode Biasing

An internal bias network connected to a midsupply voltage

establishes common-mode voltages in the VGA and postamp.

An externally bypassed buffer maintains the voltage. The bypass

capacitors form an important ac ground connection, because

the VCM network makes a number of important connections

internally, including the center tap of the VGA’s differential

input attenuator, the feedback network of the VGA’s fixed gain

amplifier, and the feedback network of the postamplifier in both

gain settings. For best results, use a 1 nF and a 0.1 μF capacitor

in parallel, with the 1 nF nearest to the VCM pin. Separate

VCM pins are provided for each channel. For dc-coupling to a

3 V ADC, the output common-mode voltage is adjusted to

1.5 V by biasing the VCM pin.

Output and input-referred noise as a function of V_GAINare

plotted in Figure 25 and Figure 27 for the short-circuited input

conditions. The input noise voltage is simply equal to the output

noise divided by the measured gain at each point in the control

range.

The output-referred noise is flat over most of the gain range,

because it is dominated by the fixed output-referred noise of the

VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz

in HI gain mode. At the high end of the gain control range, the

noise of the LNA and source prevail. The input-referred noise

reaches its minimum value near the maximum gain control

voltage, where the input-referred contribution of the VGA

becomes very small.

POSTAMPLIFIER

The final stage has a selectable gain of 3.5 dB (×1.5) or 15.5 dB

(×6), set by the logic pin, HILO. Figure 79 is a simplified block

diagram.

Gm2

+

At lower gains, the input-referred noise, and thus noise figure,

increases as the gain decreases. The instantaneous dynamic

range of the system is not lost, however, because the input

capacity increases with it. The contribution of the ADC noise

floor has the same dependence as well. The important

relationship is the magnitude of the VGA output noise floor

relative to that of the ADC.

VOH

Gm1

F2

VCM

F1

Gm2

With its low output-referred noise levels, these devices ideally

drive low voltage ADCs. The converter noise floor drops 12 dB

for every 2 bits of resolution and drops at lower input full-scale

voltages and higher sampling rates. ADC quantization noise is

discussed in the Applications section.

VOL

–

Gm1

Figure 79. Postamplifier Block Diagram

Separate feedback attenuators implement the two gain settings.

These are selected in conjunction with an appropriately scaled

input stage to maintain a constant 3 dB bandwidth between the

two gain modes (~150 MHz). The slew rate is 1200 V/μs in HI

gain mode and 300 V/μs in LO gain mode. The feedback

networks for HI and LO gain modes are factory trimmed to

adjust the absolute gains of each channel.

The preceding noise performance discussion applies to a

differential VGA output signal. Although the LNA noise

performance is the same in single-ended and differential

applications, the VGA performance is not. The noise of the

VGA is significantly higher in single-ended usage, because the

contribution of its bias noise is designed to cancel in the differential

Rev. E | Page 28 of 40

AD8331/AD8332/AD8334

Noise

Output clamping can be used for ADC input overload

The topology of the postamplifier provides constant input-

referred noise with the two gain settings and variable

output-referred noise. The output-referred noise in HI gain

mode increases (with gain) by four. This setting is recommended

when driving converters with higher noise floors. The extra gain

boosts the output signal levels and noise floor appropriately. When

driving circuits with lower input noise floors, the LO gain mode

optimizes the output dynamic range.

protection, if needed, or postamp overload protection when

operating from a lower common-mode level, such as 1.5 V. The

user should be aware that distortion products increase as output

levels approach the clamping levels, and the user should adjust

the clamp resistor accordingly. For additional information, see

the Applications section.

The accuracy of the clamping levels is approximately 5% in LO

or HI mode. Figure 80 illustrates the output characteristics for a

Although the quantization noise floor of an ADC depends on a

number of factors, the 48 nV/√Hz and 178 nV/√Hz levels are

well suited to the average requirements of most 12-bit and 10-bit

converters, respectively. An additional technique, described in

the Applications section, can extend the noise floor even lower

for possible use with 14-bit ADCs.

few values of R_CLMP

.

5.0

4.5

R

= ∞

CLMP

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

8.8kΩ

3.5kΩ

Output Clamping

R

= 1.86kΩ

CLMP

Outputs are internally limited to a level of 4.5 V p-p differential

when operating at a 2.5 V common-mode voltage. The postamp

implements an optional output clamp engaged through a

resistor from R_CLMPto ground. Table 8 shows a list of

recommended resistor values.

3.5kΩ

8.8kΩ

R

= ∞

CLMP

–3

–2

–1

0

1

2

3

V

(V)

INH

Figure 80. Output Clamping Characteristics

Rev. E | Page 29 of 40

AD8331/AD8332/AD8334

APPLICATIONS

LNA—EXTERNAL COMPONENTS

C

LMD

0.1µF

LNA

SOURCE

FB

The LMD pin (connected to the bias circuitry) must be bypassed to

ground and signal sourced to the INH pin capacitively coupled

using 2.2 nF to 0.1 ꢁF capacitors (see Figure 81).

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

0.1µF

LMD2

INH2

LMD1

INH1

C

*

SH

5V

C

*

FB

5V

3

VPS2

LON2

LOP2

VPS1

LON1

LOP1

COM1

VIP1

The unterminated input impedance of the LNA is 6 kꢀ. The

user can synthesize any LNA input resistance between 50 ꢀ and

6 kꢀ. R_FBis calculated according to Equation 6 or selected from

Table 7.

R

*

FB

1nF

LNA OUT

0.1µF

4

5

6

COM2

VIP2

33 kꢀ ×

(

R_IN

)

7

R_FB

=

(6)

0.1µF

6 kꢀ –

(

R_IN

)

0.1µF

1nF

8

VIN2

VIN1

Table 7. LNA External Component Values for Common

Source Impedances

9

V

VCM2

GAIN

RCLMP

VOH2

VOL2

COMM

GAIN

VCM1

HILO

ENB

1nF

5V

0.1µF

1nF

10

11

12

13

14

R_IN(Ω)

R_FB(Nearest STD 1% Value, Ω)

C_SH(pF)

70

280

22

5V

ꢀ7

412

12

0.1µF

1nF

*

VGA OUT

VOH1

100

200

700

6 k

762

8

1.2

None

1.13 k

3.01 k

∞

VOL1

VPSV

5V

1nF

0.1µF

*SEE TEXT

Figure 81. Basic Connections for a Typical Channel (AD8332 Shown)

When active input termination is used, a decoupling capacitor

(C_FB) is required to isolate the input and output bias voltages of

the LNA.

LNA

DECOUPLING

RESISTOR

TO EXT

CIRCUIT

R

FB

The shunt input capacitor, C_SH, reduces gain peaking at higher

frequencies where the active termination match is lost due to

the gain roll-off of the LNA at high frequencies. The value of

VIP

5Ω

50Ω

LON

100Ω

VCM

C_SHdiminishes as R_INincreases to 500 Ω, at which point no

LNA

capacitor is required. Suggested values for C_SHfor 50 Ω ≤ R_IN

≤

C

SH

LOP

5Ω

200 Ω are shown in Table 7.

VIN

When a long trace to Pin INH is unavoidable, or if both LNA

LNA

TO EXT

CIRCUIT

outputs drive external circuits, a small ferrite bead (FB) in series

with Pin INH preserves circuit stability with negligible effect on

noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or

equivalent). Other values can prove useful.

DECOUPLING

RESISTOR

Figure 82. Interconnections of the LNA and VGA

Both LNA outputs are available for driving external circuits.

Pin LOP should be used in those instances when a single-ended

LNA output is required. The user should be aware of stray

capacitance loading of the LNA outputs, in particular LON. The

LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is

routed to a remote PC board, it tolerates a load capacitance up

to 100 pF with the addition of a 49.9 Ω series resistor or ferrite

75 Ω/100 MHz bead.

Figure 82 shows the interconnection details of the LNA output.

Capacitive coupling between the LNA outputs and the VGA

inputs is required because of the differences in their dc levels

and the need to eliminate the offset of the LNA. Capacitor

values of 0.1 μF are recommended. There is 0.4 dB loss in gain

between the LNA output and the VGA input due to the 5 Ω

output resistance. Additional loading at the LOP and LON

outputs affect LNA gain.

Gain Input

The GAIN pin is common to both channels of the AD8332. The

input impedance is nominally 10 MΩ and a bypass capacitor

from 100 pF to1 nF is recommended.

Rev. E | Page 30 of 40

AD8331/AD8332/AD8334

Optional Output Voltage Limiting

Parallel connected devices can be driven by a common voltage

source or DAC. Decoupling should take into account any

bandwidth considerations of the drive waveform, using the total

distributed capacitance.

The RCLMP pin provides the user with a means to limit the

output voltage swing when used with loads that have no

provisions for prevention of input overdrive. The peak-to-peak

limited voltage is adjusted by a resistor to ground, and Table 8

lists several voltage levels and the corresponding resistor value.

Unconnected, the default limiting level is 4.5 V p-p.

If gain control noise in LO gain mode becomes a factor,

maintaining ≤15 nV/√Hz noise at the GAIN pin ensures

satisfactory noise performance. Internal noise prevails below

15 nV/√Hz at the GAIN pin. Gain control noise is negligible in

HI gain mode.

Note that third harmonic distortion increases as waveform

amplitudes approach clipping. For lowest distortion, the clamp

level should be set higher than the converter input span. A

clamp level of 1.5 V p-p is recommended for a 1 V p-p linear

output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for

a 0.5 V p-p operation. The best solution is determined

experimentally. Figure 84 shows third harmonic distortion

as a function of the limiting level for a 2 V p-p output signal.

A wider limiting level is desirable in HI gain mode.

VCM Input

The common-mode voltage of Pin VCM, Pin VOL, and Pin VOH

defaults to 2.5 V dc. With output ac-coupled applications, the

VCM pin is unterminated; however, it must still be bypassed in

close proximity for ac grounding of internal circuitry. The VGA

outputs can be dc connected to a differential load, such as an

ADC. Common-mode output voltage levels between 1.5 V and

3.5 V can be realized at Pin VOH and Pin VOL by applying the

desired voltage at Pin VCM. DC-coupled operation is not

recommended when driving loads on a separate PC board.

–20

V

= 0.75V

GAIN

–30

–40

–50

–60

–70

–80

The voltage on the VCM pin is sourced by an internal buffer

with an output impedance of 30 Ω and a 2 mA default output

current (see Figure 83). If the VCM pin is driven from an

external source, its output impedance should be <<30 Ω and its

current drive capability should be >>2 mA. If the VCM pins of

several devices are connected in parallel, the external buffer

should be capable of overcoming their collective output currents.

When a common-mode voltage other than 2.5 V is used, a

voltage-limiting resistor, R_CLMP, is needed to protect against

overload.

HILO = LO

HILO = HI

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

CLAMP LIMIT LEVEL (V p-p)

Figure 84. HD3 vs. Clamping Level for 2 V p-p Differential Input

INTERNAL

CIRCUITRY

2mA MAX

Table 8. Clamp Resistor Values

R

<< 30Ω

NEW V

CM

O

VCM

30Ω

Clamp Resistor Value (kΩ)

Clamp Level (V p-p)

HILO = LO

1.21

2.ꢀ4

4.ꢀ7

ꢀ.7

HILO = HI

100pF

0.1µF

0.7

1.0

1.7

2.0

2.7

3.0

3.7

4.0

4.4

AC GROUNDING FOR

INTERNAL CIRCUITRY

2.21

4.02

6.49

9.73

14.ꢀ

23.2

39.2

ꢀ3.2

Figure 83. VCM Interface

Logic Inputs—ENB, MODE, and HILO

11

The input impedance of all enable pins is nominally 25 kΩ and

can be pulled up to 5 V (a pull-up resistor is recommended) or

driven by any 3 V or 5 V logic families. The enable pin, ENB,

powers down the VGA—when pulled low, the VGA output

voltages are near ground. Multiple devices can be driven from a

common source. Consult Table 3, Table 4, Table 5, and Table 6

for circuit functions controlled by the enable pins.

16.9

26.ꢀ

49.9

100

Pin HILO is compatible with 3 V or 5 V CMOS logic families. It

is either connected to ground or pulled up to 5 V, depending on

the desired gain range and output noise.

Rev. E | Page 31 of 40

AD8331/AD8332/AD8334

4V p-p DIFF,

48nV/ Hz

2V p-p DIFF,

24nV/ Hz

Output Decoupling

When driving capacitive loads greater than about 10 pF, or long

circuit connections on other boards, an output network of

resistors and/or ferrite beads can be useful to ensure stability.

These components can be incorporated into a Nyquist filter

such as the one shown in Figure 81. In Figure 81, the resistor

value is 84.5 Ω. The AD8332-EVAL incorporates 100 ꢀ in

parallel with a 120 nH bead. Lower value resistors are permissible

for applications with nearby loads or with gains less than 40 dB.

The exact values of these components can be selected empirically.

187Ω

VOH

VOL

ADC

AD6644

374Ω

2:1

LPF

187Ω

Figure 86. Adjusting the Noise Floor for 14-Bit ADCs

OVERLOAD

These devices respond gracefully to large signals that overload

its input stage and to normal signals that overload the VGA

when the gain is set unexpectedly high. Each stage is designed

for clean-limited overload waveforms and fast recovery when

gain setting or input amplitude is reduced.

An antialiasing noise filter is typically used with an ADC. Filter

requirements are application dependent.

When the ADC resides on a separate board, the majority of

filter components should be placed nearby to suppress noise

picked up between boards and to mitigate charge kickback from

the ADC inputs. Any series resistance beyond that required for

output stability should be placed on the ADC board. Figure 85

shows a second-order, low-pass filter with a bandwidth of

20 MHz. The capacitor is chosen in conjunction with the 10 pF

input capacitance of the ADC.

Signals larger than 275 mV at the LNA input are clipped to

5 V p-p differential prior to the input of the VGA. Figure 48

shows the response to a 1 V p-p input burst. The symmetric

overload waveform is important for applications, such as CW

Doppler ultrasound, where the spectrum of the LNA outputs

during overload is critical. The input stage is also designed to

accommodate signals as high as 2.5 V without triggering the

slow-settling ESD input protection diodes.

OPTIONAL

BACKPLANE

Both stages of the VGA are susceptible to overload. Postamp

limiting is more common and results in the clean-limited

output characteristics found in Figure 49. Recovery is fast in all

cases. The graph in Figure 87 summarizes the combinations of

input signal and gain that lead to the different types of overload.

0.1µF

1.5µH

84.5Ω

158Ω

18pF

ADC

Figure 85. 20 MHz Second-Order, Low-Pass Filter

POSTAMP

OVERLOAD

X-AMP

OVERLOAD

POSTAMP

OVERLOAD

X-AMP

OVERLOAD

DRIVING ADCs

15mV 25mV

4mV

25mV

43.5

56.5

The output drive accommodates a wide range of ADCs. The

noise floor requirements of the VGA depend on a number of

application factors, including bit resolution, sampling rate, full-

scale voltage, and the bandwidth of the noise/antialias filter. The

output noise floor and gain range can be adjusted by selecting

HI or LO gain mode.

41dB

29dB

24.5dB

LO GAIN

MODE

HI GAIN

MODE

The relative noise and distortion performance of the two gain

modes can be compared in Figure 25 and Figure 31 through

Figure 41. The 48 nV/√Hz noise floor of the LO gain mode is

suited to converters with higher sampling rates or resolutions

(such as 12 bits). Both gain modes can accommodate ADC full-

scale voltages as high as 4 V p-p. Because distortion performance

remains favorable for output voltages as high as 4 V p-p (see

Figure 36), it is possible to lower the output-referred noise even

further by using a resistive attenuator (or transformer) at the

output. The circuit in Figure 86 has an output full-scale range of

2 V p-p, a gain range of −10.5 dB to +37.5 dB, and an output

noise floor of 24 nV/√Hz, making it suitable for some 14-bit

ADC applications.

–4.5

1m

7.5

1m

10m

0.1 0.275

1

10m

0.1 0.275

1

INPUT AMPLITUDE (V)

Figure 87. Overload Gain and Signal Conditions

The previously mentioned clamp interface controls the

maximum output swing of the postamp and its overload

response. When the clamp feature is not used, the output level

defaults to approximately 4.5 V p-p differential centered at

2.5 V common mode. When other common-mode levels are set

through the VCM pin, the value of R_CLMPshould be selected for

graceful overload. A value of 8.3 kΩ or less is recommended for

1.5 V or 3.5 V common-mode levels (7.2 kΩ for HI gain mode).

This limits the output swing to just above 2 V p-p differential.

Rev. E | Page 32 of 40

AD8331/AD8332/AD8334

OPTIONAL INPUT OVERLOAD PROTECTION

MULTIPLE INPUT MATCHING

Applications in which high transients are applied to the LNA

input can benefit from the use of clamp diodes. A pair of back-

to-back Schottky diodes can reduce these transients to manageable

levels. Figure 88 illustrates how such a diode-protection scheme

can be connected.

Matching of multiple sources with dissimilar impedances can be

accomplished as shown in Figure 90. A relay and low supply

voltage analog switch can be used to select between multiple

sources and their associated feedback resistors. An ADG736

dual SPDT switch is shown in this example; however, multiple

switches are also available and users are referred to the Analog

Devices Selection Guide for switches and multiplexers.

OPTIONAL

SCHOTTKY

COMM 20

OVERLOAD

CLAMP

0.1µF

FB

2

INH

ENBL 19

DISABLING THE LNA

C

R

3

FB

SH

3

4

Where accessible, connection of the LNA enable pin to ground

powers down the LNA, resulting in a current reduction of about

half. In this mode, the LNA input and output pins can be left

unconnected; however, the power must be connected to all the

supply pins for the disabling circuit to function. Figure 89

illustrates the connections using an AD8331 as an example.

VPSL

LON

R

C

FB

SH

2

1

BAS40-04

Figure 88. Input Overload Clamping

When selecting overload protection, the important parameters

are forward and reverse voltages and t_rr(or τ_rr). The Infineon

BAS40-04 series shown in Figure 88 has a τ_rrof 100 ps and V_Fof

310 mV at 1 mA. Many variations of these specifications can be

found in vendor catalogs.

1

20

19

18

17

16

15

14

13

12

11

NC

COMM

LMD

AD8331

2

NC

INH

ENBL

ENBV

COMM

VOL

C

FB

0.018µF

LAYOUT, GROUNDING, AND BYPASSING

5V

3

VPSL

LON

LOP

COML

VIP

5V

Due to their excellent high frequency characteristics, these

devices are sensitive to their PCB environment. Realizing

expected performance requires attention to detail critical to

good high speed board design.

4

NC

A multilayer board with power and ground planes is

5

recommended with blank areas in the signal layers filled with

ground plane. Be certain that the power and ground pins

provided for robust power distribution to the device are

connected. Decouple the power supply pins with surface-mount

capacitors as close as possible to each pin to minimize impedance

paths to ground. Decouple the LNA power pins from the VGA

supply using ferrite beads. Together with the capacitors, ferrite

beads eliminate undesired high frequencies without reducing

the headroom. Use a larger value capacitor for every 10 chips to

20 chips to decouple residual low frequency noise. To minimize

voltage drops, use a 5 V regulator for the VGA array.

VOUT

6

VOH

0.1µF

7

VPOS

5V

VIN

0.1µF

8

HILO

RCLMP

VCM

VIN

HILO

Several critical LNA areas require special care. The LON and

LOP output traces must be as short as possible before connecting to

the coupling capacitors connected to Pin VIN and Pin VIP. R_FB

must be placed near the LON pin as well. Resistors must be

placed as close as possible to the VGA output pins, VOL and

VOH, to mitigate loading effects of connecting traces. Values

are discussed in the Output Decoupling section.

9

MODE

R

CLMP

10

GAIN

VCM

Figure 89. Disabling the LNA

Signal traces must be short and direct to avoid parasitic effects.

Wherever there are complementary signals, symmetrical layout

should be employed to maintain waveform balance. PCB traces

should be kept adjacent when running differential signals over a

long distance.

Rev. E | Page 33 of 40

AD8331/AD8332/AD8334

ADG736

Using the EVAL-AD8332/AD9238 evaluation board and a high

speed ADC FIFO evaluation kit connected to a laptop, an FFT

can be performed on the AD8332. With the on-board clock of

20 MHz, minimal low-pass filtering, and both channels driven

with a 1 MHz filtered sine wave, the THD is −75 dB, noise floor

is −93 dB, and HD2 is −83 dB.

1.13kΩ

SELECT R

FB

280Ω

LON

LOP

18nF

5Ω

200Ω

50Ω

INH

HIGH DENSITY QUAD LAYOUT

LNA

LMD

The AD8334 is the ideal solution for applications with limited

board space. Figure 94 represents four channels routed to and

away from this very compact quad VGA. Note that none of the

signal paths crosses and that all four channels are spaced apart

to eliminate crosstalk.

5Ω

0.1µF

AD8332

Figure 90. Accommodating Multiple Sources

ULTRASOUND TGC APPLICATION

In this example, all of the components shown are 0402 size;

however, the same layout is executable at the expense of slightly

more board area. The sketch also assumes that both sides of the

printed circuit board are available for components, and that the

bypass and power supply decoupling circuitry is located on the

wiring side of the board.

The AD8332 ideally meets the requirements of medical and

industrial ultrasound applications. The TGC amplifier is a key

subsystem in such applications, because it provides the means

for echolocation of reflected ultrasound energy.

Figure 91 through Figure 93 are schematics of a dual, fully

differential system using the AD8332 and the AD9238, 12-bit

high speed ADC with conversion speeds as high as 65 MSPS.

Rev. E | Page 34 of 40

AD8331/AD8332/AD8334

S3

E

IN2

TP5

AD8332ARU

C50

0.1µF

1

28

27

26

LMD1

LMD2

C49

TP6

C70

0.1µF

L12

120nH FB

L13

120nH FB

C60

0.1µF

TP3

2

3

S1

IN1

(RED)

+5V

INH1

INH2

E

C79

TB1

+5V

C80

22pF

JP5

IN2

JP6

IN1

22pF

CFB2

18nF

CFB1

18nF

+5VLNA

+

C46

1µF

TP4

(BLACK)

VPS1

LON1

LOP1

COM1

VIP1

VPS2

LON2

LOP2

COM2

VIP2

RFB1

274Ω

C41

C74

1nF

+5VLNA

RFB2

274Ω

0.1µF

TB2

GND

L7

4

25

24

23

22

21

20

19

120nH FB

+5VGA

5

L6

120nH FB

+5VLNA

C42

0.1µF

C59

0.1µF

6

C51

0.1µF

C53

0.1µF

7

VCM1

8

VIN2

VIN1

VCM1

JP13

C78

1nF

C48

0.1µF

9

VCM2

GAIN

RCLMP

VOH2

VOL2

COM

VCM1

HILO

ENB

C43

0.1µF

C77

1nF

+5VGA

10

HI GAIN

JP10

TP2 GAIN

TP7 GND

C83

1nF

+5VGA

LO GAIN

ENABLE

18

11

12

JP16

R3

C68

1nF

C69

0.1µF

DISABLE

(R

)

CLMP

17

16

15

VOH1

VOL1

VPSV

JP8

DC2H

R27

100Ω

R24

100Ω

JP9

OPTIONAL 4-POLE LOW-PASS

FILTER

OPTIONAL 4-POLE LOW-PASS

FILTER

13

14

C58

0.1µF

L19

L17

SAT

L11

120nH FB

L9

120nH FB

L1

C54

0.1µF

L15

SAT

V

+B

SAT

V +A

IN

C64

SAT

C65

SAT

JP17

C67

SAT

C66

SAT

C55

0.1µF

JP12

L20

SAT

L10

120nH FB

C56

0.1µF

L18

SAT

L14

SAT

L16

SAT

L8

120nF FB

V

–A

–B

IN

JP7

DC2L

R26

100Ω

R25

100Ω

+5VGA

C45

0.1µF

C85

1nF

JP10

Figure 91. Schematic, TGC, VGA Section Using an AD8332 and AD9238

Rev. E | Page 37 of 40

AD8331/AD8332/AD8334

VR1

+3.3VAVDD

ADP3339AKC-3.3

L5

120nH FB

C44

1µF

+5V

+

C22

0.1µF

C21

1nF

C31

0.1µF

3

2

1

ADCLK

IN OUT GND

L4

R11

C2

10µF

6.3V

+

120nH FB

100Ω

JP2

R10

1

2

64

63

62

61

60

59

58

57

56

55

AGND

VIN+_A

AVDD

0Ω

SHARED

REF

Y

R5

OUT

TAB

C30

33Ω

0.1µF

V

+_A

CLK_A

IN

C61

18pF

L3

120nH FB

N

3

VIN–_A SHARED_REF

–_A

IN

R14

4.7kΩ

R6

33Ω

4

C29

0.1µF

R4

AGND

AVDD

REFT_A

REFB_A

VREF

MUX_SELECT

PDWN_A

OEB_A

OTR_A

D11_A (MSB)

D10_A

D9_A

R12

1.5kΩ

+3.3VADDIG

C17

C18

1nF

1.5kΩ

R15

0Ω

5

0.1µF

C33

10µF

6.3V

L2

120nH FB

C35

0.1µF

6

+

C40

0.1µF

C52

C1

0.1µF

10nF

7

OTR_A

C36

0.1µF

TP9

+

8

D11_A

D10_A

D9_A

VREF

C12

10µF

6.3V

C32

9

0.1µF

C34

10µF

6.3V

SENSE

REFB_B

REFT_B

AVDD

AGND

VIN–_B

VIN+_B

AGND

AVDD

CLK_B

DCS

C38

0.1µF

10

C57

10nF

C39

10µF

11

12

13

14

15

16

54

53

D8_A

C37

0.1µF

+3.3VADDIG

DRGND

DRVDD

D7_A

C23

0.1µF

C25

1nF

C16

0.1µF

C15

1nF

1.5kΩ

52

51

50

49

R8

33Ω

V

–B

IN

D7_A

D6_A

D5_A

D4_A

D3_A

D2_A

D1_A

D0_A

DNC

C62

18pF

D6_A

+B

IN

R7

33Ω

+3.3VCLK

D5_A

R18

499Ω

17

18

19

20

48

47

46

45

44

43

S2

D4_A

C63

C20

0.1µF

C19

1nF

EXT CLOCK

0.1µF

R16

5kΩ

D3_A

R17

49.9Ω

D2_A

R19

499Ω

JP3

JP11

DFS

D1_A

R20

4.7kΩ

R41

4.7kΩ

21

22

PDWN_B

OEB_B

DNC

D0_A

DNC

+3.3VCLK

ADCLK

TP 12

23

24

25

26

27

28

29

42

41

40

39

38

37

36

DNC

C47

10µF

6.3V

+

C86

0.1µF

ADCLK

DNC

DRVDD

DRGND

OTR_B

D11_B (MSB)

D10_B

D9_B

C11

10µF

6.3V

+

C13

1nF

C14

0.1µF

U5

74VHC04

U5

74VHC04

EXT

3

D0_B

D1_B

D2_B

D0_B

R9

0Ω

4

1

V

OE

3

5

4

1

9

2

DD

20MHz

OUT

JP4

D1_B

OTR_B

D11_B

D10_B

D9_B

2

3

1

INT

D2_B

GND

TP 13

DATA

CLK

2

U5

74VHC04

U5

74VHC04

DRGND

DRVDD

D3_B

3

U6

SG-636PCE

6

8

1

JP1

2

D3_B

D4_B

D5_B

30

31

32

35

34

33

D8_B

U5

D4_B

D7_B

74VHC04

13

12

D5_B

D6_B

SPARES

11

10

+3.3VADDIG

U5

74VHC04

C24

1nF

C26

0.1µF

Figure 92. Converter Schematic, TGC Using an AD8332 and AD9238

Rev. E | Page 36 of 40

AD8331/AD8332/AD8334

R40

1

20

10

18

17

16

15

14

13

12

22Ω

U10

74VHC541

GND

DATACLKA

G1

G2

A1

A2

A3

A4

A5

A6

A7

A8

VCC

+3.3VDVDD

+

C3

0.1µF

C28

10µF

6.3V

19

2

4

1

3

22 × 4

RP 1

1

8

2

3

4

5

6

7

8

22 × 4

8

1

2

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

RP 9

7

2

3

4

1

7

6

5

8

6

5

OTR_A

D11_A

D10_A

D9_A

3

4

1

6

5

8

7

10

12

14

16

9

8

22 × 4

RP2

11

13

15

22 × 4

RP 10

7

2

3

4

2

3

4

1

2

7

6

5

8

7

D8_A

6

5

D7_A

9

11

18

20

22

24

26

28

30

32

34

36

38

40

17

19

21

23

25

27

29

31

33

35

37

39

D6_A

22 × 4

RP 3

3

4

1

2

6

5

8

7

+3.3VDVDD

1

20

10

18

17

U7

74VHC541

G1

G2

A1

A2

A3

A4

A5

A6

VCC

+

22 × 4

RP 4

C76

10µF

6.3V

C8

0.1µF

C10

0.1µF

19

GND

8

1

2

3

4

1

2

3

22 × 4

D5_A

D4_A

D3_A

D2_A

D1_A

D0_A

Y1

Y2

Y3

Y4

Y5

Y6

3

4

6

5

RP 11

7

6

5

4

5

6

7

8

9

16

15

14

13

12

11

8

22 × 4

RP 12

7

2

3

4

6

5

DNC

A7

A8

Y7

Y8

SAM080UPM

+3.3VDVDD

1

20

10

18

17

16

15

14

13

12

11

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

U2

74VHC541

G1

G2

A1

A2

A3

A4

A5

VCC

GND

Y1

+

C27

C7

C9

0.1µF

19

1

22 × 4

RP 13

8

10µF

6.3V

0.1µF

22 × 4

RP 5

2

3

4

7

6

5

2

3

4

5

6

7

8

9

1

2

3

4

8

7

6

5

8

OTR_B

D11_B

D10_B

D9_B

Y2

Y3

22 × 4

RP 14

1

2

8

7

Y4

1

2

3

4

22 × 4

RP 6

D8_B

Y5

7

6

5

3

6

D7_B

A6

A7

A8

Y6

Y7

Y8

4

1

5

8

D6_B

D5_B

22 × 4

1

2

3

4

1

8

7

6

5

8

22 × 4

RP 7

+3.3VDVDD

1

20

10

RP 15

G1

G2

A1

A2

A3

A4

A5

A6

A7

A8

U3 VCC

74VHC541

+

C75

C4

0.1µF

C5

0.1µF

C6

0.1µF

19

10µF

6.3V

GND

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

22 × 4

RP 8

2

3

4

1

7

6

5

8

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

D4_B

D3_B

D2_B

D1_B

D0_B

DNC

2

3

4

7

6

5

74

76

78

80

73

75

77

79

22 × 4

RP 16

2

3

4

7

6

5

SAM080UPM

DNC

R39

22Ω

DATACLK

Figure 93. Interface Schematic, TGC Using an AD8332 and AD9238

Rev. E | Page 3ꢀ of 40

AD8331/AD8332/AD8334

CH 1 LNA INPUT

64

63

62 61

60

59

58 57

56

55

54

53

52

51

50 49

CH 2 LNA INPUT

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

INH2

COM12

VOH1

VOL1

VPS12

VOL2

VOH2

COM12

MODE

NC

2

LMD2

CH 1 DIFFERENTIAL

OUTPUT

3

COM2X

4

LON2

5

LOP2

6

CH 2 DIFFERENTIAL

OUTPUT

VIP2

7

VIN2

AD8334

POWER SUPPLY DECOUPLING

LOCATED ON WIRING SIDE

8

VPS2

9

VPS3

10

COM34

VOH3

VOL3

VPS34

VOL4

VOH4

COM34

VIN3

11

CH 3 DIFFERENTIAL

OUTPUT

VIP3

12

LOP3

13

LON3

14

COM3X

CH 4 DIFFERENTIAL

OUTPUT

15

LMD3

16

33

INH3

CH 3 LNA INPUT

21

29

17

18

19

20

22

23

24

25

26 27

28

30

31

32

CH 4 LNA INPUT

Figure 94. Signal Path and Board Layout for AD8334

Rev. E | Page 38 of 40

AD8331/AD8332/AD8334

OUTLINE DIMENSIONS

0.345

0.341

0.337

9.80

9.70

9.60

20

1

11

28

15

0.158

0.154

0.150

4.50

4.40

4.30

0.244

0.236

0.228

10

6.40 BSC

PIN 1

1

14

PIN 1

0.065

0.049

0.069

0.053

0.65

BSC

1.20 MAX

0.15

0.05

8°

0°

0.010

0.004

8°

0°

0.75

0.60

0.45

0.025

BSC

0.012

0.008

0.30

0.19

SEATING

PLANE

0.050

0.016

0.20

0.09

0.010

0.006

SEATING

PLANE

COPLANARITY

0.10

COPLANARITY

0.004

COMPLIANT TO JEDEC STANDARDS MO-137-AD

COMPLIANT TO JEDEC STANDARDS MO-153-AE

Figure 96. 20-Lead Shrink Small Outline Package [QSOP]

(RQ-20)

Figure 95. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in Inches

Dimensions shown in millimeters

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

3.25

3.10 SQ

2.95

EXPOSED

PAD

(BOTTOM VIEW)

4.75

BSC SQ

0.50

0.40

0.30

17

16

8

9

0.25 MIN

0.80 MAX

0.65 TYP

3.50 REF

12° MAX

THE EXPOSE PAD IS NOT CONNECTED

INTERNALLY. FOR INCREASED RELIABILITY

OF THE SOLDER JOINTS AND MAXIMUM

THERMAL CAPABILITY IT IS RECOMMENDED

THAT THE PAD BE SOLDERED TO

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

THE GROUND PLANE.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 97. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

Rev. E | Page 39 of 40

AD8331/AD8332/AD8334

0.30

0.25

0.18

9.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

64

49

48

1

PIN 1

INDICATOR

*

4.85

4.70 SQ

4.55

8.75

BSC SQ

TOP

VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.45

0.40

0.35

33

32

16

17

7.50

REF

THE EXPOSE PAD IS NOT CONNECTED

INTERNALLY. FOR INCREASED RELIABILITY

OF THE SOLDER JOINTS AND MAXIMUM

THERMAL CAPABILITY IT IS RECOMMENDED

THAT THE PAD BE SOLDERED TO

0.80 MAX

0.65 TYP

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

THE GROUND PLANE.

SEATING

PLANE

0.50 BSC

0.20 REF

*

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

EXCEPT FOR EXPOSED PAD DIMENSION

Figure 98. 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

9 mm × 9 mm Body, Very Thin Quad

(CP-64-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD8331ARQ

AD8331ARQ-REEL

AD8331ARQ-REELꢀ

AD8331ARQZ¹

AD8331ARQZ-RL¹

AD8331ARQZ-Rꢀ¹

AD8331-EVAL

Temperature Range

Package Description

Package Option

RQ-20

–40°C to +87°C

20-Lead Shrink Small Outline Package (QSOP)

Evaluation Board with AD8331ARQ

RQ-20

AD8332ACP-R2

AD8332ACP-REEL

AD8332ACP-REELꢀ

AD8332ACPZ-Rꢀ¹

AD8332ACPZ-RL¹

AD8332ARU

AD8332ARU-REEL

AD8332ARU-REELꢀ

AD8332ARUZ¹

–40°C to +87°C

32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

28-Lead Thin Shrink Small Outline Package (TSSOP)

Evaluation Board with AD8332ARU

CP-32-2

RU-28

AD8332ARUZ-Rꢀ¹

AD8332ARUZ-RL¹

AD8332-EVAL

RU-28

EVAL-AD8332/AD9238

AD8334ACPZ-WP¹

AD8334ACPZ-REEL¹

AD8334ACPZ-REELꢀ¹

AD8334-EVAL

Evaluation Board with AD8332ARU and AD9238 ADC

64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

Evaluation Board with AD8334ACP

–40°C to +87°C

CP-64-1

¹Z = Pb-free part.

registered trademarks are the property of their respective owners.

C03199-0-4/06(E)

Rev. E | Page 40 of 40


型号：	AD8331ARQZ-RL
厂家：	ADI
描述：	Ultralow Noise VGAs with Preamplifier and Programmable RIN 超低噪声可变增益放大器与前置放大器和可编程RIN 消费电路商用集成电路放大器光电二极管
文件：	总40页 (文件大小：876K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD8331ARQZ-RL [ADI]

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