AD8331 [ADI]
Ultralow Noise VGAs with Preamplifier and Programmable RIN; 超低噪声可变增益放大器与前置放大器和可编程RIN
| 型号： | AD8331 |
| 厂家： | 
ADI |
| 描述： | Ultralow Noise VGAs with Preamplifier and Programmable RIN |
| 文件： | 总32页 (文件大小：482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Noise VGAs with
Preamplifier and Programmable RIN
AD8331/AD8332
FUNCTIONAL BLOCK DIAGRAM
FEATURES
LON1 LOP1
25 24
VIP1 VIN1
22 21
VPSV
15
VCM1
20
VCM2
9
HILO
19
Ultralow noise preamplifier
VPS1
26
23
Voltage noise = 0.74 nV/√Hz
Current noise = 2.5 pA/√Hz
V
MID
COM1
3.5dB/15.5dB
[(–48 to 0) + 21] dB
+19dB
3 dB bandwidth: 120 MHz
17 VOH1
16 VOL1
–
+
INH1 27
POST
AMP1
VGA 1
Low power: 125 mW/channel
Wide gain range with programmable postamp
–4.5 dB to +43.5 dB
LNA 1
–
28
LMD1
+
BIAS
(V
BIAS AND
INTERPOLATOR
GAIN
INT
10 GAIN
13 VOL2
)
MID
+7.5 dB to +55.5 dB
+
1
–
LMD2
Low output-referred noise: 48 nV/√Hz typical
Active input impedance matching
Optimized for 10-/12-bit ADCs
Selectable output clamping level
Single 5 V supply operation
POST
AMP2
VGA 2
–
LNA 2
+
2
3
INH2
12
VOH2
VPS2
CLAMP
COM2
6
4
5
7
8
14
18
11
LON2 LOP2
VIP2 VIN2
COMM
ENB
RCLMP
Available in space-saving chip scale package
Figure 1. AD8332 Shown 28-Lead TSSOP
APPLICATIONS
50
40
V
= 1V
GAIN
Ultrasound and sonar time-gain control
High performance AGC systems
I/Q signal processing
0.8V
30
0.6V
High speed dual ADC driver
20
0.4V
0.2V
GENERAL DESCRIPTION
10
The AD8331/AD8332 are single- and dual-channel ultralow
noise, linear-in-dB, variable gain amplifiers. Although optimized
for ultrasound systems, they are usable as low noise variable
gain elements at frequencies up to 120 MHz.
0
0V
–10
–20
100k
1M
10M
FREQUENCY (Hz)
100M
1G
Each channel consists of an ultralow noise preamplifier (LNA),
an X-AMP® VGA with 48 dB of gain range, and a selectable gain
postamplifier with adjustable output limiting. The LNA gain is
19 dB with a single-ended input and differential outputs capable
of accurate, programmable active input impedance matching by
selecting an external feedback resistor. Active impedance
control optimizes noise performance for applications that
benefit from input matching.
Figure 2. Frequency Response vs. Gain
The VGA’s low output-referred noise is advantageous in driving
high speed differential ADCs. The gain of the postamplifier may
be pin selected to 3.5 dB or 15.5 dB to optimize gain range and
output noise for 12-bit or 10-bit converter applications. The
output may be limited to a user-selected clamping level,
preventing input overload to a subsequent ADC. An external
resistor adjusts the clamping level.
The 48 dB gain range of the VGA makes these devices suitable
for a variety of applications. Excellent bandwidth uniformity is
maintained across the entire range. The gain control interface
provides precise linear-in-dB scaling of 50 dB/V for control
voltages between 40 mV and 1 V. Factory trim ensures excellent
part-to-part and channel-to-channel gain matching. Differential
signal paths lead to superb second and third order distortion
performance and low crosstalk.
The operating temperature range is –40°C to +85°. The
AD8331 is available in a 20-lead QSOP package, and the
AD8332 in 28-lead TSSOP and 32-lead LFCSP packages. They
require a single 5 V supply, and the quiescent power
consumption is 125 mW/ch. A power-down (enable) pin is
provided.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD8331/AD8332
LNA – External Components................................................... 22
Driving ADCs ............................................................................. 24
Overload...................................................................................... 24
Optional Input Overload Protection. ...................................... 25
Layout, Grounding, And Bypassing ......................................... 25
Multiple Input Matching ........................................................... 25
Disabling the LNA...................................................................... 25
Measurement Considerations................................................... 26
Ultrasound TGC Application ................................................... 26
Pin Configuration and Function Descriptions........................... 30
AD8331........................................................................................ 30
AD8332........................................................................................ 31
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
TABLE OF CONTENTS
REVISION HISTORY.................................................................. 2
AD8331, AD8332—Specifications.................................................. 3
Absolute Maximum Ratings............................................................ 6
ESD CAUTION ............................................................................ 6
AD8331, AD8332—Typical Performance Characteristics .......... 7
Test Circuits..................................................................................... 15
Theory of Operation ...................................................................... 17
Overview...................................................................................... 17
Low Noise Amplifier (LNA)...................................................... 17
Variable Gain Amplifier............................................................. 19
Postamplifier ............................................................................... 21
Applications..................................................................................... 22
REVISION HISTORY
Revision C
11/03—Data Sheet Changed from REV. B to REV. C
Addition of New Part...........................................................Universal
Changes to Figures ...............................................................Universal
Updated Outline Dimensions..........................................................32
5/03—Data Sheet Changed from REV. A to REV. B
Edits to Ordering Guide....................................................................32
Edits to Ultrasound TGC Application section................................25
Added Figure 71, Figure 72, and Figure 73......................................26
Updated Outline Dimensions............................................................31
2/03—Data Sheet Changed from REV. 0 to REV. A
Edits to Ordering Guide.....................................................................32
Rev. C | Page 2 of 32
AD8331/AD8332
AD8331, AD8332—SPECIFICATIONS
Table 1. TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF,
VCM pin floating, –4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.
Parameter
Conditions
Min
Typ
Max Unit
LNA CHARACTERISTICS
Gain
Single-Ended Input
to Differential Output
19
dB
Input to Output (Single-Ended)
AC-Coupled
RFB = 280 Ω
13
2ꢀ7
70
dB
mV
Ω
Input Voltage Range
Input Resistance
RFB = 412 Ω
ꢀ7
Ω
RFB = 762 Ω
RFB = 1.13 kΩ
RFB = ∞
100
200
6
13
7
Ω
Ω
kΩ
pF
Ω
MHz
V/µs
Input Capacitance
Output Impedance
–3 dB Small Signal Bandwidth
Slew Rate
Single-Ended, Either Output
VOUT = 0.2 V p-p
130
670
Input Voltage Noise
RS = 0 Ω, HI or LO Gain,
RFB = ∞, f = 7 MHz
RFB = ∞, HI or LO Gain, f = 7 MHz
f = 10 MHz, LOP Output
RS = RIN = 70 Ω
0.ꢀ4
2.7
nV/√Hz
pA/√Hz
Input Current Noise
Noise Figure
Active Termination Match
Unterminated
3.ꢀ
2.7
dB
dB
RS = 70 Ω, RFB = ∞
Harmonic Distortion @ LOP1 or LOP2
HD2
VOUT = 0.7 V p-p,
Single-Ended, f = 10 MHz
–76
–ꢀ0
167
dBc
dBc
mA
HD3
Output Short-Circuit Current
LNA + VGA CHARACTERISTICS
–3 dB Small Signal Bandwidth
–3 dB Large Signal Bandwidth
Slew Rate
Pins LON, LOP
VOUT = 0.2 V p-p
VOUT = 2 V p-p
LO Gain
120
110
300
MHz
MHz
V/µs
V/µs
HI Gain
1200
Input Voltage Noise
RS = 0 Ω, HI or LO Gain,
0.82
nV/√Hz
R
FB = ∞, f = 7 MHz
Noise Figure
VGAIN = 1.0 V
Active Termination Match
RS = RIN = 70 Ω,
f = 10 MHz, Measured
RS = RIN = 200 Ω,
f = 7 MHz, Simulated
RS = 70 Ω, RFB = ∞,
f = 10 MHz, Measured
RS = 200 Ω, RFB = ∞,
f = 7 MHz, Simulated
4.17
2.0
dB
dB
dB
dB
Unterminated
2.7
1.0
Output-Referred Noise
VGAIN = 0.7 V, LO Gain
48
1ꢀ8
1
nV/√Hz
nV/√Hz
Ω
V
GAIN = 0.7 V, HI Gain
Output Impedance, Postamplifier
Output Signal Range, Postamplifier
DC to 1 MHz
RL ≥ 700 Ω,
Unclamped, Either Pin
VCM 1.127
4.7
V
Differential
V p-p
Output Offset Voltage
Differential
Common-Mode
Output Short-Circuit Current
VGAIN = 0.7 V
–70
–127
7
–27
47
+70
+100
mV
mV
mA
Rev. C | Page 3 of 32
AD8331/AD8332
Parameter
Conditions
Min
Typ
Max Unit
dBc
Harmonic Distortion
VGAIN = 0.7 V, VOUT = 1 V p-p
HD2
HD3
HD2
HD3
–88
–87
–68
–67
ꢀ
–80
–ꢀ2
38
f = 1 MHz
dBc
dBc
dBc
dBm1
dBc
dBc
dBm
dBm
f = 10 MHz
Input 1 dB Compression Point
Two-Tone Intermodulation
Distortion (IMD3)
VGAIN = 0.27 V, VOUT = 1 V p-p, f = 1 MHz–10 MHz
VGAIN = 0.ꢀ2 V, VOUT = 1 V p-p, f = 1 MHz
VGAIN = 0.7 V, VOUT = 1 V p-p, f = 10 MHz
VGAIN = 0.7 V, VOUT = 1 V p-p, f = 1 MHz
Output Third Order Intercept
V
GAIN = 0.7 V, VOUT = 1 V p-p, f = 10 MHz
33
Channel-to-Channel Crosstalk
(AD8332)
V
GAIN = 0.7 V, VOUT = 1 V p-p, f = 1 MHz
–84
dB
Overload Recovery
VGAIN = 1.0 V,
VIN = 70 mV p-p/1 V p-p,
f = 10 MHz
7
2
ns
ns
Group Delay Variation
ACCURACY
Absolute Gain Error2
7 MHz < f < 70 MHz, Full Gain Range
0.07 V < VGAIN < 0.10 V
0.10 V < VGAIN < 0.97 V
0.97 V < VGAIN < 1.0 V
0.1 V < VGAIN < 0.97 V
0.1 V < VGAIN < 0.97 V
–1
–1
–2
+0.7
0.3
–1
0.2
0.1
+2
+1
+1
dB
dB
dB
dB
dB
Gain Law Conformance3
Channel-to-Channel Gain Matching
GAIN CONTROL INTERFACE
(Pin GAIN)
Gain Scaling Factor
Gain Range
0.10 V < VGAIN < 0.97 V
LO Gain
HI Gain
70
–4.7 to +43.7
+ꢀ.7 to +77.7
0 to 1.0
10
dB/V
dB
dB
V
MΩ
ns
Input Voltage (VGAIN) Range
Input Impedance
Response Time
48 dB Gain Change to 90% Full Scale
ꢀ70
COMMON-MODE INTERFACE
(Pin VCMn)
Input Resistance
Output CM Offset Voltage
Voltage Range
Current Limited to 1 mA
VCM = 2.7 V
30
–27
Ω
mV
–127
+100
V
OUT = 2.0 V p-p
1.7 to 3.7
V
ENABLE INTERFACE
(Pins ENB, ENBL, ENBV)
Logic Level to Enable Power
Logic Level to Disable Power
Input Resistance
2.27
0
7
1.0
V
V
Pin ENB
Pin ENBL
Pin ENBV
VINH = 30 mV p-p
27
40
ꢀ0
300
4
kΩ
kΩ
kΩ
µs
ms
Power-Up Response Time
V
INH = 170 mV p-p
HILO GAIN RANGE INTERFACE
(Pin HILO)
Logic Level to Select HI Gain Range
Logic Level to Select LO Gain Range
Input Resistance
2.27
0
7
1.0
V
V
kΩ
70
1 All dBm values are referred to 70 Ω, unless otherwise noted.
2 Conformance to theoretical gain expression (see Equation 1).
3 Conformance to best fit dB linear curve.
Rev. C | Page 4 of 32
AD8331/AD8332
Parameter
Conditions
Min
Typ
Max Unit
OUTPUT CLAMP INTERFACE
(Pin RCLMP; HI or LO Gain)
Accuracy
HILO = LO
HILO = HI
RCLMP = 2.ꢀ4 kΩ, VOUT = 1 V p-p (Clamped)
RCLMP = 2.21 kΩ, VOUT = 1 V p-p (Clamped)
70
ꢀ7
mV
mV
MODE INTERFACE
(Pin MODE)
Logic Level for Positive Gain Slope
Logic Level for Negative Gain Slope
Input Resistance
0
2.27
1.0
7
V
V
kΩ
200
POWER SUPPLY
(Pins VPS1, VPS2, VPSV, VPSL, VPOS)
Supply Voltage
4.7
7.0
27
127
7.7
V
mA
mW
Quiescent Current per Channel
Power Dissipation per channel
Disable Current
No Signal
AD8332 (VGA and LNA)
AD8331 (VGA and LNA)
AD8332 (ENBL)
AD8332 (ENBV)
AD8331 (ENBL)
300
240
12
13
11
600
400
µA
µA
Each Channel
Each Channel
mA
mA
mA
mA
dB
AD8331 (ENBV)
PSRR
14
–68
VGAIN = 0, f = 100 kHz
Rev. C | Page 7 of 32
AD8331/AD8332
ABSOLUTE MAXIMUM RATINGS
Table 2. Absolute Maximum Ratings
Parameter
Rating
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Voltage
Supply Voltage (VPSn, VPSV, VPSL, VPOS)
Input Voltage (INHn)
ENB, ENBL, ENBV, HILO Voltage
GAIN Voltage
7.7 V
VS + 200 mV
VS + 200 mV
2.7 V
Power Dissipation
RU-28 Package (AD8332)4
CP-32 Package (AD8332)7
RQ-20 Package (AD8331)4
Temperature
0.96 W
1.9ꢀ W
0.ꢀ8 W
Operating Temperature
Storage Temperature
Lead Temperature (Soldering 60 sec)
θJA
–40°C to +87°C
–67°C to +170°C
300°C
RU-28 Package (AD8332)4
CP-32 Package (AD8332)7
RQ-20 Package (AD8331)4
θJC
68°C/W
33°C/W
83°C/W
RU-28 Package (AD8332)4
CP-32 Package (AD8332)7
RQ-20 Package (AD8331)4
14°C/W
33°C/W
n/a
4 Four-Layer JEDEC Board (2S2P).
7 Exposed pad soldered to board, nine thermal vias in pad — JEDEC 4-Layer
Board J-STD-71-9.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 6 of 32
AD8331/AD8332
AD8331, AD8332—TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM = 2.5 V,
–4.5 dB to +43.5 dB gain (HILO = LO), and differential signal voltage, unless otherwise specified.
60
50
40
30
20
10
0
50
40
30
20
10
SAMPLE SIZE = 80 UNITS
= 0.5V
V
GAIN
HILO = HI
MODE = HI
(AC PACKAGE
ONLY)
MODE = LO
HILO = LO
–10
0
0
0.2
0.4
0.6
(V)
0.8
1.0 1.1
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
V
GAIN
GAIN ERROR (dB)
Figure 3. Gain vs. VGAIN and MODE (MODE Available on AC Package)
Figure 6. Gain Error Histogram
2.0
25
20
15
10
5
SAMPLE SIZE = 50 UNITS
V = 0.2V
1.5
1.0
GAIN
+25°C
–40°C
0.5
0
0
25
20
15
10
5
–0.5
V
= 0.7V
GAIN
+85°C
–1.0
–1.5
–2.0
0
0
0.2
0.4
0.6
(V)
0.8
1.0 1.1
V
GAIN
CHANNEL-TO-CHANNEL GAIN MATCH (dB)
Figure 4. Absolute Gain Error vs. VGAIN at Three Temperatures
Figure 7. Gain Match Histogram for VGAIN = 0.2 V and 0.7 V
2.0
50
1.5
1.0
V
= 1V
GAIN
40
0.8V
30
0.5
10MHz
0.6V
1MHz
0
20
0.4V
0.2V
–0.5
10
30MHz
70MHz
–1.0
–1.5
–2.0
0
0V
–10
–20
0
0.2
0.4
0.6
(V)
0.8
1.0 1.1
V
GAIN
100k
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 5. Absolute Gain Error vs. VGAIN at Various Frequencies
Figure 8. Frequency Response for Various Values of VGAIN
Rev. C | Page ꢀ of 32
AD8331/AD8332
60
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
V
= 1V
GAIN
V
= 1 V p-p
OUT
50
40
0.8V
0.6V
0.4V
30
20
10
V
= 1V
0.2V
0V
GAIN
0.9V
0.7V
0.4V
0
0.5V
–10
100k
1M
10M
FREQUENCY (Hz)
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 9. Frequency Response for Various Values of VGAIN, HILO = HI
Figure 12. Channel-to-Channel Crosstalk vs.
Frequency for Various Values of VGAIN
30
50
45
40
35
30
25
20
15
10
V
= 0.5 V
GAIN
0.1µF
COUPLING
R
= R = 50Ω, 75Ω, 100Ω
S
IN
20
10
R
= R = 1kΩ
IN
S
R
= R = 500Ω
S
IN
0
R
= R = 200Ω
IN
S
–10
–20
–30
–40
1µF
COUPLING
5
0
1M
10M
100M
1G
100k
100k
1M
10M
FREQUENCY (Hz)
100M
FREQUENCY (Hz)
Figure 13. Group Delay vs. Frequency
Figure 10. Frequency Response for Various Matched Source Impedances
20
10
30
T = –40°C
HI GAIN
T = +85°C
V
R
= 0.5V
GAIN
= ∞
T = +25°C
FB
T = +25°C
20
10
0
–10
–20
T = +85°C
T = –40°C
0
20
10
–10
–20
–30
–40
LO GAIN
T = +85°C
T = –40°C
0
T = +25°C
T = –40°C
–10
–20
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
(V)
100k
1M
10M
100M
1G
FREQUENCY (Hz)
V
GAIN
Figure 11. Frequency Response, Unterminated, RS = 50 Ω
Figure 14. Representative Differential Output Offset Voltage vs. VGAIN at Three
Temperatures
Rev. C | Page 8 of 32
AD8331/AD8332
50j
35
30
25
20
15
10
5
SAMPLE SIZE = 100
0.2V < V < 0.7V
100j
25j
GAIN
f = 100kHz
R
R
= 50Ω
= 270
IN
,
Ω
FB
R
R
= 75Ω,
IN
= 412
Ω
FB
R
R
= 100
Ω
,
IN
= 549
Ω
FB
17
Ω
0
Ω
R
R
= 200
= 1.1k
Ω
Ω
,
IN
FB
0
49.6 49.7 49.8 49.9 50.0 50.1 50.2 50.3 50.4 50.5
GAIN SCALING FACTOR
R
R
= 6kΩ,
IN
=
∞
FB
–25j
–100j
Figure 15. Gain Scaling Factor Histogram
–50j
Figure 18. Smith Chart, S11 vs. Frequency, 0.1 MHz to 200 MHz
for Various Values of RFB
100
10
1
SINGLE ENDED, PIN VOH OR VOL
R
= ∞
L
20
RIN = 50
Ω
Ω
, 75
Ω
,
AND 100
15
10
RIN = 200
Ω
5
RIN = 1k
Ω
RIN = 200
Ω
RIN = 500
Ω
0
–5
–10
–15
–20
0.1
100k
1M
10M
FREQUENCY (Hz)
100M
100k
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 16. Output Impedance vs. Frequency
Figure 19. LNA Frequency Response,
Single-Ended, for Various Values of RIN
10k
1k
R
= ∞, C = 0pF
SH
FB
20
15
R
R
= 6.65kΩ, C = 0pF
SH
FB
10
R
= ∞
= 3.01kΩ, C = 0pF
SH
FB
FB
5
R
= 1.1kΩ, C = 1.2pF
SH
FB
0
R
= 549Ω, C = 8.2pF
FB
SH
100
–5
R
R
= 412Ω, C = 12pF
–10
–15
–20
FB
FB
SH
= 270Ω, C = 22pF
SH
10
100k
1M
10M
100M
FREQUENCY (Hz)
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 17. LNA Input Impedance vs. Frequency for
Various Values of RFB and CSH
Figure 20. LNA Frequency Response, Unterminated, Single-Ended
Rev. C | Page 9 of 32
AD8331/AD8332
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
500
R
= 0, R = ∞,
FB
= 1V, f = 10MHz
S
f = 10MHz
V
GAIN
400
300
200
100
0
HILO = HI
HILO = LO
–50
–30
–10
10
30
50
70
90
0
0.2
0.4
0.6
0.8
1.0
TEMPERATURE (°C)
V
(V)
GAIN
Figure 24. Short-Circuit Input-Referred Noise vs. Temperature
Figure 21. Output-Referred Noise vs. VGAIN
10
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
R
= 0, R = ∞, V = 1V
FB GAIN
S
f = 5MHz, R
=
∞, V
= 1V
GAIN
FB
HILO = LO OR HI
1.0
R
= THERMAL NOISE ALONE
S
0.1
1
10
100
1k
100k
1M
10M
FREQUENCY (Hz)
100M
SOURCE RESISTANCE (
Ω
)
Figure 22. Short-Circuit Input-Referred Noise vs. Frequency
Figure 25. Input-Referred Noise vs. RS
100
7
6
5
4
3
2
1
0
INCLUDES NOISE OF VGA
R
= 0, R = ∞,
FB
S
HILO = LO OR HI, f = 10MHz
R
= 50Ω
10
IN
75Ω
100Ω
200Ω
1
R
= ∞
FB
SIMULATION
100
0.1
50
1k
0
0.2
0.4
0.6
(V)
0.8
1.0
SOURCE RESISTANCE (Ω)
V
GAIN
Figure 26. Noise Figure vs. RS for Various Values of RIN
Figure 23. Short-Circuit Input-Referred Noise vs. VGAIN
Rev. C | Page 10 of 32
AD8331/AD8332
50
45
40
35
30
25
20
15
10
5
–30
–40
–50
–60
–70
–80
–90
–100
f = 10MHz
= 1V p-p
f = 10MHz, R = 50Ω
S
V
OUT
HILO = LO,
HD3
HILO = LO, R = 50Ω
IN
HILO = HI, R = 50Ω
IN
HILO = LO,
HD2
HILO = LO, R = ∞
FB
HILO = HI,
HD2
HILO = HI,
HD3
HILO = HI, R = ∞
FB
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
0
200 400 600 800 1.0k 1.2k 1.4k 1.6k 1.8k 2.0k
(Ω)
V
(V)
R
GAIN
LOAD
Figure 27. Noise Figure vs. VGAIN
Figure 30. Harmonic Distortion vs. RLOAD
30
25
20
15
10
5
–40
–50
–60
–70
–80
–90
–100
f = 10MHz
= 1V p-p
V
OUT
HILO = HI, R = 50Ω
IN
HILO = HI, R = ∞
FB
HILO = HI,
HD2
HILO = LO,
HD3
HILO = LO, R = 50Ω
IN
HILO = HI,
HD3
HILO = LO,
HD2
HILO = LO, R = ∞
FB
f = 10MHz, R = 50Ω
S
0
10
15
20
25
30
35
40
45
50
55
60
0
10
20
30
(pF)
40
50
GAIN (dB)
C
LOAD
Figure 28. Noise Figure vs. Gain
Figure 31. Harmonic Distortion vs. CLOAD
0
–40
–50
–60
–70
–80
–90
–100
f = 10MHz
G = 30dB
–10
GAIN = 30 dB
V
= 1V
OUT
P-P
HILO = HI,
HD3
–20
–30
–40
–50
–60
–70
–80
–90
–100
HILO = LO,
HD3
HILO = LO,
HD3
HILO = LO,
HD2
HILO = HI,
HD2
HILO = LO,
HD2
HILO = HI,
HD2
HILO = HI,
HD3
1M
10M
FREQUENCY (Hz)
100M
0
1
2
3
4
V
(V p-p)
OUT
Figure 29. Harmonic Distortion vs. Frequency
Figure 32. Harmonic Distortion vs. Differential Output Voltage
Rev. C | Page 11 of 32
AD8331/AD8332
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
V
= 1V p-p COMPOSITE (f + f )
OUT
1
2
V
= 1V p-p
OUT
G = 30dB
–20
–40
INPUT RANGE
LIMITED WHEN
HILO = LO
HILO = LO,
HD3
HILO = LO,
HD2
–60
HILO = HI,
HD2
–80
HILO = HI,
HD3
–100
–120
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.0
1.0
10M
100M
1M
V
(V)
FREQUENCY (Hz)
GAIN
Figure 36. IMD3 vs. Frequency
Figure 33. Harmonic Distortion vs. VGAIN, f = 1 MHz
40
35
30
25
20
15
10
5
0
–20
HILO = HI,
1MHz
V
= 1V p-p
OUT
HILO = LO,
10MHz
HILO = LO,
HD2
INPUT RANGE
LIMITED WHEN
HILO = LO
HILO = HI,
10MHz
–40
HILO = LO,
HD3
HILO = LO,
1MHz
–60
V
= 1V p-p COMPOSITE (f + f )
OUT
1
2
–80
HILO = HI,
HD2
HILO = HI,
HD3
–100
–120
0
0
0.5
0.6
0.7
0.8
0.9
1.0
0.1
0.2
0.3
0.4
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
V
(V)
GAIN
V
(V)
GAIN
Figure 37. Output Third Order Intercept vs. VGAIN
Figure 34. Harmonic Distortion vs. VGAIN, f = 10 MHz
10
5
2mV
100
90
f = 10MHz
0
HILO = LO
HILO = HI
–5
–10
–15
–20
–25
–30
10
0
10ns
50mV
Figure 38. Small Signal Pulse Response, G = 30 dB,
Top: Input, Bottom: Output Voltage, HILO = HI or LO
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
V
(V)
GAIN
Figure 35. Input 1 dB Compression vs. VGAIN
Rev. C | Page 12 of 32
AD8331/AD8332
5
4
3
2
1
0
20mV
100
90
HILO = HI
HILO = LO
10
0
10ns
500mV
0
10
20
30
40
50
Figure 39. Large Signal Pulse Response, G = 30 dB,
HILO = HI or LO, Top: Input, Bottom: Output Voltage
R
(kΩ)
CLMP
Figure 42. Clamp Level vs. RCLMP
2
1
0
4
C
= 50pF
= 0pF
G = 30dB
INPUT
L
G = 40dB
3
2
R
= 48.1kΩ
= 7.15kΩ
R
= 16.5kΩ
CLMP
CLMP
C
L
1
0
R
R
= 2.67kΩ
CLMP
CLMP
–1
–2
–3
–4
–1
INPUT IS NOT TO SCALE
–40 –30 –20 –10
–2
0
10 20 30 40
TIME (ns)
50 60
70 80
–10
0
10
20
30
40
50
60
TIME (ns)
Figure 40. Large Signal Pulse Response for
Various Capacitive Loads, CL = 0 pF, 10 pF, 20 pF, 50 pF
Figure 43. Clamp Level Pulse Response
200mV
500mV
100
90
10
0
100ns
200mV
400ns
Figure 44. LNA Overdrive Recovery, VINH 0.05 V p-p to
1 V p-p Burst, VGAIN = 0.27 V, VGA Output Shown
Figure 41. Pin GAIN Transient Response,
Top: VGAIN, Bottom: Output Voltage
Rev. C | Page 13 of 32
AD8331/AD8332
2V
50mV
100
90
10
0
100ns
1V
1ms
Figure 45. VGA Overdrive Recovery, VINH 4 mV p-p to 70 mV p-p Burst,
GAIN = 1 V, VGA Output Shown Attenuated 24 dB
Figure 48. Enable Response, Large Signal,
Top: VENB, Bottom: VOUT, VINH = 150 mV p-p
V
0
–10
–20
–30
–40
–50
–60
–70
–80
50mV
VPS1, V
= 0.5V
GAIN
100
90
VPSV, V
= 0.5V
GAIN
VPS1, V
GAIN
= 0V
10
0
100ns
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 46. VGA Overdrive Recovery, VINH 4 mV p-p to 275 mV p-p Burst,
GAIN = 1 V, VGA Output Shown Attenuated 24 dB
Figure 49. PSRR vs. Frequency (No Bypass Capacitor)
V
60
55
50
V
= 0.5V
GAIN
2V
AD8332
45
40
35
30
25
20
AD8331
40
200mV
1ms
0
20
60
80
100
–40
–20
TEMPERATURE (°C)
Figure 47. Enable Response, Top: VENB, Bottom: VOUT, VINH = 30 mV p-p
Figure 50. Quiescent Supply Current vs. Temperature
Rev. C | Page 14 of 32
AD8331/AD8332
TEST CIRCUITS
NETWORK ANALYZER
50Ω
OUT
50Ω
IN
1.8nF
270Ω
FB*
120nH
237Ω
0.1µF
0.1µF
DUT
INH
LMD
28Ω
1:1
22pF
237Ω
28Ω
0.1µF
0.1µF
*FERRITE BEAD
Figure 51. Gain and Bandwidth Measurements
OSCILLOSCOPE
1.8nF
270Ω
237Ω
FB*
120nH
50Ω
0.1µF
0.1µF
DUT
INH
LMD
IN
28Ω
22pF
1:1
50Ω
237Ω
0.1µF
0.1µF
28Ω
*FERRITE BEAD
Figure 52. Transient Measurements
SPECTRUM
ANALYZER
A
G
B
FB*
120nH
0.1µF
0.1µF
50Ω
0.1µF
49Ω
INH
LMD
IN
1:1
DUT
1Ω
22pF
50Ω
*FERRITE BEAD
0.1µF
Figure 53. Used for Noise Measurements
Rev. C | Page 17 of 32
AD8331/AD8332
SPECTRUM
ANALYZER
1.8nF
270Ω
237Ω
FB*
50Ω
0.1µF
DUT
0.1µF
120nH
INH
IN
28Ω
1:1
22pF
LMD
50Ω
237Ω
28Ω
0.1µF
0.1µF
*FERRITE BEAD
Figure 54. Distortion
NETWORK ANALYZER
50Ω
OUT
50Ω
IN
50Ω
1.8nF
270Ω
FB*
237Ω
0.1µF
DUT
120nH 0.1µF
INH
LMD
50Ω
28Ω
237Ω
1:1
22pF
0.1µF
*FERRITE BEAD
0.1µF
28Ω
Figure 55. S11 Measurements
Rev. C | Page 16 of 32
AD8331/AD8332
THEORY OF OPERATION
60
50
40
30
20
10
0
OVERVIEW
MODE = HI
(WHERE AVAILABLE)
The following discussion applies to all part numbers. Figure 56
and Figure 1 are functional block diagrams of the AD8331 and
AD8332, respectively.
HILO = HI
LON LOP VIP VIN
VPOS
14
VCM
11
HILO
19
4
5
7
8
MODE = LO
3.5dB/
15.5dB
VPSL
3
6
V
MID
AD8331
COML
VGA
15
16
VOH
VOL
2
1
INH
POST
AMP1
HILO = LO
∆
G = –48dB to 0dB
+21dB
LNA
LMD
LNA
BIAS
BIAS AND
INTERPOLATOR
GAIN
INT
CLAMP
9
MODE
–10
(V
)
MID
0
0.2
0.4
0.6
(V)
0.8
1.0 1.1
GAIN 10
V
GAIN
12
20
17
19
18
COMM
COMM ENBL
ENBV
RCLMP
Figure 58. Gain Control Characteristics
Figure 56. Functional Block Diagram — AD8331
When MODE is set high, (where available):
Each channel contains an LNA that provides user-adjustable
input impedance termination, a differential X-AMP VGA, and a
programmable gain postamplifier with adjustable output
voltage limiting. Figure 57 shows a simplified block diagram.
GAIN(dB) = – 50 dB V ×V
+ 45.5 dB, HILO = LO
3
( )
(
)
GAIN
or
GAIN(dB) = – 50 dB V ×V
+ 57.5 dB, HILO = HI
4
( )
(
)
GAIN
LON
VIN
The LNA converts a single-ended input to a differential output
with a voltage gain of 19 dB. When only one output is used, the
gain is 13 dB. The inverting output is used for active input
impedance termination. Each of the LNA outputs is capacitively
coupled to a VGA input. The VGA consists of an attenuator
with a range of 48 dB followed by an amplifier with 21 dB of
gain, for a net gain range of –27 dB to +21 dB. The X-AMP
gain-interpolation technique results in low gain error and
uniform bandwidth, and differential signal paths minimize
distortion.
X-AMP VGA
POSTAMP
PREAMPLIFIER
19dB
[(–48 to 0) + 21] dB
3.5dB/15.5dB
INH
+
VOH
VOL
LNA
–
LMD
VIP
LOP
RCLMP
HILO
BIAS AND
INTERPOLATOR*
BIAS
(V
GAIN
V
CLAMP*
MID
)
MID
INTERFACE*
GAIN
VCM
*SHARED BETWEEN CHANNELS
Figure 57. Simplified Block Diagram
The final stage is a logic programmable amplifier with gains of
3.5 dB or 15.5 dB. The LO and HI gain modes are optimized
for 12-bit and 10-bit A/D converter applications, in terms of
output-referred noise and absolute gain range. Output voltage
limiting may be programmed by the user.
The linear-in-dB gain control interface is trimmed for slope and
absolute accuracy. The overall gain range is 48 dB, extending
from –4.5 dB to +43.5 dB or from +7.5 dB to +55.5 dB,
depending on the setting of the HILO pin. The slope of the gain
control interface is 50 dB/V, and the gain control range is 40 mV
to 1 V, leading to the following expressions for gain:
LOW NOISE AMPLIFIER (LNA)
Good noise performance relies on a proprietary ultralow noise
preamplifier at the beginning of the signal chain, which
minimizes the noise contribution in the following VGA. Active
impedance control optimizes noise performance for
applications that benefit from input matching.
GAIN(dB) = 50
dB V
×VGAIN– 6.5 dB, HILO = LO 1
( )
( )
or
GAIN(dB) = 50
dB V ×VGAIN + 5.5 dB, HILO = HI 2
( )
( )
The gain characteristics are shown in Figure 58.
Rev. C | Page 1ꢀ of 32
AD8331/AD8332
CFB is needed in series with RFB, since the dc levels at Pins LON
and INH are unequal. Expressions for choosing RFB in terms of
RIN and for choosing CFB are found in the Applications section.
CSH and the ferrite bead enhance stability at higher frequencies
where the loop gain declines and prevents peaking. Frequency
response plots of the LNA are shown in Figure 19 and Figure 20.
The bandwidth is approximately 130 MHz for matched input
impedances of 50 Ω to 200 Ω and declines at higher source
impedances. The unterminated bandwidth (RFB = ∞) is
approximately 80 MHz.
A simplified schematic of the LNA is shown in Figure 59. INH
is capacitively coupled to the source. An on-chip bias generator
centers the output dc levels at 2.5 V and the input voltages at
3.25 V. A capacitor CLMD of the same value as the input coupling
capacitor CINH is connected from the LMD pin to ground.
C
FB
R
FB
LOP
VPOS
LON
I
I
0
0
Each output can drive external loads as low as 100 Ω in addition
to the 100 Ω input impedance of the VGA (200 Ω differential).
Capacitive loading up to 10 pF is permissible. All loads should
be ac-coupled. Typically, Pin LOP output is used as a single-
ended driver for auxiliary circuits, such as those used for
Doppler mode ultrasound imaging, and Pin LON drives RFB.
Alternatively, a differential external circuit can be driven from
the two outputs, in addition to the active feedback termination.
In both cases, important stability considerations discussed in
the Applications section should be carefully observed.
C
INH
INH
LMD
Q2
Q1
C
LMD
C
SH
R
S
I
I
0
0
Figure 59. Simplified LNA Schematic
The LNA supports differential output voltages as high as
The impedance at each LNA output is 5 Ω. A 0.4 dB reduction
in open-circuit gain results when driving the VGA, and 0.8 dB
with an additional 100 Ω load at the output. The differential
gain of the LNA is 6 dB higher. If the load is less than 200 Ω on
either side, a compensating load is recommended on the
opposite output.
5 V p-p with positive and negative excursions of 1.25 V, about
a common-mode voltage of 2.5 V. Since the differential gain
magnitude is 9, the maximum input signal before saturation is
275 mV or 550 mV p-p. Overload protection ensures quick
recovery time from large input voltages. Since the inputs are
capacitively coupled to a bias voltage near midsupply, very large
inputs can be handled without interacting with the ESD
protection.
LNA Noise
The input-referred voltage noise sets an important limit on
system performance. The short-circuit input voltage noise of the
LNA is 0.74 nV/√Hz or 0.82 nV/√Hz (at maximum gain),
including the VGA noise. The open-circuit current noise is
2.5 pA/√Hz. These measurements, taken without a feedback
resistor, provide the basis for calculating the input noise and
noise figure performance of the configurations in Figure 60.
Figure 61 and Figure 62 are simulations extracted from these
results, and the 4.1 dB NF measurement with the input actively
matched to a 50 Ω source. Unterminated (RFB = ∞) operation
exhibits the lowest equivalent input noise and noise figure.
Figure 61 shows the noise figure versus source resistance, rising
at low RS, where the LNA voltage noise is large compared to the
source noise, and again at high RS due to current noise. The
VGA’s input-referred voltage noise of 2.7 nV/√Hz is included in
all of the curves.
Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input-
referred voltage noise of 0.74 nV/√Hz. This is achieved with a
modest current consumption of 10 mA per channel (50 mW).
On-chip resistor matching results in precise gains of 4.5 per side
(9 differential), critical for accurate impedance control. The use
of a fully differential topology and negative feedback minimizes
distortion. Low HD2 is particularly important in second
harmonic ultrasound imaging applications. Differential
signaling enables smaller swings at each output, further
reducing third order distortion.
Active Impedance Matching
The LNA supports active impedance matching through an
external shunt feedback resistor from Pin LON to Pin INH. The
input resistance RIN is given by Equation 5, where A is the
single-ended gain of 4.5, and 6 kΩ is the unterminated input
impedance.
6 kΩ × RFB
RFB
1+ A
RIN
=
6 kΩ =
5
( )
33 kΩ + RFB
Rev. C | Page 18 of 32
AD8331/AD8332
UNTERMINATED
The primary purpose of input impedance matching is to
R
IN
improve the system transient response. With resistive
termination, the input noise increases due to the thermal noise
of the matching resistor and the increased contribution of the
LNA’s input voltage noise generator. With active impedance
matching, however, the contributions of both are smaller than
they would be for resistive termination by a factor of 1/(1 +
LNA Gain). Figure 61 shows their relative noise figure (NF)
performance. In this graph, the input impedance has been swept
with RS to preserve the match at each point. The noise figures
for a source impedance of 50 Ω are 7.1 dB, 4.1 dB, and 2.5 dB,
respectively, for the resistive, active, and unterminated
configurations. The noise figures for 200 Ω are 4.6 dB, 2.0 dB,
and 1.0 dB, respectively.
R
S
+
–
V
OUT
V
IN
RESISTIVE TERMINATION
R
IN
R
S
+
–
R
V
S
OUT
V
IN
ACTIVE IMPEDANCE MATCH –R = R
S
IN
R
FB
R
IN
R
S
+
–
V
OUT
V
IN
Figure 62 is a plot of the NF versus RS for various values of RIN,
which is helpful for design purposes. The plateau in the NF for
actively matched inputs mitigates source impedance variations.
For comparison purposes, a preamp with a gain of 19 dB and
noise spectral density of a 1.0 nV/√Hz, combined with a VGA
with 3.75 nV/√Hz, would yield a noise figure degradation of
approximately 1.5 dB (for most input impedances), significantly
worse than the AD8332 performance.
R
FB
R
=
IN
1 + 4.5
Figure 60. Input Configurations
7
6
5
4
3
2
1
0
INCLUDES NOISE OF VGA
RESISTIVE TERMINATION
The equivalent input noise of the LNA is the same for single-
ended and differential output applications. The LNA noise
figure improves to 3.5 dB at 50 Ω without VGA noise, but this
is exclusive of noise contributions from other external circuits
connected to LOP. A series output resistor is usually
recommended for stability purposes, when driving external
circuits on a separate board (see the Applications section). In
low noise applications, a ferrite bead is even more desirable.
(R = R
)
S
IN
ACTIVE IMPEDANCE MATCH
UNTERMINATED
SIMULATION
100
VARIABLE GAIN AMPLIFIER
50
1k
The differential X-AMP VGA provides precise input
attenuation and interpolation. It has a low input-referred noise
of 2.7 nV/√Hz and excellent gain linearity. A simplified block
diagram is shown in Figure 63.
R
(Ω)
S
Figure 61. Noise Figure vs. RS for Resistive,
Active Matched, and Unterminated Inputs
7
6
INCLUDES NOISE OF VGA
GAIN
GAIN INTERPOLATOR
(BOTH CHANNELS)
POST-AMP
5
4
3
2
R
= 50Ω
IN
g
m
6dB
VIP
70Ω
48dB
R
2R
100
Ω
200
Ω
VIN
R
=
∞
FB
1
0
SIMULATION
100
POST-AMP
50
1k
R
(Ω)
S
Figure 63. Simplified VGA Schematic
Figure 62. Noise Figure vs. RS for Various Fixed Values of RIN, Actively Matched
Rev. C | Page 19 of 32
AD8331/AD8332
Gain control response time is less than 750 ns to settle within
10% of the final value for a change from minimum to max-
imum gain.
X-AMP VGA
The input of the VGA is a differential R-2R ladder attenuator
network, with 6 dB steps per stage and a net input impedance of
200 Ω differential. The ladder is driven by a fully differential
input signal from the LNA and is not intended for single-ended
operation. LNA outputs are ac-coupled to reduce offset and
isolate their common-mode voltage. The VGA inputs are biased
through the ladder’s center tap connection to VCM, which is
typically set to 2.5 V and is bypassed externally to provide a
clean ac ground.
VGA Noise
In a typical application, a VGA compresses a wide dynamic
range input signal to within the input span of an ADC. While
the input-referred noise of the LNA limits the minimum
resolvable input signal, the output-referred noise, which
depends primarily on the VGA, limits the maximum
instantaneous dynamic range that can be processed at any one
particular gain control voltage. This limit is set in accordance
with the quantization noise floor of the ADC.
The signal level at successive stages in the input attenuator falls
from 0 dB to –48 dB, in 6 dB steps. The input stages of the
X-AMP are distributed along the ladder, and a biasing interpolator,
controlled by the gain interface, determines the input tap point.
With overlapping bias currents, signals from successive taps merge
to provide a smooth attenuation range from 0 dB to –48 dB. This
circuit technique results in excellent, linear-in-dB gain law
conformance and low distortion levels and deviates 0.2 dB or less
from ideal. The gain slope is monotonic with respect to the control
voltage and is stable with variations in process, temperature, and
supply.
Output and input-referred noise as a function of VGAIN are
plotted in Figure 21 and Figure 23 for the short-circuited input
condition. The input noise voltage is simply equal to the output
noise divided by the measured gain at each point in the control
range.
The output-referred noise is flat over most of the gain range,
since it is dominated by the fixed output-referred noise of the
VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz
in HI gain mode. At the high end of the gain control range, the
noise of the LNA and source prevail. The input-referred noise
reaches its minimum value near the maximum gain control
voltage, where the input-referred contribution of the VGA
becomes very small.
The X-AMP inputs are part of a gain-of-12 feedback amplifier,
which completes the VGA. Its bandwidth is 150 MHz. The input
stage is designed to reduce feedthrough to the output and
ensure excellent frequency response uniformity across gain
setting (see Figure 8 and Figure 9).
At lower gains, the input-referred noise, and thus noise figure,
increases as the gain decreases. The instantaneous dynamic
range of the system is not lost, however, since the input capacity
increases with it. The contribution of the ADC noise floor has
the same dependence as well. The important relationship is
the magnitude of the VGA output noise floor relative to that
of the ADC.
Gain Control
Position along the VGA attenuator is controlled by a single-
ended analog control voltage, VGAIN, with an input range of 40 mV
to 1.0 V. The gain control scaling is trimmed to a slope of 50 dB/V
(20 mV/dB). Values of VGAIN beyond the control range saturate to
minimum or maximum gain values. Both channels of the
AD8332 are controlled from a single gain interface to preserve
matching. Gain can be calculated using Equations 1 and 2.
With its low output-referred noise levels, these devices ideally
drive low-voltage ADCs. The converter noise floor drops 12 dB
for every 2 bits of resolution and drops at lower input full-scale
voltages and higher sampling rates. ADC quantization noise is
discussed in the Applications section.
Gain accuracy is very good since both the scaling factor and
absolute gain are factory trimmed. The overall accuracy relative
to the theoretical gain expression is 1 dB for variations in
temperature, process, supply voltage, interpolator gain ripple, trim
errors, and tester limits. The gain error relative to a best-fit line for
a given set of conditions is typically 0.2 dB. Gain matching
between channels is better than 0.1 dB (see Figure 7, which shows
gain errors in the center of the control range). When VGAIN < 0.1
or > 0.95, gain errors are slightly greater.
The preceding noise performance discussion applies to a
differential VGA output signal. Although the LNA noise
performance is the same in single-ended and differential
applications, the VGA performance is not. The noise of the
VGA is significantly higher in single-ended usage, since the
contribution of its bias noise is designed to cancel in the
differential signal. A transformer can be used with single-ended
applications when low noise is desired.
The gain slope may be inverted, as shown in Figure 58 (avail-
able in most versions). The gain drops with a slope of
–50 dB/V across the gain control range from maximum to
minimum gain. This slope is useful in applications, such as
automatic gain control, where the control voltage is
proportional to the measured output signal amplitude. The
inverse gain mode is selected by setting the MODE pin HI.
Rev. C | Page 20 of 32
AD8331/AD8332
Gm2
Gm1
+
Gain control noise is a concern in very low noise applications.
Thermal noise in the gain control interface can modulate the
channel gain. The resultant noise is proportional to the output
signal level and usually only evident when a large signal is
present. Its effect is observable only in LO gain mode, where the
noise floor is substantially lower. The gain interface includes an
on-chip noise filter, which reduces this effect significantly at
frequencies above 5 MHz. Care should be taken to minimize
noise impinging at the GAIN input. An external RC filter may
be used to remove VGAIN source noise. The filter bandwidth
should be sufficient to accommodate the desired control
bandwidth.
VOH
F2
VCM
F1
Gm2
VOL
–
Gm1
Figure 64. Postamplifier Block Diagram
Common-Mode Biasing
Although the quantization noise floor of an ADC depends on a
number of factors, the 48 nV/√Hz and 178 nV/√Hz levels are
well suited to the average requirements of most 12-bit and
10-bit converters, respectively. An additional technique,
described in the Applications section, can extend the noise floor
even lower for possible use with 14-bit ADCs.
An internal bias network connected to a midsupply voltage
establishes common-mode voltages in the VGA and postamp.
An externally bypassed buffer maintains the voltage. The bypass
capacitors form an important ac ground connection, since the
VCM network makes a number of important connections
internally, including the center tap of the VGA’s differential
input attenuator, the feedback network of the VGA’s fixed gain
amplifier, and the feedback network of the postamplifier in both
gain settings. For best results, use a 1 nF and a 0.1 µF capacitor
in parallel, with the 1 nF nearest to Pin VCM. Separate VCM
pins are provided for each channel. For dc-coupling to a 3 V
ADC, the output common-mode voltage is adjusted to 1.5 V by
biasing the VCM pin.
Output Clamping
Outputs are internally limited to a level of 4.5 V p-p differential
when operating at a 2.5 V common-mode voltage. The postamp
implements an optional output clamp engaged through a
resistor from RCLMP to ground. Table shows a list of
recommended resistor values.
Output clamping can be used for ADC input overload
protection, if needed, or postamp overload protection when
operating from a lower common-mode level, such as 1.5 V. The
user should be aware that distortion products increase as output
levels approach the clamping levels and should adjust the clamp
resistor accordingly. Also, see the Applications section.
POSTAMPLIFIER
The final stage has a selectable gain of 3.5 dB or 15.5 dB, set by
the logic Pin HILO. These correspond to linear gains of 1.5 or 6.
A simplified block diagram of the postamplifier is shown in
Figure 64.
The accuracy of the clamping levels is approximately 5% in LO
or HI mode. Figure 65 illustrates the output characteristics for a
Separate feedback attenuators implement the two gain settings.
These are selected in conjunction with an appropriately scaled
input stage to maintain a constant 3 dB bandwidth between the
two gain modes (~150 MHz). The slew rate is 1200 V/µs in HI
gain mode and 300 V/µs in LO gain mode. The feedback
networks for HI and LO gain modes are factory trimmed to
adjust the absolute gains of each channel.
few values of RCLMP
.
5.0
4.5
R
=
∞
CLMP
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
8.8k
Ω
Ω
3.5k
Noise
R
= 1.86k
Ω
The topology of the postamplifier provides constant input-
referred noise with the two gain settings and variable output-
referred noise. The output-referred noise in HI gain mode
increases (with gain) by four. This setting is recommended
when driving converters with higher noise floors. The extra gain
boosts the output signal levels and noise floor appropriately.
When driving circuits with lower input noise floors, the LO gain
mode optimizes the output dynamic range.
CLMP
–3
–2
–1
0
1
2
3
V
(V)
INH
Figure 65. Output Clamping Characteristics
Rev. C | Page 21 of 32
AD8331/AD8332
C
LMD
0.1µF
LNA
SOURCE
FB
APPLICATIONS
1
2
3
28
27
26
LMD2
LMD1
INH1
0.1µF
LNA – EXTERNAL COMPONENTS
CSH
*
INH2
The LMD pin (connected to the bias circuitry) must be
bypassed to ground, and signal source to the INH pin
capacitively coupled using 2.2 nF to 0.1 μF capacitors (see
Figure 66).
1nF
5V
0.1
CFB
RFB
*
+5V
VPS2
VPS1
*
F
4
5
6
7
8
9
25
24
23
22
21
20
19
18
17
16
LON2
LOP2
COM2
VIP2
LON1
LOP1
COM1
VIP1
LNA OUT
The unterminated input impedance of the LNA is 6 kΩ. The
user may synthesize any LNA input resistance between 50 Ω
and 6 kΩ. RFB is calculated according to Equation 6 or selected
from Table .
1nF
0.1µF
0.1µF
VIN2
VIN1
1nF
VGAIN
VCM2
GAIN
RCLMP
VOH2
VOL2
COMM
VCM1
33 kΩ × R
(
)
IN
1nF
0.1µF
RFB
=
6
( )
10
11
12
6 kΩ – R
HILO
ENB
(
)
5V
5V
IN
1nF
Table 3. LNA External Component Values
for Common Source Impedances
0.1µF
*
*
VOH1
VOL1
VPSV
VGA OUT
VGA OUT
13
14
RIN (Ω) RFB (Nearest STD 1% Value, Ω)
CSH (pF)
22
12
8
1.2
0.1µF
15
70
ꢀ7
100
200
700
6k
280
412
762
1.13k
3.01k
∞
5V
1nF
*
SEE TEXT
Figure 66. Basic Connections for a Typical Channel (AD8332 Shown)
None
None
TO EXT
CIRCUIT
When active input termination is used, a 0.1 µF capacitor (CFB) is
required to isolate the input and output bias voltages of the LNA.
VIP
50Ω
50Ω
5Ω
5Ω
LON
LOP
100Ω
100Ω
VCM
The shunt input capacitor, CSH, reduces gain peaking at higher
frequencies where the active termination match is lost due to
the HF gain roll-off of the LNA. Suggested values are shown in
Table ; for unterminated applications, reduce the capacitor value
by half.
LNA
CSH
VIN
TO EXT
CIRCUIT
When a long trace to Pin INH is unavoidable, or if both LNA
outputs drive external circuits, a small ferrite bead (FB) in series
with Pin INH preserves circuit stability with negligible effect on
noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or
equivalent). Other values may prove useful.
Figure 67. Interconnections of the LNA and VGA
Both LNA outputs are available for driving external circuits. Pin
LOP should be used in those instances when a single-ended
LNA output is required. The user should be aware of stray
capacitance loading of the LNA outputs, in particular LON. The
LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is
routed to a remote PC board, it will tolerate a load capacitance
up to 100 pF with the addition of a 49.9 Ω series resistor or
ferrite 75 Ω/100 MHz bead.
Figure 67 shows the interconnection details of the LNA output.
Capacitive coupling between LNA outputs and the VGA inputs
is required because of differences in their dc levels and to
eliminate the offset of the LNA. Capacitor values of 0.1 µF are
recommended. There is 0.4 dB loss in gain between the LNA
output and the VGA input due to the 5 Ω output resistance.
Additional loading at the LOP and LON outputs will affect
LNA gain.
Rev. C | Page 22 of 32
AD8331/AD8332
Gain Input
Logic Inputs—ENB, MODE, and HILO
Pin GAIN is common to both channels of the AD8332. The
input impedance is nominally 10 MΩ and a bypass capacitor
from 100 pF to1 nF is recommended.
The input impedance of all enable pins is nominally 25 kΩ and
may be pulled up to 5 V (a pull-up resistor is recommended) or
driven by any 3 V or 5 V logic families. The enable pins perform
a power-down function, when disabled, the VGA outputs are
near ground. Multiple devices may be driven from a common
source. Consult the pin-function tables for circuit functions
controlled by the enable pins.
Parallel connected devices may be driven by a common voltage
source or DAC. Decoupling should take into account any
bandwidth considerations of the drive waveform, using the total
distributed capacitance.
Pin HILO is compatible with 3 V or 5 V CMOS logic families. It
is either connected to ground or pulled up to 5 V, depending on
the desired gain range and output noise.
If gain control noise in LO gain mode becomes a factor,
maintaining ≤15 nV/√Hz noise at the GAIN pin will ensure
satisfactory noise performance. Internal noise prevails below
15 nV/√Hz at the GAIN pin. Gain control noise is negligible in
HI gain mode.
Optional Output Voltage Limiting
The RCLMP pin provides the user with a means to limit the
output voltage swing when used with loads that have no
provisions for prevention of input overdrive. The peak-to-peak
limited voltage is adjusted by a resistor to ground, and Table
lists several voltage levels and the corresponding resistor value.
Unconnected, the default limiting level is 4.5 V p-p.
VCM Input
The common-mode voltage of Pins VCM, VOL, and VOH
defaults to 2.5 Vdc. With output ac-coupled applications, the
VCM pin will be unterminated; however, it must still be
bypassed in close proximity for ac grounding of internal
circuitry. The VGA outputs may be dc connected to a
differential load, such as an ADC. Common-mode output
voltage levels between 1.5 V and 3.5 V may be realized at Pins
VOH and VOL by applying the desired voltage at Pin VCM.
DC-coupled operation is not recommended when driving loads
on a separate PC board.
Note that third harmonic distortion will increase as waveform
amplitudes approach clipping. For lowest distortion, the clamp
level should be set higher than the converter input span. A
clamp level of 1.5 V p-p is recommended for a 1 V p-p linear
output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for a
0.5 V p-p operation. The best solution will be determined
experimentally. Figure 69 shows third harmonic distortion
as a function of the limiting level for a 2 V p-p output signal.
A wider limiting level is desirable in HI gain mode.
The voltage on the VCM pin is sourced by an internal buffer
with an output impedance of 30 Ω and a 2 mA default output
current (see Figure 68). If the VCM pin is driven from an
external source, its output impedance should be <<30 Ω and its
current drive capability should be >>2 mA. If the VCM pins of
several devices are connected in parallel, the external buffer
should be capable of overcoming their collective output
currents. When a common-mode voltage other than 2.5 V is
used, a voltage-limiting resistor, RCLMP, is needed to protect
against overload.
–20
V
= 0.75V
GAIN
–30
–40
–50
–60
–70
–80
HILO = LO
HILO = HI
INTERNAL
CIRCUITRY
2mA MAX
R
<< 30Ω
NEW V
O
CM
V
CM
30Ω
100pF
0.1µF
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
AC GROUNDING FOR
INTERNAL CIRCUITRY
CLAMP LIMIT LEVEL (V p-p)
Figure 69. HD3 vs. Clamping Level for 2 V p-p Differential Input
Figure 68. VCM Interface
Rev. C | Page 23 of 32
AD8331/AD8332
Table 4. Clamp Resistor Values
The relative noise and distortion performance of the two gain
modes can be compared in Figure 21 and Figure 27 through
Figure 37. The 48 nV/√Hz noise floor of the LO gain mode is
suited to converters with higher sampling rates or resolutions
(such as 12 bits). Both gain modes can accommodate ADC full-
scale voltages as high as 4 V p-p. Since distortion performance
remains favorable for output voltages as high as 4 V p-p (see
Figure 32), it is possible to lower the output-referred noise even
further by using a resistive attenuator (or transformer) at the
output. The circuit in Figure 71 has an output full-scale range of
2 V p-p, a gain range of –10.5 dB to +37.5 dB, and an output
noise floor of 24 nV/√Hz, making it suitable for some 14-bit
ADC applications.
Clamp Level
(V p-p)
Clamp Resistor Value (kΩ)
HILO = LO
1.21
2.ꢀ4
4.ꢀ7
ꢀ.7
HILO = HI
0.7
1.0
1.7
2.0
2.7
3.0
3.7
4.0
4.4
2.21
4.02
6.49
9.73
14.ꢀ
23.2
39.2
ꢀ3.2
11
16.9
26.ꢀ
49.9
100
4V p-p DIFF, 2V p-p DIFF,
Output Filtering and Series Resistor
Requirements
48n V/
24n V/
HZ
HZ
187Ω
2:1
LPF
VOH
VOL
To ensure stability at the high end of the gain control range,
series resistors or ferrite beads are recommended for the
outputs when driving large capacitive loads, or circuits on other
boards,. These components can be part of the external
noise filter.
ADC
AD6644
374Ω
187Ω
Figure 71. Adjusting the Noise Floor for 14-Bit ADCs
OVERLOAD
Recommended resistor values are 84.5 Ω for LO gain mode and
100 Ω for HI gain mode (see Figure 66) and are placed near
Pins VOH and VOL. Lower value resistors are permissible for
applications with nearby loads or with gains less than 40 dB.
Lower values are best selected empirically.
These devices respond gracefully to large signals that overload
its input stage and to normal signals that overload the VGA
when the gain is set unexpectedly high. Each stage is designed
for clean-limited overload waveforms and fast recovery when
gain setting or input amplitude is reduced.
An antialiasing noise filter is typically used with an ADC. Filter
requirements are application dependent.
Signals larger than 275 mV at the LNA input are clipped to
5 V p-p differential prior to the input of the VGA. Figure 44
shows the response to a 1 V p-p input burst. The symmetric
overload waveform is important for applications, such as CW
Doppler ultrasound, where the spectrum of the LNA outputs
during overload is critical. The input stage is also designed to
accommodate signals as high as 2.5 V without triggering the
slow-settling ESD input protection diodes.
When the ADC resides on a separate board, the majority of
filter components should be placed nearby to suppress noise
picked up between boards and mitigates charge kickback from
the ADC inputs. Any series resistance beyond that required for
output stability should be placed on the ADC board. Figure 70
shows a second order low-pass filter with a bandwidth of
20 MHz. The capacitor is chosen in conjunction with the 10 pF
input capacitance of the ADC.
Both stages of the VGA are susceptible to overload. Postamp
limiting is more common and results in the clean-limited
output characteristics found in Figure 45. Under more extreme
conditions, the X-AMP will overload, causing the minor glitches
evident in Figure 46. Recovery is fast in all cases. The graph in
Figure 72 summarizes the combinations of input signal and
gain that lead to the different types of overload.
OPTIONAL
BACKPLANE
0.1µ
0.1µ
F
F
1.5µ
1.5µ
H
H
84.5Ω
84.5Ω
158Ω
158Ω
18pF
ADC
Figure 70. 20 MHz Second-Order Low-Pass Filter
DRIVING ADCS
The output drive will accommodate a wide range of ADCs. The
noise floor requirements of the VGA will depend on a number
of application factors, including bit resolution, sampling rate,
full-scale voltage, and the bandwidth of the noise/antialias filter.
The output noise floor and gain range can be adjusted by
selecting HI or LO gain mode.
Rev. C | Page 24 of 32
AD8331/AD8332
POSTAMP
X-AMP
POSTAMP
X-AMP
OVERLOAD
OVERLOAD
OVERLOAD
OVERLOAD
LAYOUT, GROUNDING, AND BYPASSING
15mV 25mV
4mV
25mV
43.5
56.5
Due to their excellent high frequency characteristics, these
devices are sensitive to their PCB environment. Realizing
expected performance requires attention to detail critical to
good high speed board design.
41dB
29dB
24.5dB
24.5dB
LO GAIN
MODE
HI GAIN
MODE
A multilayer board with power and ground plane is
recommended, and unused area in the signal layers should be
filled with ground. The multiple power and ground pins provide
robust power distribution to the device and must all be
connected. The power supply pins should each be with multiple
values of high frequency ceramic chip capacitors to maintain
low impedance paths to ground over a wide frequency range.
These should have capacitance values of 0.01 μF to 0.1 μF in
parallel with 100 pF to 1 nF, and be placed as close as possible to
the pins. The LNA power pins should be decoupled from the
VGA using ferrite beads. Together with the decoupling
capacitors, ferrite beads help eliminate undesired high
frequencies without reducing the headroom, as do small value
resistors.
–4.5
1m
7.5
1m
10m
0.1 .275
1
10m
0.1 0.275
1
INPUT AMPLITUDE (V)
INPUT AMPLITUDE (V)
Figure 72. Overload Gain and Signal Conditions
The previously mentioned clamp interface controls the
maximum output swing of the postamp and its overload
response. When no RCLMP resistor is provided, this level defaults
to near 4.5 V p-p differential to protect outputs centered at a
2.5 V common mode. When other common-mode levels are set
through the VCM pin, the value of RCLMP should be chosen for
graceful overload. A value of 8.3 kΩ or less is recommended for
1.5 V or 3.5 V common-mode levels (7.2 kΩ for HI gain mode).
This limits the output swing to just above 2 V p-p diff.
Several critical LNA areas require special care. The LON and
LOP output traces must be as short as possible before
connecting to the coupling capacitors connected to Pins VIN
and VIP. RFB must be placed nearby the LON pin as well.
Resistors must be placed as close as possible to the VGA output
pins VOL and VOH to mitigate loading effects of connecting
traces. Values are discussed in the section entitled Output
Filtering and Series Resistor
OPTIONAL INPUT OVERLOAD PROTECTION.
Applications in which high transients are applied to the LNA
input may benefit from the use of clamp diodes. A pair of back-
to-back Schottky diodes can reduce these transients to
manageable levels. Figure 73 illustrates how such a diode-
protection scheme may be connected.
Requirements.
OPTIONAL
SCHOTTKY
Signal traces must be short and direct to avoid parasitic effects.
Wherever there are complementary signals, symmetrical layout
should be employed to maintain waveform balance. PCB traces
should be kept adjacent when running differential signals over a
long distance.
OVERLOAD
CLAMP
COMM 20
ENBL 19
0.1µF
RSH
CSH
FB
2
INH
CFB
RFB
3
3
4
VPS
LON
MULTIPLE INPUT MATCHING
2
1
Matching of multiple sources with dissimilar impedances can
be accomplished as shown in the circuit of Figure 75. A relay
and low supply voltage analog switch may be used to select
between multiple sources and their associated feedback
resistors. An ADG736 dual SPDT switch is shown in this
example; however, multiple switches are also available and users
are referred to the Analog Devices Selection Guide for switches
and multiplexers.
BAS40-04
Figure 73. Input Overload Clamping
When selecting overload protection, the important parameters
are forward and reverse voltages and trr (or τrr.). The Infineon
BAS40 series shown in Figure 73 has a τrr of 100 ps and VF of
310 mV at 1 mA. Many variations of these specifications can be
found in vendor catalogs.
DISABLING THE LNA
Where accessible, connection of the LNA enable pin to ground
will power down the LNA, resulting in a current reduction of
about half. In this mode, the LNA input and output pins may be
left unconnected, however the power must be connected to all
the supply pins for the disabling circuit to function. Figure 74
illustrates the connections using an AD8331 as an example.
Rev. C | Page 27 of 32
AD8331/AD8332
1
20
19
18
17
16
NC
COMM
LMD
MEASUREMENT CONSIDERATIONS
Figure 51 through Figure 55 show typical measurement
configurations and proper interface values for measurements
with 50 Ω conditions.
AD8331
2
NC
INH
ENBL
ENBV
COMM
VOL
C
FB
0.018µF
Short-circuit input noise measurements are made using
Figure 53. The input-referred noise level is determined by
dividing the output noise by the numerical gain between Point
A and Point B and accounting for the noise floor of the
spectrum analyzer. The gain should be measured at each
frequency of interest and with low signal levels since a 50 Ω
load is driven directly. The generator is removed when noise
measurements are made.
+5V
3
VPS
LON
LOP
COML
+5V
4
5
NC
NC
VOUT
ULTRASOUND TGC APPLICATION
6
15
14
13
12
11
VOH
The AD8332 ideally meets the requirements of medical and
industrial ultrasound applications. The TGC amplifier is a key
subsystem in such applications, since it provides the means for
echolocation of reflected ultrasound energy.
0.1µF
7
VIP
VPOS
+5V
VIN
Figure 76 through Figure 78 are schematics of a dual, fully
differential system using the AD8332 and AD9238 12-bit high
speed ADC with conversion speeds as high as 65 MSPS. In this
example, the VGA outputs are dc-coupled, using the reference
output of the ADC and a level shifter to center the common-
mode output voltage to match that of the converter. Consult the
data sheet of the converter to determine whether external CMV
biasing is required. AC coupling is recommended if the CMV
of the VGA and ADC are widely disparate.
0.1µF
8
HILO
CLMP
VCM
VIN
HILO
9
MODE
MODE
R
CLMP
10
GAIN
VCM
GAIN
Using the circuit shown, and a high speed ADC FIFO
evaluation kit connected to a laptop PC, an FFT can be
performed on the AD8332. With the on-board clock of 20 MHz,
and minimal low-pass filtering, and both channels driven with a
1 MHz filtered sine wave, the THD is –75 dB, noise floor –93 dB
and HD2 –83 dB.
Figure 74. Disabling the LNA
ADG736
1.13kΩ
SELECTRFB
280Ω
LON
18nF
5Ω
200Ω
INH
LOP
LNA
LMD
5Ω
50Ω
0.1µF
AD8332
Figure 75. Accommodating Multiple Sources
Rev. C | Page 26 of 32
AD8331/AD8332
S3
E
IN2
TP5
AD8332ARU
C50
0.1µF
1
28
27
26
LMD1
LMD2
C49
0.1µF
TP6
C70
0.1µF
L12
120nH FB
TP3
(RED)
L13
C60
0.1µF
+5V
120nH FB
2
3
S1
IN1
TB1
+5V
INH2
INH1
VPS1
LON1
LOP1
COM1
VIP1
E
C79
C80
22PF
JP5
IN2
JP6
IN1
22 PF
CFB2
18nF
+
C46
1µF
CFB1
18nF
TP4
(BLACK)
TB2
+5VLNA
VPS2
LON2
LOP2
COM2
VIP2
RFB1
274Ω
C41
0.1µF
C74
1nF
+5VLNA
RFB2
274Ω
GND
L7
120nH FB
+5VGA
4
25
24
23
22
21
20
19
L6
120nH FB
5
+5VLNA
C42
0.1µF
C59
0.1µF
6
C51
0.1µF
C53
0.1µF
0.1µF
7
7
3
2
VREF
AD8541
6
VCM1
4
8
VIN2
VIN1
JP13
VCM1
C71 1nF
C78
1nF
C48
0.1µF
JP14
9
VCM2
GAIN
CLMP
VOH2
VOL2
COM
VCM1
C43
0.1µF
C77
1nF
VCM
R23
2kΩ
R22
1kΩ
+5VGA
10
HI GAIN
JP10
TP2 GAIN
TP7 GND
HILO
ENB
C83
1nF
+5VGA
LO GAIN
ENABLE
JP16
DISABLE
18
11
12
R3
C68
1nF
C69
0.1µF
(R
)
CLMP
17
16
15
VOH1
VOL1
VPSV
JP8
DC2H
R27
100Ω
R24
100Ω
JP9
OPTIONAL 4-POLE LOW-PASS
FILTER
OPTIONAL 4-POLE LOW-PASS
FILTER
13
14
C58
0.1µF
L19
L17
SAT
SAT
C54
0.1µF
L11
120nH FB
L9
L1
SAT
L15
SAT
120nH FB
V
+A
IN
V
+B
IN
C64
SAT
C65
SAT
JP17
C67
SAT
C66
SAT
JP12
L20
SAT
C55
L10
C56
L18
SAT
L14
SAT
L16
SAT
L8
0.1µF 120nH FB
0.1µF
120nF FB
V
–B
V
–A
IN
IN
JP7
DC2L
R25
100Ω
R26
+5VGA
C45
0.1µF
100Ω
C85
1nF
JP10
Figure 76. Schematic, TGC, VGA Section
Rev. C | Page 2ꢀ of 32
AD8331/AD8332
VR1
+3.3VAVDD
ADP3339AKC-3.3
L5
C44
1µF
120nH FB
+3.3VCLK
C31
+5V
+
C22
0.1µF
C21
1nF
0.1µ
F
3
2
1
ADCLK
IN OUT GND
L4
R11
C2
10µF
6.3V
+
120nH FB
100Ω
+3.3VADDIG
C30
R10
1
2
3
4
5
6
64
63
62
61
60
59
JP 2
SHARED
REF
AGND
AVDD
0Ω
R5
OUT
TAB
33Ω
0.1µ
F
V
+_A
–_A
VIN+_A
VIN –_A
AGND
CLK_A
SHARED_REF
MUX_SELECT
PDWN_A
OEB_A
OTRA_A
D11_A(MSB)
D10_A
IN
Y
C61
18pF
L3
N
120nH FB
V
+3.3VAVDD
C29
IN
R14
4.7kΩ
R6
33Ω
R4
R12
1.5kΩ
+3.3VADDIG
0.1µ
F
C17
C18
1nF
1.5kΩ
R15
0Ω
0.1µF
C33
10µF
6.3V
AVDD
L2
C35
0.1µF
120nH FB
+3.3VDVDD
C1
REFT_A
+
C40
0.1µF
C52
10nF
7
8
58
57
56
55
54
53
0.1µF
REFB_A
VREF
OTR_A
C36
0.1µF
TP 9
D11_A
D10_A
D9_A
+
VREF
C12
10µF
6.3V
C32
0.1µF
9
SENSE
REFB_B
C34
10µF
6.3V
C38
0.1µF
10
11
12
13
D9_A
C39
10µF
C57
10nF
REFT_B
AVDD
AGND
VIN –_B
VIN+_B
AGND
AVDD
CLK_B
DCS
D8_A
D8_A
C37
0.1µF
+3.3VADDIG
DRGND
DRVDD
D7_A
C23
0.1µF
C25
1nF
C16
0.1µF
C15
1nF
1.5kΩ
1.5kΩ
52
51
50
49
R8
33Ω
14
15
16
17
18
19
V
V
–B
+B
D7_A
D6_A
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A
DNC
IN
C62
18pF
D6_A
IN
R7
33Ω
+3.3VCLK
D5_A
R18
48
47
46
D4_A
S2
C63
499Ω
C20
0.1µF
C19
1nF
EXT CLOCK
0.1µF
R16
5kΩ
D3_A
R17
49.9Ω
D2_A
R19
499Ω
JP 3
JP 11
20
21
22
45
44
43
42
41
40
39
38
37
36
DFS
D1_A
R20
4.7kΩ
R41
4.7kΩ
PDWN_B
OEB_B
DNC
D0_A
DNC
+3.3VCLK
ADCLK
TP 12
23
24
25
26
27
28
29
DNC
DNC
DNC
DNC
C47
10µF
6.3V
+
C86
0.1µF
ADCLK
4
DNC
DRVDD
DRGND
OTRB_B
D11_B(MSB)
D10_B
C11
+
C13
1nF
C14
0.1µF
10µF
U5
74VHC04
U5
74VHC04
EXT
3
6.3V
D0_B
D1_B
D2_B
D0_B
R9
0Ω
4
1
V
OE
3
5
1
9
2
DD
20MHz
OUT
JP 4
D1_B
OTR_B
D11_B
D10_B
D9_B
2
3
1
INT
D2_B
GND
TP 13
DATA
2
U5
U5
74VHC04
CLK
DRGND
DRVDD
D3_B
74VHC04
3
U6
SG-636PCE
6
8
D9_B
1
2
JP 1
D3_B
D4_B
D5_B
30
31
32
35
34
33
D8_B
D8_B
U5
74VHC04
D4_B
D7_B
D7_B
13
12
10
D5_B
D6_B
D6_B
SPARES
11
+3.3VADDIG
U5
74VHC04
C24
1nF
C26
0.1µF
Figure 77. Converter Schematic
Rev. C | Page 28 of 32
AD8331/AD8332
R40
22Ω
1
20
+3.3VDVDD
U10
74VHC541
GND
DATACLKA
G1
VCC
+
C3
0.1µF
C28
19
2
10
18
17
16
2
4
6
8
1
3
5
7
10µF
G2
A1
A2
A3
22 × 4
6.3V
22 × 4
1
8
1
2
8
Y1
Y2
Y3
RP 9
7
RP 1
3
2
3
4
1
7
6
5
8
OTR_A
D11_A
3
4
1
6
5
4
5
6
7
8
15
14
13
12
10
12
14
16
9
D10_A
D9_A
D8_A
D7_A
A4
A5
A6
A7
Y4
Y5
Y6
Y7
22 × 4
8
22 × 4
11
13
15
RP 10
7
RP2
2
3
4
2
3
4
1
2
7
6
5
8
7
6
5
9
11
18
20
22
24
17
19
21
23
D6_A
A8
Y8
22 × 4
RP 3
3
4
6
5
+3.3VDVDD
26
28
30
32
25
27
29
31
33
1
20
10
18
17
U7
74VHC541
G1
G2
A1
A2
VCC
1
2
8
7
+
22 × 4
C76
10µF
6.3V
C8
0.1µF
C10
0.1µF
19
GND
RP 4
8
1
2
3
4
22 × 4
2
3
D5_A
D4_A
Y1
Y2
3
4
6
5
RP 11
7
34
36
38
40
6
5
4
5
6
7
8
16
15
14
13
D3_A
D2_A
D1_A
D0_A
A3
A4
A5
A6
Y3
Y4
Y5
Y6
35
37
39
1
8
22 × 4
RP 12
7
2
3
4
6
5
12
11
DNC
DNC
A7
A8
Y7
Y8
SAM080UPM
9
+3.3VDVDD
1
20
10
18
42
44
46
48
41
43
45
47
U2
74VHC541
G1
G2
A1
VCC
GND
Y1
+
+
C27
C7
C9
0.1µF
1
8
19
22 × 4
10µF
6.3V
0.1µF
RP 13
22 × 4
2
3
4
7
6
5
2
3
1
2
3
4
8
7
6
5
8
OTR_B
RP 5
17
16
15
14
D11_B
D10_B
D9_B
D8_B
D7_B
A2
A3
A4
A5
Y2
Y3
Y4
Y5
4
5
6
7
8
9
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
22 × 4
1
2
8
7
RP 14
22 × 4
1
2
3
4
RP 6
7
6
5
13
12
11
3
6
A6
A7
A8
Y6
Y7
Y8
4
1
5
8
D6_B
D5_B
22 × 4
22 × 4
1
2
3
4
1
8
7
6
5
8
RP 7
+3.3VDVDD
20
1
19
2
RP 15
G1
G2
A1
U3 VCC
74VHC541
GND
+
C75
10µF
C4
0.1µF
C5
0.1µF
C6
0.1µF
10
18
22 × 4
6.3V
2
3
4
1
7
6
5
8
D4_B
Y1
RP 8
2
3
4
7
6
5
3
4
5
6
7
8
9
17
16
15
14
D3_B
D2_B
D1_B
D0_B
DNC
A2
A3
A4
A5
Y2
Y3
Y4
Y5
22 × 4
RP 16
2
3
4
7
6
5
13
12
11
A6
A7
A8
Y6
Y7
Y8
SAM080UPM
DNC
R39
22Ω
DATACLK
Figure 78. Interface Schematic
Rev. C | Page 29 of 32
AD8331/AD8332
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8331
PIN 1
1
2
20 COMM
LMD
INH
IDENTIFIER
19
18
ENBL
ENBV
VPSL
LON
LOP
3
4
17 COMM
AD8331
TOP VIEW
(Not to Scale)
5
16
15
14
VOL
6
VOH
VPOS
COML
VIP
7
8
VIN
13 HILO
MODE
9
12
11
RCLMP
VCM
10
GAIN
Figure 79. 20-Lead QSOP
Table 5. 20–Lead QSOP (RQ PACKAGE)
Pin No.
Name
LMD
INH
Description
1
2
LNA Signal Ground
LNA Input
3
4
7
6
ꢀ
8
9
10
11
12
13
14
17
16
1ꢀ
18
19
20
VPSL
LON
LOP
COML
VIP
VIN
MODE
GAIN
VCM
CLMP
HILO
VPOS
VOH
LNA 7V Supply
LNA Inverting Output
LNA Noninverting Output
LNA Ground
VGA Noninverting Input
VGA Inverting Input
Gain Slope Logic Input
Gain Control Voltage
Common-Mode Voltage
Output Clamping Level
Gain Range Select (HI or LO)
VGA 7 V Supply
Noninverting VGA Output
Inverting VGA Output
VGA Ground
VGA Enable
LNA Enable
VOL
COMM
ENBV
ENBL
COMM
VGA Ground
Rev. C | Page 30 of 32
AD8331/AD8332
AD8332
1
2
PIN 1
IDENTIFIER
28
27
26
25
24
23
22
21
20
19
LMD2
INH2
LMD1
INH1
32 31 30 29
PIN 1
27 26 25
28
3
VPS2
LON2
LOP2
COM2
VIP2
VPS1
LON1
LOP1
COM1
VIP1
24
23
22
21
20
19
18
17
COMM
VOH1
VOL1
VPSV
NC
VOL2
VOH2
COMM
LON1
VPS1
INH1
1
2
3
4
5
6
7
8
4
INDICATOR
5
AD8332
TOP VIEW
(Not to Scale)
AD8332
TOP VIEW
(Not to Scale)
LMD1
LMD2
INH2
VPS2
LON2
6
7
8
VIN2
VIN1
9
VCM2
GAIN
RCLMP
VOH2
VOL2
COMM
VCM1
HILO
9
10
13 14 15 16
11 12
10
11
12
13
14
18 ENB
17 VOH1
16 VOL1
15 VPSV
Figure 81. 32-Lead LFCSP
Table 7. 32–Lead LFCSP (AC PACKAGE)
Pin No.
Name
LON1
VPS1
INH1
LMD1
LMD2
INH2
VPS2
LON2
LOP2
COM2
VIP2
Description
Figure 80. 28-Lead TSSOP
1
2
3
4
7
6
ꢀ
8
CH1 LNA Inverting Output
CH1 LNA Supply 7 V
CH1 LNA Input
CH1 LNA Signal Ground
CH2 LNA Signal Ground
CH2 LNA Input
Table 6. 28–Lead TSSOP (AR PACKAGE)
Pin No.
Name
LMD2
INH2
VPS2
LON2
LOP2
COM2
VIP2
Description
1
2
3
4
7
6
ꢀ
8
CH2 LNA Signal Ground
CH2 LNA Input
CH2 Supply LNA 7 V
CH2 LNA Inverting Output
CH2 LNA Noninverting Output
CH2 LNA Ground
CH2 VGA Noninverting Input
CH2 VGA Inverting Input
CH2 Common-Mode Voltage
Gain Control Voltage
Output Clamping Resistor
CH2 Noninverting VGA Output
CH2 Inverting VGA Output
VGA Ground (Both Channels)
VGA Supply 7 V (Both Channels)
CH1 Inverting VGA Output
CH1 Noninverting VGA Output
Enable—VGA/LNA
VGA Gain Range Select (HI or LO)
CH1 Common-Mode Voltage
CH1 VGA Inverting Input
CH1 VGA Noninverting Input
CH1 LNA Ground
CH2 LNA Supply 7 V
CH2 LNA Inverting Output
CH2 LNA Noninverting Output
CH2 LNA Ground
CH2 VGA Noninverting Input
CH2 VGA Inverting Input
CH2 Common-Mode Voltage
Gain Slope Logic Input
Gain Control Voltage
Output Clamping Level Input
VGA Ground
9
10
11
12
13
14
17
16
1ꢀ
18
19
20
21
22
23
24
27
26
2ꢀ
28
29
30
31
32
VIN2
9
VCM2
GAIN
RCLMP
VOH2
VOL2
COMM
VPSV
VOL1
VOH1
ENB
VIN2
10
11
12
13
14
17
16
1ꢀ
18
19
20
21
22
23
24
27
26
2ꢀ
28
VCM2
MODE
GAIN
RCLMP
COMM
VOH2
VOL2
NC
VPSV
VOL1
VOH1
COMM
ENBV
ENBL
HILO
CH2 Noninverting VGA Output
CH2 Inverting VGA Output
Not Connected
VGA Supply 7 V
HILO
VCM1
VIN1
CH1 Inverting VGA Output
CH1 Noninverting VGA Output
VGA Ground
VGA Enable
LNA Enable
VGA Gain Range Select (HI or LO)
CH1 Common-Mode Voltage
CH1 VGA Inverting Input
CH1 VGA Noninverting Input
CH1 LNA Ground
VIP1
COM1
LOP1
LON1
VPS1
INH1
LMD1
CH1 LNA Noninverting Output
CH1 LNA Inverting Output
CH1 LNA Supply 7 V
CH1 LNA Input
CH1 LNA Signal Ground
VCM1
VIN1
VIP1
COM1
LOP1
CH1 LNA Noninverting Output
Rev. C | Page 31 of 32
AD8331/AD8332
OUTLINE DIMENSIONS
9.80
9.70
9.60
0.341
BSC
20
1
11
10
0.154
BSC
28
15
0.236
BSC
4.50
4.40
4.30
PIN 1
6.40 BSC
1
14
PIN 1
0.065
0.049
0.069
0.053
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
SEATING
PLANE
0.050
0.016
0.010
0.006
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
COPLANARITY
0.004
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-137AD
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 84. 20 Lead Shrink Outline [QSOP] (RQ-20)
Dimensions shown in millimeters
Figure 82. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28)
Dimensions shown in millimeters
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
3.25
3.10 SQ
2.95
4.75
BSC SQ
TOP
BOTTOM
VIEW
VIEW
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
12° MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 83. 32-Lead Frame Chip Scale Package [LFCSP] (CP-32)
Dimensions shown in millimeters
ORDERING GUIDE
AD8331/AD8332
Models
Temperature Range
–40°C to +87°C
Package Description
Package Outline
RQ-20
AD8331ARQ
Shrink Small Outline Package 170 mil Body, 27 mil pitch
Shrink Small Outline Package 170 mil Body, 27 mil pitch
Shrink Small Outline Package 170 mil Body, 27 mil pitch
Evaluation Board with AD8331ARQ
AD8331ARQ-REEL
AD8331ARQ-REELꢀ
AD8331-EVAL
–40°C to +87°C
RQ-20
RQ-20
–40°C to +87°C
AD8332ARU
–40°C to +87°C
–40°C to +87°C
–40°C to +87°C
–40°C to +87°C
–40°C to +87°C
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP)
RU-28
RU-28
RU-28
CP-32
CP-32
AD8332ARU-REEL
AD8332ARU-REELꢀ
AD8332ACP-REEL
AD8332ACP-REELꢀ
AD8332-EVAL
Lead Frame Chip Scale Package (LFCSP)
Evaluation Board with AD8332ARU
©
2003 Analog Devices, Inc. All rights reserved. Trademarks
and registered trademarks are the property of their respective owners.
C03199-0-11/03(C)
Rev. C | Page 32 of 32
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