AD8334ACP-REEL7 [ADI]
IC QUAD INSTRUMENTATION AMPLIFIER, 110 MHz BAND WIDTH, QCC64, 9 X 9 MM, MO-220VMMD, LFCSP-64, Instrumentation Amplifier;
| 型号： | AD8334ACP-REEL7 |
| 厂家： | 
ADI |
| 描述： | IC QUAD INSTRUMENTATION AMPLIFIER, 110 MHz BAND WIDTH, QCC64, 9 X 9 MM, MO-220VMMD, LFCSP-64, Instrumentation Amplifier 放大器 |
| 文件： | 总14页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Low Noise, Low Cost
Variable Gain Amplifier
Preliminary Technical Data
AD8335
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low Noise Preamplifier (PrA)
Voltage Noise = 1.3 nV/√Hz Typical
Current Noise = 2.4 pA/√Hz Typical
NF = 7 dB (RS = RIN = 50Ω)
Single Ended Input; Vin-max = 625 mVpp
Active Input Match
Input SNR (Noise BW = 20 MHz) = 92 dB
VGA
Differential Output
64 PIN LFCSP
51
+
61
60
59
55
58
52
49
47
48
46
56
50
54
43
41
42
VOH1
CMV1
VOL1
VGN1
SL12
-
63
64
PIP1
+
ATTENUATOR
20/28dB
GAIN INT
GAIN INT
20/28dB
18dB
VMD1
-48 to 0dB
PMD1
-
-
+
INTERPOLATOR
INTERPOLATOR
53
5
VCM2
POP2
PON2
PMD2
PIP2
VGN2
VOL2
CMV2
VOH2
4
Vout-max = 4 Vpp, RL= 500 Ω Diff.
Gain Range (8 dB Output Gain Step)
-10 dB to +38 dB – LO Gain Mode
-2 dB to +46 dB – HI Gain Mode
Accurate Linear-in-dB Gain Control
PrA + VGA Performance
-3 dB Bandwidth of 70 MHz
Excellent Overload Performance
Supply: +5 V
-
+
1
+
ATTENUATOR
18dB
VMD2
-48 to 0dB
2
-
+
-
6
VIP2
7
VIN2
10
11
15
16
12
13
28
VIN3
VIP3
39
40
38
27
31
25
35
33
34
VOH3
CMV3
VOL3
VGN3
SL34
-
PIP3
+
+
ATTENUATOR
20/28dB
GAIN INT
GAIN INT
20/28dB
18dB
VMD3
-48 to 0dB
PMD3
POP3
PON3
VCM3
-
-
+
Power Consumption
INTERPOLATOR
INTERPOLATOR
92 mW/channel (370 mW total)
76 mW/channel (PrA Off; 305 mW total)
Power Down
VGN4
VOL4
CMV3
VOH4
+
17
18
PMD4
PIP4
-
APPLICATIONS
Medical Imaging (Ultrasound, Gamma Cameras)
Sonar
Test and Measurement
ATTENUATOR
18dB
VMD4
22
-48 to 0dB
+
-
29
32
20
21
26
23
30
Precise, Stable Wideband Gain Control
Figure 1.
Functional Block Diagram
GENERAL DESCRIPTION
Assuming a 20 MHz noise bandwidth (NBW), the Nyquist frequency
for a 40 MHz ADC, the input SNR is 92 dB. The HILO pin optimizes
the output SNR for 10 and 12 bit ADCs with 1 or 2 Vpp full-scale (FS)
inputs.
The AD8335 is a quad Variable Gain Amplifier (VGA) with low
noise preamplifier intended for cost and power sensitive
applications. AD8335 features four channels with 48 dB gain range;
fully differential signal paths; and active input preamplifier
matching. The AD8335 has an output gain switch of 8 dB and
separate gain controls for each channel.
Channels 1 and 2 are enabled through the EN12pin while channels 3
and 4 are enabled through the EN34pin. For VGA only applications,
the PrAs can be powered down, significantly reducing power
consumption.
The aggregate input referred voltage noise at maximum gain is 1.3
nV/√Hz; the preamplifier (PrA) has 1.2 nV/√Hz. The PrA has a
single-ended to differential gain of 8 (18.06 dB) and a maximum input
The AD8335 is available in a 64 pin chip scale (9x9 mm) package
signal capability is 625 mVPK-PK
.
for the industrial temperature range of -40°C to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,
U.S.A.
REV. PrA 06/09/2004
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its
use. Specifications subject to change without notice. No license is granted by
implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective
companies.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
2004
Analog Devices, Inc. All rights reserved.
AD8335
Preliminary Technical Data
TABLE OF CONTENTS
Absolute Maximum Ratings............................................................ 5
VGA ................................................................................................8
Attenuator ..................................................................................9
Gain Control..............................................................................9
Output Stage ..............................................................................9
VGA Noise .................................................................................9
Applications..................................................................................... 11
Overload...................................................................................... 11
Logic Inputs................................................................................. 11
Driving ADCs............................................................................. 11
Pin Configuration and Functional Descriptions........................ 13
AD8335 - Typical Performance Characteristics .................. Error!
Bookmark not defined.
Test Circuits.................................. Error! Bookmark not defined.
Background ....................................................................................... 6
Theory of Operation ........................................................................ 7
Enable Summary........................................................................... 7
Preamp........................................................................................... 8
Noise........................................................................................... 8
REVISION HISTORY
REV. PrA 06/09/2004 | Page 2 of 14
Preliminary Technical Data
AD8335
AD8335—Preliminary Specifications
Table 1. VS = +5 V, TA = 25°C, RL = 500 Ω, f = 5 MHz, CL = 10 pF, LO gain range (-10 to +38 dB), RFB = 249 Ω (PrA RIN = 50 Ω) and
signal voltage specified differential, per channel performance, dBm (50 Ω) unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Unit
PrA CHARACTERISTICS
Gain
Single Ended Input to Differential Output
Single Ended Input to Single Ended Output
PrA Output limited to 5Vpp
18
12
625
50
dB
dB
mVpp
Ω
Input Voltage Range
Input Resistance
RFB = 249 Ω (closest 1% value resistors are shown)
RFB = 374 Ω
75
Ω
100
14.7
RFB = 499 Ω
Ω
RFB = ∞, low frequency value into PIPx
PIPx(Pins 2,15,18,63)
kΩ
pF
Input Capacitance
-3dB Small Signal Bandwidth
Input Voltage Noise
Input Current Noise
Noise Figure
1.5
110
1.15
2.4
MHz
With RFB = 249 Ω
RS = 0 Ω, RFB = ∞
nV/√Hz
pA/√Hz
Active Termination Match
Unterminated
7
dB
dB
RS = RIN = 50 Ω
4.4
RS = 50 Ω, RFB = ∞
PrA + VGA CHARACTERISTICS
-3 dB Small Signal Bandwidth
70
85
MHz
Unterminated: RS = 50 Ω, RFB = ∞
Matched: RS = RIN = 50 Ω
LO Gain, VGN = 3V
MHz
Slew Rate
V/µs
HI Gain, VGN = 3V
V/µs
Input Voltage Noise
Noise Figure
1.3
Pins VGNx= 3V, RS = 0 Ω, RFB = ∞
Pins VGNx= 3V, f = 1-10 MHz
nV/√Hz
Active Termination Match
7
dB
dB
dB
dB
RS = RIN = 50 Ω
4.5
5.0
1.3
38
95
5
RS = RIN = 100 Ω
Unterminated
RS = 50 Ω, RFB = ∞
RS = 500 Ω, RFB = ∞
LO Gain; VGN < 2V
HI Gain; VGN < 2V
Output Referred Noise
nV/√Hz
nV/√Hz
Vpp
Peak Output Voltage
Output Resistance
Differential, RL ≥ 500 Ω
f < 1MHz, pins VOHx,VOLx
Set to mid-supply for PrA and VGA
Differential (VOHx-VOLx)
Common-Mode (VOHx-VS/2,VOLx-VS/2)
Vout = 1 Vpp, LO Gain, Vgain = 2V
f = 1 MHz
f = 1 MHz
f = 10 MHz
f = 10 MHz
1
Ω
V
mV
mV
Common-Mode Level
Output Offset Voltage
VS/2
Harmonic Distortion
HD2
HD3
HD2
-67
-56
-56
-55
dBc
dBc
dBc
dBc
HD3
Harmonic Distortion
HD2
Vout = 1 Vpp, HI Gain, Vgain = 2V
f = 1 MHz
-57
-67
-56
-56
18
dBc
dBc
dBc
dBc
dBm
HD3
HD2
HD3
f = 1 MHz
f = 10 MHz
f = 10 MHz
VGN = 3V (see TPCxx for P1dB vs VGN)
Output 1 dB Compression (OP1dB)
Two Tone IM3 Distortion
Vout = 1 Vpp, VGN = 3V (see TPCxx for IM3 vs
VGN)
REV. PrA 06/09/2004| Page 3 of 14
AD8335
Preliminary Technical Data
Parameter
Conditions
f = 1 MHz
f = 10 MHz
Min
Typ
Max
Unit
dBc
dBc
-65
Output IP3 (OIP3)
Vout = 1 Vpp, VGN = 3V (see TPCxx for OIP3 vs
VGN)
f = 1 MHz
f = 10 MHz
Vout = 1 Vpp, f = 1 MHz
Vgain = 3V, Vin = 12.5 mVpp to 1Vpp
Full gain range, f = 1-10 MHz
Pins VGNx
dBm
dBm
dBc
ns
37
Channel-to-Channel Crosstalk
Overload Recovery
Group Delay Variation
GAIN CONTROL INTERFACE
Normal Operating Range
Maximum Range
ns
0
0
-10
-2
3
V
V
dB
dB
dB/V
No gain foldover
VS
38
46
Gain Range
LO Gain Mode; (pins HLxx = 0 V)
HI Gain Mode; (pins HLxx = VS)
Nominal (pins SL12and SL34= 2.50 V)
Scale Factor
20
-0.3
5
Bias Current
µA
MHz
ns
Response Bandwidth
Response Time
GAIN ACCURACY
Absolute Gain Error
48 dB Gain Change
Pins VGNx
0.5
-6
6
dB
dB
dB
dB
dB
dB
dB
0 ≤ Vgain ≤ 0.4 V
0 .4 ≤ Vgain ≤ 2.6 V
±0.7
-0.5
2.6 ≤ Vgain ≤ 3 V
Gain Law Conformance Over Temperature
Intercept
0 .4 ≤ Vgain ≤ 2.6 V; -40°C < TA < 85°C
LO Gain Mode; PrA matched to 50 Ω
HI Gain Mode; PrA matched to 50 Ω
0 .4 ≤ Vgain ≤ 2.6 V
-16.2
-8.2
Channel-to-Channel Matching
ENABLE/HILO INTERFACE
Logic Level High
Logic Level Low
Bias Current
Pins HLxx,SPxxand ENxx
2.75
0
5
1
V
V
Logic High
Logic Low
40
-6
µA
µA
Ω
Input Resistance
HILO Response Time
Enable Response Time
µs
µs
POWER SUPPLY
Supply Voltage
Quiescent Current
Over Temperature
Quiescent Power
Quiescent Current
Quiescent Power
Quiescent Current
Disable Current
PSRR
Pins VPPxand VPVx
4.5
5
19
5.5
V
Per Channel – PrA and VGA Enabled
-40°C < TA < 85°C
Per Channel – PrA and VGA Enabled
Per Channel – PrA Disabled, VGA Enabled
Per Channel – PrA Disabled, VGA Enabled
All Channels Enabled
mA
mA
mW
mA
mW
mA
mA
dB
95
13
65
76
0.8
All Channels Disabled
Vgain = 3 V
REV. PrA 06/09/2004 | Page 4 of 14
Preliminary Technical Data
AD8335
ABSOLUTE MAXIMUM RATINGS
Table 2. AD8335 Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings
Parameter
Rating
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
θJA
TBD°C/W
6 V
Supply Voltage VS
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
TBD°C
–40°C to +85°C
–65°C to +150°C
Lead Temperature Range (Soldering 60 sec) 300°C
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. PrA 06/09/2004| Page 5 of 14
AD8335
Preliminary Technical Data
BACKGROUND
at the receiver front-end of less than 0.8 nV/√Hz with
simultaneous maximum signal capability of greater than 500
mVpp for a total input dynamic range of 167 dBc/Hz is state
of the art, as exhibited by the AD8332 and AD8334 VGAs.
For low end and portable ultrasound machines, power and
cost are of primary importance; for those machines, noise on
the order of 1.3 nV/√Hz and slightly lower dynamic range are
an acceptable tradeoff for lower power.
Since a detailed discussion of ultrasound systems is beyond
the scope of this data sheet, the reader is encouraged to
consider the following article for more detailed background
information -- “How Ultrasound System Considerations
Influence Front-End Component Choice”, Analog Dialogue,
Vol. 36, No. 3, May-July 2003.
The primary intended application for the AD8335 is medical
ultrasound, Figure 1 shows a simplified block diagram of an
ultrasound system. In ultrasound a key function is Time Gain
Control (TGC), this is compensation for signal attenuation
by the body for which a linear-in-dB VGA is needed. The key
requirements in an ultrasound signal chain are – very low
noise; active input termination; good overload recovery; low
power; and differential ADC drive. Because ultrasound
machines use beamforming techniques that require a large
number (32 up to 256 or 512) of transmit and receive
channels, the lowest power at lowest possible noise is of key
importance. Most modern machines use digital
beamforming; i.e. they sample the signal right after the TGC
amplifier and implement the beamforming function in the
digital domain. Typical ADC resolution currently is 10 bits
with sampling rates greater than 40 MSPS; 12 bits are used in
high-end systems. In premium machines, noise performance
(http://www.analog.com/library/analogDialogue/archives/36-
03/ultrasound/index.html).
HV
TX AMPs
Beamformer
Central Control
Tx
Beamformer
System
TGCs
HV
MUX/
T/R
Switches
Rx Beamformer
(B & F Mode)
LNAs
DEMUX
CW (analog)
Beamformer
Transducer
Spectral
Doppler
Processing
(D Mode)
Image &
Motion
Processing
(B Mode)
Color
Cable
Doppler (PW)
Processing
(F Mode)
TGC - Time Gain Compensation
(VGA Function)
Display
Audio
Output
Figure 1.
Simplified Ultrasound System Diagram
REV. Pra 06/09/2004| Page 6 of 14
Preliminary Technical Data
THEORY OF OPERATION
AD8335
one pin, HL12, and channels 3 and 4 another pin, HL34,
Figure 2 is a simplified block diagram of a single channel of
the AD8335. The part has four identical channels that can be
enabled two at a time – channels 1&2 and 3&4. Furthermore,
the preamps can be shutdown by connecting the SPxxpins
to the positive supply, to enable them the pins should be
grounded. The ENxxpins should be tied to the positive
supply to enable the VGAs and the overall channel. Each
channel consists of a low-noise preamplifier (PrA) followed
by a VGA with 8 dB gain switch. This HILO switch sets the
maximum VGA gain to either 20 or 28 dB for 0 and 5 V
applied to the HLxxpins, respectively. Channel 1 and 2 share
typically these pins would be tied together externally to set
the appropriate VGA gain depending on which ADC
resolution is used – LO gain, 12 bit ADC; HI gain, 10 bit
ADC. The signal path is fully differential all the way from the
preamplifier input through the VGA output to maximize
signal swing and reduce even order distortion; however, the
preamplifiers are designed to be driven from a single-ended
signal source. Any gain mentioned in this document is
measured from the single-ended PrA input to the differential
output of either the PrA or the VGA.
-
+1
+
-
+1
+
Outamp
20/28dB
Rfb
VOH
+
-
Rs
+1
+1
PON VIN
POP VIP
INP
INL
-
+
-
-
+
Atten 1
+
PrA
gm
-48 to 0 dB
18 dB
-
-
+
-
+
+
+
VPS
GAIN Interface
Interpolator
VOL
-
BIAS
+1
COM
VGAIN
VSLP
VCM
ENB
HILO
HILO
Figure 2.
Simplified Block Diagram of Single Channel
Referring to Figure 2 the PrA has a gain of 18.06 dB (x8) from
single-ended input to differerntial output; then comes an
attenuator with a total range of 48.16 dB (x1/256); followed by
an output stage that has either a gain of 20.0 (x10) or 27.96
(x25) for a total gain range of –10.1 to 38.06 dB (LO gain mode)
and –2.14 to 46.02 dB (HI gain mode). These gain numbers are
the theoretically exact values, however, due to manufacturing
tolerances they will never be achieved precisely and therefore in
the rest of this document we will use the following approximate
gain ranges: -10 to +38 dB (LO gain mode) and –2 to +46 dB
(HI gain mode). Equation 1 shows how the absolute gain can be
calculated - gain errors are determined by subtracting Equation
1 from the actual data -
are –7.4 and –1.4 dB, respectively.
Each channel consumes 92 mW on a +5 V supply, for a total of
about 370 mW when all four channels are enabled. The PrA
consumes 35 % and the VGA about 65 % of the power per
channel. The PrAs can be shut down via the SP12and SP34
pins if a user wants to only use the VGAs. Note that if a signal is
applied to the PrA inputs there will be feedtrough of the signal
even if the PrA is off if Rfb is used; to eliminate any feedthrough
it is important that the feedback resistor is removed.
ENABLE SUMMARY
The following table summarizes the enable/shutdown logic:
EN1
2
SP1
2
EN3
4
SP3
4
PrA1
2
VGA1
2
PrA3
4
VGA3
4
Isuppl
y
H
H
L
L
H
L
H
H
L
L
H
L
On
Off
Off
Off
On
On
Off
Off
On
Off
Off
Off
On
On
Off
Off
74mA
48mA
0.6mA
0.6mA
Gain = 20⋅VGAIN + ICPT ,
where ICPT = -15.4 dB for LO gain mode and matched PrA
input (RIN = 50 Ω and RFB = 250 Ω); ICPT = -9.4 dB for LO gain
mode and unmatched input; for HI gain mode these numbers
(1)
L
H
L
H
REV. PrA 06/09/2004| Page 7 of 14
AD8335
Preliminary Technical Data
actual 1.2 nV/√Hz of the PrA results in an overall IRN of 1.3
nV/√Hz. Note that these noise numbers contain ALL amplifier
noise sources including the VGA and the preamplifier gain
resistors! Often noise numbers of amplifiers do not include the
gain setting resistors, and an op-amp might be presented as say
1 nV/√Hz, but once the gain resistors are included the noise can
be much higher.
PREAMP
The preamp is based on a fully differential design similar to the
one that has been used in the AD8331/2/4 family of VGAs and
is optimized for single-ended input drive; this means that pins
PMDxwhich are the negative input to the differential
preamplifier, should always be AC grounded to provide a
balanced differential signal at the PrA outputs. For more
detailed information regarding the preamplifier architecture,
see the LNA section in the AD8332 data sheet. The current
discussion will give a functional overview only.
The preamplifier consists of a fixed gain amplifier with
differential outputs. Since a negative output and a fixed gain-of-
8 (18.06 dB) is available, one can produce an “active input
termination” by connecting a feedback resistor between the
negative output and the positive input pin PIPx. This is a well
known technique to synthesize a fixed input resistance. The
result is a synthesized input resistance of
Figure 1 shows the simulated Noise Figure (NF) at 1 MHz
verses source resistance, RS, and a fixed RIN of the preamplifier;
i.e. RIN = 50, 75, 100, 200 Ω, and 14.7 kΩ which is the resistance
value seen looking into pins PIPxwhen RFB = ∞. As can be seen
from this figure, the minimum NF for RIN = 50 Ω is at slightly
less than 7 dB. Note that for this preamplifier the minimum NF
is always at about the desired RIN -- 50 Ω, 75 Ω, 100 Ω, 200 Ω.
For RFB = ∞ the minimum NF is at about 480 Ω, this optimum
noise resistance can also be calculated by dividing the input
referred voltage noise by the current noise.
16
RFB
Includes Noise of VGA
15
RIN =
,
(2)
A
RIN = 50Ω
(1+
)
RFB = 250Ω
2
14
13
12
11
10
9
where A/2 is half of the differential gain, or the gain from the
PIPxinputs to the PONxoutputs. Since the amplifier has a gain
of x8 from its input to its differential output, it is important to
note that the gain A/2 is the gain from pin PIPxto PONxwhich
is 6 dB lower at 12.04 dB (x4); furthermore, the actual input
resistance is reduced by the 14.7 kΩ seen looking into pins
PIPxwith pins PMDxAC grounded. So, to calculate the needed
RFB for a desired RIN, especially for higher RINs, it is important to
use equation 3.
R
IN = 75Ω
RFB = 375Ω
R
IN = 100Ω
RFB = 500Ω
8
7
RFB
6
RIN =
||14.7kΩ
(3)
(1+ 4)
5
R
IN = 200Ω
For example, to set RIN = 200 Ω one needs an RFB = 1.013 kΩ; if
one would use the simple equation 2 to calculate RIN one would
get an actual value of 197 Ω, this would result in less than a 0.1
dB gain error in this particular example. Typically other factors
might influence the absolute gain accuracy more significantly,
for example, a widely varying source resistance. At higher
frequencies, the input capacitance of the PrA will also come
into play and needs to be considered. The user will have to
determine what level of matching accuracy is desired and adjust
RFB accordingly. The bandwidths (BW) of the preamplifier and
VGA are about 110 MHz each, this results in a cascaded BW of
approximately 80 MHz. Ultimately the BW of the PrA limits
the accuracy of the synthesized RIN; for RIN = RS up to about 500
Ω the best match is between 100 kHz and 10 MHz, where the
lower frequency limit is determined by the size of the AC
coupling capacitors, while the upper limit is determined by the
BW rolloff of the preamplifier.
RFB = 1kΩ
4
3
R
IN = 14.7kΩ
Simulation Results
2
RFB = ∞
1
10
100
Rs - Ω
1e3
Figure 1.
Simulated Noise Figure vs. RS for Various Fixed Values of RIN
,
Actively Matched
VGA
The basic architecture, an X-AMPTM, can be seen in the block
diagram in Figure 2. This architecture consists of a ladder
attenuator, followed by a fixed-gain amplifier with selectable
input stages. Earlier instances of this architecture can be found
in the AD600/602, AD603 to AD605, and more recently in the
AD8331-8334, and AD8367 VGAs. Through a proprietary,
temperature compensated interpolator design, the bias currents
to the input gm stages are continuously steered from “right to
left” (decreasing attenuation) – this results in lowest to highest
gain. Only one of the output feedback resistance networks,
output stages, and feedback buffers is selected at a time by the
HILO (HL12and HL34) pins. The VGA output gain switch of
Noise
The total input referred noise (IRN) is 1.3 nV/√Hz. With a
gain-of-8 (18dB) in the preamp the 3.7 nV/√Hz of the VGA are
0.46 nV/√Hz referred to the PrA input, that together with the
REV. PrA 06/09/2004 | Page 8 of 14
Preliminary Technical Data
AD8335
8 dB (x2.5) is intended to adjust the output noise level to either
a 10 or 12 bit ADC noise floor assuming a full scale (FS) of 1
Vpp. The reason is that at low gains the ADC SNR should limit
the overall SNR and since for a given FS the “ceiling” is fixed
(typically modern ADCs have either a 1 Vpp or 2 Vpp FS), one
needs to adjust the noise floor of the preceding VGA depending
on the ADC resolution. For example, a 12 bit ADC has
theoretically 12 dB better SNR than a 10 bit ADC, in practice
about 8 dB are typical and this is the reason for the 8 dB gain
switch implemented in this design. As the gain is changed the
IRN and the quiescent power consumption of the VGA are not
changed; this then has the desired result that the output
referred noise (ORN) will change simply by the gain change, in
this design 8 dB, without affecting any other parameters, like
power, bandwidth, etc.
3V with the most linear gain range from about 0.5 to 2.5 V
where the error is typically less than ±0.2 dB while the error
increases below and above those values respectively (see Error!
Reference source not found. in the typical performance
characteristics). The VGAIN voltage can also be increased all
the way to the positive supply without gain foldover.
Each channel has a separate gain control pin that would be
normally tied together in an ultrasound application, but for
other uses where separate gain controls are necessary one would
simply connect the appropriate gain control signal to each
channel.
Output Stage
The output stage of the VGA is essentially duplicated to provide
an 8 dB (x2.5) gain switch. The gain switch is intended to
optimize the output noise floor for either a 10 or 12 bit ADC. In
LO gain mode the VGA gain is 20 dB (x10) and 28 dB (x25) in
HI gain mode. One or the other of the output stages, gain
resistors, and feedback buffers is selected depending on the
HILO (pins HLxx) logic setting.
Attenuator
The attenuator is an 8-stage differential R-2R ladder with a total
attenuation of 48.16 dB – 6.02 dB per tap. The effective input
resistance per side is 320 Ω nominally for a total differential
resistance of 640 Ω. The common-mode voltage of the
attenuator and the VGA is set by an amplifier that takes the
mid-supply voltage from a point in the preamplifier - this allows
for DC coupling of the PrA to the VGA without introducing
large offsets due to common-mode differences. However, when
DC coupling between the PrA and VGA, any offset from the
PrA will be amplified as the gain is increased this produces an
exponentially increasing VGA output offset. By AC coupling
between the PrA and the VGA the output offset stays flat with
change in gain so in general it is recommended that AC
coupling be used. As can be seen from Figure 2 again, pins
VCMxconnect to the respective midpoints on each channel and
are used to AC decouple the mid-point common-mode node at
higher frequencies. It is very important that at least a 0.1 µF
capacitor is used, with better decoupling at higher frequencies
when another smaller capacitor like a 10 nF cap is connected in
parallel. The internal +1 buffer only provides correct common-
mode bias levels and any dynamic currents have to be absorbed
by the external decoupling caps.
The bandwidth is maintained constant at 100 MHz by changing
the compensation capacitance as the gain switches from LO to
HI and vice versa. The power consumption also doesn’t change
as the gain is switched.
To reduce power consumption one typically reduces the supply
voltage as much as possible. For analog circuits this directly
reduces the dynamic range because of the more limited swing.
One way to get back at least 6dB of dynamic range is to use
differential signaling throughout the chip, because of this it is
best to set the common mode level to half the supply voltage
throughout the signal chain for maximum signal swing.
Differential signaling has the added benefit of suppressing the
even order harmonics. One drawback of differential signaling is
the increased number of pins and passive components for a
given function, but this is the tradeoff for the improved even
order performance and reduced power.
The output is designed to drive a nominal differential load of
500 Ω or greater. The signal swing can be as large as 5Vpp
differential before the output stage starts clipping. Note,
however, that distortion will increase before reaching the actual
hard clipping level. For a typical value of 1Vpp or 2Vpp, the full-
scale (FS) values of modern day ADCs, the distortion can be
found in Error! Reference source not found. through Error!
Reference source not found.. Typically one would use AC
coupling at each of the VGA outputs followed by a differential
anti-alias filter when driving an ADC. Note that almost all
modern ADCs have differential inputs and want to be driven
differentially for optimum performance. For more information
see the Applications section of this data sheet.
Gain Control
The gain control interface has two inputs: VGAIN (pins VGNx)
and VSLP (pins SLxx). The “slope” input is intended only as a
decoupling pin and the only guaranteed gain slope is 20 dB/V,
the default. However, if a voltage is applied to the VSLP inputs
one can increase the gain slope by reducing the slope voltage.
For example, if a voltage of 1.67 V is applied to pins SLxx the
gain slope changes to 30 dB/V; to calculate the gain slope use
the following equation:
2.5V × 20dB/V
VSLP =
(4)
Slope
VGAIN varies the gain of the VGA through the interpolator by
selecting the appropriate input stages that are connected to the
input attenuator. The nominal VGAIN range for 20 dB/V is 0 to
VGA Noise
The output noise of the VGA is constant verses gain as is the
REV. PrA 06/09/2004| Page 9 of 14
AD8335
Preliminary Technical Data
case in all X-AMPs, this causes the input referred noise to
increase as the gain is decreased. Note that this is exactly what is
needed in a receiver application where a wide dynamic range is
compressed down to a smaller one with a fixed ceiling and noise
floor as is the case when driving ADCs. The VGA output noise
is about 38 nV/√Hz in LO gain mode and 2.5 times higher than
this, 95 nV/√Hz, in HI gain mode. As the gain is increased
eventually the noise of the preamplifier will dominate and at the
maximum VGA gain the output noise will be about 105 nV/√Hz
and 263 nV/√Hz for LO and HI gain modes respectively.
The output SNR is determined by the noise floor and the largest
signal level which is typically limited by the FS of the ADC. One
source of noise that can be troublesome is called “modulation
noise”, essentially the noise introduced by the gain control input.
Normally one tends to look at the main amplifier signal path for
noise, but since a VGA is really a multiplier that has the
following function
Vgain×Vin
Vout =
(4)
Vref
Vref (Bias) and Vgain (gain control interface) will also be
contributors under certain conditions. It is therefore important
that the gain control signals are kept “clean”, especially at higher
gain control slopes.
REV. PrA 06/09/2004 | Page 10 of 14
Preliminary Technical Data
AD8335
overload event. If one imagines for the moment that the
APPLICATIONS
external clamping diodes are removed and that VD is 10 V, then
during a positive going high voltage transmit pulse the upper
left and lower right HV diodes will be reverse biased, while the
lower left and upper right HV diodes will be forward biased. In
this case, without the external clamping diodes present the
voltage at the INP pin will try to go to +VD=10V; this obviously
will overload the preamplifier. Actually, the output of the
preamp can swing about 5 Vpp which results in a maximum
input signal capability of 5 Vpp/8 = 625 mVpp at node INP.
OVERLOAD
Excellent overload behavior is of primary importance in
ultrasound. This is because in the initial transmit phase high
voltage pulses are sent to the transducer elements and those are
mostly blocked by the T/R (Transmit/Receive) switch but
voltages as high as a couple of volts can leak across the diodes
and overload the TGC amplifier (see Figure 1). The T/R switch
is essentially a diode bridge built with high voltage diodes. Since
ultrasound is mostly a pulse system and time-of-flight is used to
determine depth it is of great importance to recover from
overload as fast as possible after the overload event goes away to
make sure that the next pulse is not disturbed by the previous
one. Typically the gain is at the low end initially and then gets
ramped-up as the reflected pulses get weaker with deeper
penetration, this change of gain with time is the reason for the
name “Time Gain Compensation - TGC” amplifier. Overload
can happen in both the preamp and the VGA – for low gains
right after transmit, the PrA will be overloaded; while the VGA
can get overloaded when the gain has increased because of
depth penetration and at the same time a strong reflection is
coming back due to acoustically hard material like bone. It is
therefore important to have good overload behavior in the
complete signal path.
Now if there were internal back-to-back diodes, shown dotted,
then until the pulse has settled (the coupling caps have charged)
these diodes would clamp the input voltage. However, there are
large currents flowing and therefore lots of charge gets dumped
on the coupling caps. This can be a particular problem in
ultrasound where the shape of the pulses will vary depending on
which imaging modality is used. If there is any sequence of
mostly positive pulses then the INL coupling cap will get
“pumped up” and over time because of different time constants
there will be a difference voltage that can take a long time to
settle. Since the system is a sampled system any left over signal
from the previous pulse can cause interference and therefore
image or Doppler degradation. Therefore, the AD8335 does not
have internal input clamping diodes and it is highly
recommended that external diodes be used to protect overload
of the preamplifier. It should be noted though that the
preamplifier does have overload protection designed in just not
in the front-end where it is most effective.
Ideally the PrA and VGA should not need external overload
protection, however, because he AD8335 is a single supply part
there are issues to be considered because of the needed AC
coupling along the signal path. Figure 2 shows the typical front-
end circuitry in an ultrasound application. There is the T/R
switch implemented with high voltage diodes (DHV) and back-
to-back connected input clamping diodes before the AC
coupling capacitors. These clamping diodes will hold the input
voltage to about ±0.7 V. The PrA will be overloaded but the
coupling capacitors are not disturbed significantly. The external
clamping diodes are essential for having good overload
protection!
It is important to point out that both the preamplifier and VGA
do have overload protection built in and will recover very
quickly after an overload event. Because of the unique situation
at the input of the preamplifier though, extra external
protection is strongly recommended as explained above.
LOGIC INPUTS
The AD8335 has three types of logic inputs – the enable pins
EN12and EN34, the preamp shutdown pins SP12and SP34,
and the HILO pins HL12and HL34. The enable inputs turn
on-and-off each of the corresponding pairs of channels; the
preamp shutdown pins do the same for just the preamplifiers;
and inputs HL12 and HL34 set the HILO gain for channels 1
and 2, and 3 and 4, respectively. The shutdown of the
preamplifier allows users that want the lowest possible power
consumption to use only the VGAs. The reverse is not possible -
the VGAs cannot be shutdown independently so that the
preamplifiers can be used alone.
+VD
Rfb
DHV
DHV
DHV
Rs
INP
INL
PON
POP
+
PrA
-
18 dB
-
DHV
+
Clamping
Diodes
Explanation
see text
DRIVING ADCs
-VD
The AD8335 VGA is designed to drive 10 and 12 bit ADCs with
minimal extra components. Note that the AD8335 is a single +5
V part and many of the newest ADCs operate from a +3 V
supply, this will require a level shift between the VGA output
and the ADC input. This level shift is most easily accomplished
Figure 2.
Clamping of Preamplifier
The user might now ask – why not integrate the clamping
diodes inside the IC (shown here in a dotted line)? To explain
this one needs to first explain what is happening during an
REV. PrA 06/09/2004| Page 11 of 14
AD8335
Preliminary Technical Data
via AC coupling caps, especially if the signal is a bandpass (or
pulse signal) as is the case in ultrasound and many
communications applications.
times the number of components than a single-ended filter
since the components that in the single-ended case are tied to
ground will be now connected across the differential signal
path. This saves one component per shunt component, while
the series components will double.
The anti-aliasing filters (AAF) should be implemented
differentially. A fully differential AAF will require about 1.5
REV. PrA 06/09/2004 | Page 12 of 14
Preliminary Technical Data
AD8335
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
64
63
57
49
48
62
61 60
59
58
56
55
54
53
52
51
50
PMD2
1
2
CMV1
VOH1
VOL1
VPV1
VPV2
VOL2
VOH2
CMV2
CMV3
VOH3
PIN 1
IDENTIFIER
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PIN2
VPP2
3
PON2
POP2
VIP2
VIN2
COM2
4
5
6
7
8
AD8334
TOP VIEW
(Not to Scale)
9
COM1
VIN3
VIP3
POP3
PON3
10
11
12
13
14
15
16
VOL3
VPV3
VPV4
VOL4
VOH4
VPP3
PIN3
PMD3
CMV4
30
17
18
19
20 21
23
24
25
26
27
28
29
31
32
22
Figure 1.
64 LFCSP
Table 3. Pin Function Descriptions
Pin Mnemonic Function
No.
Pin Mnemonic
No.
Function
PMD2
PIP2
VPP2
PON2
POP2
VIP2
VIN2
COM2
COM3
VIN3
VIP3
POP3
PON3
VPP3
PIP3
PMD3
PMD4
PIP4
VPP4
PON4
POP4
VIP4
VIN4
COM4
VGN4
VCM4
VGN3
VCM3
EN34
SP34
SL34
HL34
CMV4
VOH4
VOL4
VPV4
VPV3
VOL3
VOH3
CMV3
CMV2
VOH2
VOL2
VPV2
VPV1
VOL1
VOH1
CMV1
HL12
SL12
SP12
EN12
VCM2
VGN2
VCM1
VGN1
COM1
VIN1
VIP1
POP1
PON1
VPP1
PIP1
PMD1
1
2
3
4
5
6
7
8
Preamp Input Common – Ch2
Preamp Input – Ch2
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VGA Common – Ch4
VGA Output Positive – Ch4
VGA Output Negative – Ch4
Positive Supply VGA – Ch4
Positive Supply VGA – Ch3
VGA Output Negative – Ch3
VGA Output Positive – Ch3
VGA Common – Ch3
Positive Supply Preamp – Ch2
Preamp Output Negative – Ch2
Preamp Output Positive – Ch2
VGA Input Positive – Ch2
VGA Input Negative – Ch2
Ground Preamp – Ch2
9
Ground Preamp – Ch3
VGA Common – Ch2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VGA Input Negative – Ch3
VGA Input Positive – Ch3
Preamp Output Positive – Ch3
Preamp Output Negative – Ch3
Positive Supply Preamp – Ch3
Preamp Input – Ch3
Preamp Input Common – Ch3
Preamp Input Common – Ch4
Preamp Input – Ch4
Positive Supply Preamp – Ch4
Preamp Output Negative – Ch4
Preamp Output Positive – Ch4
VGA Input Positive – Ch4
VGA Input Negative – Ch4
Ground Preamp – Ch4
Gain Control – Ch4
Common Mode Decoupling Pin – Ch4
Gain Control – Ch3
Common Mode Decoupling Pin – Ch3
Enable – Ch3 and Ch4
Shutdown - Preamp3 and Preamp4
Slope Decoupling Pin – Ch3 and Ch4
HILO Pin – Ch3 and Ch4
VGA Output Positive – Ch2
VGA Output Negative – Ch2
Positive Supply VGA – Ch2
Positive Supply VGA – Ch1
VGA Output Negative – Ch1
VGA Output Positive – Ch1
VGA Common – Ch1
HILO Pin – Ch1 and Ch2
Slope Decoupling Pin – Ch1 and Ch2
Shutdown - Preamp1 and Preamp2
Enable – Ch1 and Ch2
Common Mode Decoupling Pin – Ch2
Gain Control – Ch2
Common Mode Decoupling Pin – Ch1
Gain Control – Ch1
Ground Preamp – Ch1
VGA Input Negative – Ch1
VGA Input Positive – Ch1
Preamp Output Positive – Ch1
Preamp Output Negative – Ch1
Positive Supply Preamp – Ch1
Preamp Input – Ch1
Preamp Input Common – Ch1
REV. PrA 06/09/2004| Page 13 of 14
AD8335
Preliminary Technical Data
0.30
9.00
BSC SQ
0.25
0.18
0.60 MAX
0.60 MAX
64
49
48
1
PIN 1
INDICATOR
4.85
4.70
4.55
8.75
BSCSQ
BOTTOM VIEW OF
EXPOSED PAD
TOP
VIEW
SQ*
0.45
0.40
0.35
33
32
16
17
7.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12ꢀMAX
0.05 MAX
0.02 NOM
0.50 BSC
0.20REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION.
THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT
IT BE SOLDERED TO THE GROUND PLANE
Figure 1. 64 Lead Frame Chip Scale Package (LFCSP) (CP-64) – Dimensions shown in millimeters
ORDERING GUIDE
AD8335
Temperature Range
–40°C to +85°C
Package Description
Package Outline
CP-64
AD8335ACP-REEL
AD8334ACP-REEL7
AD8335-EVAL
Lead Frame Chip Scale Package (LFCSP)
Lead Frame Chip Scale Package (LFCSP)
Evaluation Board with AD8335ACP
–40°C to +85°C
CP-64
REV. PrA 06/09/2004 | Page 14 of 14
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