AD8354_17 [ADI]
RF Gain Block;
| 型号： | AD8354_17 |
| 厂家： | 
ADI |
| 描述： | RF Gain Block |
| 文件： | 总16页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 MHz to 2.7 GHz
RF Gain Block
AD8354
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fixed gain of 20 dB
Operational frequency of 1 MHz to 2.7 GHz
Linear output power up to 4 dBm
Input/output internally matched to 50 Ω
Temperature and power supply stable
Noise figure: 4.2 dB
BIAS AND VREF
VPOS
INPT
VOUT
COM2
Power supply: 3 V or 5 V
COM1
AD8354
APPLICATIONS
VCO buffers
Figure 1.
General Tx/Rx amplification
Power amplifier predrivers
Low power antenna drivers
GENERAL DESCRIPTION
The AD8354 is a broadband, fixed-gain, linear amplifier that
operates at frequencies from 1 MHz up to 2.7 GHz. It is
intended for use in a wide variety of wireless devices, including
cellular, broadband, CATV, and LMDS/MMDS applications.
The noise figure is 4.2 dB at 900 MHz. The reverse isolation
(S12) is −33 dB at 900 MHz.
The AD8354 can also operate with a 5 V power supply; in
which case, no external inductor is required. Under these
conditions, the AD8354 delivers 4.88 dBm with 20 dB of gain
at 900 MHz. The dc supply current is 26 mA. At 900 MHz, the
OIP3 is greater than 19 dBm; at 2.7 GHz, the OIP3 is 15 dBm.
The noise figure is 4.4 dB at 900 MHz. The reverse isolation
(S12) is −33 dB.
By taking advantage of ADI’s high performance, complementary Si
bipolar process, these gain blocks provide excellent stability
over process, temperature, and power supply. This amplifier is
single-ended and internally matched to 50 Ω with a return loss
of greater than 10 dB over the full operating frequency range.
The AD8354 provides linear output power of nearly 4.3 dBm
with 20 dB of gain at 900 MHz when biased at 3 V and an
external RF choke is connected between the power supply and
the output pin. The dc supply current is 24 mA. At 900 MHz,
the output third-order intercept (OIP3) is greater than 18 dBm;
at 2.7 GHz, the OIP3 is 14 dBm.
The AD8354 is fabricated on ADI’s proprietary, high performance,
25 GHz, Si complementary, bipolar IC process. The AD8354 is
available in a chip scale package that uses an exposed paddle for
excellent thermal impedance and low impedance electrical
connection to ground. It operates over a −40°C to +85°C
temperature range, and an evaluation board is also available.
Rev. F
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2002–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8354
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 13
Basic Connections...................................................................... 13
Applications Information .............................................................. 14
Low Frequency Applications Below 100 MHz........................... 14
Evaluation Board ............................................................................ 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
REVISION HISTORY
2/2017—Rev. E to Rev. F
8/2005—Rev. A to Rev. B
Changed CP-8-1 to CP-8-23 ........................................ Throughout
Changes to Figure 2.......................................................................... 6
Changes to Ordering Guide .......................................................... 16
Updated Outline Dimensions....................................................... 16
Updated Format..................................................................Universal
Changes to Product Title, Features, and General Description....1
Changes to Basic Connections Section ....................................... 13
Added Low Frequency Applications Below 100 MHz Section ..... 14
Changes to Ordering Guide.......................................................... 16
Updated Outline Dimensions....................................................... 16
11/2013—Rev. D to Rev. E
Changes to Figure 2.......................................................................... 6
Added Figure 35, Renumbered Sequentially .............................. 12
Added Exposed Pad Notation to Outline Dimensions ............. 16
Changes to Ordering Guide .......................................................... 16
6/2002—Rev. 0 to Rev. A
Changes to Ordering Guide.............................................................4
Replaced TPC 34 ............................................................................ 10
Updated Outline Dimensions....................................................... 13
3/2009—Rev. C to Rev. D
Changes to Lead Temperature (Soldering, 60 sec) Parameter,
Table 3 ................................................................................................ 5
Changes to Ordering Guide .......................................................... 16
2/2002—Revision 0: Initial Version
12/2005—Rev. B to Rev. C
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Moved Figure 39 to Page 15; Renumbered Sequentially........... 15
Changes to Ordering Guide .......................................................... 16
Rev. F | Page 2 of 16
Data Sheet
AD8354
SPECIFICATIONS
VS = 3 V, TA = 25°C, 100 nH external inductor between VOUT and VPOS, ZO = 50 Ω, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
Gain
1
2700
MHz
dB
f = 900 MHz
19.5
f = 1.9 GHz
18.6
dB
f = 2.7 GHz
17.1
dB
Delta Gain
f = 900 MHz, −40°C ≤ TA ≤ +85°C
f = 1.9 GHz, −40°C ≤ TA ≤ +85°C
f = 2.7 GHz, −40°C ≤ TA ≤ +85°C
VPOS 10%, f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz
f = 1.9 GHz
−0.97
−1.05
−1.33
0.54
0.37
0.2
dB
dB
dB
dB/V
dB/V
dB/V
dB
Gain Supply Sensitivity
Reverse Isolation (S12)
−33.5
−38
dB
f = 2.7 GHz
−32.9
dB
RF INPUT INTERFACE
Input Return Loss
Pin INPT
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
24.4
23
12.7
dB
dB
dB
RF OUTPUT INTERFACE
Pin VOUT
Output Compression Point
f = 900 MHz, 1 dB compression
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz, −40°C ≤ TA ≤ +85°C
f = 1.9 GHz, −40°C ≤ TA ≤ +85°C
f = 2.7 GHz, −40°C ≤ TA ≤ +85°C
f = 900 MHz
4.6
3.7
2.7
0.7
0.7
0.8
23.6
16.5
14.6
dBm
dBm
dBm
dB
dB
dB
dB
dB
dB
Delta Compression Point
Output Return Loss
f = 1.9 GHz
f = 2.7 GHz
DISTORTION/NOISE
Output Third-Order Intercept
f = 900 MHz, ∆f = 1 MHz, PIN = −28 dBm
f = 1.9 GHz, ∆f = 1 MHz, PIN = −28 dBm
f = 2.7 GHz, ∆f = 1 MHz, PIN = −28 dBm
f = 900 MHz, ∆f = 1 MHz, PIN = −28 dBm
f = 900 MHz
19
16
dBm
dBm
dBm
dBm
dB
14.2
29.7
4.2
4.8
5.4
Output Second-Order Intercept
Noise Figure
f = 1.9 GHz
f = 2.7 GHz
dB
dB
POWER INTERFACE
Pin VPOS
Supply Voltage
2.7
16
3
3.3
31
V
mA
mA/V
µA/°C
Total Supply Current
Supply Voltage Sensitivity
Temperature Sensitivity
23
6.2
33
−40°C ≤ TA ≤ +85°C
Rev. F | Page 3 of 16
AD8354
Data Sheet
VS = 5 V, TA = 25°C, no external inductor between VOUT and VPOS, ZO = 50 Ω, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
Gain
1
2700
MHz
dB
f = 900 MHz
19.5
f = 1.9 GHz
18.7
dB
f = 2.7 GHz
17.3
dB
Delta Gain
f = 900 MHz, −40°C ≤ TA ≤ +85°C
f = 1.9 GHz, −40°C ≤ TA ≤ +85°C
f = 2.7 GHz, −40°C ≤ TA ≤ +85°C
VPOS 10%, f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
−0.93
−0.99
−1.21
0.32
0.21
0.08
−33.5
−37.6
−32.9
dB
dB
dB
dB/V
dB/V
dB/V
dB
dB
dB
Gain Supply Sensitivity
Reverse Isolation (S12)
RF INPUT INTERFACE
Input Return Loss
Pin INPT
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
24.4
23.9
13.5
dB
dB
dB
RF OUTPUT INTERFACE
Pin VOUT
Output Compression Point
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz, −40°C ≤ TA ≤ +85°C
f = 1.9 GHz, −40°C ≤ TA ≤ +85°C
f = 2.7 GHz, −40°C ≤ TA ≤ +85°C
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
4.8
4.6
3.6
0.37
−0.14
−0.05
23.7
22.5
17.6
dBm
dBm
dBm
dB
dB
dB
dB
dB
dB
Delta Compression Point
Output Return Loss
DISTORTION/NOISE
Output Third-Order Intercept
f = 900 MHz, ∆f = 50 MHz, PIN = −30 dBm
f = 1.9 GHz, ∆f = 50 MHz, PIN = −30 dBm
f = 2.7 GHz, ∆f = 50 MHz, PIN = −30 dBm
f = 900 MHz, ∆f = 1 MHz, PIN = −28 dBm
f = 900 MHz
19.3
17.3
15.3
28.7
4.4
dBm
dBm
dBm
dBm
dB
Output Second-Order Intercept
Noise Figure
f = 1.9 GHz
5
dB
f = 2.7 GHz
5.6
dB
POWER INTERFACE
Pin VPOS
Supply Voltage
4.5
17
5
25
4
5.5
34
V
mA
mA/V
µA/°C
Total Supply Current
Supply Voltage Sensitivity
Temperature Sensitivity
TA = 27°C
−40°C ≤ TA ≤ +85°C
28
Rev. F | Page 4 of 16
Data Sheet
AD8354
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Stresses at or above those listed under Absolute Maximum
Rating
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Supply Voltage, VPOS
Input Power (re: 50 Ω)
Equivalent Voltage
Internal Power Dissipation
Paddle Not Soldered
5.5 V
10 dBm
700 mV rms
325 mW
812 mW
Paddle Soldered
θJA (Paddle Soldered)
80°C/W
θJA (Paddle Not Soldered)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
AD8354ACP (Non-RoHS Compliant)
AD8354ACPZ (RoHS Compliant)
200°C/W
150°C
−40°C to +85°C
−65°C to +150°C
ESD CAUTION
240°C
260°C
Rev. F | Page 5 of 16
AD8354
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COM1
NC
1
2
3
4
8
7
6
5
COM1
VOUT
VPOS
COM2
AD8354
TOP VIEW
INPT
COM2
NOTES
1. NC = NO CONNECT.
2. THE EXPOSEDPAD MUST BE CONNECTED
TO A LOW IMPEDANCE GROUND PAD.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
COM1
NC
Description
1, 8
2
Device Common. Connect to low impedance ground.
No Connection.
3
4, 5
6
INPT
COM2
VPOS
RF Input Connection. Must be ac-coupled.
Device Common. Connect to low impedance ground.
Positive Supply Voltage.
7
VOUT
RF Output Connection. Must be ac-coupled.
Rev. F | Page 6 of 16
Data Sheet
AD8354
TYPICAL PERFORMANCE CHARACTERISTICS
90
90
120
120
60
60
150
150
30
30
180
0
180
0
330
330
210
210
300
300
240
240
270
270
Figure 3. S11 vs. Frequency, VS = 3 V, TA = 25°C, 100 MHz ≤ f ≤ 3 GHz
Figure 6. S22 vs. Frequency, VS = 3 V, TA = 25°C, 100 MHz ≤ f ≤ 3 GHz
25
25
GAIN AT 3.3V
GAIN AT –40°C
20
20
GAIN AT 2.7V
15
10
5
GAIN AT 3.0V
15
GAIN AT +25°C
GAIN AT +85°C
10
5
0
0
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. Gain vs. Frequency, VS = 2.7 V, 3 V, and 3.3 V, TA = 25°C
Figure 7. Gain vs. Frequency, VS = 3 V, TA = −40°C, +25°C, and +85°C
0
0
–5
–5
–10
–15
–20
–25
–10
–15
–20
–25
–30
S
AT –40°C
12
S
AT 3.3V
–30
–35
–40
12
S
AT +25°C
12
–35
S
AT 2.7V
S
AT 3.0V
12
12
S
AT +85°C
1000
12
–
40
0
500
1000
1500
2000
2500
3000
0
500
1500
2000
2500
3000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. Reverse Isolation vs. Frequency, VS = 2.7 V, 3 V, and 3.3 V, TA = 25°C
Figure 8. Reverse Isolation vs. Frequency, VS = 3 V, TA = −40°C, +25°C, and +85°C
Rev. F | Page 7 of 16
AD8354
Data Sheet
7
6
5
4
3
2
1
6
5
4
3
2
1
0
P
AT +85°C
1dB
P
AT 3.3V
1dB
P
AT +25°C
1dB
PPAT3.0V
1dB
P
AT –40°C
1dB
P
AT 2.7V
1dB
0
–1
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. P1dB vs. Frequency, VS = 3 V, TA = −40°C, +25°C, and +85°C
Figure 9. P1dB vs. Frequency, VS = 2.7 V, 3 V, and 3.3 V, TA = 25°C
50
45
50
45
40
35
40
35
30
25
20
15
10
30
25
20
15
10
5
5
0
0
14.4
14.6
14.8
15.0
15.2
15.4
15.6
15.8
16.0
2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
OUTPUT 1dB COMPRESSION POINT (dBm)
OIP3 (dBm)
Figure 10. Distribution of P1dB, VS = 3 V, TA = 25°C, f = 2.2 GHz
Figure 13. Distribution of OIP3, VS = 3 V, TA = 25°C, f = 2.2 GHz
22
22
OIP3 AT 3.3V
20
18
16
14
12
20
18
16
14
12
OIP3 AT +25°C
OIP3 AT +85°C
OIP3 AT 3.0V
OIP3 AT 2.7V
OIP3 AT –40°C
10
10
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. OIP3 vs. Frequency, VS = 2.7 V, 3 V, and 3.3 V, TA = 25°C
Figure 14. OIP3 vs. Frequency, VS = 3 V, TA = −40°C, +25°C, and +85°C
Rev. F | Page 8 of 16
Data Sheet
AD8354
6.0
5.8
5.6
5.4
5.2
5.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
NF AT +85°C
NF AT 3.0V
NF AT 3.3V
4.8
4.6
4.4
4.2
4.0
NF AT +25°C
NF AT –40°C
NF AT 2.7V
500
0
500
1000
1500
2000
2500
3000
0
1000
1500
2000
2500
3000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Noise Figure vs. Frequency, VS = 2.7 V, 3 V, and 3.3 V, TA = 25°C
Figure 18. Noise Figure vs. Frequency, VS = 3 V, TA = −40°C, +25°C, and +85°C
40
30
I
AT 3.3V
S
35
30
25
20
25
20
I
AT 2.7V
S
I
AT 3.0V
S
15
10
5
15
10
5
0
0
–60
4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
NOISE FIGURE (dB)
Figure 16. Distribution of Noise Figure, VS = 3 V, TA = 25°C, f = 2.2 GHz
Figure 19. Supply Current vs. Temperature, VS = 2.7 V, 3 V, and 3.3 V
90
90
120
120
60
60
150
150
30
30
180
0
180
0
330
210
330
210
300
240
300
240
270
270
Figure 20. S22 vs. Frequency, VS = 5 V, TA = 25°C, 100 MHz ≤ f ≤ 3 GHz
Figure 17. S11 vs. Frequency, VS = 5 V, TA = 25°C, 100 MHz ≤ f ≤ 3 GHz
Rev. F | Page 9 of 16
AD8354
Data Sheet
25
20
15
10
25
GAIN AT –40°C
GAIN AT 5.5V
GAIN AT 4.5V
20
15
10
5
GAIN AT 5.0V
�
GAIN AT +25°C
GAIN AT +85°C
5
0
0
0
500
1000
1500
2000
2500
3000
0
500
2000
FREQUENCY (MHz)
2500
3000
1000
1500
FREQUENCY (MHz)
Figure 21. Gain vs. Frequency, VS = 4.5 V, 5 V, and 5.5 V, TA = 25°C
Figure 24. Gain vs. Frequency, VS = 5 V, TA = −40°C, +25°C, and +85°C
0
0
–5
–10
–15
–20
–25
–30
–35
–40
–5
–10
–15
–20
–25
–30
–35
–40
S
AT 4.5V
S
AT –40°C
12
12
S
AT 5.0V
S
AT 5.5V
12
12
S
AT +25°C
12
S
AT +85°C
12
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25. Reverse Isolation vs. Frequency, VS = 5 V, TA = −40°C, +25°C, and +85°C
Figure 22. Reverse Isolation vs. Frequency, VS = 4.5 V, 5 V, and 5.5 V, TA = 25°C
6
7
P
AT +85°C
AT –40°C
1dB
6
P
AT 5.5V
1dB
5
4
3
2
5
4
P
1dB
P
AT +25°C
1dB
P
AT 5.0V
1dB
3
2
1
0
P
AT 4.5V
1dB
1
0
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 26. P1dB vs. Frequency, VS = 5 V, TA = –40°C, +25°C, and +85°C
Figure 23. P1dB vs. Frequency, VS = 4.5 V, 5 V, and 5.5 V, TA = 25°C
Rev. F | Page 10 of 16
Data Sheet
AD8354
35
30
25
20
15
10
50
45
40
35
30
25
20
15
10
5
5
0
0
3.95 4.00 4.05 4.10 4.15 4.20 4.25 4.30 4.35 4.40 4.45 4.50
16.0 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 17.0 17.1 17.2
OIP3 (dBm)
OUTPUT 1dB COMPRESSION POINT (dBm)
Figure 27. Distribution of P1dB, VS = 5 V, TA = 25°C, f = 2.2 GHz
Figure 30. Distribution of OIP3, VS = 5 V, TA = 25°C, f = 2.2 GHz
22
20
18
16
22
OIP3 AT 5.5V
OIP3 AT –40°C
20
18
OIP3 AT +85°C
OIP3 AT +25°C
16
14
12
10
OIP3 AT 5.0V
OIP3 AT 4.5V
14
12
10
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 31. OIP3 vs. Frequency, VS = 5 V, TA = –40°C, +25°C, and +85°C
Figure 28. OIP3 vs. Frequency, VS = 4.5 V, 5 V, and 5.5 V, TA = 25°C
7.5
7.0
7.0
6.5
6.0
5.5
5.0
6.5
6.0
5.5
5.0
NF AT 5.5V
NF AT +85°C
4.5
NF AT +25°C
4.0
4.5
4.0
NF AT –40°C
NF AT 4.5V
2000
3.5
3.0
NF AT 5.0V
500
0
500
1000
1500
2000
2500
3000
0
1000
1500
2500
3000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 29. Noise Figure vs. Frequency, VS = 4.5 V, 5 V, and 5.5 V, TA = 25°C
Figure 32. Noise Figure vs. Frequency, VS = 5 V, TA = –40°C, +25°C, and +85°C
Rev. F | Page 11 of 16
AD8354
Data Sheet
40
35
30
25
20
15
10
5
20
19
18
17
0
15
10
–5
–10
–15
16
15
14
5
0
–30
–25
–20
–15
(dBm)
–10
–5
0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6
P
IN
NOISE FIGURE (dB)
Figure 36. Output Power and Gain vs. Input Power, VS = 3 V, TA = 25°C, f = 900 MHz
Figure 33. Distribution of Noise Figure, VS = 5 V, TA = 25°C, f = 2.2 GHz
35
20
19
18
17
16
15
14
15
10
5
30
I
I
AT 5.5V
AT 4.5V
S
25
20
15
10
5
S
0
I
AT 5.0V
S
–5
–10
–15
0
–60
–30
–25
–20
–15
–10
–5
0
–40
–20
0
20
40
60
80
100
P
(dBm)
IN
TEMPERATURE (°C)
Figure 34. Supply Current vs. Temperature, VS = 4.5 V, 5 V, and 5.5 V
Figure 37. Output Power and Gain vs. Input Power, VS = 5 V, TA = 25°C, f = 900 MHz
32
30
28
26
24
22
20
18
16
I
AT 5V, +85°C
S
I
I
AT 3V, +85°C
AT 5V, +25°C
S
S
I
AT 3V, +25°C
S
I
I
AT 5V, –40°C
AT 3V, –40°C
S
S
–10
–8
–6
–4
–2
(dBm)
0
2
4
6
P
OUT
Figure 35. Supply Current vs. POUT and Temperature, VS = 5 V
Rev. F | Page 12 of 16
Data Sheet
AD8354
THEORY OF OPERATION
The AD8354 is a 2-stage, feedback amplifier employing both
shunt-series and shunt-shunt feedback. The first stage is
degenerated and resistively loaded and provides approximately
10 dB of gain. The second stage is a PNP-NPN Darlington
output stage, which provides another 10 dB of gain. Series-
shunt feedback from the emitter of the output transistor sets the
input impedance to 50 Ω over a broad frequency range. Shunt-
shunt feedback from the amplifier output to the input of the
Darlington stage helps to set the output impedance to 50 Ω. The
amplifier can be operated from a 3 V supply by adding a choke
inductor from the amplifier output to VPOS. Without this
choke inductor, operation from a 5 V supply is also possible.
It is critical to supply very low inductance ground connections
to the ground pins (Pin 1, Pin 4, Pin 5, and Pin 8) as well as to
the backside exposed paddle. This ensures stable operation.
The AD8354 is designed to operate over a wide supply voltage
range, from 2.7 V to 5.5 V. The output of the part, VOUT, is
taken directly from the collector of the output amplifier stage.
This node is internally biased to approximately 3.2 V when the
supply voltage is 5 V. Consequently, a dc blocking capacitor
should be connected between the output pin, VOUT, and the
load that it drives. The value of this capacitor is not critical, but
it should be 100 pF or larger.
When the supply voltage is 3 V, it is recommended that an
external RF choke be connected between the supply voltage
and the output pin, VOUT. This increases the dc voltage applied
to the collector of the output amplifier stage, which improves
performance of the AD8354 to be very similar to the performance
produced when 5 V is used for the supply voltage. The inductance
of the RF choke should be approximately 100 nH, and care
should be taken to ensure that the lowest series self-resonant
frequency of this choke is well above the maximum frequency
of operation for the AD8354.
BASIC CONNECTIONS
The AD8354 RF gain block is a fixed gain amplifier with single-
ended input and output ports whose impedances are nominally
equal to 50 Ω over the frequency range 1 MHz to 2.7 GHz.
Consequently, it can be directly inserted into a 50 Ω system
with no impedance matching circuitry required. The input and
output impedances are sufficiently stable vs. variations in
temperature and supply voltage that no impedance matching
compensation is required. A complete set of scattering
parameters is available at www.analog.com.
Bypass the supply voltage input, VPOS, using a large value
capacitance (approximately 0.47 µF or larger) and a smaller,
high frequency bypass capacitor (approximately 100 pF)
physically located close to the VPOS pin.
The input pin (INPT) is connected directly to the base of the
first amplifier stage, which is internally biased to approximately 1 V;
therefore, a dc blocking capacitor should be connected between the
source that drives the AD8354 and the input pin, INPT.
The recommended connections and components are shown in
Figure 41.
Rev. F | Page 13 of 16
AD8354
Data Sheet
APPLICATIONS INFORMATION
The AD8354 RF gain block can be used as a general-purpose,
fixed gain amplifier in a wide variety of applications, such as a
driver for a transmitter power amplifier (see Figure 38). Its
excellent reverse isolation also makes this amplifier suitable for
use as a local oscillator buffer amplifier that would drive the
local oscillator port of an upconverter or downconverter mixer
(see Figure 39).
LOW FREQUENCY APPLICATIONS BELOW 100 MHz
The AD8354 RF gain block can be used below 100 MHz. To
accomplish this, the series dc blocking capacitors, C1 and C2,
need to be changed to a higher value that is appropriate for the
desired frequency. C1 and C2 were changed to 0.1 µF to accomplish
the sweeps in Figure 40.
21.5
dB-S21
Mkr 1:
97.638034MHz 19.40dB
21.0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
HIGH POWER
AD8354
AMPLIFIER
1
Figure 38. AD8354 as a Driver Amplifier
MIXER
AD8354
LOCAL OSCILLATOR
CH 1: START 300.000kHz
STOP 100.000MHz
Figure 39. AD8354 as a LO Driver Amplifier
Figure 40. Low Frequency Application from
300 kHz to 100 MHz at 5 V VPOS, −12 dBm Input Power
Rev. F | Page 14 of 16
Data Sheet
AD8354
EVALUATION BOARD
Figure 41 shows the schematic of the AD8354 evaluation board.
Note that L1 is shown as an optional component that is used to
obtain maximum gain only when VP = 3 V. The board is powered
by a single supply in the 2.7 V to 5.5 V range. The power supply
is decoupled by a 0.47 µF and a 100 pF capacitor.
AD8354
1
COM1
COM1
8
C2
1000pF
OUTPUT
2
3
4
NC
VOUT
VPOS
COM2
7
6
5
C1
L1
INPUT 1000pF
INPT
COM2
C3
100pF
C4
0.47µF
Figure 42. Silkscreen Top
NC = NO CONNECT
Figure 41. Evaluation Board Schematic
Table 5. Evaluation Board Configuration Options
Default
Value
Component Function
C1, C2
AC coupling capacitors.
1000 pF,
0603
C3
High frequency bypass capacitor.
Low frequency bypass capacitor.
100 pF,
0603
0.47 µF,
0603
C4
L1
Optional RF choke, used to increase
current through output stage when
VP = 3 V. Not recommended for use
when VP = 5 V.
100 nH,
0603
Figure 43. Component Side
Rev. F | Page 15 of 16
AD8354
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
1.89
1.74
1.59
3.25
3.00
2.75
0.55
0.40
0.30
0.20 MIN
5
8
2.25
2.00
1.75
EXPOSED PAD
0.60
0.45
0.30
4
1
BOTTOM VIEW
TOP VIEW
PIN 1
PIN 1 INDEX
AREA
NS
INDIC ATOR AREA OPTIO
(SEE DETAIL A)
0.50 BSC
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET
0.30
SEATING
PLANE
0.23
0.18
0.203 REF
Figure 44. 8-Lead Lead Frame Chip Scale Package [LFCSP]
2 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-23)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
Package Description
8-Lead LFCSP, 7" Tape and Reel
Evaluation Board
Package Option
Branding
AD8354ACPZ-REEL7
AD8354-EVALZ
CP-8-23
0G
1 Z = RoHS Compliant Part.
©2002–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02722-0-2/17(F)
Rev. F | Page 16 of 16
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