AD8372ACPZ-R71 [ADI]
41 dB Range, 1 dB Step Size, Programmable Dual VGA; 41分贝范围，步进为1 dB大小，可编程双通道VGA
| 型号： | AD8372ACPZ-R71 |
| 厂家： | 
ADI |
| 描述： | 41 dB Range, 1 dB Step Size, Programmable Dual VGA |
| 文件： | 总16页 (文件大小：722K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
41 dB Range, 1 dB Step Size,
Programmable Dual VGA
AD8372
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Dual independent digitally controlled VGA
Differential input and output
ENB1
IPC1
REF2
OPC1
AD8372
150 Ω differential input
INC1
ONC1
RXT2
Open-collector differential output
7.8 dB noise figure to 100 MHz @ maximum gain
HD2/HD3 better than 77 dBc for 1 V p-p differential output
−3 dB bandwidth of 150 MHz
RXT2
CHANNEL 1
POSTAMP
CLK1
SDO1
SDI1
CLK2
SDO2
SDI2
REGISTERS
AND
GAIN DECODER
LCH1
41 dB gain range
LCH2
1 dB step size 0.2 dB
Serial 8-bit bidirectional SPI control interface
Wide input dynamic range
Pin-programmable output stage
Power-down feature
Single 5 V supply: 106 mA per channel
32-lead LFCSP, 5 mm × 5 mm package
OPC2
ONC2
ENB2
IPC2
INC2
CHANNEL 2
POSTAMP
REF1
Figure 1.
APPLICATIONS
Differential ADC drivers
CMTS upstream direct sampling receivers
CATV modem signal scaling
Generic RF/IF gain stages
Single-ended-to-differential conversion
GENERAL DESCRIPTION
The AD8372 is a dual, digitally controlled, variable gain
amplifier that provides precise gain control, high IP3, and
low noise figure. The excellent distortion performance and
moderate signal bandwidth make the AD8372 a suitable
gain control device for a variety of multichannel receiver
applications.
setting resistors can be adjusted to manipulate the gain and
distortion performance of each channel. This is a flexible
feature in applications where it is desirable to trade off distortion
performance for lower power consumption.
The AD8372 is powered on by applying the appropriate logic
level to the ENB1, ENB2 pins. When powered down, the AD8372
consumes less than 2.6 mA and offers excellent input-to-output
isolation. The gain setting is preserved when powered down.
For wide input dynamic range applications, the AD8372
provides a broad 41 dB gain range. The gain is programmed
through a bidirectional 4-pin serial interface. The serial inter-
face consists of a clock, latch, data input, and data output lines
for each channel.
Fabricated on an Analog Devices high frequency BiCMOS
process, the AD8372 provides precise gain adjustment capabilities
with good distortion performance. The quiescent current of the
AD8372 is typically 106 mA per channel. The AD8372 amplifier
comes in a compact, thermally enhanced 5 mm × 5 mm 32-lead
LFCSP package and operates over the temperature range of
−40°C to +85°C.
The AD8372 provides the ability to set the transconductance of
the output stage using a single external resistor. The RXT1 and
RXT2 pins provide a band gap derived stable reference voltage
of 1.56 V. Typically 2.0 kΩ shunt resistors to ground are used to
set the maximum gain to a nominal value of 31 dB. The current
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD8372
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 10
Single-Ended and Differential Signals..................................... 10
Passive Filter Techniques........................................................... 10
Digital Gain Control.................................................................. 10
Driving Analog-to-Digital Converters.................................... 10
Evaluation Board Schematic ......................................................... 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Serial Control Interface Timing ................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
REVISION HISTORY
11/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8372
SPECIFICATIONS
VS = 5 V, T = 25°C, ZS = 150 ꢀ, ZL = 250 ꢀ at 35 MHz, 1 V p-p differential output, RXT1 = RXT2 = 2.0 kΩ, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
INPUT STAGE
VOUT < 1 V p-p, CLOAD < 3pF
130
MHz
Pin IPCI, Pin INC1, Pin IPC2, and Pin INC2
Maximum Input Swing at Each Input Pin
Input Resistance
Common-Mode Input Voltage
CMRR
5
V p-p
Ω
V
Differential
150
2.4
55
Gain code = 1x101010 (max gain)
dB
GAIN
Maximum Voltage Gain
Minimum Voltage Gain
Gain Step Size
Gain Step Accuracy
Gain Flatness
Gain code = 1x101010
Gain code = 1x000001
32
dB
dB
dB
dB
dB
mdB/°C
ns
−9
1.0
0.3
0.7
7.5
20
From gain code 1x000001 to 1x101010
From gain code 1x000001 to 1x101010
Gain code = 1x101010, from 5 MHz to 65MHz
Gain code = 1x101010
For 6 dB gain step, 10% settling
Pin OPCI, Pin ONC1, Pin OPC2, and Pin ONC2
At P1dB, gain code = 1x101010
Differential
Gain Temperature Sensitivity
Step Response
OUTPUT STAGE
Output Voltage Swing
Output Resistance
Channel Isolation
9
3.5
55
V p-p
kΩ
dB
Measured at differential output for differential input
applied to alternate channel
NOISE/HARMONIC PERFORMANCE
5 MHz
Gain code = 1x101010 (max gain)
Gain code = 1x101010 (max gain)
Gain code = 1x101010 (max gain)
Gain code = 1x101010
Noise Figure
7.8
79
91
32
18.2
dB
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
35 MHz
dBc
dBc
dBm
dBm
Noise Figure
7.8
79
87
35
18.1
dB
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
65 MHz
dBc
dBc
dBm
dBm
Noise Figure
7.9
78
85
35
17.9
dB
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
85 MHz
dBc
dBc
dBm
dBm
Noise Figure
8.1
77
85
35
17.7
dB
Second Harmonic
Third Harmonic
Output IP3
dBc
dBc
dBm
dBm
Output 1 dB Compression Point
Rev. 0 | Page 3 of 16
AD8372
Parameter
Conditions
Min
Typ
Max
Unit
POWER INTERFACE
Supply Voltage
4.5
5.5
V
Quiescent Current per Channel
Thermal connection made to exposed paddle under
device
−40°C ≤ TA ≤ +85°C
ENB1 and ENB2 low
−40°C ≤ TA ≤ +85°C
106
1.2
mA
vs. Temperature
Power-Down Current, Both Channels
vs. Temperature
135
1.3
0.8
mA
mA
mA
ENABLE INTERFACE
Enable Threshold
ENB1, ENB2 Input Bias Current
GAIN CONTROL INTERFACE
Pin ENB1 and Pin ENB2
Minimum voltage to enable the device
ENB1, ENB2 = 0 V
V
nA
400
Pin CLK1, Pin CLK2, Pin SDI1, Pin SDI2, Pin SDO1, Pin
SDO2, Pin LCH1, and Pin LCH2
VIH
Minimum voltage for a logic high
2.4
V
Input Bias Current
Serial Port Output Feedthrough
400
−60
nA
dB
Worse-case feedthrough from CLK1, CLK2, SDI1,
SDI2, SDO1, SDO2, LCH1, LCH2 to OPC1 and ONC2,
or OPC2 and ONC2
Table 2. Gain Code vs. Voltage Gain Look-Up Table
8-Bit Binary Gain Code1
RW DC 000000
RW DC 000001
RW DC 000010
RW DC 000011
RW DC 000100
RW DC 000101
RW DC 000110
RW DC 000111
RW DC 001000
RW DC 001001
RW DC 001010
RW DC 001011
RW DC 001100
RW DC 001101
RW DC 001110
RW DC 001111
RW DC 010000
RW DC 010001
RW DC 010010
RW DC 010011
RW DC 010100
RW DC 010101
Voltage Gain (dB)
8-Bit Binary Gain Code1
RW DC 010110
RW DC 010111
RW DC 011000
RW DC 011001
RW DC 011010
RW DC 011011
RW DC 011100
RW DC 011101
RW DC 011110
RW DC 011111
RW DC 100000
RW DC 100001
RW DC 100010
RW DC 100011
RW DC 100100
RW DC 100101
RW DC 100110
RW DC 100111
RW DC 101000
RW DC 101001
RW DC 101010
RW DC 101011
Voltage Gain (dB)
< −60
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
+1
+2
+3
+4
+5
+6
+7
+8
+9
+10
+11
+12
+13
+14
+15
+16
+17
+18
+19
+20
+21
+22
+23
+24
+25
+26
+27
+28
+29
+30
+31
+32
< −60
1 RW is the Read/Write bit, RW = 0 for read mode, RW = 1 for write mode. DC is
the Don’t Care bit.
Rev. 0 | Page 4 of 16
AD8372
SERIAL CONTROL INTERFACE TIMING
tCLK
tPW
CLK1 OR CLK2
LCH1 OR LCH2
tLH
tLS
tDS
tDH
SDI1 OR SDI2
NOTES
WRITE BIT
DON'T CARE
LSB
LSB + 1
LSB + 2
MSB – 2
MSB – 1
MSB
1. THE FIRST SDI BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL GAIN WORD REGISTER. FOR A
WRITE OPERATION, THE FIRST BIT SHOULD BE A HIGH LOGIC LEVEL, FOR A READ OPERATION THE FIRST BIT SHOULD BE A LOGIC 1.
THE GAIN WORD BIT IS THEN REGISTERED INTO THE SDI PIN ON THE NEXT RISING CLOCK.
Figure 2. Write Mode Timing Diagram
tLH
tPW
tCLK
tD
CLK1 OR CLK2
LCH1 OR LCH2
SDI1 OR SDI2
tLS
tDS
tDH
READ BIT
DC
LSB
DC
DC
LSB + 2
DC
DC
DC
MSB
DC
SDO1 OR SDO2
NOTES
LSB + 1
MSB – 2
MSB – 1
1. THE GAIN WORD BIT IS UPDATED AT THE SDO PIN ON THE FALLING CLOCK EDGE.
Figure 3. Read Mode Timing Diagram
Table 3. Serial Programming Timing Parameters
Parameter
Min
10
Unit
ns
Clock Pulse Width (tPW
)
Clock Period (tCK
Write Mode
)
20
ns
Setup Time Data vs. Clock (tDS
Hold Time Data vs. Clock (tDH
Setup Time Latch vs. Clock (tLS)
)
0.0
1.6
−1.8
2.0
ns
ns
ns
ns
)
Hold Time Latch vs. Clock (tLH
Read Mode
)
Clock to Data Out (tD)
4.5
ns
Rev. 0 | Page 5 of 16
AD8372
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage, VS
5.5 V
ENB1, ENB2, SDI1, SDI2, SDO1, SDO2,
CLK1, CLK2, LCH1, LCH2
VS + 500 mV
Differential Input Voltage, VIPC1 − VINC1
,
V p-p
V
IPC2 − VINC2
Internal Power Dissipation
1.4 W
θJA (Exposed Paddle Soldered Down)
θJC (At Exposed Paddle)
34.6°C/W1, 2
3.6°C/W2
ESD CAUTION
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
150°C
−40°C to +85°C
−65°C to +150°C
1 Still air.
2 All values are modeled using a standard 4-layer JEDEC test board with the
pad soldered to the board and thermal vias in the board.
Rev. 0 | Page 6 of 16
AD8372
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVS1
LCH1
SDI1
CLK1
CLK2
SDI2
1
2
3
4
5
6
7
8
24 OPC1
23 ONC1
22 AGD1
21 SDO1
20 SDO2
19 AGD2
18 ONC2
17 OPC2
PIN 1
INDICATOR
AD8372
TOP VIEW
(Not to Scale)
LCH2
DVS2
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
DVS1
LCH1
SDI1
CLK1
CLK2
SDI2
LCH2
DVS2
DGD2
INC2
Description
1
2
3
4
5
6
7
8
Digital Supply Pin for Channel 1
Latch Input for Channel 1
Serial Data Input for Channel 1
Clock Input for Channel 1
Clock Input for Channel 2
Serial Data Input for Channel 2
Serial Data Input for Channel 2 Latch Input for Channel 2
Digital Supply Pin for Channel 2
Digital Ground for Channel 2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Negative Input for Channel 2
IPC2
REF2
Positive Input for Channel 2
Reference Voltage for Channel 2
External Bias Setting Resistor Connection for Channel 2
Analog Ground for Channel 2
Chip Enable Pin for Channel 2
Analog Supply Pin for Channel 2
Positive Output for Channel 2
Negative Output for Channel 2
Analog Ground for Channel 2
Serial Data Output for Channel 2
Serial Data Output for Channel 1
Analog Ground for Channel 1
Negative Output for Channel 1
Positive Output for Channel 1
Analog Supply Pin for Channel 1
Chip Enable Pin for Channel 1
Analog Ground for Channel 1
External Bias Setting Resistor Connection for Channel 1
Reference Voltage for Channel 1
Positive Input for Channel 1
RXT2
AGD2
ENB2
AVS2
OPC2
ONC2
AGD2
SDO2
SDO1
AGD1
ONC1
OPC1
AVS1
ENB1
AGD1
RXT1
REF1
IPC1
INC1
DGD1
Negative Input for Channel 1
Digital Ground for Channel 1
Rev. 0 | Page 7 of 16
AD8372
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, ZS = 150 Ω, ZL = 250 ꢀ, 1 V p-p differential output, both channels enabled, unless otherwise noted.
20
19
18
17
16
15
40
30
20
+25°C
10
+85°C
–40°C
0
–10
–20
–30
0
10
20
30
40
50
60
70
80
90
1M
10M
100M
1G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 8. P1dB, Maximum Gain
Figure 5. Gain vs. Frequency by Gain Code (All Codes),
Differential In, Differential Out
180
9
8
7
6
5
4
3
2
1
0
–60
–65
–70
–75
–80
–85
–90
–95
–100
160
140
120
100
80
HD2
HD3
60
40
20
0
0
100000000
200000000
300000000
0
10
20
30
40
50
60
70
80
90
50000000
150000000
250000000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. 2nd and 3rd Harmonic Distortion
Figure 9. Input Equivalent Parallel Impedance
100
90
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
OIP2 – A = 32
V
OIP2 – A = 10
V
OIP2 – A = –9
V
OIP3 – A = 10
OIP3 – A = 32
V
V
OIP3 – A = –9
V
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. OIP2 and OIP3
Figure 10. CMRR vs. Frequency
Rev. 0 | Page 8 of 16
AD8372
50
45
40
35
30
25
20
15
10
5
A
= 0dB
V
A
= 10dB
= 20dB
V
A
V
V
A
= 32dB
0
20ns/DIV
0
20
40
60
80
100 120 140 160 180 200
FREQUENCY (MHz)
Figure 11. Noise Figure vs. Frequency
Figure 13. AD8372 Response to 6 dB Step Change in Gain (Gain Register
Setting 36 to Setting 42); Falling Edge Shown is Serial Clock Input Edge
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 12. Isolation, Input to Opposite Output at Maximum Gain
(To calculate output to output gain, subtract 29 dB from this plot)
Rev. 0 | Page 9 of 16
AD8372
THEORY OF OPERATION
The AD8372 is a dual differential variable gain amplifier. Each
amplifier consists of a 150 Ω digitally controlled 6 dB attenuator
followed by a 1 dB vernier and a fixed gain transconductance
amplifier.
primarily to the use of differential signaling techniques to
cancel various distortion components in the device. In addition,
all ac characterization was done using differential signal paths.
Using this device with either the input or the output in a single-
ended circuit significantly degrades the overall performance of
the AD8372.
The differential output on each amplifier consists of a pair of
open-collector transistors. It is recommended that each open-
collector output be biased to +5 V with a high value inductor.
A 33 μH inductor, such as the Coilcraft® 1812LS-333XJL, is an
excellent choice for this component. A 250 Ω resistor should be
placed across the differential outputs to provide a current-to-
voltage conversion and as a source impedance for passive
filtering, post AD8372.
PASSIVE FILTER TECHNIQUES
The AD8372 has a 100 Ω differential input impedance. For
optimal performance, the differential output load should be
250 Ω. When designing passive filters around the AD8372,
these impedances must be taken into account.
DIGITAL GAIN CONTROL
The gain for each side is based on a 250 Ω differential load and
varies as the RLOAD changes per the following equations:
The digital gain control interface consists of four pins: SDI,
SDO, CLK, and LATCH. The interface is active when the
LATCH pin is shifted low. Gain words are written into the
AD8372 via the SDI pin, and read back from the SDO pin. The
first bit clocked into the data input pin determines whether the
interface is in write or read mode. The second bit is a don’t care
bit, while the remaining six bits program the gain. In read
mode, the SDO pin clocks out the 6-bit gain word, LSB to MSB.
The gain can be programmed between −9 dB and 32 dB in 1 dB
steps. Timing details are given in Figure 2 and Figure 3. The
gain code table is given in Table 3.
Gain = 20log(RLOAD/250), for voltage gain
Gain = 10log(RLOAD/250), for power gain
The dependency of the gain on the load is due to the open-
collector output stage that is biased using external chokes. The
inductance of the chokes and the resistance of the load deter-
mine the low frequency pole of the amplifier. The high frequency
pole is set by the parasitic capacitance of the chokes and outputs
in parallel with the output resistance.
The total supply current of 106 mA per side consists of 70 mA
for the combined outputs and about 36 mA through the power
supply pins. Each side has an external resistor (REXT) to ground
to set the transconductance of the output stage. For optimum
distortion, 106 mA total current per side is recommended,
making the REXT value about 2.0 kΩ. Each side has a 2.4 V
reference pin and that same common-mode voltage appears on
the inputs. This reference should be decoupled using a 0.1 μF
capacitor. The part can be powered down to less than 2.6 mA by
setting the ENB pin low for the appropriate side.
DRIVING ANALOG-TO-DIGITAL CONVERTERS
The AD8372 was designed with the intention of driving high
speed, high dynamic range ADCs. The circuit in Figure 14
represents a simplified front end of one-half of the AD8372 dual
VGA driving an AD9445 14-bit, 125 MHz analog-to-digital
converter. The input of the AD8372 is driven differentially
using a 1:3 impedance ratio transformer, which also matches
the 150 Ω input resistance to a 50 Ω source. The open-collector
outputs are biased through the 33 μH inductors and are ac-
coupled from the 142 Ω load resistors that, in parallel with the
2 kΩ input resistance of the ADC, provide a 250 Ω load for gain
accuracy. The ADC is ac-coupled from the 142 Ω resistors to
negate a dc affect on the input common-mode voltage of the
AD9445. Including the series 33 Ω resistors improves the
isolation of the AD8372 from the switching currents caused by
the ADC input sample and hold. The AD9445 represents a 2 kΩ
differential load and requires a 2 V p-p signal when VREF = 1 V
for a full-scale output. This circuit provides variable gain,
isolation, and source matching for the AD9445. Using this
circuit with the AD8372 in a gain of 32 dB (maximum gain), an
SFDR performance of 74.5 dBc is achieved at 85 MHz. See
Figure 15.
The noise figure of the AD8372 is 7.8 dB at maximum gain and
increases as the gain is reduced. The increase in noise figure is
equal to the reduction in gain.
The linearity of the part measured at the output is first-order
independent of the gain setting.
Layout considerations should include minimizing capacitance
on the outputs by avoiding ground planes under the chokes, and
equalizing the output line lengths for phase balance.
SINGLE-ENDED AND DIFFERENTIAL SIGNALS
The AD8372 was designed to be used by applying differential
signals to the inputs and using the differential output drive of
the device to drive the next device in the signal chain. The
excellent distortion performance of the AD8372 is due
Rev. 0 | Page 10 of 16
AD8372
5V
5V
33µH
142Ω
0.1µF
0.1µF 0.1µF
33Ω
33Ω
1:3
VIN+
VIN–
½
14
AD9445
AD8372
VGA
14-BIT ADC
50Ω
0.1µF
0.1µF 0.1µF
AC
33µH
142Ω
5V
Figure 14. AD8372 Driving an AD9445 ADC
0
–10
1
FUND: –1.053dBFS
SNR: 58.12dBc
2ND: –74.55dBc
3RD: –86.45dBc
4TH: –91.35dBc
5TH: –89.57dBc
6TH: –91.15dBc
SNRFS: 59.18dBc
THD: –73.99dBc
–20
SINAD: 58.01dBc
SFDR: 74.73dBc
WO SPUR: –85.5dBc
NOISE FLOOR: –101.3dB
–30
–40
–50
–60
2
–70
–80
3
5
6
4
–90
–100
–110
–120
–130
–140
–150
ENCODE: 105MHz
SAMPLES: 32768
FUND LEAK: 100
HARM LEAK: 3
DC LEAK: 6
ANALOG: 19.8766MHz
0
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
Figure 15. 74.5 dB SFDR Performance of the AD8372 Driving the AD9445 ADC
Rev. 0 | Page 11 of 16
AD8372
EVALUATION BOARD SCHEMATIC
1 4 0 1 - 7 0 5
2
1 1 8
H U 3 3
L 4
2
1 1 8
H U 3 3
L 3
2
1 1 8
H U 3 3
L 2
2
1 1 8
H U 3 3
L 1
1
A V S
2
A V S
B 1 E N
B 2 E N
D N A G
1 D A G
1 T R X
1 F R E
1 C I P
2 G A D
2 T R X
2 F R E
2 C I P
1 C I N
2 C I N
1 D D G
2 D D G
INC2
IPC1
I
P R
C
S
E
6
1
2
3
C
S E
I
P R
1
2
3
6
4
4
INC1
IPC2
W 3
W 4
W 5
W 6
W 7
W 8
Figure 16. AD8372 Evaluation Board Schematic
Rev. 0 | Page 12 of 16
AD8372
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 17. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Ordering
Quantity
Model
Package Description
Option
CP-32-2
CP-32-2
AD8372ACPZ-WP1
AD8372ACPZ-R71
AD8372-EVALZ1
−40°C to +85°C
−40°C to +85°C
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Waffle Pack
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7”Reel
Evaluation Board
1,500
1 Z = RoHS Compliant Part.
Rev. 0 | Page 13 of 16
AD8372
NOTES
Rev. 0 | Page 14 of 16
AD8372
NOTES
Rev. 0 | Page 15 of 16
AD8372
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07051-0-11/07(0)
Rev. 0 | Page 16 of 16
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