AD8389ACPZ [ADI]
Triple, 6-Channel LCD Timing Delay-Locked Loop; 三人间， 6通道LCD时序延迟锁定环
| 型号： | AD8389ACPZ |
| 厂家： | 
ADI |
| 描述： | Triple, 6-Channel LCD Timing Delay-Locked Loop |
| 文件： | 总12页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Triple, 6-Channel LCD Timing
Delay-Locked Loop
AD8389
PRODUCT FEATURES
High speed
Up to 85 MHz clock rate
Triple (R, G, B) output
Matched delay lines
Low power dissipation: 40 mW
Reference to rising or falling edge of MONITI input
Selectable loop delay
PRODUCT DESCRIPTION
The AD8389 is a triple 6-channel LCD microdisplay delay-
locked timing loop. As part of a closed-loop system, the AD8389
maintains a constant delay between the common input, DXI,
and each independent feedback reference, MONITxI.
The AD8389 consists of a selectable fixed delay element, a phase
detector, a charge pump, and six matched variable delay lines
per color. The phase detector, charge pump, and master delay
line form a closed loop when connected to a compatible LCD
microdisplay. Five additional delay lines track the master for a
complete set of matched timing signals.
Available in 48-lead 7 mm × 7 mm LFCSP
APPLICATIONS
LCD microdisplay horizontal timing
The AD8389 dissipates 40 mW nominal power. The AD8389 is
offered in a 48-lead 7 mm × 7 mm LFCSP package and operates
over the commercial temperature range of 0°C to 85°C.
FUNCTIONAL BLOCK DIAGRAM
AVDD(4) AVSS(4)
DRVDD(2) DRVSS(2)
AD8389
COMPEDGE
SLOW
PHASE
DETECTOR
CHARGE
PUMP
SELECTABLE
DELAY
VCONTR
MONITRI
DXRO
ENBX1RO
ENBX2RO
ENBX3RO
ENBX4RO
CLXRO
6
/
MATCHED VARIABLE
DELAY LINES (6-CHANNEL)
DXI
ENBX1I
ENBX2I
ENBX3I
ENBX4I
CLXI
6
PHASE
DETECTOR
CHARGE
PUMP
VCONTG
MONITGI
/
DXGO
ENBX1GO
ENBX2GO
ENBX3GO
ENBX4GO
CLXGO
6
/
MATCHED VARIABLE
DELAY LINES (6-CHANNEL)
PHASE
DETECTOR
CHARGE
PUMP
VCONTB
MONITBI
DXBO
ENBX1BO
ENBX2BO
ENBX3BO
ENBX4BO
CLXBO
6
/
MATCHED VARIABLE
DELAY LINES (6-CHANNEL)
INTERNAL
TIMING
CLK
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD8389
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Exposed Paddle............................................................................. 4
Maximum Power Dissipation ..................................................... 4
Pin Configuration and Function Descriptions............................. 5
Timing.................................................................................................6
Operating Principles .........................................................................7
Operation .......................................................................................7
Outline Dimensions..........................................................................9
Ordering Guide .............................................................................9
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 12
AD8389
SPECIFICATIONS
Table 1. @ 25°C, AVDD = DRVDD = 3.3 V, TMIN = 0°C, TMAX = 85°C, unless otherwise noted
Parameter
Conditions
Min
Typ
1.5
75
Max
Unit
LOGIC INPUTS
CIN
IIN
VIH
VIL
VTH
pF
µA
V
V
V
–2
2.0
AGND
+2
AVDD
0.8
OUTPUTS
VOH
VOL
IO = –2 µA
IO = +2 µA
DRVDD – 0.4
V
V
DVRSS + 0.4
TIMING SPECIFICATIONS
Operating Frequency
CLK, fCLK
60
85
(2t1)–1
(2t1)–1
MHz
Hz
Hz
CLXI, ENBX(1–4)I
DXI, MONITxI
Input Low Pulse Width, t1—All Inputs except CLK
DXI, MONITxI
280
30
4.7
4.7
2
ns
ns
ns
ns
ns
ns
ns
ENBX(1–4)I, CLXI
CLK High Pulse Width, t2
CLK Low Pulse Width, t3
CLK to DXI Setup Time, t4
Output Rise, Fall Times—tr, tf
Delay t5
Output Skew, t6
t5 ≤ 130 ns
t5 ≤ 170ns
t5 ≤ 230ns
CL = 30 pF
DXI to DXxO
CL = 30 pF
5
350
22
0.3
0.45
0.7
2.5
3.4
5
ns
ns
ns
t5 ≤ 230ns
Loop Delay, t7
COMPEDGE = H, SLOW = H
COMPEDGE = H, SLOW = L
COMPEDGE = L, SLOW = H
COMPEDGE = L, SLOW = L
POWER SUPPLIES
AVDD Operating Range
DRVDD Operating Range
Total Operating Current
Power Dissipation
Operating Temperature
9/(fCLK) + t4
15/(fCLK) + t4
26/(fCLK) + t4
32/(fCLK) + t4
ns
ns
ns
ns
3
3
3.6
3.6
V
V
mA
mW
°C
fCLK = 75 MHz, CL = 30 pF
fCLK = 75 MHz, CL = 30 pF
11
40
0
85
Rev. 0 | Page 3 of 12
AD8389
ABSOLUTE MAXIMUM RATINGS
Table 2. AD8389 Stress Ratings1
Parameter
EXPOSED PADDLE
Rating
To ensure high reliability, the exposed paddle must be soldered
to GND.
Supply Voltages
AVDDx – AVSSx
DRVDDx – DRVSSx
3.9 V
3.9 V
MAXIMUM POWER DISSIPATION
Input Voltages
The maximum power that can be safely dissipated by the
AD8389 is limited by its junction temperature. The maximum
safe junction temperature for plastic encapsulated devices as
determined by the glass transition temperature of the plastic is
approximately 150°C. Exceeding this limit temporarily may
cause a shift in the parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can
result in device failure.
Maximum Digital Input Voltage
Minimum Digital Input Voltage
Internal Power Dissipation2
LFCSP Package @ TA = 25°C
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 10 sec)
AVDD + 0.3 V
AVSS – 0.3 V
4.8 W
0°C to 85°C
–65°C to +125°C
300°C
1 Stresses above those listed under the Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to the absolute maximum ratings for extended periods may
reduce device reliability.
To ensure operation within the specified operating temperature
range, it is necessary to limit the maximum power dissipation as
follows:
2 48-Lead LFCSP Package:
θJA = 26°C/W (JEDEC Standard 4-layer PCB in still air)
θJC = 20°C/W
P
DMAX = (TJMAX – TA)/θJA
5.0
4.5
4.0
3.5
3.0
2.5
2.0
25
35
45
55
65
75
85
95
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 4 of 12
AD8389
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVSS
MONITRI
MONITGI
MONITBI
AVDD
1
2
3
4
5
6
7
8
9
36 DXRO
PIN 1
INDICATOR
35 ENBX1RO
34 ENBX2RO
33 ENBX3RO
32 ENBX4RO
31 CLXRO
AD8389
AVSS
TOP VIEW
VCONTR
AVDD
30 DXGO
(Not to Scale)
29 ENBX1GO
28 ENBX2GO
27 ENBX3GO
26 ENBX4GO
25 CLXGO
48-LEAD LFCSP
7mm × 7mm
AVSS
VCONTG 10
VCONTB 11
AVSS 12
NC =
NO CONNECT
Figure 3. 48-Lead LFCSP, 7 mm × 7 mm Pin Configuration
Table 3. Pin Function Descriptions
Mnemonic
AVDD, DRVDD
AVSS, DRVSS
CLK
Function
Power Supply
Ground
Description
Power Supply.
Ground.
Clock Input. Active edge is the rising edge.
Clock
COMPEDGE
Edge Select
When set HIGH, the phase detector compares the falling edge of DXIN with the rising edge of
MONITxI. When set LOW, the phase detector compares the rising edge of DXIN with the falling
edge of MONITxI.
SLOW
Delay Select
When set HIGH and COMPEDGE = HIGH, the delay between the falling edges of DXI and the
rising edges of MONITI is maintained at 9/(fCLK) + t4. The delay is maintained at 26/(fCLK) + t4 when
COMPEDGE = LOW. When set LOW and COMPEDGE = HIGH, the delay between the falling edges
of DXI and the rising edges of MONITI is maintained at 15/(fCLK) + t4. The delay is maintained at
32/(fCLK) + t4 with COMPEDGE = LOW.
DXI
CLXI
Reference Input
Input
LCD Timing Input from the Image Processor. Used as the input to all phase detectors.
LCD Timing Input from the Image Processor.
ENBX(1–4)I
MONITxI
Inputs
Feedback Inputs
LCD Timing Inputs from the Image Processor.
Inputs from the LCD. Used as the feedback input to each phase detector. When the AD8389
forms part of a closed loop, it maintains a constant delay between the DXI input and this
reference input pin.
DXxO
CLXxO
ENBX(1–4)xO
VCONTx
Delayed Outputs
Delayed Outputs
Delayed Outputs
Control Voltage
200 pF capacitors connected between these pins and the AVSS plane are required for proper
operation of the internal charge pump.
Rev. 0 | Page 5 of 12
AD8389
TIMING
Table 4. Timing Specifications
Parameter
Conditions
Min
Typ
Max
Unit
Operating Frequency
CLK, fCLK
CLXI, ENBX(1–4)I
60
75
85
(2t1)–1
(2t1)–1
MHz
Hz
Hz
DXI, MONITxI
Input Low Pulse Width, t1—All Inputs except CLK
DXI, MONITxI
ENBX(1–4)I, CLXI
CLK High Pulse Width—t2
CLK Low Pulse Width—t3
CLK to DXI Setup Time—t4
Output Rise, Fall Time—tr, tf
Delay—t5
280
30
4.7
4.7
2
ns
ns
ns
ns
ns
ns
ns
t5 ≤ 230ns
CL = 30 pF
DXI to DXxO
CL = 30 pF
5
350
22
Output Skew— t6
t5 ≤ 130 ns
t5 ≤ 170ns
t5 ≤ 230ns
0.3
0.45
0.7
2.5
3.4
5
ns
ns
ns
Loop Delay, t7
COMPEDGE = H, SLOW = H
COMPEDGE = H, SLOW = L
COMPEDGE = L, SLOW = H
COMPEDGE = L, SLOW = L
9/(fCLK) + t4
15/(fCLK) + t4
26/(fCLK) + t4
32/(fCLK) + t4
ns
ns
ns
ns
t3
DXI
t2
V
V
CLK
TH
TH
t7
MONITxI
DXO
t4
t4
tEXT
DXI
t5
t1
Figure 4. CLK and DXI Timing
DXxO
CLXxO
ENBX(1–4)XO
t6
Figure 5. Input and Output Waveforms at COMPEDGE = HIGH
Rev. 0 | Page 6 of 12
AD8389
OPERATING PRINCIPLES
MON
MONITO
DXI
MONITRI
MONITI
DXO
DX
DXI
DXRO
H SHIFT
REGISTER
CLXIN,
ENBX(1–4)I
CLXO,
ENBX(1–4)O
CLX,
ENBX(1–4)
CLXRO,
ENBX(1–4)O
VCONTR
AD8384/AD8385
RED LCD
200pF
LEVEL SHIFTER SECTION
AD8389
Figure 6. AD8389 Application in the Red Channel of an LCD Projection System
The image quality of an LCD system is dependent on the timing
relationship between the control inputs, DX, CLX, ENBX(1–4),
and the video channels.
OPERATION
As part of a closed loop, the AD8389 maintains a constant delay
between the common input, DXI, and each independent
feedback reference, MONITxI. The block diagram of such
closed-loop system is shown in Figure 6.
TFT delay and switching speed variations, due to temperature
variations and LCD aging, degrade image quality if not
compensated.
A constant delay, t7, selected via the COMPEDGE and SLOW
control inputs, is applied to the DXI input to approximate the
nominal, initially expected total delay, t7, through the level
shifters and the LCD as shown in Table 5.
An internal reference TFT connected to an internal pull-up
resistor, as shown in Figure 6, characterizes the internal S/H
TFTs of the LCD and monitors switching speed and delay
variations due to aging and temperature. When the MON
output of an LCD that includes such an internal reference TFT
is connected to the reference input of the AD8389 delay-locked
timing loop, continuously optimized timing of the LCD is
maintained automatically.
Table 5
COMPEDGE
1
1
SLOW
Constant Delay
DX
0
1
15/fCLK + t4
9/fCLK + t4
CONSTANT
MONITRI
0
0
0
1
32/fCLK + t4
26/fCLK + t4
CONSTANT
DX
MONITRI
Rev. 0 | Page 7 of 12
AD8389
The phase detector compares the delayed DX and MONITxI
reference inputs and automatically adjusts the variable delay (t5),
maintaining the constant delay (t7) between the active edges of
DX and MONITxI. Five matched delay lines maintain the phase
relationship between DXxO, CLXxO, and ENBX(1–4)xO.
CLK
CONSTANT
DX
MONITRI
CLX
When the loop is locked, t7 = t5 + tEXT, where tEXT is the total
delay through the level shifter and the LCD.
ENBX1
ENBX2
ENBX3
ENBX4
The external delay of a typical system is the sum of the level
shifter delay (20 ns typical) and the LCD delay, (typically in the
range of 20 ns to 120 ns). At a 75 MHz operating clock
frequency, the maximum expected total delay of 140 ns is equal
to 10.5 clock cycles, requiring COMPEDGE = 1, SLOW = 0 for
systems using negative active edge for DX.
DXO
MONITI
CLXO
ENBX1O
ENBX2O
ENBX3O
ENBX4O
Figure 7. Typical Input Waveforms at the AD8389 and at the LCD.
COMPEDGE = HIGH.
Rev. 0 | Page 8 of 12
AD8389
OUTLINE DIMENSIONS
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
5.25
5.10 SQ
4.95
6.75
BSC SQ
TOP
VIEW
BOTTOM
VIEW
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 8. 48-Lead Frame Chip Scale Package [LFCSP] (CP-48)
ORDERING GUIDE
Model
AD8389ACPZ1
Temperature Range
Package Description
Package Option
CP-48
0°C to 85°C
48-Lead Lead Frame Chip Scale Package
1
Z = lead-free.
Rev. 0 | Page 9 of 12
AD8389
NOTES
Rev. 0 | Page 10 of 12
AD8389
NOTES
Rev. 0 | Page 11 of 12
AD8389
NOTES
©
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04515–0–10/03(0)
Rev. 0 | Page 12 of 12
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