AD8420ARMZ [ADI]
Wide Supply Range, Micropower,; 宽电源电压范围，微功耗，
| 型号： | AD8420ARMZ |
| 厂家： | 
ADI |
| 描述： | Wide Supply Range, Micropower, |
| 文件： | 总28页 (文件大小：513K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wide Supply Range, Micropower,
Rail-to-Rail Instrumentation Amplifier
AD8420
Data Sheet
FEATURES
PIN CONFIGURATION
AD8420
Maximum supply current: 80 μA
Minimum CMRR: 100 dB
Drives heavy capacitive loads: ~700 pF
Rail-to-rail output
Input voltage range goes below ground
Gain set with 2 external resistors
Can achieve low gain drift at any gain
Very wide power supply range
Single supply: 2.7 V to 36 V
NC
+IN
–IN
1
2
3
4
8
7
6
5
V
OUT
–
+
FB
+
–
REF
TOP VIEW
(Not to Scale)
–V
+V
S
S
Figure 1.
Table 1. Instrumentation Amplifiers by Category1
Dual supply: 2.7 V to 18 V
Bandwidth (G = 100): 2.5 kHz
Input voltage noise: 55 nV/√Hz
High dc precision
Maximum offset voltage: 125 μV
Maximum offset drift: 1 μV/°C
Maximum differential input voltage: 1 V
8-lead MSOP package
Zero
Military Low
Grade Power
Digital
Gain
General Purpose Drift
AD8221, AD8222
AD8220, AD8224
AD8231 AD620
AD8290 AD621
AD8420
AD8235,
AD8236
AD627
AD8226,
AD8227
AD8250
AD8251
AD8226, AD8227
AD8228
AD8293 AD524
AD8553 AD526
AD8253
AD8231
AD8295, AD8224
AD8556 AD624
AD8557
AD623
AD8223
APPLICATIONS
1 See www.analog.com for the latest instrumentation amplifiers.
Bridge amplifiers
Pressure measurement
Medical instrumentation
Portable data acquisition
Multichannel systems
GENERAL DESCRIPTION
Single-supply operation, micropower current consumption, and
rail-to-rail output swing make the AD8420 ideal for battery-
powered applications. Its rail-to-rail output stage maximizes
dynamic range when operating from low supply voltages. Dual-
supply operation (±±1 ꢀV and low power consumption make
the AD8420 ideal for a wide variety of applications in medical
or industrial instrumentation.
The AD8420 is a low cost, micropower, wide supply range,
instrumentation amplifier with a rail-to-rail output and a novel
architecture that allows for extremely flexible design. It is optimized
to amplify small differential voltages in the presence of large
common-mode signals.
The AD8420 is based on an indirect current feedback architecture
that gives it an excellent input common-mode range. Unlike
conventional instrumentation amplifiers, the AD8420 can easily
amplify signals at or even slightly below ground without requiring
dual supplies. The AD8420 has rail-to-rail output, and the output
voltage swing is completely independent of the input common-
mode voltage.
The AD8420 is available in an 8-lead MSOP package. Performance
is specified over the full temperature range of −40°C to +81°C,
and the part is operational from −40°C to +±21°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
AD8420
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. ±
Gain Accuracy ............................................................................ 20
Input ꢀoltage Range................................................................... 20
Input Protection ......................................................................... 20
Layout .......................................................................................... 2±
Driving the Reference Pin......................................................... 2±
Input Bias Current Return Path ............................................... 22
Radio Frequency Interference (RFIV........................................ 22
Output Buffering ........................................................................ 23
Applications Information.............................................................. 24
AD8420 in Electrocardiography (ECGV.................................. 24
Classic Bridge Circuit ................................................................ 21
4 mA to 20 mA Single-Supply Receiver .................................. 21
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Applications....................................................................................... ±
Pin Configuration............................................................................. ±
General Description......................................................................... ±
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... ±9
Architecture................................................................................. ±9
Setting the Gain .......................................................................... ±9
REVISION HISTORY
3/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
AD8420
SPECIFICATIONS
+ꢀS = +1 ꢀ, −ꢀS = 0 ꢀ, ꢀREF = 0 ꢀ, ꢀ+IN = 0 ꢀ, ꢀ−IN = 0 ꢀ, TA = 21°C, G = ± to ±000, RL = 20 kΩ, specifications referred to input, unless
otherwise noted. All Table 2 limits are valid from ꢀS = 3 ꢀ to ꢀS = ±1 ꢀ, unless otherwise specified.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR DC to 60 Hz
CMRR at 1 kHz
NOISE
VCM = 0 V to 2.7 V
100
100
dB
dB
Voltage Noise
Spectral Density
Peak to Peak
f = 1 kHz, VDIFF ≤ 100 mV
f = 0.1 Hz to 10 Hz, VDIFF ≤ 100 mV
55
1.5
nV/√Hz
μV p-p
Current Noise
Spectral Density
Peak to Peak
f = 1 kHz
f = 0.1 Hz to 10 Hz
80
3
fA/√Hz
pA p-p
VOLTAGE OFFSET
Offset
VS = 3 V to VS = 5 V
VS = 5 V
TA = −40°C to +85°C
VS = 2.7 V to 5 V
125
150
1
μV
μV
μV/°C
dB
Average Temperature Coefficient
Offset RTI vs. Supply (PSR)
INPUTS
86
Valid for REF and FB pair, as well
as +IN and −IN
TA = +25°C
TA = +85°C
TA = −40°C
TA = −40°C to +85°C
TA = +25°C
TA = +85°C
Input Bias Current1
20
30
27
24
30
nA
nA
nA
pA/°C
nA
Average Temperature Coefficient
Input Offset Current
1
1
1
nA
nA
TA = −40°C
Average Temperature Coefficient
Input Impedance
TA = −40°C to +85°C
0.5
pA/°C
Differential
130||2
MΩ||pF
Common Mode
1000||2
MΩ||pF
Differential Input Operating Voltage
Input Operating Voltage (+IN, −IN, REF, or FB)
TA = –40°C to +85°C
TA = +25°C
TA = +85°C
−1
+1
V
V
V
V
−VS − 0.15
−VS − 0.05
−VS − 0.2
+VS − 2.2
+VS − 1.8
+VS − 2.7
TA = –40°C
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1
G = 10
G = 100
G =1000
Settling Time 0.01%
G = 1
G = 10
G = 100
250
25
2.5
kHz
kHz
kHz
kHz
0.25
VS = 5 V
−1 V to +1 V output step
−4.5 V to +4.5 V output step
−4.5 V to +4.5 V output step
3
130
1
μs
μs
ms
V/μs
Slew Rate
1
Rev. 0 | Page 3 of 28
AD8420
Data Sheet
Parameter
GAIN2
Test Conditions/Comments
Min
Typ
Max
Unit
G = 1 + (R2/R1)
Gain Range
Gain Error
G = 1
G = 10 to 1000
Gain vs. Temperature
OUTPUT
1
1000
V/V
VOUT = 0.1 V to 1.1 V, VREF = 0.1 V
VOUT = 0.2 V to 4.8 V
TA = −40°C to +85°C
0.02
0.1
10
%
%
0.05
ppm/°C
Output Swing
VS = 5 V, RL = 10 kΩ to midsupply
VS = 5 V, RL = 20 kΩ to ground
TA = +25°C
−VS + 0.1
−VS + 0.1
−VS + 0.1
+VS − 0.15
+VS − 0.2
+VS − 0.15
V
V
V
TA = +85°C
TA = −40°C
Short-Circuit Current
POWER SUPPLY
Operating Range
10
70
mA
Single-supply operation3
2.7
55
36
V
Quiescent Current
VS = 5 V
TA = +25°C
TA = +85°C
TA = −40°C
80
95
65
μA
μA
μA
TEMPERATURE RANGE
Specified
Operational4
−40
−40
+85
+125
°C
°C
1 The input stage uses PNP transistors; therefore, input bias current always flows out of the part.
2 For G > 1, errors from External Resistor R1 and External Resistor R2 should be considered in addition to these specifications, including error from FB pin bias current.
3 Minimum supply voltage indicated for V+IN, V−IN, and VREF = 0 V.
4 See the Typical Performance Characteristics section for operation between 85°C and 125°C.
Rev. 0 | Page 4 of 28
Data Sheet
AD8420
+ꢀS = +±1 ꢀ, −ꢀS = −±1 ꢀ, ꢀREF = 0 ꢀ, TA = 21°C, G = ± to ±000, RL = 20 kΩ, specifications referred to input, unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR DC to 60 Hz
CMRR at 1 kHz
VCM = −10 V to +10 V
100
100
dB
dB
NOISE
Voltage Noise
Spectral Density
Peak to Peak
f = 1 kHz, VDIFF ≤ 100 mV
f = 0.1 Hz to 10 Hz, VDIFF ≤ 100 mV
55
1.5
nV/√Hz
μV p-p
Current Noise
Spectral Density
Peak to Peak
f = 1 kHz
f = 0.1 Hz to 10 Hz
80
3
fA/√Hz
pA p-p
VOLTAGE OFFSET
Offset
Average Temperature Coefficient
Offset RTI vs. Supply (PSR)
INPUTS
VS = 15 V1
TA = −40°C to +85°C
VS = 15 V
250
1
μV
μV/°C
dB
100
Valid for REF and FB pair, as well
as +IN and −IN
TA = +25°C
TA = +85°C
TA = −40°C
TA = −40°C to +85°C
TA = +25°C
TA = +85°C
Input Bias Current2
20
30
27
24
30
nA
nA
nA
pA/°C
nA
Average Temperature Coefficient
Input Offset Current
1
1
1
nA
nA
TA = −40°C
Average Temperature Coefficient
Input Impedance
TA = −40°C to +85°C
0.5
pA/°C
Differential
130||3
MΩ||pF
Common Mode
1000||3
MΩ||pF
Differential Input Operating Voltage
Input Operating Voltage (+IN, −IN, REF, or FB)
TA = −40°C to +85°C
TA = +25°C
TA = +85°C
−1
1
V
V
V
V
−VS − 0.15
−VS − 0.05
−VS − 0.2
+VS − 2.2
+VS − 1.8
+VS − 2.7
TA = −40°C
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1
250
25
2.5
kHz
kHz
kHz
kHz
G = 10
G = 100
G =1000
0.25
Settling Time 0.01%
G = 1
G = 10
G = 100
Slew Rate
−1 V to +1 V output step
−5 V to +5 V output step
−5 V to +5 V output step
3
130
1
μs
μs
ms
V/μs
1
GAIN3
G = 1 + (R2/R1)
Gain Range
Gain Error
1
1000
V/V
G = 1
G = 10 to 1000
Gain vs. Temperature
VOUT
VOUT
=
=
1 V
10 V
0.02
0.1
10
%
%
0.05
TA = −40°C to +85°C
ppm/°C
Rev. 0 | Page 5 of 28
AD8420
Data Sheet
Parameter
OUTPUT
Test Conditions/Comments
Min
Typ
Max
Unit
Output Swing
RL = 20 kΩ to Ground
TA = +25°C
TA = +85°C
TA = –40°C
−VS + 0.13
−VS + 0.15
−VS + 0.11
+VS − 0.2
+VS − 0.23
+VS − 0.16
V
V
V
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
10
85
mA
Dual-supply operation4
VS = 15 V
TA = +25°C
TA = +85°C
TA = −40°C
2.7
70
18
V
100
120
90
μA
μA
μA
TEMPERATURE RANGE
Specified
Operational5
−40
−40
+85
+125
°C
°C
1 See the Typical Performance Characteristics section for the offset voltage vs. supply.
2 The input stage uses PNP transistors; therefore, input bias current always flows out of the part.
3 For G > 1, errors from External Resistor R1 and External Resistor R2 should be considered in addition to these specifications, including error from FB pin bias current.
4 Minimum positive supply voltage indicated for V+IN, V−IN, and VREF = 0 V. With V+IN, V−IN, and VREF = −VS, minimum supply is 1.35 V.
5 See the Typical Performance Characteristics section for operation between 85°C and 125°C.
Rev. 0 | Page 6 of 28
Data Sheet
AD8420
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
θJA is specified for a device in free air.
Parameter
Rating
Supply Voltage
18 V
Table 5.
Output Short-Circuit Current
Maximum Voltage at −IN or +IN
Minimum Voltage at −IN or +IN
Maximum Voltage at REF or FB
Minimum Voltage at REF or FB
Storage Temperature Range
ESD
Indefinite
−VS + 40 V
−VS − 0.5 V
+VS + 0.5 V
−VS − 0.5 V
−65°C to +150°C
Package
θJA
Unit
8-Lead MSOP, 4-Layer JEDEC Board
135
°C/W
ESD CAUTION
Human Body Model
Charge Device Model
Machine Model
2.5 kV
1.5 kV
0.1 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 28
AD8420
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8420
NC
+IN
–IN
1
2
3
4
8
7
6
5
V
OUT
–
+
FB
+
–
REF
TOP VIEW
(Not to Scale)
–V
+V
S
S
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
NC
This pin is not connected internally. For best CMRR vs. frequency and leakage performance, connect this pin to
negative supply.
2
3
4
5
6
7
8
+IN
−IN
−VS
+VS
REF
FB
Positive Input.
Negative Input
Negative Supply.
Positive Supply.
Reference Input.
Feedback Input.
Output.
VOUT
Rev. 0 | Page 8 of 28
Data Sheet
AD8420
TYPICAL PERFORMANCE CHARACTERISTICS
T = 21°C, +ꢀS = 1 ꢀ, RL = 20 kꢁ, unless otherwise noted.
MEAN: 4.63764
SD: 1.09498
MEAN: –34.8195
SD: 31.3406
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
–150
–100
–50
0
50
100
150
0
2
4
6
8
10
V
(µV)
CMRR, ±15V (µV/V)
OS
Figure 3. Typical Distribution of Input Offset Voltage
Figure 6. Typical Distribution of CMRR
700
600
500
400
300
200
100
0
MEAN: 22.6643
SD: 0.6058
MEAN: 22.706
SD: 0.615728
700
600
500
400
300
200
100
0
20
21
22
23
24
25
20
21
22
23
24
25
POSITIVE BIAS CURRENT (nA)
g
POSITIVE BIAS CURRENT (nA)
m2
Figure 7. Typical Distribution of REF, FB Bias Current
Figure 4. Typical Distribution of Input Bias Current
1200
1000
800
600
400
200
0
1200
1000
800
600
400
200
0
MEAN: 0.000646761
SD: 0.111551
MEAN: 0.00144205
SD: 0.112088
–0.9
–0.6
–0.3
0
0.3
0.6
0.9
–0.9
–0.6
–0.3
0
0.3
0.6
0.9
g
OFFSET CURRENT (nA)
OFFSET CURRENT (nA)
m2
Figure 5. Typical Distribution of Input Offset Current
Figure 8. Typical Distribution of REF, FB Offset Current
Rev. 0 | Page 9 of 28
AD8420
Data Sheet
3.0
0.5
0.4
0.3
0.2
0.1
0
15
10
5
0.6
0.4
0.2
0
V
G = 1
= +5V
V = ±15V
S
G = 100
S
V
OUT
2.5
2.0
1.5
1.0
0.5
0
V
I
IN
OUT
I
IN
0
–5
–10
–15
–0.2
–0.4
–0.6
–0.1
–5
0
5
10
15
20
25
30
35
40
–20
–15
–10
–5
0
5
10
15
20
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 9. Input Overvoltage Performance, G = 1
Figure 12. Input Overvoltage Performance, G = 100, VS = 15 V
3
2
0.6
0.4
0.2
0
15
V
G = 1
= ±15V
S
V
OUT
–1.0V, +12.3V
0.0V, +12.8V
+1.0V, +12.3V
10
5
I
IN
1
0
0
–5
–1
–2
–3
–0.2
–0.4
–0.6
–10
–15
–20
–1.0V, –14.6V
+1.0V, –14.6V
0.0V, –15.1V
–20
–15
–10
–5
0
5
10
15
20
25
–1.2 –1.0 –0.8 –0.6 –0.4 –0.2
0
0.2 0.4 0.6 0.8 1.0 1.2
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 10. Input Overvoltage Performance, G = 1, VS = 15 V
Figure 13. Input Common-Mode Voltage vs. Output Voltage,
G = 1, VS = 15 V
3.0
6
5
4
3
2
1
0
0.5
0.4
0.3
0.2
0.1
0
V
= 5V
S
G = 100
V
OUT
2.5
2.0
1.5
1.0
0.5
0
+4mV, +2.8V
+1.0V, +2.3V
I
IN
+1.0V, +0.4V
+4mV, –0.1V
–0.5
–0.1
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
–5
0
5
10
15
20
25
30
35
40
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 11. Input Overvoltage Performance, G = 100
Figure 14. Input Common-Mode Voltage vs. Output Voltage, G = 1, VS = 5 V
Rev. 0 | Page 10 of 28
Data Sheet
AD8420
3.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
R
= 2.5V
= 10kΩ TO MIDSUPPLY
REF
L
3.0
2.5
2.0
1.5
1.0
0.5
0
+2.5V, +2.8V
+44mV, +2.8V
+4.8V, +2.78V
+3.03V, +2.46V
+1.5V, +2.3V
+1.5V, +0.4V
+3.03V, +0.16V
+44mV, –0.1V
+4.8V, –80mV
+2.5V, –0.1V
–0.5
–0.5
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
–0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 15. Input Common-Mode Voltage vs. Output Voltage,
G = 1, VS = 5 V, VREF = 2.5 V
Figure 18. Input Common-Mode Voltage vs. Output Voltage,
G = 100, VS = 5 V
0.6
3.5
3.0
+4mV, +0.5V
0.5
+86mV, +2.79V
+2.5V, +2.8V
+4.8V, +2.79V
0.4
0.3
2.5
2.0
1.5
1.0
0.5
0
0.2
0.1
+0.6V, +0.2V
0
+86mV, –90mV
+2.5V, –0.1V
+4.8V, –90mV
–0.1
–0.2
+4mV, –0.1V
0.1
–0.5
–0.5
–0.1
0
0.2
0.3
0.4
0.5
0.6
0.7
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 16. Input Common-Mode Voltage vs. Output Voltage, G = 1, VS = 2.7 V
Figure 19. Input Common-Mode Voltage vs. Output Voltage,
G = 100, VS = 5 V, VREF = 2.5 V
20
15
0.6
+29mV, +0.5V
+2.53V, +0.49V
0.5
0.4
0.3
0.2
0.1
0
–14.9V, +12.7V
+14.8V, +12.7V
0.0V, +12.8V
10
5
0
–5
–10
–15
–20
0.0V, –15.1V
–0.1
–0.2
–14.9V, –15.0V
+14.8V, –15.0V
+29mV, –0.1V
0.5
+2.53V, –90mV
2.0 2.5
–20
–15
–10
–5
0
5
10
15
20
–0.5
0
1.0
1.5
3.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 17. Input Common-Mode Voltage vs. Output Voltage,
G = 100, VS = 15 V
Figure 20. Input Common-Mode Voltage vs. Output Voltage,
G = 100, VS = 2.7 V
Rev. 0 | Page 11 of 28
AD8420
Data Sheet
40
35
30
25
20
15
10
120
100
80
60
40
20
0
V
= ±15V
S
–0.2V
+2.7V
GAIN = 1000
GAIN = 100
GAIN = 10
BANDWIDTH
LIMIT
I
I
(+IN)
(–IN)
BIAS
BIAS
GAIN = 1
5
–2.0
0
0.5
1.0
1.5
2.0
2.5
3.0
0.1
1
10
100
1k
10k
100k
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 21. Input Bias Current vs. Common-Mode Voltage
Figure 24. Positive PSRR vs. Frequency, RTI, VS = 15 V
400
120
100
80
60
40
20
0
V
= ±15V
S
SPECIFIED
300
200
PERFORMANCE RANGE
GAIN = 1000
I
(+IN)
BIAS
GAIN = 100
100
0
BANDWIDTH
LIMIT
–100
–200
–300
–400
GAIN = 10
GAIN = 1
I
(–IN)
BIAS
–1.5
–2.0
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1
1
10
100
FREQUENCY (Hz)
1k
10k
100k
DIFFERENTIAL INPUT VOLTAGE (V)
Figure 22. Input Bias Current vs. Differential Input Voltage, VS = 15
Figure 25. Negative PSRR vs. Frequency, RTI, VS = 15 V
100
70
V
= ±15V
S
GAIN = 1000
GAIN = 100
60
50
80
40
GAIN = 1000
60
30
GAIN = 10
GAIN = 1
20
GAIN = 100
40
10
GAIN = 10
0
BANDWIDTH
20
0
–10
–20
–30
LIMIT
GAIN = 1
10k
0.1
1
10
100
1k
100k
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. PSRR vs. Frequency on 5 V Supply
Figure 26. Gain vs. Frequency
Rev. 0 | Page 12 of 28
Data Sheet
AD8420
70
120
100
80
60
40
20
0
V
= 2.7V
S
GAIN = 1000
60
50
GAIN = 100
40
30
GAIN = 10
20
10
GAIN = 1
0
–10
–20
–30
V
V
= ±15V
S
= ±10V
CM
1
10
100
1k
10k
100k
1M
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
FREQUENCY (Hz)
DIFFERENTIAL INPUT VOLTAGE (V)
Figure 27. Gain vs. Frequency, 2.7 V Single Supply
Figure 30. CMRR vs. Differential Input Voltage
140
120
100
80
120
110
100
90
V
= ±15V
V
= 5V
S
BANDWIDTH
LIMIT
S
GAIN = 1000
GAIN = 100
80
70
60
GAIN = 10
60
50
GAIN = 1
40
40
20
30
0
20
0.1
1
10
100
FREQUENCY (Hz)
1k
10k
100k
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
Figure 28. CMRR vs. Frequency, RTI, VS = 15 V
Figure 31. Supply Current vs. Temperature, VS = +5 V
140
120
100
80
30
25
20
15
10
5
250
200
150
100
50
V
= ±15V
S
–IN BIAS CURRENT
+IN BIAS CURRENT
GAIN = 1000
GAIN = 100
60
GAIN = 10
GAIN = 1
40
0
OFFSET CURRENT
20
0
0
–50
0.1
1
10
100
1k
10k
100k
–40 –25 –10
5
20
35
50
65
80
95 110 125
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 29. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance, VS = 15 V
Figure 32. Input Bias Current and Input Offset Current vs. Temperature
Rev. 0 | Page 13 of 28
AD8420
Data Sheet
30
25
20
15
10
5
200
150
100
50
400
300
NORMALIZED TO 25°C
–IN BIAS CURRENT
+IN BIAS CURRENT
200
100
0
–100
–200
–300
–400
0
OFFSET CURRENT
–50
–100
0
–40 –25 –10
5
20
35
50
65
80
95 110 125
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 33. FB, REF Bias Current and FB, REF Offset Current vs. Temperature
Figure 36. Offset Drift
1000
5
4
REPRESENTATIVE DATA
NORMALIZED AT 25°C
V
V
= ±1V
= ±15V
V = ±15V
S
IN
S
800
600
3
PART A
PART B
400
2
200
1
PART A: 0.024ppm/°C
PART B: 0.038ppm/°C
0
0
–200
–400
–600
–800
–1000
–1
–2
–3
–4
REPRESENTATIVE DATA
NORMALIZED TO 25ºC
–40
–25
–10
5
20
35
50
65
80
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 34. Gain Error vs. Temperature, G = 1, VIN
=
1 V, VS = 15 V
Figure 37. CMRR vs. Temperature, G = 1, VS = 15 V
1000
+V
S
V
V
= ±0.1V
= ±15V
R
= 20kΩ
IN
S
L
800
600
–0.1
–0.2
–0.3
400
–40°C
+25°C
+85°C
+125°C
PART A
PART B
200
0
–200
–400
–600
–800
–1000
+0.3
+0.2
+0.1
REPRESENTATIVE DATA
NORMALIZED TO 25ºC
–V
S
–40
–25
–10
5
20
35
50
65
80
2
4
6
8
10
12
16
18
20
TEMPERATURE (°C)
SUPPLY VOLTAGE (±V )
S
Figure 38. Output Voltage Swing vs. Supply Voltage, RL = 20 kΩ
Figure 35. Gain Error vs. Temperature, G = 1, VIN
=
0.1 V, VS = 15 V
Rev. 0 | Page 14 of 28
Data Sheet
AD8420
+V
+V
S
S
–0.2
–0.4
–0.6
–0.8
–0.2
–0.4
–0.6
–0.8
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
+0.8
+0.6
+0.4
+0.2
+0.8
+0.6
+0.4
+0.2
V
V
= 5V
= 2.5V
S
REF
–V
–V
S
S
1k
10k
100k
1M
0.1
1
LOAD RESISTANCE (ꢀ)
OUTPUT CURRENT (mA)
Figure 39. Output Voltage Swing vs. Load Resistance, VS = 5 V
Figure 42. Output Voltage Swing vs. Output Current, VS = 15
+V
S
2k
1k
–0.2
–0.4
–0.6
–0.8
–40°C
+25°C
+85°C
+125°C
+0.8
GAIN = 1
100
+0.6
GAIN = 10
V
V
= 5V
S
+0.4
+0.2
= 2.5V
REF
GAIN = 100
1k
–V
S
0.1
20
0.1
1
1
10
100
10k
100k
OUTPUT CURRENT (mA)
FREQUENCY (Hz)
Figure 40. Output Voltage Swing vs. Load Resistance, VS = 5 V
Figure 43. Voltage Noise Spectral Density vs. Frequency, RTI
15
10
5
0
–5
–40°C
–10
+25°C
+85°C
+125°C
0.4µV/DIV
1s/DIV
–15
1k
10k
100k
1M
LOAD RESISTANCE (ꢀ)
Figure 41. Output Voltage Swing vs. Load Resistance, VS = 15 V
Figure 44. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1
Rev. 0 | Page 15 of 28
AD8420
Data Sheet
1k
V
= ±5V
S
1V/DIV
1.78µs TO 0.1%
3.31µs TO 0.01%
100
0.02%/DIV
20µs/DIV
10
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 48. Large Signal Pulse Response and Settling Time, G = 1
Figure 45. Current Noise Spectral Density vs. Frequency
V
= ±5V
S
4.5V/DIV
67µs TO 0.1%
138µs TO 0.01%
0.02%/DIV
200µs/DIV
1.5pA/DIV
1s/DIV
Figure 46. 0.1 Hz to 10 Hz Current Noise
Figure 49. Large Signal Pulse Response and Settling Time, G = 10
30
27
24
21
18
15
12
9
V
= ±5V
S
V
= ±15V, G = 15V/V
S
4.5V/DIV
600ms TO 0.1%
1.04ms TO 0.01%
0.02%/DIV
6
V
= +5V, G = 5V/V
S
3
20ms/DIV
0
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 47. Large Signal Frequency Response
Figure 50. Large Signal Pulse Response and Settling Time, G = 100
Rev. 0 | Page 16 of 28
Data Sheet
AD8420
20mV/DIV
4µs/DIV
20mV/DIV
2ms/DIV
Figure 51. Small Signal Pulse Response, G = 1, RL = 20 kΩ, CL = 100 pF
Figure 54. Small Signal Pulse Response, G = 1000, RL = 20 kΩ, CL = 100 pF
NO LOAD
220pF
470pF
780pF
20mV/DIV
20µs/DIV
20mV/DIV
5µs/DIV
Figure 52. Small Signal Pulse Response, G = 10, RL = 20 kΩ, CL = 100 pF
Figure 55. Small Signal Response with Various Capacitive Loads,
G = 1, RL = ∞
90
85
80
75
70
65
60
55
50
20mV/DIV
200µs/DIV
0
5
10
15
20
25
30
35
40
SUPPLY VOLTAGE (V)
Figure 56. Supply Current vs. Supply Voltage
Figure 53. Small Signal Pulse Response, G = 100, RL = 20 kΩ, CL = 100 pF
Rev. 0 | Page 17 of 28
AD8420
Data Sheet
90
TESTED WITH DUAL SUPPLIES
CENTERED AT 0V
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
0
4
8
12
16
20
24
28
32
36
SUPPLY VOLTAGE (V)
Figure 57. Offset Voltage vs. Supply Voltage
Rev. 0 | Page 18 of 28
Data Sheet
AD8420
THEORY OF OPERATION
+V
S
–
+
AD8420
A
g
V
OUT
I3
–V
+V
S
S
V
R2
R1
b
–
+
ESD
PROTECTION
FB
+IN
–V
+V
S
S
g
m1
m2
I1
I2
ESD
PROTECTION
REF
–IN
–V
S
Figure 58. Simplified Schematic
ARCHITECTURE
Table 7. Suggested Resistors for Various Gains, 1% Resistors
The AD8420 is based on an indirect current feedback topology
consisting of three amplifiers: two matched transconductance
amplifiers that convert voltage to current and one integrator
amplifier that converts current to voltage.
R1 (kΩ)
R2 (kΩ)
Short
49.9
80.6
90.9
95.3
97.6
100
Gain
1.00
2.00
5.03
10.09
20.06
49.8
101
None
49.9
20
10
5
2
1
1
1
For the AD8420, assume that all initial voltages and currents are
zero until a positive differential voltage is applied between the
inputs, +IN and −IN. Transconductance Amplifier gm± converts this
input voltage into a current, I±. Because the voltage across gm2 is
initially zero, I2 is zero and I3 equals I±.
200
499
1000
201
500
1001
I3 is integrated to the output, making the output voltage, ꢀOUT
increase. This voltage continues to increase until the same differ-
,
1
While the ratio of R2 to R± sets the gain, the designer determines
the absolute value of the resistors. Larger values reduce power
consumption and output loading; smaller values limit the FB input
bias current and offset current error. For best output swing and
distortion performance, keep (R± + R2V || RL ≥ 20 kꢁ.
ential input voltage across the inputs of gm± is replicated across
the inputs of gm2, generating a current (I2V equal to I±. This reduces
the Difference Current I3 to zero so that the output remains at a
stable voltage. The gain in the configuration shown in Figure 18 is
set by R2 and R±.
A method that allows large value feedback resistors while limiting
FB bias current error is to place a resistor of value R± || R2 in
series with the REF terminal, as shown in Figure 19. At higher
gains, this resistor can simply be the same value as R±.
In traditional instrumentation amplifiers, the input common-
mode voltage can limit the available output swing, typically
depicted in a hexagon plot. Because the AD8420 converts the
input differential signals to current, this limit does not apply. This
is particularly important when amplifying a signal with a common-
mode voltage near one of the supply rails.
+IN
V
I
+
–
OUT
B
AD8420
To improve robustness and ease of use, the AD8420 includes
overvoltage protection on its inputs. This protection scheme
allows wide differential input voltages without damaging the part.
I
B
FB
I
REF
F
–IN
B
I
R
B
SETTING THE GAIN
+
R1||R2
R1
R2
–
The transfer function of the AD8420 is
R2
R1
G = 1 +
V
V
OUT = G(V+IN − V−INV + VREF
REF
where:
Figure 59. Cancelling Out Error from FB Input Bias Current
R2
R1
G =±+
Rev. 0 | Page 19 of 28
AD8420
Data Sheet
GAIN ACCURACY
INPUT PROTECTION
Unlike most instrumentation amplifiers, the relative match of
the two gain setting resistors determines the gain accuracy of
the AD8420 rather than a single resistor. For example, if two
resistors have exactly the same absolute error, there is no error
in gain. Conversely, two ±% resistors can cause approximately 2%
maximum gain error at high gains. Temperature coefficient
mismatch of the gain setting resistors increases the gain drift
of the instrumentation amplifier circuit. Because these external
resistors do not have to match any on-chip resistors, resistors
with good TC tracking can achieve excellent gain drift.
The current into the AD8420 inputs is limited internally. This
ensures that the diodes that limit the differential voltage seen by
the internal amplifier do not draw excessive current when they
turn on. The part can handle large differential input voltages,
regardless of the amount of gain applied, without damage. As a
result, the AD8420 inputs are protected from voltages beyond
the positive rail. If voltages beyond the negative rail are expected,
external protection must be used.
Keep all of the AD8420 terminals within the voltage range specified
in the Absolute Maximum Ratings section. All terminals of the
AD8420 are protected against ESD.
When the differential voltage at the inputs approaches the
differential input limit, the diodes start to conduct, limiting
the voltage seen by the inputs. This can look like increased gain
error at large differential inputs. Performance of the AD8420 is
specified for ±± ꢀ differential from −40°C to +81°C. However,
at higher temperatures, the reduced forward voltage of the diodes
limits the differential input to a smaller voltage. Figure 60 tracks
±% error across the operating temperature range to show the
effect of temperature on the input limit.
Input Voltages Beyond the Rails
For applications that require protection beyond the negative rail,
one option is to use an external resistor in series with each input
to limit current during overload conditions. In this case, size the
resistors to limit the current into the AD8420 to 6 mA.
R
PROTECT ≥ (Negative Supply − VINV/6 mA
Although the AD8420 inputs must still be kept within the −ꢀS +
40 ꢀ limitation, the I × R drop across the protection resistor
increases the protection on the positive side to approximately
(40 ꢀ + Negative SupplyV + 300 μA × RPROTECT
2.0
NEGATIVE VOLTAGE
V = ±15V
S
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
An alternate protection method is to place diodes at the AD8420
inputs to limit voltage and resistors in series with the inputs to
limit the current into these diodes. To keep input bias current at
a minimum for normal operation, use low leakage diode clamps,
such as the BAꢀ±99. The AD8420 also combines well with TꢀS
diodes, such as the PTꢀSxS±UR.
POSITIVE VOLTAGE
+V
S
+V
+V
S
S
R
R
PROTECT
PROTECT
I
+
IN+
–
+
IN+
–
V
V
–V
+V
S
S
AD8420
AD8420
–40 –25 –10
5
20
35
50
65
80
95 110 125
R
R
TEMPERATURE (°C)
PROTECT
PROTECT
+
+
IN–
–
Figure 60. Differential Input Limit vs. Temperature
–V
–V
S
S
V
V
IN–
–V
–
S
INPUT VOLTAGE RANGE
SIMPLE METHOD
ALTERNATE METHOD
The allowed input range of the AD8420 is much simpler than
traditional architectures. For the transfer function of the AD8420
to be valid, the input voltage should follow two rules:
Figure 61. Protection for Voltages Beyond the Rails
Large Differential Input Voltage
The AD8420 is able to handle large differential input voltage
without damage to the part. Refer to Figure 9, Figure ±0,
Figure ±±, and Figure ±2 for overvoltage performance. The
AD8420 differential voltage is internally limited with diodes to
±± ꢀ. If this limit is exceeded, the diodes start to conduct and
draw current, as shown in Figure 22. This current is limited
internally to a value that is safe for the AD8420, but if the input
current cannot be tolerated in the system, place resistors in
series with each input with the following value:
•
•
Keep the differential input voltage within ±± ꢀ.
Keep the voltage on the +IN, −IN, REF, and FB pins in the
specified input voltage range.
Because the output swing is completely independent of the
input common-mode voltage, there are no hexagonal figures
or complicated formulas to follow, and no limitation for the
output swing the amplifier has for input signals with changing
common mode.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VDIFF −±ꢀ
±
2
RPROTECT
≥
IMAX
Rev. 0 | Page 20 of 28
Data Sheet
AD8420
Reference
LAYOUT
The output voltage of the AD8420 is developed with respect to
the potential on the reference terminal. Take care to tie REF to the
appropriate local ground. The differential voltage at the inputs is
reproduced between the REF and FB pins; therefore, it is important
to set ꢀREF so that the voltage at FB does not exceed the input range.
Common-Mode Rejection Ratio over Frequency
Poor layout can cause some of the common-mode signal to be
converted to a differential signal before reaching the in-amp. This
conversion can occur when the path to the positive input pin
has a different frequency response than the path to the negative
input pin. For best CMRR vs. frequency performance, the input
source impedance and capacitance of each path should be closely
matched. This includes connecting Pin ± to −ꢀS, which matches the
parasitic capacitance and the leakage between the inputs and
adjacent pins. Place additional source resistance in the input
path (for example, for input protectionV close to the in-amp inputs
to minimize their interaction with the parasitic capacitance from
the printed circuit board (PCBV traces.
DRIVING THE REFERENCE PIN
Traditional instrumentation amplifier architectures require the
reference pin to be driven with a low impedance source. In these
architectures, impedance at the reference pin degrades both CMRR
and gain accuracy. With the AD8420 architecture, resistance at
the reference pin has no effect on CMRR.
+IN
V
OUT
Power Supplies
AD8420
FB
Use a stable dc voltage to power the instrumentation amplifier.
Noise on the supply pins can adversely affect performance. For
more information, see the PSRR performance curves in Figure 24
and Figure 21.
REF
R1
–IN
R2
R
REF
R2 + R
REF
G = 1 +
R1
V
REF
Place a 0.± μF capacitor as close as possible to each supply pin.
As shown in Figure 62, a ±0 μF tantalum capacitor can be used
farther away from the part. This capacitor, which is intended to
be effective at low frequencies, can usually be shared by other
precision integrated circuits. Keep the traces between these
integrated circuits short to minimize interaction of the trace
parasitic inductance with the shared capacitor.
Figure 63. Calculating Gain with Reference Resistance
Resistance at the reference pin does affect the gain of the AD8420,
but if this resistance is constant, the gain setting resistors can be
adjusted to compensate. For example, the AD8420 can be driven
with a voltage divider as shown in Figure 64.
+V
S
+IN
V
OUT
0.1µF
10µF
AD8420
FB
+IN
–IN
REF
V
–IN
V
S
OUT
R1
R2
AD8420
R3
R4
R2 + R3||R4
R1
G = 1 +
R1
R2
Figure 64. Using Resistor Divider to Set Reference Voltage
0.1µF
10µF
–V
S
Figure 62. Supply Decoupling, REF, and Output Referred to Local Ground
Rev. 0 | Page 21 of 28
AD8420
Data Sheet
INCORRECT
CORRECT
+V
+V
S
S
V
V
V
V
OUT
OUT
OUT
OUT
AD8420
AD8420
–V
–V
S
S
TRANSFORMER
TRANSFORMER
+V
+V
S
S
V
OUT
AD8420
AD8420
10Mꢀ
–V
–V
S
S
THERMOCOUPLE
THERMOCOUPLE
+V
+V
S
S
C
C
C
V
OUT
1
R
R
fHIGH-PASS
=
2πRC
AD8420
AD8420
C
–V
–V
S
S
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 65. Creating an IBIAS Path
+V
S
INPUT BIAS CURRENT RETURN PATH
0.1µF
10µF
The input bias current of the AD8420 must have a return path
to ground. When the source, such as a thermocouple, cannot
provide a return current path, create one, as shown in Figure 61.
C
330pF
5%
C
R
20kꢀ
1%
+IN
–IN
V
OUT
R
20kꢀ
1%
C
D
AD8420
RADIO FREQUENCY INTERFERENCE (RFI)
3300pF
All instrumentation amplifiers can rectify high frequency out-of-
band signals. Once rectified, these signals appear as dc offset errors
at the output. High frequency signals can be filtered with a low-pass
RC network placed at the input of the instrumentation amplifier, as
shown in Figure 66. The filter limits the input signal bandwidth
according to the following relationship:
C
330pF
5%
C
R1
R2
0.1µF
10µF
–V
S
Figure 66. Suggested RFI Suppression Filter
CD affects the differential signal and CC affects the common-mode
signal. ꢀalues of R and CC are chosen to minimize out of band
RFI at the expense of reduced signal bandwidth. Mismatch
between the R × CC at the positive input and the R × CC at the
negative input degrades the CMRR of the AD8420. By using a
value of CD that is at least one magnitude larger than CC, the
effect of the mismatch is reduced and performance is improved.
±
FilterFrequencyDIFF
FilterFrequencyCM
=
2πR(2CD +CC V
±
=
2πRCC
where CD ≥ ±0 CC.
Rev. 0 | Page 22 of 28
Data Sheet
AD8420
Because the ADA4692-2 is a dual op amp, another op amp is
OUTPUT BUFFERING
now free for use as an active filter stage or to buffer another
AD8420 output on the same PCB. Figure 68 shows another
suggestion for how to use this second op amp. In this circuit,
the voltage from the wiper of a potentiometer is buffered by the
ADA4692-2, allowing a variable level shift of the output. Resistors
above and below the potentiometer reduce the total range of the
level shift but increase the precision. If the potentiometer were
connected directly to the REF pin of the AD8420, gain error would
be introduced from the variable resistance. The potentiometer can
be tuned in hardware or software, depending on the type of
potentiometer chosen. For a list of digital potentiometers made
by Analog Devices, Inc., visit www.analog.com/digipots/.
+5V
The AD8420 is designed to drive loads of 20 kꢁ or greater but
can deliver up to ±0 mA to heavier loads at lower output voltage
swings (see Figure 42V. If more output current is required, buffer
the AD8420 output with a precision op amp. Figure 67 shows
the recommended configuration using the ADA4692-2 as a single
supply. This low power op amp can swing its output from ± ꢀ to
4 ꢀ on a single 1 ꢀ supply while sourcing or sinking more than
30 mA of current. When using this configuration, the load seen
by the AD8420 is approximately R± + R2.
+5V
0.1µF
+V
S
0.1µF
+V
S
0.1µF
V
IN
AD8420
V
ADA4692-2
OUT
R1
R2
0.1µF
V
V
–V
IN
AD8420
OUT
S
V
REF
R
R
–V
S
CW
R1
R2
W
REF
Figure 67. Output Buffering
CCW
ADA4692-2
SUGGESTION FOR SECOND
AMPLIFIER: VARIABLE
LEVEL SHIFT WITHOUT
AFFECTING GAIN
Figure 68. Variable Level Shift
Rev. 0 | Page 23 of 28
AD8420
Data Sheet
APPLICATIONS INFORMATION
architecture, the offset can be accounted for in the input stage
by unbalancing the transconductance amplifier at the REF and
FB pins. In the steady state, the offset at the input is not gained
to the output, and higher frequency signals can be gained and
passed through. Using the AD8420 in this way, the offset tolerance
is nearly the differential input range of the part (±± ꢀV.
AD8420 IN ELECTROCARDIOGRAPHY (ECG)
A high-pass filter is commonly used in ECG signal conditioning
circuitry to remove electrode offset and motion artifacts. To avoid
degrading the input impedance and CMRR of the system, this
filtering is typically implemented after the instrumentation
amplifier, which limits the gain that can be applied with the
instrumentation amplifier.
Figure 69 shows an ECG front end that applies a gain of ±00 to
the signal while rejecting dc and high frequencies. This circuit
combines the AD8420 with the AD8617, which is a low power,
low cost, dual, precision CMOS op amp.
With a 3-op-amp instrumentation amplifier, gain is applied in the
first stage. Because of this, the electrode offset is gained and then
must be removed afterward with a high-pass filter. In the AD8420
THREE-POLE LPF,
INSTRUMENTATION
BESSEL RESPONSE
AMPLIFIER
G = +100
FC = 50Hz
200pF
+5V
402kꢀ
A
B
100kꢀ
2000pF
100kꢀ
200pF
0.015μF
110kꢀ
200kꢀ
200kꢀ
AD8420
FB
100kꢀ
1kꢀ
500kꢀ
0.022μF
+5V
REF
–5V
3.3μF
8200pF
C
10Mꢀ
+5V
–5V
AD8657-1
AD8657-2
–5V
INTEGRATOR PROVIDES
HIGH-PASS POLE AT 0.5Hz
Figure 69. AD8420 in an ECG Front End
Rev. 0 | Page 24 of 28
Data Sheet
AD8420
CLASSIC BRIDGE CIRCUIT
4 mA TO 20 mA SINGLE-SUPPLY RECEIVER
Figure 70 shows the AD8420 configured to amplify the signal from
a classic resistive bridge. This circuit works in dual-supply mode or
single-supply mode. Typically, the same voltage that powers the
instrumentation amplifier excites the bridge. Connecting the
bottom of the bridge to the negative supply of the instrumentation
amplifier sets up an input common-mode voltage that is located
midway between the supply voltages. The voltage on the REF pin
can be varied to suit the application. For example, the REF pin
is tied to the ꢀREF pin of an analog-to-digital converter (ADCV
whose input range is (ꢀREF ± ꢀINV. With an available output swing
on the AD8420 of (−ꢀS + ±00 mꢀV to (+ꢀS − ±10 mꢀV, the
maximum programmable gain is simply this output range divided
by the input range.
The 80 μA maximum supply current, input range that goes
below ground, and low drift characteristics make the AD8420 a
very good candidate for use in a 4 mA to 20 mA loop. Figure 7±
shows how a signal from a 4 mA to 20 mA transducer can be
interfaced to the AD8420. The signal from a 4 mA to 20 mA
transducer is single-ended, which initially suggests the need for
a simple shunt resistor to ground to convert the current to a voltage.
However, any line resistance in the return path (to the transducerV
adds a current-dependent offset error; therefore, the current must
be sensed differentially.
In this example, a 1 ꢁ shunt resistor generates a differential voltage
at the inputs of the AD8420 between 20 mꢀ (for 4 mA inV and
±00 mꢀ (for 20 mA inV with a very low common-mode value.
With the gain resistors shown, the AD8420 amplifies the ±00 mꢀ
input voltage by a factor of 40 to 4.0 ꢀ.
+V
S
0.1µF
V
V
V
AD8420
DIFF
OUT
REF
0.1µF
–V
S
Figure 70. Classic Bridge Circuit
5V
0.1µF
–
4mA TO 20mA
TRANSDUCER
LINE
IMPEDANCE
AD8420
0.8V TO 4.0V
4mA TO 20mA
5ꢀ
G = 40
+
–
+
R1 R2
POWER
SUPPLY
R2 = 97.6kꢀ
R1 = 2.49kꢀ
Figure 71. 4 mA to 20 mA Receiver Circuit
Rev. 0 | Page 25 of 28
AD8420
Data Sheet
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 72. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Model1
Temperature Range
Package Description
Branding
Y3Y
Y3Y
AD8420ARMZ
AD8420ARMZ-R7
AD8420ARMZ-RL
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
8-Lead Mini Small Outline Package [MSOP], Tube
8-Lead Mini Small Outline Package [MSOP], 7-Inch Tape and Reel
8-Lead Mini Small Outline Package [MSOP], 13-Inch Tape and Reel
RM-8
RM-8
RM-8
Y3Y
1 Z = RoHS Compliant Part.
Rev. 0 | Page 26 of 28
Data Sheet
NOTES
AD8420
Rev. 0 | Page 27 of 28
AD8420
NOTES
Data Sheet
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09945-0-3/12(0)
Rev. 0 | Page 28 of 28
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