AD8582AR [ADI]
+5 Volt, Parallel Input Complete Dual 12-Bit DAC; +5伏，并行输入完整的双通道12位DAC
| 型号： | AD8582AR |
| 厂家： | 
ADI |
| 描述： | +5 Volt, Parallel Input Complete Dual 12-Bit DAC |
| 文件： | 总8页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+5 Volt, Parallel Input
a
Complete Dual 12-Bit DAC
AD8582
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Com plete Dual 12-Bit DAC
No External Com ponents
Single +5 Volt Operation
1 m V/ Bit w ith 4.095 V Full Scale
True Voltage Output, ±5 m A Drive
Very Low Pow er: 5 m W
AD8582
V
V
DD
12
12-BIT
DAC A
DAC A
LDA
OUTA
REGISTER
INPUT A
REGISTER
CS
A/B
APPLICATIONS
12
2
DATA
V
REFERENCE
REF
Digitally Controlled Calibration
Portable Equipm ent
Servo Controls
INPUT B
REGISTER
Process Control Equipm ent
PC Peripherals
12
DAC B
REGISTER
12-BIT
DAC B
LDB
V
OUTB
AGND
MSB
DGND
RST
GENERAL D ESCRIP TIO N
T he high speed parallel data interface connects to the fastest
processors without wait states. T he double-buffered input struc-
ture allows the user to load the input registers one at a time,
then a single load strobe tied to both LDA + LDB inputs will
update both DAC outputs simultaneously. LDA and LDB can
also be activated independently to immediately update their re-
spective DAC registers. An address input decodes DAC A or
DAC B when the chip select CS input is strobed. An asynchro-
nous reset input sets the output to zero scale. T he MSB bit can
be used to establish a preset to midscale when the reset input is
strobed.
T he AD8582 is a complete, parallel input, dual 12-bit, voltage
output DAC designed to operate from a single +5 volt supply.
Built using a CBCMOS process, this monolithic DAC offers the
user low cost, and ease-of-use in +5 volt only systems.
Included on the chip, in addition to the DACs, are a rail-to-rail
amplifier, latch and reference. T he reference (VREF) is trimmed
to 2.5 volts output, and the on-chip amplifier gains up the DAC
output to 4.095 volts full scale. T he user needs only supply a +5
volt supply.
T he AD8582 is coded natural binary. T he op amp output
swings from 0 volt to +4.095 volts for a one-millivolt-per-bit
resolution, and is capable of driving ±5 mA. Operation down to
4.3 V is possible with output load currents less than 1 mA.
T he AD8582 is available in the 24-pin plastic DIP and the sur-
face mount SOIC-24. Each part is fully specified for operation
over –40°C to +85°C, and the full +5 V ± 5% power supply
range.
5.0
2.0
∆∆VFS
DATA = FFF
≤ 1 LSB
H
V
T
= +5V
1.5
1.0
T
= +25°C
DD
A
4.8
4.6
4.4
4.2
4.0
= –55°C, +25°C, +85°C
A
0.5
PROPER OPERATION
WHEN V SUPPLY
VOLTAGE ABOVE
CURVE
0.0
DD
–0.5
–1.0
= +25°C & +85°C
= –55°C
–1.5
–2.0
0.01
0.1
1.0
10
100
0
1024
2048
3072
4096
OUTPUT LOAD CURRENT – mA
DIGITAL INPUT CODE – Decimal
Figure 1. Minim um Supply Voltage vs. Load
Figure 2. Linearity Error vs. Digital Code and Tem perature
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD8582–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ V = +5.0 V ± 5%, R = No Load, –40°C ≤ T ≤ +85°C, unless otherwise noted)
DD
L
A
P ar am eter
Sym bol
Condition
Min
Typ
Max
Units
ST AT IC PERFORMANCE
Resolution
N
Note 1
12
–2
–1
Bits
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
Full-Scale T empco
INL
DNL
VZSE
VFS
±3/4
±3/4
+0.2
4.095
±16
+2
+1
+3
4.111
LSB
LSB
mV
Monotonic
Data = 000H
Data = FFFH,2
Notes 2 and 3
4.079
V
T CVFS
ppm/°C
MAT CHING PERFORMANCE
Linearity Matching Error
∆VFSA/B
±1
LSB
REFERENCE OUT PUT
Output Voltage
VREF
IREF
LNREJ
LDREG
2.484
2.500
2.516
–5
0.08
0.1
V
mA
%/V
%/mA
Output Source Current
Line Rejection
Load Regulation
Note 4
IREF = 0 mA to 5 mA
ANALOG OUT PUT
Output Current
IOUT
LDREG
CL
Data = 800H
±5
3
mA
LSB
pF
Load Regulation at Half Scale
Capacitive Load
RL = 402 Ω to ∞, Data = 800H
1
500
No Oscillation3
DYNAMIC CHARACT ERIST ICS3
Crosstalk
CT
tS
FT
>64
16
35
dB
µs
nV s
Voltage Output Settling T ime5
Digital Feedthrough
T o ±1 LSB of Final Value
Signal Measured at DAC Output, While
Changing Data (LDA = LDB = “1”)
LOGIC INPUT S
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
VIL
VIH
IIL
0.8
V
V
µA
pF
2.4
10
10
CIL
Note 3
T IMING SPECIFICAT IONS3, 6
Chip Select Pulse Width
DAC Select Setup
DAC Select Hold
Data Setup
tCSW
tAS
tAH
tDS
tDH
tLS
tLH
tLDW
tRSW
30
30
0
30
10
20
10
20
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold
Load Setup
Load Hold
Load Pulse Width
Reset Pulse Width
SUPPLY CHARACT ERIST ICS
Positive Supply Current
IDD
VIH = 2.4 V, VIL = 0.8 V
VIL = 0 V, VDD = +5 V
VIH = 2.4 V, VIL = 0.8 V
VIL = 0 V, VDD = +5 V
∆VDD = ±5%
4
1
20
5
7
2
35
10
mA
mA
mW
mW
Power Dissipation7
PDISS
PSS
Power Supply Sensitivity
0.002
0.004 %/%
NOT ES
11 LSB = 1 mV for 0 V to +4.095 V output range.
2Includes internal voltage reference error.
3T hese parameters are guaranteed by design and not subject to production testing.
4Very little sink current is available at the VREF pin. Use external buffer if setting up a virtual ground.
5Settling time is not guaranteed for the first six codes 0 through 5.
6All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
7Power dissipation is a calculated value IDD × 5 V.
Specifications subject to change without notice.
REV. 0
–2–
AD8582
P IN D ESCRIP TIO N
D escription
ABSO LUTE MAXIMUM RATINGS*
VDD to DGND & AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
Logic Inputs to DGND . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . . . (T J max–T A)/θJA
T hermal Resistance, θJA
24-Pin Plastic DIP Package (N-24) . . . . . . . . . . . . . 62°C/W
24-Lead SOIC Package (SOL-24) . . . . . . . . . . . . . . 73°C/W
Maximum Junction T emperature (TJ max) . . . . . . . . . . 150°C
Operating T emperature Range . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
P in No. Nam e
1, 24
VOUT A
VOUT B
Voltage outputs from the DACs. Fixed
output voltage range of 0 V to 4.095 V
with 1 mV/LSB. An internal
temperature stabilized reference
maintains a fixed full-scale voltage
independent of time, temperature and
power supply variations.
2
AGND Analog Ground. Ground reference for
the internal bandgap reference voltage,
the DAC, and the output buffer.
3
DGND Digital ground for input logic.
4, 21
LDA,
LDB
Load DAC register strobes. T ransfers
input register data to the DAC registers.
Active low inputs, Level sensitive latch.
May be connected together to double-
buffer load DAC registers.
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
5
MSB
Digital Input: High presets DAC
registers to half scale (800H), Low
clears DAC registers to zero (000H)
upon RST assertion.
tCSW
CS
tAH
tAS
6
RST
Active low digital input that clears the
DAC register to zero, setting the DAC
to minimum scale when MSB pin = 0,
or half-scale when MSB pin = 1.
A/B
tDH
tDS
D0–D11
tLDW
tLH
7–18
DB0–11 T welve Binary Data Bit Inputs. DB11 is
the MSB and DB0 is the LSB.
tLS
LDA, LDB
tRSW
19
20
22
23
CS
Chip Select. Active low input.
RST
A/B
VDD
VREF
Select DAC A = 0 or DAC B = 1.
Positive Supply. Nominal value +5 V, ±5%.
tS
tS
± 1LSB
ERROR BAND
V
OUT
Nominal 2.5 V reference output
voltage. T his node must be buffered if
required to drive external loads.
Timing Diagram
P IN CO NFIGURATIO NS
N-24
SO L-24
O RD ERING INFO RMATIO N*
24-P in P lastic D IP
24-P in SO IC
Tem perature
Range
P ackage
D escription
P ackage
O ption
24
1
Model
V
1
2
3
4
5
6
7
8
9
24
23
22
V
V
V
OUTA
OUTB
REF
DD
AGND
DGND
AD8582AN
AD8582AR
–40°C to +85°C 24-Pin Plastic DIP N-24
–40°C to +85°C 24-Lead SOIC SOL-24
Die
AD8582
TOP VIEW
(Not to Scale)
AD8582Chips +25°C
21 LDB
LDA
MSB
RST
20
19
18
17
16
15
A/B
*For die specifications contact your local Analog Devices sales office. T he
AD8582 contains 1270 transistors.
AD8582
TOP VIEW
(Not to Scale)
CS
DB0
DB1
DB11
DB10
12
13
DB2
DB9
DB8
DB3 10
DB4
14 DB7
13
11
DB5 12
DB6
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8582 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD8582
Table I. Control Logic Truth Table
CS
A/B
LDA
LDB
RST
MSB
Input Register
D AC Register
L
L
L
L
H
H
X
X
H
L
H
L
H
X
X
X
X
X
H
H
L
H
L
^
X
X
X
H
H
H
L
L
^
X
X
X
H
H
H
H
H
H
L
L
^
X
X
X
X
X
X
L
Write to A
Write to B
Write to A
Write to B
Latched
Latched
Reset to Zero Scale
Reset to Midscale
Latch Reset Value
Latched
Latched
A T ransparent
B T ransparent
A & B T ransparent
Latched
Reset to Zero Scale
Reset to Midscale
Latch Reset Value
H
X
^Denotes positive edge triggered.
O P ERATIO N
V
2.5V
VOLTAGE SWITCHED 12-BIT
R-2R D/A CONVERTER
REF
RAIL-TO-RAIL
OUTPUT
AMPLIFIER
BANDGAP
REFERENCE
T he AD8582 is a complete, ready-to-use dual 12-bit digital-to-
analog converter. Only one +5 V power supply is necessary for
operation. It contains two voltage-switched, 12-bit, laser-
trimmed digital-to-analog converters, a curvature-corrected
bandgap reference, rail-to-rail output op amps, input registers,
and DAC registers. T he parallel data interface consists of twelve
data bits, DB0–DB11, an address select pin A/B, two load
strobe pins (LDA, LDB) and an active low CS strobe. In addi-
tion an asynchronous RST pin will set all DAC register bits to
zero causing the VOUT to become zero volts, or to midscale for
trimming applications when the MSB pin is programmed to
Logic 1. T his function is useful for power on reset or system
failure recovery to a known state.
2R
V
OUT
R
BUFFER
R2
2R
R1
R
2R
AV = 4.095/2.5
= 1.638V/V
2R
SPDT
N CH FET
SWITCHES
2R
D /A CO NVERTER SECTIO N
Figure 3. Equivalent Schem atic of Analog Portion
T he internal DAC is a 12-bit voltage-mode device with an
output that swings from AGND potential to the 2.5 volt in-
ternal bandgap voltage. It uses a laser trimmed R-2R
ladder which is switched by N channel MOSFET s. T he out-
put voltage of the DAC has a constant resistance independent
of digital input code. T he DAC output (not available to the
user) is internally connected to the rail-to-rail output op amp.
O UTP UT SECTIO N
T he rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 4 shows an equivalent output schematic of
the rail-to-rail amplifier with its N channel pull-down FET s that
will pull an output load directly to GND. T he output sourcing
current is provided by a P channel pull-up device that can sup-
ply GND terminated loads, especially important at the –5%
supply tolerance value of 4.75 volts.
AMP LIFIER SECTIO N
T he internal DAC’s output is buffered by a low power con-
sumption precision amplifier. T his low power amplifier contains
a differential PNP pair input stage which provides low offset
voltage and low noise, as well as the ability to amplify the zero-
scale DAC output voltages. T he rail-to-rail amplifier is config-
ured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the
4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an
equivalent circuit schematic of the analog section.
V
DD
P-CH
V
OUT
N-CH
T he op amp has a 16 µs typical settling time to 0.01%. T here
are slight differences in settling time for negative slewing signals
versus positive. See the oscilloscope photos in the T ypical Per-
formances section of this data sheet.
AGND
Figure 4. Equivalent Analog Output Circuit
REV. 0
–4–
AD8582
Figures 5 and 6 in the typical performance characteristics sec-
tion provide information on output swing performance near
ground and full-scale as a function of load. In addition to resis-
tive load driving capability, the amplifier has also been carefully
designed and characterized for up to 500 pF capacitive load
driving capability.
One advantage of the rail-to-rail output amplifiers used in the
AD8582 is the wide range of usable supply voltage. T he part is
fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current
capability near full scale can be tolerated, operation of the
AD8582 is possible down to +4.3 volts. T he minimum operat-
ing supply voltage versus load current plot, in Figure 1, pro-
vides information for operation below VDD = +4.75 V.
REFERENCE SECTIO N
T he internal 2.5 V curvature-corrected bandgap voltage refer-
ence is laser trimmed for both initial accuracy and low tempera-
ture coefficient. T he voltage generated by the reference is
available at the VREF pin. Since VREF is not intended to drive ex-
ternal loads, it must be buffered. T he equivalent emitter fol-
lower output circuit of the VREF pin is shown in Figure 3.
TIMING AND CO NTRO L
T he input registers are level triggered and acquire data from the
data bus during the time period when CS is low. T he input reg-
ister selected is determined by the A/B select pin, see T able I.
for a complete description. When CS goes high, the data is
latched into the register and held until CS returns low. T he
minimum time required for the data to be present on the bus
before CS returns high is called the data setup time (tDS) as seen
in T iming Diagram. T he data hold time (tDH) is the amount
of time that the data has to remain on the bus after CS goes
high. T he high speed timing offered by the AD8582 provides
for direct interface with no wait states in all but the fastest
microprocessors.
Bypassing the VREF pin will improve noise performance; how-
ever, bypassing is not required for proper operation. Figure 8
shows broadband noise performance.
P O WER SUP P LY
T he very low power consumption of the AD8582 is a direct re-
sult of a circuit design optimizing use of the CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors good analog accuracy is achieved.
T he data from the input registers is transferred to the DAC reg-
isters by the active low LDA and LDB pins. If these inputs are
tied together, a single logic input can perform a double buffer
update of the DAC registers, which in turn simultaneously
changes the analog output voltages to a new value. If the LDA
and LDB pins are wired low, they become transparent. In this
mode the input register data will directly control the output
voltages. Refer to the Control Logic T ruth T able for a com-
plete description.
For power-consumption sensitive applications it is important to
note that the internal power consumption of the AD8582 is
strongly dependent on the actual logic-input voltage levels
present on the DB0–DB11, CS, A/B, MSB, LDA, LDB and
RST pins. Since these inputs are standard CMOS logic struc-
tures they contribute static power dissipation dependent on the
actual driving logic VOH and VOL voltage levels. T he graph in
Figure 9 shows the effect on total AD8582 supply current as a
function of the actual value of input logic voltage. Conse-
quently, for optimum dissipation use of CMOS logic versus
Unipolar O utput O per ation
T his is the basic mode of operation for the AD8582. T he
AD8582 has been designed to drive loads as low as 820Ω in par-
allel with 500 pF. T he code table for this operation is shown in
T able II.
T T L provides minimal dissipation in the static state. A VINL
=
0 V on the DB0–11 pins provides the lowest standby dissipation
of 1 mA typical with a +5 V power supply.
As with any analog system, it is recommended that the AD8582
power supply be bypassed on the same PC card that contains
the chip. Figure 10 shows the power supply rejection versus fre-
quency performance. T his should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
Table II. Unipolar Code Table
H exadecim al
Num ber in D AC
Register
D ecim al Num ber
in D AC Register
Analog O utput
Voltage (V)
FFF
801
800
7FF
000
4095
2049
2048
2047
0
+ 4.095
+ 2.049
+ 2.048
+ 2.047
0
REV. 0
–5–
AD8582–Typical Performance Characteristics
80
100
5
V
= +5V
= +25°C
DD
V
= +5V
POSITIVE0
CURRENT0
LIMIT0
DD
T
A
60
40
DATA = 000
H
4
10
R
TIED TO AGND
L
DATA = FFF
H
20
0
3
2
DATA = 800
H
1
R
TIED TO +2V
L
T
= +85°C
–20
A
T
= –40°C
A
–40
0.1
R
L
TIED TO +5V
1
0
NEGATIVE
CURRENT
LIMIT
DATA = 000
H
–60
–80
T
= +25°C
A
0.01
1
1
2
3
10
100
1000
100
1k
10k
100k
10
OUTPUT SINK CURRENT – µA
OUTPUT VOLTAGE – Volts
LOAD RESISTANCE – Ω
Figure 6. Pull-Down Voltage vs.
Output Sink Current Capability
Figure 5. Output Swing vs. Load
Figure 7. IOUT vs. VOUT
5
100
80
V
T
= +5V ±200mV AC
DD
T
= +25°C
T
= +25°C
A
A
= +25°C
A
4
3
2
1
0
NBW = 630kHz
V
= +4.75V
DATA = FFF
H
DD
V
= +5V
DD
60
40
20
0
0
1
2
3
4
5
100
1k
FREQUENCY – Hz
10k
100k
TIME = 100µs/DIV
10
LOGIC VOLTAGE VALUE – Volts
Figure 8. Broadband Noise
Figure 9. Supply Current vs. Logic
Input Voltage
Figure 10. Power Supply Rejection
vs. Frequency
5
5V
5
5
100
90
0
LDB
0
0
4
3
2048 TO 2047
15µs
10
10
V
T
= +5V
DD
2.048
2.038
2.028
2.018
2.008
= +25
°C
A
2
V
T
= +5V
DD
A
10
= +25°C
1
0
0%
1V
20µs
TIME = 20µs/DIV
TIME – 500ns/DIV
TIME – 5µs/DIV
Figure 13. Output Voltage Rise
Tim e Detail
Figure 12. Large Signal Settling Tim e
Figure 11. Midscale Transition
Perform ance
REV. 0
–6–
AD8582
45
40
4.115
4.110
4.105
TUE =
SS = 297 UNITS
ΣINL+ZS+FS
V
T
= +5V
= +25°C
DD
V
= +4.75V
DD
A
NO LOAD
SS = 298 UNITS
5
0
V
T
= +4.75V
DD
35
30
= +25°C
A
4.100
4.095
σAVG +1σ
25
20
15
15µs
4.090
4.085
10
5
AVG
σAVG –1σ
4.080
4.075
0
–8 –7 –6 –5 –4 –3 –2 –1
0
1
–50
–25
0
25
50
75
100 125
TIME – 5µs/DIV
TOTAL UNADJUSTED ERROR – mV
TEMPERATURE –
°C
Figure 14. Output Voltage Fall
Tim e Detail
Figure 15. Total Unadjusted Error
Histogram
Figure 16. Full-Scale Voltage vs.
Tem perature
3
2
1
0
3
100
V
= +5V
DD
V
T
= +5V
V
= +4.75V
DD
DD
SS = 135 UNITS
DATA = FFF
2
1
= +25°C
NO LOAD
A
H
DATA = FFF
H
SS = 298 UNITS
10
1.0
0.1
σ
AVG +2
σ
0
AVG
–1
–2
–3
σ
AVG –2
σ
–1
0
100
200
300
400
500
600
–50 –25
0
25
50
75
100 125
10
100
1k
FREQUENCY – Hz
10k
100k
TEMPERATURE –
°C
HOURS OF OPERATION AT +150°C
Figure 17. Zero-Scale Voltage vs.
Tem perature
Figure 18. Output Voltage Noise
Density vs. Frequency
Figure 19. Long-Term Drift
Accelerated by Burn-In
8
V
= +2.4V
DATA
5V
5µs
2V
7
6
1µs
NO LOAD
1
0
CS = HIGH
100
90
100
90
V
= +5.25V
∞
T = +25°C
A
DD
V
DD
5
R
= ∞
L
V
= +5.00V
DD
V
DD
= +5V
0V
4
3
V
REF
10
10
0V
V
= +4.75V
DD
0%
2
0%
10mV
2V
1
0
TIME – 5µs/DIV
TIME – 1µs/DIV
–50 –25
0
25
50
75
100 125
TEMPERATURE –
°C
Figure 20. Supply Current vs.
Tem perature
Figure 21. Reference Startup vs.
Tim e
Figure 22. Digital Feedthrough vs.
Tim e
REV. 0
–7–
AD8582
0.10
10
0.000
V
= +4.75V
8
∆ V = +4.75 TO +5.25V
DD
DD
∆V = +4.75V
DD
–0.001
6
4
0.08
0.06
0.04
0.02
0.00
∆I = 5mA
L
σAVG +1σ
AVG
2
–0.002
σAVG +1σ
σAVG +1σ
0
AVG
AVG
–2
–4
–0.003
–0.004
–6
–8
σAVG –1σ
σAVG – 1σ
σAVG –1σ
–10
–50 –25
–0.005
0
25
50
75
100 125
–50 –25
0
25
50
75
100 125
–50
–25
0
25
50
75
100 125
TEMPERATURE –
°C
TEMPERATURE –
°C
TEMPERATURE –
°C
Figure 23. Reference Error vs.
Tem perature
Figure 24. Reference Load Regulation
vs. Tem perature
Figure 25. Reference Line Regulation
vs. Tem perature
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
N-24
24-P in Nar r ow Body P lastic D IP
13
24
1
PIN 1
0.280 (7.11)
0.240 (6.10)
12
1.275 (32.30)
1.125 (28.60)
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
0.070 (1.77)
0.045 (1.15)
SEATING
PLANE
SO L-24
24-Lead Wide Body SO IC
13
24
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
PIN 1
1
12
0.1043 (2.65)
0.6141 (15.60)
0.5985 (15.20)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.0500 (1.27)
0.0157 (0.40)
8
0
°
°
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0125 (0.32)
0.0091 (0.23)
REV. 0
–8–
相关型号：
AD8582AR-REEL
DUAL, PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, PDSO24, SOIC-24
ROCHESTER
AD8582ARZ
DUAL, PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, PDSO24, SOIC-24
ROCHESTER
AD8591ART-REEL
CMOS Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers with Shutdown
ADI
AD8591ART-REEL7
IC OP-AMP, 30000 uV OFFSET-MAX, 2.2 MHz BAND WIDTH, PDSO6, SOT-23, 6 PIN, Operational Amplifier
ADI
©2020 ICPDF网 联系我们和版权申明